TW201919453A - Printed circuit board and method for manufacturing the same - Google Patents

Abstract

The present invention related to a printed circuit board and method for manufacturing the same. The printed circuit board according to an embodiment of the present invention includes a first insulating layer, a circuit pattern formed on the first insulating layer and exposed on one surface of the first insulating layer; a second insulating layer laminated on one surface of the first insulating layer and having a cavity area exposing the circuit pattern; and an insulator pattern interposed between the first insulating layer and the second insulating layer, extended into the interior of the cavity area and protruded from the bottom of the cavity area.

Description

Printed circuit board and method of manufacturing same

The following description relates to a printed circuit board and a method of manufacturing the same.

Adapting to the technical requirements associated with mobile phones and other electronic devices that have become more versatile, lighter, thinner and smaller in the information technology field, inserting integrated circuits, semiconductor wafers, or Demand for various electronic components such as active devices and passive devices has increased. In recent years, various methods of embedding components in panels have been developed.

Various cavity structures are formed to insert various components into the substrate. Therefore, various processing techniques are required. In addition, there is a need for a technique that prevents damage to the circuit due to processing.

An example of a method of manufacturing a printed circuit board with components embedded is described in U.S. Patent No. 7,882,433.

The Summary is provided to introduce a selection of concepts in the <Desc/Clms Page number> This Summary is not intended to identify key features or essential features of the claimed subject matter.

The following description is intended to provide a printed circuit board and a method of manufacturing the printed circuit board that can accurately process the cavity structure without damaging the circuit in the process of forming the cavity structure in which the electronic component is inserted.

According to an aspect of the present invention, a printed circuit board is provided, the printed circuit board including: a first insulating layer; a circuit pattern formed on the first insulating layer and on one surface of the first insulating layer Exposing; a second insulating layer laminated on one surface of the first insulating layer and having a cavity region exposing the circuit pattern; and an insulator pattern having the first insulating layer interposed therebetween One surface between the second insulating layers and another surface protruding from the bottom surface of the cavity region and formed along a boundary of the cavity region.

According to another aspect of the present invention, a method of manufacturing a printed circuit board is provided, the method comprising: forming a circuit pattern on one surface of a first insulating layer; forming a boundary of a cavity region on the first insulating layer Forming an insulator pattern along the boundary; forming a protective layer covering the cavity region; forming a second insulating layer on one surface of the first insulating layer; removing the second insulating layer along the insulator pattern Forming the cavity region; and removing the protective layer to expose the circuit pattern.

The following detailed description is provided to assist the reader in a comprehensive understanding of the methods, devices, and/or systems described herein. Various modifications, adaptations, and equivalents of the methods, devices, and/or systems described herein will be apparent to those skilled in the art. The order of operations described herein is merely an example, and is not limited to the order of operations referred to herein, but will be apparent to those of ordinary skill in the art, except where the operations must occur in a particular order. Other than that, it can be changed. In addition, descriptions of well-known functions and constructions of those skilled in the art can be omitted for clarity and clarity.

Features described herein can be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided to be thorough and complete, and the full scope of the present invention will be conveyed to those of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning Any term defined in a commonly used dictionary should be interpreted as having the same meaning as in the context of the related art, and should not be construed as having an idealized or overly formal meaning unless explicitly defined otherwise.

Regardless of the figure number, the same or corresponding components will be given the same reference numerals, and the same or corresponding components will not be described again. Throughout the description of the present invention, the detailed description will be omitted when it is stated that the specific related conventional techniques are not related to the viewpoint of the present invention. Terms such as "first" and "second" may be used in the description of various components, but the above components should not be limited to the above terms. The above terms are only used to distinguish between components. In the figures, some components may be exaggerated, omitted, or briefly shown, and the dimensions of the components do not necessarily reflect the actual dimensions of the components.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. Printed circuit board and electronic component package

Figure 1 shows an example of a printed circuit board. 2 and 3 show enlarged views of an example of a cavity area of a printed circuit board.

Referring to FIGS. 1 and 2, a printed circuit board according to an example includes a first insulating layer 10, a circuit pattern 15, a second insulating layer 20, and an insulator pattern 40.

The first insulating layer 10 electrically insulates the circuit pattern 15 formed on the inner or outer layer. The first insulating layer 10 may be made of a resin material. The first insulating layer 10 may include a thermosetting resin such as an epoxy resin and/or a thermoplastic resin such as polyimide (PI), and may be a prepreg (PPG) or a buildup film (build- The form of up film) is formed.

The circuit pattern 15 is formed in the first insulating layer 10 and is formed of a metal (for example, copper) that can transmit an electrical signal. The circuit pattern 15 may be formed on one surface, the other surface, or the inner side of the first insulating layer 10. For example, the circuit pattern 15 may include a via hole penetrating the first insulating layer 10 to connect one surface of the first insulating layer 10 to the other surface, and the pad is formed on the first surface One surface or the other surface of the insulating layer 10 is connected to the through hole.

Referring to FIGS. 1 and 2, a circuit pattern 16 having a structure embedded in the first insulating layer 10 is formed on one surface of the first insulating layer 10. For example, the embedded circuit pattern 16 may have a circuit structure in which a trace substrate is embedded, in which a fine circuit is embedded in the substrate. The fine circuit pattern 16 in the embedded trace structure can be capable of handling the fine pads of the electronic components to be inserted into the cavity region C.

The second insulating layer 20 is laminated on one surface of the first insulating layer 10 to electrically insulate the circuit pattern 15 and a portion of the second insulating layer 20 is penetrated to form the cavity region C. The second insulating layer 20 is formed of a material similar to the first insulating layer 10 in the form of a prepreg or a buildup film. The second insulating layer 20 may also be formed of another material or formed by another method. The second insulating layer 20 is formed with a through hole 22 for exposing the embedded circuit pattern 16. An electronic component is inserted into the cavity region C formed by the through hole 22, and the inserted electronic component can be connected to the embedded circuit pattern 16.

Referring to FIGS. 1 and 2, a second insulating layer 20 having a through hole 22 is laminated on one surface of the first insulating layer 10 such that the cavity region C may be formed to be the one surface of the first insulating layer 10 as The wall surface of the through hole 22 of the bottom and the second insulating layer 20 serves as a surface wall.

A third insulating layer 30 is formed on the second insulating layer 20, and through holes 22 and 32 that continuously penetrate the second insulating layer 20 and the third insulating layer 30 are formed to form the cavity region C deep.

The printed circuit board may further include a conductive post 35 connected to the circuit pattern 15 by penetrating the second insulating layer 20 and the third insulating layer 30. For example, the copper posts 35 can be bonded to the pads 17 of the circuit pattern 15. By using the conductive post 35, it is easy to electrically connect to another substrate in a package having a package on the package (POP) structure.

On the other hand, the cavity region C may have a shape that is narrowed toward the first insulating layer 10. When the through holes 22 and 32 are formed in the second insulating layer 20 or the third insulating layer 30 by laser or drilling, the boundary B of the cavity region C may be substantially as shown in FIG. vertical. That is, the inner wall of the cavity region C may be formed in the form of a vertical wall.

On the other hand, when the through holes 22' and 32' are formed in the second insulating layer 20 or the third insulating layer 30 by sand blast processing, the boundary B of the cavity region C is as shown in FIG. The illustration is formed to be inclined. That is, a structure in which the inner wall of the cavity region C is narrowed downward can be formed.

Referring to FIG. 1, the other surface of the first insulating layer 10 or one surface of the third insulating layer 30 may be an outer layer of a printed circuit board, and a solder resist layer 50 may be additionally formed on the outer layer. 60. A portion of the conductive post 35 or circuit pattern 15 may be exposed through the openings of the solder mask layers 50 and 60 to electrically connect to the external environment.

The insulator pattern 40 is formed such that one surface is sandwiched between the first insulating layer 10 and the second insulating layer 20 and the other surface extends into the cavity region C to protrude from the bottom surface of the cavity region C. The insulator pattern 40 is formed on one surface of the first insulating layer 10 and extends into the cavity region C and thus has a shape protruding from the bottom surface of the cavity region C.

Referring to FIGS. 2 and 3, one end of the insulator pattern 40 is located between the first insulating layer 10 and the second insulating layer 20 and the other end is disposed above the bottom surface of the cavity region C. The insulator pattern 40 may be formed on one surface of the first insulating layer 10 along the boundary B of the cavity region C. More specifically, the insulator pattern 40 is formed at a boundary B of the cavity region C in which an imaginary surface extending as a wall surface of the through holes 22 and 32 of the inner wall of the cavity meets with one surface of the first insulating layer 10. Location. The insulator pattern 40 formed along the boundary B of the cavity region C may have a closed loop structure and a portion of the first insulator layer 10 and the circuit pattern 15 may be exposed inward.

For example, when the cavity region C is formed in a hexahedral shape, the insulator pattern 40 is formed on the first insulating layer 10 in the form of a rectangular frame, and the first insulating layer 10 and the embedded circuit pattern 16 serve as a cavity. A surface of the bottom of the region C may be exposed to the inner side of the rectangular frame.

Referring to FIG. 12, an insulator pattern 40' may be formed to cover at least a portion of the circuit pattern 15. For example, the insulator pattern 40' may have a structure in which a portion of the insulator pattern 40' contacts the upper surface of the embedded circuit pattern 16.

The insulator pattern 40 may be formed of a photosensitive resin so that the insulator pattern 40 can be easily and selectively formed on one surface of the first insulator layer 10. For example, the insulator pattern 40 can be easily formed by selectively applying a photosensitive resin to one surface of the first insulating layer 10 along the boundary B of the cavity region C and curing the resultant.

Further, the insulator pattern 40 may be formed of a material different from the material of the second insulating layer 20. For example, the insulator pattern 40 may have higher wear resistance than the second insulating layer 20 or the third insulating layer 30 in which the through holes 22 and 32 are formed or higher than the second insulating layer 20 or the third insulating layer 30. Roughness of the material is formed. Therefore, when the through holes 22 and 32 are formed in the second insulating layer 20 or the third insulating layer 30 by sandblasting, the insulator pattern 40 can serve as a processed stopper. Details of the function of the blasting and stoppers will be explained later. Method of manufacturing a printed circuit board

4 through 11 are cross-sectional views showing an exemplary process used in a method of manufacturing a printed circuit board.

A method of manufacturing a printed circuit board according to an embodiment of the present invention includes: forming a circuit pattern 15 on a first insulating layer 10; forming an insulator pattern 40; forming a protective layer 45; forming a second insulating layer; forming a cavity region C; In addition to the protective layer 45.

Forming the circuit pattern 15 on the first insulating layer 10 includes forming a circuit pattern 15 on one surface of the first insulating layer 10. The circuit pattern 15 may also be formed on the other surface or the inner side of the first insulating layer 10. The circuit pattern 15 may include a buried circuit pattern 16, and the embedded circuit pattern 16 may have a circuit structure in which a trace substrate is embedded, in which a fine circuit is embedded in the substrate. The fine circuit of the embedded trace structure can handle the fine pads of the electronic components.

Referring to FIG. 4, a first insulating layer 10 and a circuit pattern 15 may be formed on both surfaces of a carrier substrate 5 having a release layer. For example, a metal layer can be formed by plating, and a patterning process can be performed by selective etching. In addition, the circuit pattern 15 can be formed by coating a conductive metal material on the release layer of the carrier substrate 5 and then performing a patterning process or the like. The patterning process can be a tenting process, a modified semi-additive process (MSAP) process, or a semi-additive process (SAP) process.

After the circuit pattern 15 is formed on the carrier substrate 5, the first insulating layer 10 may be pressed and laminated on the carrier substrate 5 to embed the circuit pattern 15 in the first insulating layer 10. At this time, the first insulating layer 10 may be a semi-cured prepreg. The carrier substrate 5 may be coated with an insulating resin to form the first insulating layer 10 for embedding the circuit pattern 15. On the other hand, the circuit pattern 15 may be additionally formed on the inner surface or the other surface of the first insulating layer 10 laminated on the carrier substrate 5. At this time, the circuit pattern 15 placed on the carrier substrate 5 may have an embedded structure surrounded by the first insulating layer 10.

Referring to FIG. 5, when the first insulating layer 10 on which the circuit pattern 15 is formed is separated from the carrier substrate 5, the circuit pattern 15 may have the embedded circuit pattern 16 exposed to one surface of the first insulating layer 10. When a seed layer is formed on one surface of the first insulating layer 10 contacting the carrier substrate 5, the seed layer may be removed by etching to expose the embedded in the first insulating layer 10. A circuit pattern 16 in one surface.

The forming the insulator pattern 40 may include setting the boundary B of the cavity region C on the first insulating layer 10 and forming the insulator pattern 40 along the boundary B. At this time, the insulator pattern 40 may be formed of a material different from that of the second insulating layer 20. For example, the insulator pattern 40 may be formed of a material having a higher wear resistance than the second insulating layer 20 or the third insulating layer 30 to be subsequently laminated or a higher roughness than the second insulating layer 20 or the third insulating layer 30. . Therefore, when the through holes 22 and 32 are formed in the second insulating layer 20 or the third insulating layer 30 by sandblasting, the insulator pattern 40 can serve as a processed stopper.

Referring to FIG. 6, an insulator pattern 40 may be formed on the boundary B of the cavity region C on one surface of the first insulating layer 10. Specifically, the boundary of the cavity region C (B, the imaginary surface on which the inner wall of the cavity is to be formed) may be set, and the insulator pattern 40 may be formed at a position where the boundary B meets one surface of the first insulating layer 10 . The insulator pattern 40 formed along the boundary B of the cavity region C may have a closed loop structure, and a portion of the first insulating layer 10 and the circuit pattern 15 may be exposed inward. For example, when the cavity region C is formed in a hexahedral shape, the insulator pattern 40 may be formed on the first insulating layer 10 in the form of a rectangular frame, and the first insulating layer 10 and the circuit pattern 15 as the cavity region C One surface of the bottom may be exposed to the inner side of the rectangular frame.

The insulator pattern 40 may be formed of a photosensitive resin so that the insulator pattern 40 can be easily and selectively formed on one surface of the first insulator layer 10. For example, the insulator pattern 40 can be easily formed by selectively applying a photosensitive resin to one surface of the first insulating layer 10 along the boundary B of the cavity region C and curing the resultant.

The forming the protective layer 45 may include forming a temporary protective layer 45 that protects the bottom of the cavity region C in the step of processing the subsequent cavity region C. For example, the protective layer 45 may cover the bottom of the cavity region C to protect the embedded circuit pattern 16. The protective layer 45 may be made of a material different from that of the circuit pattern 15.

Referring to FIG. 7, a protective layer 45 formed of an insulating material covering the bottom of the cavity region C may be attached to one surface of the first insulating layer 10. At this time, it is preferable that the protective layer 45 overlaps the insulator pattern 40 formed at the boundary B of the cavity region C, thereby completely covering the bottom of the cavity region C. The protective layer 45 can effectively prevent the embedded circuit pattern 16 from being damaged in the step of processing the cavity region C to be described later. In particular, since the fine circuit pattern 16 of the embedded trace structure has a very small thickness and width, the fine circuit pattern 16 may be severely damaged by a small error in processing. Therefore, when the circuit pattern 15 of the cavity region C is covered by the protective layer 45, the reliability and efficiency of manufacturing the printed circuit board can be improved.

The forming the second insulating layer 20 may include forming the second insulating layer 20 on one surface of the first insulating layer 10. The second insulating layer 20 may be formed of a material similar to the first insulating layer 10 in the form of a prepreg or a buildup film. The second insulating layer 20 may also be formed of another material or formed by another method.

Referring to FIG. 8, a second insulating layer 20 in which an insulator pattern 40 and a protective layer 45 are embedded may be laminated on one surface of the first insulating layer 10. The third insulating layer 30 may be further laminated on the second insulating layer 20. At this time, the conductive pillars 35 connected to the circuit pattern 15 via the second insulating layer 20 and the third insulating layer 30 may be additionally formed. For example, the copper posts 35 can be bonded to the pads of the circuit pattern 15.

The forming the cavity region C may include removing the second insulating layer 20 along the insulator pattern 40 to form the cavity region C. In other words, the second insulating layer 20 is removed along the boundary B of the set cavity area C.

Specifically, a cavity region C having a concave groove structure in which an electronic component or the like can be inserted and formed is formed by forming the through hole 22 in the second insulating layer 20. When the third insulating layer 30 is formed on the second insulating layer 20, the through holes 22 and 32 that continuously penetrate the second insulating layer 20 and the third insulating layer 30 may be formed. By exposing the protective layer 45 through the through holes 22 and 32, the embedded circuit pattern 16 exposed after removing the protective layer 45 to be described later can be electrically connected to the electronic component.

At this time, the processing of the cavity region C can be performed by sandblasting for selectively removing the second insulating layer (20).

Referring to FIG. 9, when the cavity region C is processed, the insulator pattern 40 may serve as a stopper for limiting the processing depth. For example, the processing of the cavity region C is performed by sandblasting, and the insulator pattern 40 serving as a stopper for sand blasting may have higher wear resistance than the second insulating layer 20 or the third insulating layer 30 and A material having a high roughness of the second insulating layer 20 or the third insulating layer 30 is formed.

Sandblasting is a processing method in which the surface of a workpiece is trimmed or cut by spraying an abrasive from a nozzle. In the past, sand was sprayed with abrasives, which was thus named sandblasting. Now, various particles such as ceramic powder (for example, alumina (alumina) or tantalum carbide), glass beads, plastic powder, or the like can be used as the abrasive. There is another type of blasting: wet sand blast, mixing the abrasive with water and then ejecting it from the nozzle; and dry sand blast, processing only the abrasive and then using air to treat it Sprayed from the nozzle.

In this embodiment, the process barrier layer 70 that selectively covers the unprocessed portion of the third insulating layer 30 is formed. The second insulating layer 20 and the third insulating layer 30 are processed by sandblasting to expose the upper portions of the insulator pattern 40 and the protective layer 45. At this time, since the insulator pattern 40 is made of a material having high wear resistance or high roughness, the insulator pattern 40 is worn or cut by sandblasting compared to the second insulator layer 20 and the third insulator layer 30. Less words. This makes it possible to prevent the boundary B portion of the cavity region C from being damaged even if sandblasting is sufficiently performed until the protective layer 45 is exposed at the central portion of the cavity region C.

The removing the protective layer 45 may include exposing the embedded circuit pattern 16 by removing the protective layer 45. The protective layer 45 can be easily removed by chemical or physical methods depending on the materials used.

Referring to FIG. 10, a protective layer 45 made of an insulating material may be removed from the first insulating layer 10.

Referring to FIG. 11, the other surface of the first insulating layer 10 or one surface of the third insulating layer 30 may be an outer layer of a printed circuit board, and solder resist layers 50 and 60 may be additionally formed on the outer layer. The conductive pillars 35 and a portion of the circuit pattern 15 may be exposed through the openings of the solder resist layers 50 and 60 to be electrically connected to the external environment.

It will be apparent to those skilled in the art that various modifications and additions to the components, or additions to the components, can be made without departing from the spirit of the invention as set forth in the appended claims. It is to be understood that the invention is not limited thereto, and various changes and modifications may be made thereto without departing from the scope of the invention.

5‧‧‧ Carrier substrate

10‧‧‧First insulation

15‧‧‧ circuit pattern

16‧‧‧Circuit pattern/fine circuit pattern/embedded circuit pattern

17‧‧‧ pads

20‧‧‧Second insulation

22, 22 ', 32, 32 '‧‧‧through holes

30‧‧‧third insulation

35‧‧‧ Conductive column / copper column

40, 40 '‧‧‧Insulator pattern

45‧‧‧Protective layer

50, 60‧‧‧ solder mask

70‧‧‧Processing barrier layer

B‧‧‧ border

C‧‧‧Cavity area

Figure 1 shows an example of a printed circuit board. 2 and 3 show enlarged views of an example of a cavity area of a printed circuit board. 4 through 11 are cross-sectional views showing an exemplary process used in the method of manufacturing the printed circuit board shown in Fig. 1. Figure 12 shows another example of a printed circuit board. Throughout the drawings and the detailed description, the same reference numerals refer to the same components. The drawings may not necessarily be drawn to scale, and the relative size, proportion, and depiction of the components in the drawings may be exaggerated for clarity, description, and convenience.

Claims (14)

A printed circuit board comprising: a first insulating layer; a circuit pattern formed on the first insulating layer and exposed on one surface of the first insulating layer; a second insulating layer laminated on the first a surface of an insulating layer having a cavity region exposing the circuit pattern; and an insulator pattern having a surface sandwiched between the first insulating layer and the second insulating layer and from the surface The bottom surface of the cavity region protrudes and forms another surface along the boundary of the cavity region. The printed circuit board of claim 1, wherein the first insulating layer and a portion of the circuit pattern are exposed in a region surrounded by the insulator pattern. The printed circuit board of claim 1, wherein the circuit pattern is embedded in the first insulating layer and includes an embedded circuit pattern, and a top surface of the embedded circuit pattern is at the first One surface of the insulating layer is exposed. The printed circuit board of claim 1, wherein the insulator pattern is made of a material different from the second insulating layer. The printed circuit board of claim 4, wherein the insulator pattern is made of a material having a higher wear resistance than the second insulating layer or a higher roughness than the second insulating layer. . The printed circuit board of claim 4, wherein the insulator pattern is made of a photosensitive resin. The printed circuit board of claim 1, wherein the cavity region is narrowed as the cavity region approaches the first insulating layer. The printed circuit board of claim 1, further comprising: a third insulating layer formed on the second insulating layer; and a conductive pillar passing through the second insulating layer and the third insulating layer A layer is formed and connected to the circuit pattern. The printed circuit board of claim 1, wherein the insulator pattern covers at least a portion of the circuit pattern. A method of manufacturing a printed circuit board, comprising: forming a circuit pattern on one surface of a first insulating layer; forming a boundary of a cavity region on the first insulating layer and forming an insulator pattern along the boundary; forming an overlay a protective layer of the cavity region; forming a second insulating layer on one surface of the first insulating layer; removing the second insulating layer along the insulator pattern to form the cavity region; and removing the A protective layer is exposed to expose the circuit pattern. The method of claim 10, wherein the forming the insulator pattern comprises disposing an insulator pattern on the boundary of the cavity region. The method of claim 11, wherein the forming the insulator pattern comprises selectively coating a photoresist resin on the boundary of the cavity region and curing the photoresist resin. The method of claim 10, wherein the forming the cavity region comprises selectively removing the second insulating layer by sandblasting. The method of claim 13, wherein the blasting further comprises: forming a processing barrier layer that selectively covers the unprocessed region of the second insulating layer.