TW201913917A - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

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Publication number
TW201913917A
TW201913917A TW106128487A TW106128487A TW201913917A TW 201913917 A TW201913917 A TW 201913917A TW 106128487 A TW106128487 A TW 106128487A TW 106128487 A TW106128487 A TW 106128487A TW 201913917 A TW201913917 A TW 201913917A
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Taiwan
Prior art keywords
material layer
polymer material
dielectric material
filler content
high filler
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TW106128487A
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English (en)
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TWI628756B (zh
Inventor
許哲瑋
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鳳凰先驅股份有限公司
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Priority to TW106128487A priority Critical patent/TWI628756B/zh
Application granted granted Critical
Publication of TWI628756B publication Critical patent/TWI628756B/zh
Priority to US16/106,107 priority patent/US10304750B2/en
Publication of TW201913917A publication Critical patent/TW201913917A/zh

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Abstract

本發明揭示一種封裝結構及其製作方法。該封裝結構包括：一第一高分子材料層，具有一第一表面；一第二高分子材料層，具有一第二表面，形成於該一第一高分子材料層上；一電路元件，具有一第三表面及一相對該第三表面的第四表面，該電路元件之第三表面設置於該第二高分子材料層上並具有一連接端於該第四表面上；一第一高充填劑含量介電材料層，包覆該電路元件及該第二高分子材料層，並覆蓋該第一高分子材料層；一第一導電線路，形成於該第一高充填劑含量介電材料層上；一第一導電通道，形成於該第一高充填劑含量介電材料層內，用以連接該第一導電線路與該連接端；一第二高充填劑含量介電材料層，包覆該第一導電線路，並覆蓋該第一高充填劑含量介電材料層；以及一第二導電通道，形成於該第二高充填劑含量介電材料層內，用以連接該第一導電線路與一外部電路；其中，該第一表面的面積大於該第二表面的面積，且該第三表面的面積等於該第二表面的面積。

Description

封裝結構及其製作方法
本發明係關於一種封裝結構以及其製作方法。
新一代電子產品不僅追求輕薄短小的高密度，更有朝向高功率發展的趨勢；因此，積體電路(Integrated Circuit，簡稱IC)技術及其後端的晶片封裝技術亦隨之進展，以符合此新一代電子產品的效能規格。
在目前「面板等級」或「晶圓等級」封裝製程中，半導體晶粒是以一種可剝除膠暫時黏貼於面板或晶圓等級的承載板上，再進行封裝膠體的鑄模製程。由於鑄模過程需要高壓力，而上述可剝除膠與承載板之間的結合性不佳，此常導致半導體晶粒會有位置偏移的現象，也因此引起後續線路層或重佈線層(ReDistribution Layer，簡稱RDL)製程的對位(alignment)不良而致良率偏低。因此，有必要發展新的封裝基板技術，以對治及改善上述的問題。
本發明一實施例提供一種封裝結構，其包含：一第一高分子材料層，具有一第一表面；一第二高分子材料層，具有一第二表面，形成於該一第一高分子材料層上；一電路元件，具有一第三表面及一相對該第三表面的第四表面，該電路元件之第三表面設置於該第二高分子材料層上並具有至少一連接端於該第四表面上；一第一高充填劑含量介電材料層，包覆該電路元件及該第二高分子材料層，並覆蓋該第一高分子材料層；一第一導電線路，形成於該第一高充填劑含量介電材料層上；一第一導電通道，形成於該第一高充填劑含量介電材料層內，用以連接該第一導電線路與該連接端；一第二高充填劑含量介電材料層，包覆該第一導 電線路，並覆蓋該第一高充填劑含量介電材料層；以及一第二導電通道，形成於該第二高充填劑含量介電材料層內，用以連接該第一導電線路與一外部電路；其中，該第一表面的面積大於該第二表面的面積，且該第三表面的面積等於該第二表面的面積。
在一實施例中，該第一高充填劑含量介電材料層包含一第一鑄模化合物，該第二高充填劑含量介電材料層包含一第二鑄模化合物。
在一實施例中，該電路元件為半導體晶粒或電子元件。
在一實施例中，該封裝結構進一步包含：一第二導電線路，形成於該第二導電通道上及該第二高充填劑含量介電材料層上；一保護層，包覆該第二導電線路，並覆蓋該第二高充填劑含量介電材料層；以及一第三導電通道，形成於該保護層內，用以連接該第二導電線路與一外部電路。
本發明另一實施例提供一種封裝結構之製作方法，其步驟包含：(A)提供一承載板及複數個電路元件，該承載板具有一第一表面，該等電路元件各具有一第二表面及一相對該第二表面的第三表面，且該等電路元件各具有至少一連接端於其第三表面上；(B)形成一第一高分子材料層於該承載板上，使得該第一高分子材料層完全覆蓋該承載板的第一表面；(C)形成一第二高分子材料層於各個該等電路元件上，使得該第二高分子材料層完全覆蓋各個該等電路元件的第二表面；(D)將該等電路元件放置於該承載板上，使得該第二高分子材料層貼合該第一高分子材料層；(E)形成一第一高充填劑含量介電材料層於該承載板上，使其包覆該電路元件；(F)形成一第一導電通道於該第一高充填劑含量介電材料層內，並形成一第一導電線路於該第一導電通道上，使得該第一導電通道連接該第一導電線路與該連接端；(G)形成一第二高充填劑含量介電材料層於該第一高充填劑含量介電材料層上，使其包覆該第一導電線路，並覆蓋該第一高充填劑含量介電材料層；(H)形成一第二導電通道於該第二高充填劑含量介電材料層內，使得該第一導電通道連接至該第一導電線路；(I)移除該承載板而得到一 包括該等電路元件的封裝結構半成品；以及(J)分割該封裝結構半成品而得到複數個封裝結構，使得該等封裝結構各具有該等電路元件的其中一者。
在一實施例中，該第一高分子材料層係以壓合或塗佈方式形成，並對該第一高分子材料層進行烘烤。
在一實施例中，該第二高分子材料層係以壓合、塗佈或印刷方式形成，並對該第二高分子材料層進行烘烤。
在一實施例中，該第一導電通道的形成方式包含：以雷射鑽孔方式於該第一高充填劑含量介電材料層內及該電路元件的該連接端上形成一貫孔；及以電鍍方式充填導電材料於該貫孔中。
本發明之實施例係藉由第二高分子材料層來提高半導體晶粒與承載板之間的結合性，可解決半導體晶粒易自承載板上剝離的問題，並可同時解決鑄模製程的過程中，易發生半導體晶粒位置自承載板上偏移的現象，進而改善後續線路層或重佈線層(RDL)製程的良率。
100、200‧‧‧封裝結構
101‧‧‧承載板
102‧‧‧封裝結構半成品
110‧‧‧第一高分子材料層
120‧‧‧第二高分子材料層
130‧‧‧電路元件
131‧‧‧連接端
140‧‧‧第一高充填劑含量介電材料層
150‧‧‧第一導電線路
160‧‧‧第一導電通道
170‧‧‧第二高充填劑含量介電材料層
180‧‧‧第二導電通道
201‧‧‧次面板
290‧‧‧導電錫球
292‧‧‧第二導電線路
294‧‧‧保護層
296‧‧‧第三導電通道
300‧‧‧面板
第1圖為根據本發明第一實施例的封裝結構之剖面示意圖。
第2圖為根據本發明第二實施例的封裝結構之剖面示意圖。
第3圖為一片面板上同時安排900個封裝基板的平面示意圖。
第4~9圖分別對應第一實施例各個製程步驟的封裝結構之剖面圖。
為使對本發明之特徵、目的及功能有更進一步的認知與瞭解，茲配合圖式詳細說明本發明的實施例如後。在所有的說明書及圖示中，將採用相同的元件編號以指定相同或類似的元件。
在各個實施例的說明中，當一元素被描述是在另一元素之「上方/上」或「下方/下」，係指直接地或間接地在該另一元素之上或之下的情況，其可能包含設置於其間的其他元素；所謂的「直接地」係指其間並未設置其他中介元素。「上方/上」或「下方/下」等的描述係以圖式為基準進行說明，但亦包含其他可能的方向轉變。 所謂的「第一」、「第二」、及「第三」係用以描述不同的元素，這些元素並不因為此類謂辭而受到限制。為了說明上的便利和明確，圖式中各元素的厚度或尺寸，係以誇張或省略或概略的方式表示，且各元素的尺寸並未完全為其實際的尺寸。
第1圖為根據本發明第一實施例的封裝結構100之剖面示意圖。該封裝結構100包含：一第一高分子材料層110、一第二高分子材料層120、一電路元件130、一第一高充填劑含量介電材料層140、一第一導電線路150、一第一導電通道160、一第二高充填劑含量介電材料層170及一第二導電通道180；其中，該第二高分子材料層120、該電路元件130、該第一導電通道160及該第一高充填劑含量介電材料層140組成第一封裝單元，而該第一導電線路150、該第二導電通道180及該第二高充填劑含量介電材料層170組成第二封裝單元，其堆疊於該第一封裝單元上。本實施例屬於平面網格陣列(Land Grid Array，簡稱LGA)的表面安裝(surface-mount)封裝結構。
該第一高分子材料層110位於該封裝結構100的底部，其組成材質可以是環氧樹脂材料，尤指是具低充填劑含量的環氧樹脂材料，其中所述充填劑可包括二氧化矽(SiO2)或氧化鋁(Al2O3)兩者之一，且所述低含量係指其含量介於5wt%至20wt%。該電路元件130可以是電子元件或半導體晶粒(die)，其係以積體電路製程技術施加於半導體晶圓，並加以切割成晶粒及接上作為連接端131的外接腳墊(或稱為接腳(pin)或墊片(pad))，例如，特殊應用積體電路(Application-Specific Integrated Circuit，簡稱ASIC)或應用處理器(Application Processor，簡稱AP)。該第二高分子材料層120設置於該電路元件130與該第一高分子材料層110之間，其組成材質可以是環氧樹脂材料，尤指是具低充填劑含量的環氧樹脂材料，其中所述充填劑可包括二氧化矽或氧化鋁兩者之一，且所述低含量係指其含量介於5wt%至20wt%。如第1圖所示，該電路元件130的連接端131朝上擺設(也就是該等連接端131設置於該電路元件130的上表面上)，並將該第二高分子材料層120形成該 電路元件130的下表面上，再將該電路元件130黏貼於該第一高分子材料層110上，使得該第二高分子材料層120的下表面貼合該第一高分子材料層110的上表面。該第二高分子材料層120可以是與該第一高分子材料層110相同或不同的組成材質，本發明對此不加以限制。由於該第一高分子材料層110與該第二高分子材料層120的組成皆為高分子材料，因此二者之間具有良好的結合性。由於該第二高分子材料層120形成該電路元件130的全部下表面上，因此該第二高分子材料層120的上表面面積等於該電路元件130的下表面面積；此外，該第二高分子材料層120的表面面積小於該第一高分子材料層110的表面面積。
該第一高充填劑含量介電材料層140可藉由封裝膠體的鑄模技術來製作，例如，壓縮鑄模法(Compression molding)，其包覆該電路元件130、該第二高分子材料層120及該第一高分子材料層110，藉以形成第一封裝單元。該第一高充填劑含量介電材料層140的組成材質可以是鑄模化合物(Molding compound)材質，例如，酚醛基樹脂(Novolac-based resin)、環氧基樹脂(Epoxy-based resin)、矽基樹脂(Silicone-based resin)等的鑄模化合物，其中所述充填劑可包括二氧化矽或氧化鋁兩者之一，且所述高含量係指其含量介於70wt%至90wt%；其中，環氧基樹脂(Epoxy-based resin)之環氧樹脂鑄模化合物(Epoxy Molding Compound，簡稱EMC)最為常用。以可商業獲得的環氧樹脂鑄模化合物為例，其主要成分重量百分率為：環氧樹脂12-15wt%、硬化劑(Novolac Resin)8-10wt%、及充填劑(Silica filler)70-90wt%，其中所添加的無機粉體充填劑係用以降低封裝材料的介電常數和介電損失係數；尤其，在晶片封裝用的鑄模化合物中，充填劑含量通常高達70-90wt%甚至更多。
該第一導電通道160係形成於該第一高充填劑含量介電材料層140內及該電路元件130的該等連接端131上，用以將該電路元件130電性連接至該第一封裝單元的外部。該第一導電線路150形成於該第一封裝單元上，且藉由該第一導電通道160，該電路元 件130的該等連接端131可連接至該第一導電線路150。該第一導電線路150可以是該封裝結構100的線路層或重佈線層(RDL)。該第二高充填劑含量介電材料層170可藉由類似該第一高充填劑含量介電材料層140的製作方式，形成於該第一高充填劑含量介電材料層140上並包覆該第一導電線路150，藉以形成第二封裝單元。該第二高充填劑含量介電材料層170的組成材質亦可以是鑄模化合物材質，例如，酚醛基樹脂、環氧基樹脂、矽基樹脂等的鑄模化合物，其中所述充填劑可包括二氧化矽或氧化鋁兩者之一，且所述高含量係指其含量介於70wt%至90wt%，且該第二高充填劑含量介電材料層170可以是與該第一高充填劑含量介電材料層140相同或不同的組成材質，本發明對此不加以限制。此外，該第二導電通道180係形成於該第二高充填劑含量介電材料層170內及該第一導電線路150上，用以將該電路元件130電性連接至該第二封裝單元外側的一外部電路。在本實施例中，該第二導電通道180為金屬柱狀物，例如銅柱，但本發明對此不加以限制。
第2圖為根據本發明第二實施例的封裝結構200之剖面示意圖。該封裝結構200與第1圖的封裝結構100相當類似，其差異處在於：該第二導電通道280為金屬錐狀物，且該封裝結構200進一步包括：形成於該第二高充填劑含量介電材料層170上的第二導電線路292、包覆該第二導電線路292及該第二高充填劑含量介電材料層170的保護層294、形成於該保護層294內的第三導電通道296、以及形成於該第三導電通道296上的導電錫球290。該保護層294可作為該封裝結構200的外側保護層，用以保護該封裝結構200免於受到來自外部環境或後續製程(例如，焊接)的可能傷害。本實施例屬於球閘陣列(Ball Grid Array，簡稱BGA)的封裝結構，該電路元件130可藉由該第一導電通道160、該第一導電線路150、該第二導電通道280、該第二導電線路292、該第三導電通道296及該導電錫球290，電性連接至該封裝結構200外側的外部電路。
以下將說明本發明第一實施例之封裝結構100的製作方法及 程序。請先留意，在本實施例中，該封裝結構100的製作係建構於所謂的「面板等級」或「晶圓等級」封裝製程；也就是說，眾多的封裝結構100以類似矩陣方式排列於一大片的原始基板以及承載板上，使得相同的製程可同時製作該等眾多的封裝結構100，直到整個製作程序完成後，再以切割方式分成各自獨立且如第1圖所示的封裝結構100。由於該等封裝結構100的製作程序都是在同一片面板等級或晶圓等級的基板上進行，因此稱之為「面板等級」或「晶圓等級」的封裝製程。例如，第3圖為一片面板300上同時安排900個封裝結構100的平面示意圖；其中，75個封裝結構100以15×5之矩陣排列而形成一次面板(sub-panel)201，且12個次面板201以2×6之矩陣而排列於整個面板300上。以下請參照第4圖~第9圖及第1圖(以第一實施例的封裝結構100為例)，其分別對應上述第一實施例封裝結構100各個製程步驟的封裝結構之剖面圖。
首先，如第4圖所示，提供一承載板101及複數個電路元件130。該承載板101為「面板等級」或「晶圓等級」的導電基板，例如，金屬基板或是表面鍍有金屬層的介電材質基板，用以承載或支持該封裝結構100的後續製程，例如，製作該封裝結構100的導電線路。上述基板的金屬成分包含鐵(Fe)、銅(Cu)、鎳(Ni)、錫(Sn)、鋁(Al)、鎳/金(Ni/Au)及其組合或合金，但本發明不以此為限。該等電路元件130可以是電子元件或半導體晶粒，其係以積體電路製程技術施加於半導體晶圓，並加以切割成晶粒及接上作為連接端131的外接腳墊，例如，特殊應用積體電路或應用處理器。該等電路元件130的連接端131朝下擺設(也就是該等連接端131設置於該等電路元件130的下表面)。
接著，可藉由壓合或塗佈(coating)技術，形成一第一高分子材料層110於該承載板101上，使得該第一高分子材料層110覆蓋該承載板101全部的上表面，並對該第一高分子材料層110進行烘烤，以使該第一高分子材料層110固定於該承載板101上。另一方面，可藉由壓合、塗佈或印刷技術，形成一第二高分子材料 層120於該等電路元件130的上表面上，使得該第二高分子材料層120覆蓋各個該等電路元件130全部的上表面，並對該第二高分子材料層120進行烘烤，以使該第二高分子材料層120層固定於該等電路元件130上。該第一高分子材料層110的組成材質可以是環氧樹脂材料，尤指是具低充填劑含量環氧樹脂材料，其中所述充填劑可包括二氧化矽或氧化鋁兩者之一，且所述低含量係指其含量介於5wt%至20wt%。該第二高分子材料層120的組成材質可以是環氧樹脂材料，尤指是具低充填劑含量環氧樹脂材料，其中所述充填劑可包括二氧化矽或氧化鋁兩者之一，且所述低含量係指其含量介於5wt%至20wt%。該第二高分子材料層120可以選用與該第一高分子材料層110相同或不同的組成材質，本發明對此不加以限制。
接著，如第5圖所示，將該等電路元件130上下翻轉而使該第二高分子材料層120位於該等電路元件130的下側後，將該等電路元件130放置於該承載板101上，使得該等電路元件130下側的該第二高分子材料層120完全貼合或黏貼於該承載板101上的該第一高分子材料層110。由於該第一高分子材料層110與該第二高分子材料層120的組成皆為高分子材料，因此二者之間具有良好的結合性，藉以改善後續封裝膠體的高壓鑄模製程可能發生該等電路元件130的位置偏移的問題。由於該第一高分子材料層110形成該承載板101的整個表面上，該第二高分子材料層120形成該電路元件130的整個表面上，因此該第一高分子材料層110的表面面積等於該承載板101的表面面積，該第二高分子材料層120的表面面積等於該電路元件130的表面面積。此處，該第二高分子材料層120的表面面積當然小於該第一高分子材料層110的表面面積。
接著，如第6圖所示，可藉由封裝膠體的鑄模技術，例如壓縮鑄模法，形成一第一高充填劑含量介電材料層140於該承載板上，使其包覆該等電路元件130並覆蓋該第一高分子材料層110，且該第一高充填劑含量介電材料層140、該電路元件130及該第二 高分子材料層120可組成第一封裝單元。該第一高充填劑含量介電材料層140的組成材質可以是鑄模化合物材質，例如，酚醛基樹脂、環氧基樹脂、矽基樹脂等的鑄模化合物；其中，環氧基樹脂之環氧樹脂鑄模化合物(EMC)最為常用，其中所述充填劑可包括二氧化矽或氧化鋁兩者之一，且所述高含量係指其含量介於70wt%至90wt%。以可商業獲得的環氧樹脂鑄模化合物為例，其主要成分重量百分率為：環氧樹脂12-15wt%、硬化劑8-10wt%、及充填劑70-90wt%，其中所添加的無機粉體充填劑係用以降低封裝材料的介電常數和介電損失係數；尤其，在晶片封裝用的鑄模化合物中，充填劑含量通常高達70-90wt%甚至更多。
接著，可藉由雷射鑽孔(Laser drilling)技術於該第一高充填劑含量介電材料層140內及該等電路元件130的連接端131上形成貫孔，並利用電鍍(Electrolytic plating)技術充填導電材料於該貫孔中，以形成第一導電通道160，如第7圖所示，用以將該電路元件130電性連接至該第一封裝單元的外部。接著，可藉由光微影(Photolithography)及電鍍技術，形成一圖案化的細線路間距(fine-pitch)之金屬層於該第一高充填劑含量介電材料層140上，以形成第一導電線路150，如第8圖所示。藉由該第一導電通道160，該電路元件130可連接至該第一導電線路150。
接著，如第9圖所示，藉由類似該第一高充填劑含量介電材料層140的製作技術，可形成第二高充填劑含量介電材料層170於該第一高充填劑含量介電材料層140上並包覆該第一導電線路150，藉以形成第二封裝單元。此外，再藉由類似該第一導電通道160的製作技術，可形成第二導電通道180係形成於該第二高充填劑含量介電材料層170內及該第一導電線路150上，用以將該電路元件130電性連接至該第二封裝單元外側的外部電路。在本實施例中，該第二導電通道180為金屬柱狀物，例如銅柱，但本發明對此不加以限制。該第二高充填劑含量介電材料層170的組成材質亦可以是鑄模化合物材質，例如，酚醛基樹脂、環氧基樹脂、矽基樹脂等的鑄模化合物，且該第二高充填劑含量介電材料層170 可以是與該第一高充填劑含量介電材料層140相同或不同的組成材質，本發明對此不加以限制。
接著，移除該承載板101而得到一包括該等電路元件130的封裝結構半成品102，並分割該封裝結構半成品102而得到複數個如第1圖所示的封裝結構100，使得該等封裝結構100各具有該等電路元件130的其中一者。
唯以上所述者，僅為本發明之較佳實施例，當不能以之限制本發明的範圍。即大凡依本發明申請專利範圍所做之均等變化及修飾，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍，故都應視為本發明的進一步實施狀況。

Claims (10)

  1. 一種封裝結構，其包括：一第一高分子材料層，具有一第一表面；一第二高分子材料層，具有一第二表面，形成於該一第一高分子材料層上；一電路元件，具有一第三表面及一相對該第三表面的第四表面，該電路元件設置於該第二高分子材料層上並具有一連接端於該第四表面上；一第一高充填劑含量介電材料層，包覆該電路元件及該第二高分子材料層，並覆蓋該第一高分子材料層；一第一導電線路，形成於該第一高充填劑含量介電材料層上；一第一導電通道，形成於該第一高充填劑含量介電材料層內，用以連接該第一導電線路與該連接端；一第二高充填劑含量介電材料層，包覆該第一導電線路，並覆蓋該第一高充填劑含量介電材料層；以及一第二導電通道，形成於該第二高充填劑含量介電材料層內，用以連接該第一導電線路與一外部電路；其中，該第一表面的面積大於該第二表面的面積，且該第三表面的面積等於該第二表面的面積。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該第一高分子材料層包含環氧樹脂材料，該第二高分子材料層包含環氧樹脂材料。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該第一高充填劑含量介電材料層包含一第一鑄模化合物，該第二高充填劑含量介電材料層包含一第二鑄模化合物。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該電路元件為半導體晶粒或電子元件。
  5. 如申請專利範圍第1項所述之封裝結構，進一步包含：一第二導電線路，形成於該第二導電通道上及該第二高充填劑含量介電材料層上； 一保護層，包覆該第二導電線路，並覆蓋該第二高充填劑含量介電材料層；以及一第三導電通道，形成於該保護層內，用以連接該第二導電線路與一外部電路。
  6. 如申請專利範圍第5項所述之封裝結構，其中，該第二導電通道為金屬柱狀物。
  7. 一種封裝結構之製作方法，其步驟包含：(A)提供一承載板及複數個電路元件，該承載板具有一第一表面，該等電路元件各具有一第二表面及一相對該第二表面的第三表面，且該等電路元件各具有一連接端於其第三表面上；(B)形成一第一高分子材料層於該承載板上，使得該第一高分子材料層完全覆蓋該承載板的第一表面；(C)形成一第二高分子材料層於各個該等電路元件上，使得該第二高分子材料層完全覆蓋各個該等電路元件的第二表面；(D)將該等電路元件放置於該承載板上，使得該第二高分子材料層貼合該第一高分子材料層；(E)形成一第一高充填劑含量介電材料層於該承載板上，使其包覆該電路元件；(F)形成一第一導電通道於該第一高充填劑含量介電材料層內，並形成一第一導電線路於該第一導電通道上，使得該第一導電通道連接該第一導電線路與該連接端；(G)形成一第二高充填劑含量介電材料層於該第一高充填劑含量介電材料層上，使其包覆該第一導電線路，並覆蓋該第一高充填劑含量介電材料層；(H)形成一第二導電通道於該第二高充填劑含量介電材料層內，使得該第一導電通道連接至該第一導電線路；(I)移除該承載板而得到一包括該等電路元件的封裝結構半成品；以及(J)分割該封裝結構半成品而得到複數個封裝結構，使得該等封裝結構各具有該等電路元件的其中一者。
  8. 如申請專利範圍第7項所述之製作方法，其步驟(B)中，該第一高分子材料層係以壓合或塗佈方式形成，並對該第一高分子材料層進行烘烤。
  9. 申請專利範圍第7項所述之製作方法，其步驟(C)中，該第二高分子材料層係以壓合、塗佈或印刷方式形成，並對該第二高分子材料層進行烘烤。
  10. 如申請專利範圍第7項所述之製作方法，其步驟(F)中，該第一導電通道的形成方式包含：以雷射鑽孔方式於該第一高充填劑含量介電材料層內及該電路元件的該連接端上形成一貫孔；以及以電鍍方式充填導電材料於該貫孔中。
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US10304750B2 (en) 2019-05-28
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