TW201911391A - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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Publication number
TW201911391A
TW201911391A TW106139482A TW106139482A TW201911391A TW 201911391 A TW201911391 A TW 201911391A TW 106139482 A TW106139482 A TW 106139482A TW 106139482 A TW106139482 A TW 106139482A TW 201911391 A TW201911391 A TW 201911391A
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Taiwan
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layer
oxide layer
layers
silicon
hafnium
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TW106139482A
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English (en)
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沙哈吉Ｂ 摩爾
潘正揚
王俊傑
張世杰
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台灣積體電路製造股份有限公司
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Publication of TW201911391A publication Critical patent/TW201911391A/zh

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    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract

根據一些實施例，本發明提供一種半導體裝置的形成方法，包括：形成電晶體的閘極堆疊。閘極堆疊的形成包括：形成氧化矽層於半導體區上；沉積氧化鉿層於氧化矽層上方；沉積氧化鑭層於氧化鉿層上方；及沉積功函數層於氧化鑭層上方。形成源極/汲極區於閘極堆疊的相反側。

Description

半導體裝置的形成方法
本發明實施例係關於一種半導體裝置的形成方法。
金屬氧化物半導體(Metal-Oxide-Semiconductor,MOS)裝置係積體電路中的基本構建元件。現有的金屬氧化物半導體(MOS)裝置通常具有由摻雜有p型或n型摻質的多晶矽所形成之閘極電極，其係使用諸如離子植入或熱擴散之摻雜操作所形成。可將閘極電極的功函數調整為矽的帶邊(band-edge)。對於n型金屬氧化物半導體(NMOS)裝置，可將功函數調整為接近矽的導帶(conduction band)。對於p型金屬氧化物半導體(PMOS)裝置，可將功函數調整為接近矽的價帶(valence band)。藉由選擇合適的摻質可達到調整多晶矽閘極電極的功函數之功效。
具有多晶矽閘極電極之金屬氧化物半導體(MOS)裝置展現載子空乏效應(carrier depletion effect)，其亦稱為多晶矽空乏效應(poly depletion effect)。當所施加的電場從接近閘極介電質的閘極區掃除載子時，發生多晶矽空乏效應而形成空乏層。在n摻雜多晶矽層中，空乏層包括離子化非移動供體位點(ionized non-mobile donor sites)，其中在p摻雜多晶矽層 中，空乏層包括離子化非移動受體位點(ionized non-mobile acceptor sites)。空乏效應導致有效閘極介電質的厚度增加，使得在半導體的表面上產生反轉層更加困難。
多晶矽空乏問題可藉由形成金屬閘極電極來解決，其中在NMOS裝置和PMOS裝置中所使用的金屬閘極亦可具有帶邊功能。因此，所得之金屬閘極包括複數層以滿足NMOS裝置和PMOS裝置的要求。
根據一些實施例，本發明提供一種半導體裝置的形成方法，包括：形成電晶體的閘極堆疊。閘極堆疊的形成包括：形成氧化矽層於半導體區上；沉積氧化鉿層於氧化矽層上方；沉積氧化鑭層於氧化鉿層上方；及沉積功函數層於氧化鑭層上方。形成源極/汲極區於閘極堆疊的相反側。
根據一些實施例，本發明提供一種半導體裝置的形成方法，包括：分別形成具有第一部分和第二部分的氧化矽層於第一半導體區和第二半導體區上方；分別沉積具有第一部分和第二部分的第一氧化鉿層於氧化矽層的第一部分和第二部分上方；分別沉積具有第一部分和第二部分的氧化鑭層於第一氧化鉿層的第一部分和第二部分上方；移除氧化鑭層的第二部分及第一氧化鉿層的第二部分；沉積第二氧化鉿層於氧化矽層的第二部分上方；及分別沉積第一功函數層於氧化鑭層的第一部分上方，並沉積第二功函數層於第二氧化鉿層上方。
根據一些實施例，本發明提供一種半導體裝置，包括：包含閘極堆疊的電晶體，閘極堆疊更包括：位於半導體 區上的氧化矽層；位於氧化矽層上方的氧化鉿層；位於氧化鉿層上方的氧化鑭層；及位於氧化鑭層上方的功函數層。源極/汲極區係位於閘極堆疊的一側。
10‧‧‧晶圓
20‧‧‧基底
22‧‧‧淺溝槽隔離區(STI)
22A‧‧‧頂表面
46‧‧‧層間介電質(ILD)
61‧‧‧箭頭
62‧‧‧光阻
66‧‧‧蓋層
84‧‧‧蝕刻停止層
86‧‧‧層間介電質(ILD)
92‧‧‧阻障層
94‧‧‧含金屬材料
100‧‧‧裝置區
122A‧‧‧頂表面
124‧‧‧半導體條
124'‧‧‧鰭
130‧‧‧虛設閘極堆疊
132‧‧‧虛設閘極介電質
134‧‧‧虛設閘極電極
136‧‧‧硬罩幕層
138‧‧‧閘極間隔物
138A‧‧‧第一介電層
138B‧‧‧第二介電層
140‧‧‧凹槽
142‧‧‧磊晶區
147‧‧‧接觸蝕刻停止層(CESL)
148‧‧‧開口
150‧‧‧替代閘極堆疊
154‧‧‧界面層(IL)
156‧‧‧矽酸鉿層
157‧‧‧氧化鉿層
158‧‧‧氧化鑭層
159‧‧‧氧化鑭矽層
160‧‧‧罩幕層
165‧‧‧導電黏合層
168‧‧‧含金屬導電層
170‧‧‧金屬區
172‧‧‧硬罩幕
174‧‧‧源極/汲極矽化物區
176‧‧‧金屬層
178‧‧‧金屬氮化物層
180‧‧‧金屬區
182‧‧‧源極/汲極接觸插塞
183‧‧‧電晶體
188‧‧‧插塞/通孔
190‧‧‧插塞/通孔
200‧‧‧裝置區
222A‧‧‧頂表面
224‧‧‧半導體條
224'‧‧‧鰭
230‧‧‧虛設閘極堆疊
232‧‧‧閘極介電質
234‧‧‧虛設閘極電極
236‧‧‧硬罩幕層
238‧‧‧閘極間隔物
238A‧‧‧層
238B‧‧‧層
240‧‧‧凹槽
242‧‧‧磊晶區
247‧‧‧接觸蝕刻停止層(CESL)
248‧‧‧開口
250‧‧‧替代閘極堆疊
254‧‧‧界面層(IL)
256‧‧‧矽酸鉿層
257‧‧‧氧化鉿層
258‧‧‧氧化鑭層
259‧‧‧氧化鑭矽層
260‧‧‧罩幕層
264‧‧‧氧化鉿層(高介電常數介電層)
265‧‧‧導電黏合層
268‧‧‧含金屬導電層
270‧‧‧金屬區
272‧‧‧硬罩幕
274‧‧‧源極/汲極矽化物區
276‧‧‧金屬層
278‧‧‧金屬氮化物層
280‧‧‧金屬區
282‧‧‧源極/汲極接觸插塞
283‧‧‧電晶體
288‧‧‧插塞/通孔
290‧‧‧插塞/通孔
A-A‧‧‧線
B-B‧‧‧線
300‧‧‧流程圖
302‧‧‧步驟
304‧‧‧步驟
306‧‧‧步驟
310‧‧‧步驟
312‧‧‧步驟
314‧‧‧步驟
316‧‧‧步驟
318‧‧‧步驟
320‧‧‧步驟
402‧‧‧線
404‧‧‧線
406‧‧‧線
408‧‧‧線
410‧‧‧線
以下將配合所附圖式詳述本發明之實施例，應注意的是，依照工業上的標準實施，以下圖示並未按照比例繪製，事實上，可能任意的放大或縮小元件的尺寸以便清楚表現出本發明的特徵。而在說明書及圖式中，除了特別說明外，同樣或類似的元件將以類似的符號表示。
第1圖至第21圖顯示根據一些實施例，形成鰭式場效電晶體(FinFET)之中間階段的剖面圖及透視圖。
第22圖顯示根據一些實施例，替代閘極堆疊的堆疊層中一些元件的擴散分佈。
第23圖顯示根據一些實施例，形成鰭式場效電晶體(FinFET)之流程圖。
應當理解，以下提供許多不同的實施方法或是例子來實行各種實施例之不同特徵。以下描述具體的元件及其排列的例子以闡述本發明。當然這些僅是例子且不該以此限定本發明的範圍。例如，元件的尺寸並不限定於所揭露的範圍或數值，而是取決於製程條件及/或裝置所期望的性質。此外，在描述中提及第一個元件形成於第二個元件上時，其可以包括第一個元件與第二個元件直接接觸的實施例，也可以包括有其他元件形成於第一個與第二個元件之間的實施例，其中第一個元 件與第二個元件並未直接接觸。為簡化及清楚起見，各種特徵可任意繪製成不同尺寸。
此外，其中可能用到與空間相關的用詞，像是“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖示中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
根據各種示例性實施例，本發明提供電晶體及其形成方法。根據一些實施例，本發明繪示出形成電晶體的中間階段，並討論一些實施例的一些變化。在各種視圖和說明性實施例中，相同的附圖標記用於表示相同的元件。在所示的示例性實施例中，將鰭式場效電晶體(Fin Field-Effect Transistors,FinFET)的形成作為範例來解釋本發明的概念。平面電晶體亦可採用本發明的概念。
第1圖至第21圖繪示在本發明一些實施例中，形成電晶體(其可為例如鰭式場效電晶體(FinFET))之中間階段的剖面圖及透視圖。第1圖至第21圖所示的步驟亦用圖表反映在第23圖所示之流程圖300中。形成的電晶體包括位於裝置區100中的第一電晶體和位於裝置區200中的第二電晶體。形成於裝置區100中的電晶體可為n型電晶體，例如：n型平面電晶體或n型鰭式場效電晶體(FinFET)。根據一些實施例，形成於裝置區200中的電晶體可為p型電晶體，例如：p型平面電晶體或p 型鰭式場效電晶體(FinFET)。根據替代實施例，形成於裝置區200中的電晶體為n型電晶體，其具有與形成於裝置區100的電晶體不同的規格。舉例而言，形成在裝置區200中的電晶體的閾值電壓可以高於形成在裝置區100中的電晶體的閾值電壓。
第1圖繪示初始結構的透視圖。初始結構包括晶圓10，其更包括基底20。基底20可為半導體基底，其可為矽基底、矽鍺基底或由其它半導體材料所形成的基底。根據一些實施例，基底20包括塊狀矽基底以及塊狀矽基底上方之磊晶矽鍺(SiGe)層或鍺層(其中不含矽)。基底20可摻雜有p型或n型雜質。可形成諸如淺溝槽隔離(Shallow Trench Isolation,STI)區的隔離區22並延伸至基底20之中。相鄰淺溝槽隔離區(STI)22之間的基底20之部分被稱為半導體條124及224，其分別位於裝置區100及200之中。
淺溝槽隔離區(STI)22可包括襯層氧化物(未示出)。可藉由熱氧化物形成襯層氧化物，熱氧化物係透過基底20之表層的熱氧化所形成。襯層氧化物亦可為使用以下方法所形成之沉積氧化矽層，例如：原子層沉積(Atomic Layer Deposition,ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition,HDPCVD)或化學氣相沉積(Chemical Vapor Deposition,CVD)。淺溝槽隔離區(STI)22還可包括在襯層氧化物上方的介電材料，其中可使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、旋轉塗佈等方法形成介電材料。
請參照第2圖，淺溝槽隔離區(STI)22係凹陷的，使得半導體條124和224的頂部突出並高於相鄰淺溝槽隔離區(STI)22的頂表面22A，以形成突出鰭124'和224'。相應的步驟於第23圖所示之流程中顯示為步驟302。可使用乾蝕刻製程來實行蝕刻，其中使用NH3和NF3作為蝕刻氣體。在蝕刻製程中，可能產生電漿，也可能包括氬氣。根據本發明的替代實施例，使用濕蝕刻製程實行淺溝槽隔離區(STI)22的凹陷。蝕刻化學品可包括例如稀釋的HF。
請參照第3圖，虛設閘極堆疊130和230分別形成在突出鰭124'和224'之頂表面和側壁上。相應的步驟於第23圖所示之流程中顯示為步驟304。虛設閘極堆疊130可包括虛設閘極介電質132及位於虛設閘極介電質132上方之虛設閘極電極134。虛設閘極堆疊230可包括虛設閘極介電質232及位於虛設閘極介電質232上方之虛設閘極電極234。可使用例如多晶矽以形成虛設閘極電極134和234，亦可使用其他材料。每個虛設閘極堆疊130和230亦可包括一個(或複數個)硬罩幕層136和236。硬罩幕層136和236可由氮化矽、碳氮化矽等所形成。每個虛設閘極堆疊130和230分別跨越單個或複數個突出鰭124'和224'。虛設閘極堆疊130和230還可具有縱向方向，其分別垂直於相應的突出鰭124'和224'之縱向方向。
接著，閘極間隔物138和238分別形成在虛設閘極疊層130和230的側壁上。同時，鰭間隔物(未示出)亦可以形成在突出鰭124'和224'的側壁上。根據本發明的一些實施例，閘極間隔物138和238係由介電材料所形成，例如矽碳氮氧化物 (SiCON)、氮化矽等，並且可具有單層結構或包括複數個介電層的多層結構。
根據一些實施例，每個閘極間隔物138包括第一介電層138A和第二介電層138B(參見第7圖)，其中層138A和138B的每一層係透過毯覆沉積步驟(blanket deposition step)接著進行各向異性蝕刻步驟所形成。根據一些實施例，介電層138A為低介電常數(low-k)介電層，且介電層138B為非低介電常數(non-low-k)介電層。介電層138A可由介電常數值(k value)低於約3.0的低介電常數(low-k)介電材料所形成，其可以由SiON或SiOCN所形成，其中形成有孔洞以將其介電常數值降低至期望的低介電常數(low-k)值。介電層138B可由例如氮化矽所形成。閘極間隔物238具有與閘極間隔物138相同的結構，且閘極間隔物238可包括分別由與層138A和138B相同的材料所形成之層238A和238B。根據其它實施例，介電層138A為非低介電常數(non-low-k)介電層，而介電層138B為低介電常數(low-k)介電層，且相應的低介電常數(low-k)介電材料和非低介電常數(non-low-k)介電材料可相似於如上所述之材料。
接著，實行蝕刻步驟(以下稱為源極/汲極凹陷)以蝕刻未被虛設閘極堆疊130和230以及閘極間隔物138和238所覆蓋之突出鰭124'和224'的部分，從而形成第4圖所示之結構。凹陷可為各向異性的，且因此位於相應的虛設閘極堆疊130/230和閘極間隔物138/238正下方的鰭124'和224'的部分被保護且不被蝕刻。根據一些實施例，凹陷的半導體條124和224 的頂表面可低於相鄰淺溝槽隔離區(STI)22的頂表面。凹槽140和240從而形成在淺溝槽隔離區(STI)22之間。可在普通的蝕刻製程或個別的製程中實行裝置區100和200中的凹陷，且凹槽140的深度可等於或不同於凹槽240的深度。
接下來，藉由在凹槽140和240中同時(或分別地)選擇性地生長半導體材料以形成磊晶區(源極/汲極區)，從而形成第5圖所示之結構。相應的步驟於第23圖所示之流程中顯示為步驟306。根據一些示例性實施例，磊晶區142係由n型的矽磷(SiP)或矽碳磷(SiCP)所形成。當裝置區200中的相應電晶體為p型電晶體時，磊晶區242可由摻雜有硼的矽鍺(SiGeB)所形成。使用不同的罩幕(未示出)分別實行磊晶區142和242的形成。根據裝置區200中的電晶體也是n型之替代實施例，磊晶區242可由與磊晶區142相同的材料所形成，且與磊晶區142同時形成。根據本發明的替代實施例，磊晶區142和242由III-V族化合物半導體所形成，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合或其多層。在凹槽140和240填充有磊晶半導體材料之後，磊晶區142和242之進一步的磊晶生長導致磊晶區142和242水平擴展，且可形成刻面(facets)。磊晶區142和242形成相應電晶體的源/汲極區。如第23圖所示，在步驟308中，可對第一磊晶源極/汲極區實行後磊晶佈植(after-epi implantation)。
第6圖繪示用於形成接觸蝕刻停止層(Contact Etch Stop Layers,CESL)147和247以及層間介電質(Inter-Layer Dielectric,ILD)46的透視圖。相應的步驟於第23圖所示之流 程中顯示為步驟310。根據本發明一些實施例，接觸蝕刻停止層(CESL)147和247係由氮化矽或碳氮化矽等所形成。舉例而言，可使用諸如原子層沉積(ALD)或化學氣相沉積(CVD)之共形的沉積方法形成接觸蝕刻停止層(CESL)147和247。層間介電質(ILD)46形成於接觸蝕刻停止層(CESL)147和247上方，且可使用例如流動化學氣相沉積(FCVD)、旋轉塗佈、化學氣相沉積(CVD)等方法形成層間介電質(ILD)46。層間介電質(ILD)46可由磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、硼摻雜的磷酸矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)或四乙基正矽酸鹽(Tetra Ethyl Ortho Silicate,TEOS)氧化物等所形成。可實行化學機械研磨(Chemical Mechanical Polish,CMP)以使層間介電質(ILD)46、虛設閘極堆疊130和230以及閘極間隔物138和238的頂表面彼此齊平。
第7圖繪示第6圖所示之結構的剖面圖，該剖面圖係從第6圖中包含線A-A的垂直平面和包含線B-B的垂直平面所獲得。在形成如第6及7圖所示的結構之後，以金屬閘極和替代閘極介電質取代包括硬罩幕層136和236、虛設閘極電極134和234以及虛設閘極介電質132和232之虛設閘極堆疊130和230。第6、7及8至21圖繪示淺溝槽隔離區(STI)22的頂表面122A和222A，且突出鰭124'和224'分別突出並高於頂表面122A和222A。
為了形成替代閘極，透過蝕刻移除如第6及7圖所示之硬罩幕層136和236、虛設閘極電極134和234以及虛設閘極 介電質132和232，形成如第8圖所示之開口148和248。相應的步驟於第23圖所示之流程中顯示為步驟312。突出鰭124'和224'的頂表面和側壁分別暴露於開口148和248。
接下來，請參照第9圖，在裝置區100和200中皆形成複數層，其中複數層中的每一層延伸至開口148和248之中，且裝置區100和200中相應的層(例如層154和254)在相同的製程中形成。相應的步驟於第23圖所示之流程中顯示為步驟314。根據本發明一些實施例，界面層(Interfacial Layers,IL)154和254分別形成於突出鰭124'和224'之暴露的表面上。每個界面層(IL)154和254可包括諸如氧化矽層之氧化層，其係透過突出鰭124'和224'之表層的熱氧化、化學氧化製程或沉積製程所形成。
使用諸如原子層沉積(ALD)或化學氣相沉積(CVD)之共形的沉積方法形成複數層156、256、157、257、158、258、159、259、160及260，故這些層中每一層的水平部分和垂直部分具有大抵上相同的厚度，例如具有小於10%的差異。根據本發明一些實施例，矽酸鉿層156和256沉積在界面層(IL)154和254上並與界面層(IL)154和254接觸。氧化鉿矽(HfSiO)層156和256可包括氧化鉿及氧化矽的化合物(混合物)。此外，鉿的原子百分比明顯低於矽的原子百分比。根據一些實施例，矽酸鉿層156和256中的鉿原子百分比低於約5%，且可為約1%至5%之間。因此，矽酸鉿層156和256主要包括氧化矽和少量氧化鉿，故被認為是界面層(IL)。由於矽酸鉿層156的鉿原子百分比低，故其可為低介電常數介電層。降低矽 酸鉿層156中的鉿原子百分比可產生改善的界面(IL/HK)品質。矽酸鉿層156和256的厚度很小，且可為約0.5nm至約3.0nm之間。根據本發明的替代實施例，由於沒有形成矽酸鉿層156和256，故覆於上方的氧化鉿層157和257分別與界面層(IL)154和254接觸。
矽酸鉿層156和256可包括HfO2和SiO2的組合，且矽酸鉿層中HfO2的百分比會影響相應的鉿百分比。矽酸鉿層156和256可以包括HfSiO4及額外的含矽分子。形成方法可包括化學氣相沉積(CVD)或原子層沉積(ALD)。根據本發明一些實施例，藉由使用原子層沉積(ALD)交替地沉積HfO2層和SiO2層以形成矽酸鉿層156和256。HfO2層和SiO2層非常薄，例如薄至一個原子層或幾個原子層。此外，可藉由調整HfO2層的厚度與SiO2層的厚度之比例來調整Hf原子百分比。用於形成HfO2層的前驅物可包括HfCl4、H2O(或O3)，其中包括諸如Ar的載體氣體。用於形成SiO2的前驅物可包括含矽前驅物及作為氧化劑的H2O(或O3)。含矽前驅物可包括矽烷、SiH[N(CH3)2]4或SiH[N(C2H5)2]3。根據另一替代實施例，前驅物可包括液體Hf[N(CH3)(C2H5)]4、SiH[N(CH3)2]和O3。當使用原子層沉積(ALD)時，沖洗氣體可選自於由氮、氦、氬及其組合所組成的群組。此外，氧化劑氣體可選自於由氧化氮、氧、臭氧、一氧化二氮、水蒸汽及其組合所組成的群組。
氧化鉿(HfO2)層157和257分別沉積在矽酸鉿層156和256上方，且可分別與矽酸鉿層156和256接觸。當未形成矽酸鉿層156和256時，氧化鉿層157和257亦可分別與界面層 (IL)154和254接觸。氧化鉿層157和257大抵上不含矽。
接下來，根據一些實施例，可為La2O3的氧化鑭(LaO)層158和258可分別形成於氧化鉿層157和257上方。根據一些實施例，氧化鑭層158和258分別與氧化鉿層157和257接觸。氧化鑭層158和258的厚度可為約0.5nm至約3.0nm之間。氧化鑭層158和258可大抵上不含矽。
根據本發明一些實施例，氧化鑭矽(LaSiO)層159和259分別沉積在氧化鑭層158和258上方並分別與氧化鑭層158和258接觸。氧化鑭矽(LaSiO)層159和259可包括氧化鑭及氧化矽的化合物(混合物)。根據本發明一些實施例，氧化鑭矽(LaSiO)層159和259中的矽原子百分比低於約10%，且可為約2%至6%之間。氧化鑭矽(LaSiO)層159和259的厚度很小，且可為約0.5nm至約3.0nm之間。根據本發明的替代實施例，由於沒有形成氧化鑭矽(LaSiO)層159和259，故覆於上方的罩幕層160和260分別與氧化鑭層158和258接觸。
接著，在裝置區100和200中形成硬罩幕層160和260。根據一些實施例，硬罩幕層160和260係由氮化鈦或氮化硼等所形成。如箭頭61所示，在形成硬罩幕層160和260之後，可實行退火。退火可為閃退火(flash anneal)或爐退火，其可在約550℃至約700℃的溫度下實行。
接下來，請參照第10圖，形成光阻62並將其圖案化，且剩餘的光阻62覆蓋硬罩幕層160，而裝置區200中的硬罩幕層260被暴露。接著，使用光阻62作為蝕刻罩幕並蝕刻硬罩幕層260，使得裝置區200中的底層被暴露。接著，移除光阻62， 且所得之結構如第11圖所示。
第12圖繪示使用硬罩幕160作為蝕刻罩幕以從裝置區200移除含鑭層(包括氧化鑭矽(LaSiO)層259和氧化鑭層258)。相應的步驟於第23圖所示之流程中顯示為步驟316。氧化鉿層257也被移除以防止鑭對裝置區200中所得之電晶體造成“污染”。根據本發明一些實施例，從裝置區200移除矽酸鉿層256。根據替代實施例，不移除矽酸鉿層256，且矽酸鉿層256將留在如第21圖所示之所得的電晶體283之層254與265之間。因此，在第12圖中，所繪示之矽酸鉿層256具有虛線邊界表示沉積的矽酸鉿層256可能存在或不存在。在隨後的圖式中，未示出矽酸鉿層256，儘管根據一些實施例可存在矽酸鉿層256。
第13圖繪示高介電常數(high-k)介電層264的形成。相應的步驟於第23圖所示之流程中顯示為步驟318。根據本發明欲形成p型電晶體於裝置區200中之一些實施例，高介電常數(high-k)介電層264由具有高介電常數(high-k)值和高價帶偏移(high valence band offset)之高介電常數(high-k)介電材料所形成。相應的高介電常數(high-k)介電材料可包括氧化鉿、氧化鋁或氧化鋯等。當形成氧化鉿時，氧化鉿層264的鉿原子百分比可高於、低於或等於氧化鉿層157中的鉿原子百分比。此外，氧化鉿層264的厚度可大於、小於或等於氧化鉿層157之相應的厚度。根據欲形成n型電晶體於裝置區200中之其他實施例，高介電常數(high-k)介電層264由具有高介電常數(high-k)值和高導帶偏移(high conduction band offset) 之高介電常數(high-k)介電材料所形成，例如氧化鋁。亦可在形成高介電常數(high-k)介電層264的同時，將高介電常數(high-k)介電層264的材料沉積於裝置區100之中。
接著，移除硬罩幕160。此外，若在形成高介電常數(high-k)介電層264時亦沉積高介電常數(high-k)介電材料於裝置區100之中，則亦從裝置區100中移除高介電常數(high-k)介電材料。結果，在裝置區100中，LaSiO層159或氧化鑭層158(如果未形成LaSiO層159)被暴露，且在裝置區200中，高介電常數(high-k)介電層264被暴露。所得之結構如第14圖所示。
第15圖繪示根據一些實施例，可包括氮化鈦矽(Titanium Silicon Nitride,TSN)之導電黏合層165和265的沉積。如箭頭所示，可實行低溫退火。退火可為閃退火或爐退火，其可在約550℃至約700℃的溫度下實行。
接下來，如第16圖所示，蓋層66形成在裝置區100和200中。根據一些實施例，蓋層66由矽所形成。利用矽蓋層66覆蓋裝置區100中的層，實行高溫退火以使結構和蓋層66下面的層穩定。退火可為在約1000℃至1150℃之間的溫度下所實行之閃退火。在退火之後，移除蓋層66。
請參照第17圖，透過沉積以形成含金屬導電層168和268。相應的步驟於第23圖所示之流程中顯示為步驟320。可以使用諸如原子層沉積(ALD)或化學氣相沉積(CVD)之共形沉積方法進行沉積，使得含金屬層168/268(及每個子層)的水平部分和垂直部分具有大抵上相等的厚度。每個含金屬層 168和268包括至少一層，或者可包括由不同材料所形成之複數層(未示出)。含金屬導電層168和268可分別形成。含金屬層168和268中層的材料可包括根據相應的FinFET是n型FinFET或p型FinFET而選擇的功函數金屬。舉例而言，由於裝置區100中的FinFET為n型FinFET，故含金屬層168(其可包括由不同材料所形成的複數層)可包括氮化鈦(TiN)層、氮化鉭(TaN)層和Al基層(例如由TiAl、TiAlN、TiAlC、TaAlN或TaAlC所形成)。當裝置區200中的FinFET為p型FinFET時，含金屬層268(其可包括由不同材料所形成的複數層)可分別包括TiN層、TaN層及另一個TiN層。接著，將填充金屬填充於層168和268上方以形成金屬區170和270。根據一些示例性實施例，填充金屬包括W、Cu、Co、Al、Ru等或其合金。
接下來，實行諸如化學機械研磨(CMP)或機械研磨之平坦化步驟，以移除在層間介電質(ILD)46頂表面上方之多餘的部分，從而形成替代閘極堆疊150和250。所得之結構如第18圖所示。閘極堆疊150包括界面層(IL)154且可能包括矽酸給層156，其中層154和156皆為界面層(IL)。替代閘極堆疊150中的高介電常數(high-k)介電層包括氧化鉿層157和氧化鑭層158，且可包括或不包括LaSiO層159。閘極堆疊250包括界面層(IL)254，且可包括或不包括矽酸鉿層256(第12圖)，其中層254和256(如果有的話)皆為界面層(IL)。替代閘極堆疊250中的高介電常數(high-k)介電層包括層264，且不包括任何含鑭層。
在閘極堆疊150中，界面層(IL)154具有2.3eV的 導帶偏移，且氧化鉿層157具有1.4eV的導帶偏移。1.4eV與2.3eV之間的顯著差異導致裝置性能的退化。位於界面層(IL)154與氧化鉿層157之間的HfSiO層具有1.8eV的中間導帶偏移，因此矽酸鉿層減輕了1.4eV與2.3eV之間的差異，從而提高裝置性能。LaSiO中的矽具有將鑭原子保持在適當位置的功能，以減少鑭擴散到氮化鈦矽(TSN)層165之中。
接下來，如第19圖所示，使閘極堆疊150和250凹陷以形成凹槽，然後填充介電材料以在凹槽中形成硬罩幕172和272。接著，實行另一個平坦化步驟，以使硬罩幕的頂表面172和272與層間介電質(ILD)46的頂表面齊平。硬罩幕172和272可以為由氮化矽、氮氧化矽、碳氧化矽等所形成之介電硬罩幕。
第20圖繪示源極/汲極矽化物區174和274以及源極/汲極接觸插塞182和282的形成。根據一些實施例，沉積金屬層176和276(例如鈦層)以作為毯覆層，隨後於在金屬層176和276的頂部上實行氮化製程以形成金屬氮化物層178和278。金屬層176和276的底部未被氮化。接下來，實行退火(其可為快速熱退火)以使金屬層176和276與源極/汲極區142和242的頂部反應以形成矽化物區174和274。金屬層176和276在層間介電質(ILD)46側壁上的部分沒有產生反應。接著，例如藉由填充鎢、鈷等以形成金屬區180和280，然後藉由平坦化以移除多餘的材料，從而造成較低的源極/汲極接觸插塞182和282。接觸插塞182包括層176、178和180，且接觸插塞282包括層276、278和280。因此形成FinFET 183和283。
請參照第20圖，形成蝕刻停止層84。根據一些實施例，蝕刻停止層84由SiN、SiCN、SiC、SiOCN或其他介電材料所形成。形成方法可包括電漿輔助化學氣相沈積(PECVD)、原子層沉積(ALD)、化學氣相沉積(CVD)等。接下來，層間介電質(ILD)86形成在蝕刻停止層84上方。層間介電質(ILD)86的材料可選自與用於形成層間介電質(ILD)46之相同的候選材料(和方法)，且層間介電質(ILD)46和86可由相同或不同的介電材料所形成。根據一些實施例，使用電漿輔助化學氣相沈積(PECVD)、可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、旋轉塗佈等形成層間介電質(ILD)86，且層間介電質(ILD)86可包括氧化矽(SiO2)。
蝕刻層間介電質(ILD)86和蝕刻停止層84以形成開口(未示出)。可使用例如反應性離子蝕刻(Reactive Ion Etch,RIE)來實行蝕刻。在隨後的步驟中，如第21圖所示，形成插塞/通孔188、190、288和290。根據本發明一些實施例，插塞/通孔188、190、288和290包括阻障層92及在阻障層上之含金屬材料94。根據本發明一些實施例，插塞/通孔188、190、288和290的形成包括形成毯覆阻障層92及在毯覆阻障層上之含金屬材料94，並實行平坦化以移除毯覆阻障層及含金屬材料的多餘部分。阻障層92可由諸如氮化鈦或氮化鉭之金屬氮化物所形成。含金屬材料94可由鎢、鈷、銅等所形成。
本發明的實施例具有一些有利的特徵。雖然氧化鉿因為其高介電常數值和高價帶偏移而成為用於p型電晶體之良好的高介電常數介電材料，但對於n型電晶體來說並不夠 好，特別是用於形成具有低閾值電壓的n型電晶體。另一方面，氧化鑭由於其高介電常數值(約30)、高帶隙(bandgap)(約6.0eV)和高導帶偏移(約2.3eV)而成為用於n型電晶體之良好的高介電常數介電材料。再者，在相同的有效氧化厚度(effective oxide thickness,EOT)下，氧化鑭具有較氧化鉿、氧化鋁和氧化矽低得多的漏電流。然而，由於鑭擴散至界面層(IL)中以誘導高界面缺陷密度(interface trap density)，故氧化鑭可能與氧化矽相互作用，因此所得之電晶體的洩漏較高。根據本發明一些實施例，使用氧化鉿層將氧化鑭與氧化矽(界面層(IL))分離，從而防止鑭擴散到氧化矽之中。
第22圖繪示從樣品晶圓所獲得之高介電常數(High-K)(在圖22中標示為“HK”，氧化鉿)層、界面層(IL)、矽及氮化鈦矽(TSN)中的鑭之擴散分佈(diffusion profiles)。高介電常數(HK)層包括氧化鉿層及在氧化鉿層上方之氧化鑭層。線402、404、406、408和410分別顯示矽、鉿、氧、鈦和鑭的濃度。線410顯示界面層(IL)不含或大抵上不含(原子百分數低於約2%)鑭，並顯示氧化鉿(HK)係用以防止鑭擴散到界面層(IL)中之良好的阻擋層。因此，藉由添加氧化鉿層，可防止鑭與氧化矽之不期望的相互作用，並降低相應電晶體的漏電流。此外，藉由使用氧化鑭作為高介電常數介電材料，可形成更多的偶極子(dipoles)，且可進一步降低漏電流。
根據一些實施例，本發明提供一種半導體裝置的形成方法，包括：形成電晶體的閘極堆疊。閘極堆疊的形成包 括：形成氧化矽層於半導體區上；沉積氧化鉿層於氧化矽層上方；沉積氧化鑭層於氧化鉿層上方；及沉積功函數層於氧化鑭層上方。形成源極/汲極區於閘極堆疊的相反側。
如前述之半導體裝置的形成方法，更包括：沉積矽酸鉿層於氧化矽層與氧化鉿層之間。
如前述之半導體裝置的形成方法，其中矽酸鉿層具有低於約10%的鉿原子百分比。
如前述之半導體裝置的形成方法，其中氧化矽層不含鉿。
如前述之半導體裝置的形成方法，更包括：沉積氧化鑭矽層於氧化鑭層上方。
如前述之半導體裝置的形成方法，更包括：移除氧化鑭層及氧化鉿層；及沉積額外的氧化鉿層於氧化矽層上方。
如前述之半導體裝置的形成方法，更包括：沉積氮化鈦矽層於氧化鑭層上方。
根據一些實施例，本發明提供一種半導體裝置的形成方法，包括：分別形成具有第一部分和第二部分的氧化矽層於第一半導體區和第二半導體區上方；分別沉積具有第一部分和第二部分的第一氧化鉿層於氧化矽層的第一部分和第二部分上方；分別沉積具有第一部分和第二部分的氧化鑭層於第一氧化鉿層的第一部分和第二部分上方；移除氧化鑭層的第二部分及第一氧化鉿層的第二部分；沉積第二氧化鉿層於氧化矽層的第二部分上方；及分別沉積第一功函數層於氧化鑭層的第 一部分上方，並沉積第二功函數層於第二氧化鉿層上方。
如前述之半導體裝置的形成方法，更包括：形成n型源極/汲極區於第一功函數層的相反側；及形成p型源極/汲極區於第二功函數層的相反側。
如前述之半導體裝置的形成方法，更包括：沉積氮化鈦矽層，氮化鈦矽層包括：位於氧化鑭層的第一部分上方之第一部分；及位於第二氧化鑭層上方並與其接觸之第二部分。
如前述之半導體裝置的形成方法，更包括：沉積氧化鑭矽層，氧化鑭矽層包括：分別位於氧化鑭層的第一部分和第二部分上方之第一部分和第二部分；及移除氧化鑭矽層的第二部分。
如前述之半導體裝置的形成方法，更包括：沉積矽酸鉿層，矽酸鉿層包括：分別位於氧化矽層的第一部分和第二部分上方之第一部分和第二部分；及移除矽酸鉿層的第二部分。
如前述之半導體裝置的形成方法，其中矽酸鉿層具有低於約10%的鉿原子百分比。
如前述之半導體裝置的形成方法，更包括：對氧化鑭層及第一氧化鉿實行退火。
根據一些實施例，本發明提供一種半導體裝置，包括：包含閘極堆疊的電晶體，閘極堆疊更包括：位於半導體區上的氧化矽層；位於氧化矽層上方的氧化鉿層；位於氧化鉿層上方的氧化鑭層；及位於氧化鑭層上方的功函數層。源極/ 汲極區係位於閘極堆疊的一側。
如前述之半導體裝置，更包括：位於第一氧化鉿層與第一氧化矽層之間的矽酸鉿層。
如前述之半導體裝置，其中矽酸鉿層與第一氧化鉿層及第一氧化矽層接觸。
如前述之半導體裝置，更包括：位於氧化鑭層上方之氧化鑭矽層。
如前述之半導體裝置，其中第一電晶體係n型電晶體。
如前述之半導體裝置，更包括：包含第二閘極堆疊之p型電晶體，第二閘極堆疊包括：位於第二半導體區上之第二氧化矽層；位於第二氧化矽層上方之第二氧化鉿層；及位於第二氧化鉿層上方之第二功函數層，其中第二氧化鉿層與第二功函數層之間沒有含鑭層。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以更佳的了解本發明的各個方面。本技術領域中具有通常知識者應該可理解，他們可以很容易的以本發明為基礎來設計或修飾其它製程及結構，並以此達到相同的目的及/或達到與本發明介紹的實施例相同的優點。本技術領域中具有通常知識者也應該了解這些相等的結構並不會背離本發明的發明精神與範圍。本發明可以作各種改變、置換、修改而不會背離本發明的發明精神與範圍。

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  1. 一種半導體裝置的形成方法，包括：形成一第一電晶體的一第一閘極堆疊，包括：形成一氧化矽層於一半導體區上；沉積一氧化鉿層於該氧化矽層上方；沉積一氧化鑭層於該氧化鉿層上方；及沉積一功函數層於該氧化鑭層上方；及形成第一源極/汲極區於該第一閘極堆疊的相反側。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750032B (zh) * 2020-02-19 2021-12-11 台灣積體電路製造股份有限公司 半導體裝置及其形成方法
US11664279B2 (en) 2020-02-19 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple threshold voltage implementation through lanthanum incorporation
TWI817408B (zh) * 2021-04-28 2023-10-01 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483372B2 (en) 2017-09-29 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Spacer structure with high plasma resistance for semiconductor devices
US11069784B2 (en) * 2019-05-17 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
JP6946374B2 (ja) * 2019-06-20 2021-10-06 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置、およびプログラム
US11227940B2 (en) * 2020-02-27 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
US11302794B2 (en) * 2020-03-17 2022-04-12 International Business Machines Corporation FinFET with dual work function metal
US20220115521A1 (en) * 2020-10-14 2022-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
CN112349792B (zh) * 2020-11-06 2023-01-31 浙江师范大学 一种单晶硅钝化接触结构及其制备方法
US20220246473A1 (en) * 2021-02-04 2022-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid film scheme for self-aligned contact
US20230022269A1 (en) * 2021-07-23 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor dies including low and high workfunction semiconductor devices
TWI828398B (zh) * 2022-10-31 2024-01-01 華邦電子股份有限公司 半導體結構及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413386B1 (en) * 2000-07-19 2002-07-02 International Business Machines Corporation Reactive sputtering method for forming metal-silicon layer
JP2005317583A (ja) * 2004-04-27 2005-11-10 Renesas Technology Corp 半導体装置およびその製造方法
JP2012156229A (ja) * 2011-01-25 2012-08-16 Renesas Electronics Corp 半導体装置およびその製造方法
KR102230196B1 (ko) * 2015-04-23 2021-03-19 삼성전자주식회사 반도체 소자 및 그 제조방법

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750032B (zh) * 2020-02-19 2021-12-11 台灣積體電路製造股份有限公司 半導體裝置及其形成方法
US11664279B2 (en) 2020-02-19 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple threshold voltage implementation through lanthanum incorporation
TWI817408B (zh) * 2021-04-28 2023-10-01 台灣積體電路製造股份有限公司 半導體裝置結構及其形成方法

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