TW201841233A - 自對準磊晶接觸流 - Google Patents

自對準磊晶接觸流 Download PDF

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TW201841233A
TW201841233A TW107102011A TW107102011A TW201841233A TW 201841233 A TW201841233 A TW 201841233A TW 107102011 A TW107102011 A TW 107102011A TW 107102011 A TW107102011 A TW 107102011A TW 201841233 A TW201841233 A TW 201841233A
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dielectric material
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郢 張
紹芳 諸
鮑新宇
雷吉那吉爾曼尼 佛列德
華 仲
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美商應用材料股份有限公司
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Abstract

提供用於形成半導體裝置（如FinFET）的方法。在一個實施例中，用於形成FinFET裝置的方法包含移除複數個鰭片中之每個鰭片之一部分，且每個鰭片之剩餘部分從介電表面凹陷。方法進一步包含在每個鰭片之剩餘部分上形成特徵，藉由介電材料填充在相鄰特徵之間形成的間隙，移除特徵，以及在每個鰭片之剩餘部分上形成填充材料。因為特徵之形狀受控制，所以可控制填充材料之形狀。

Description

自對準磊晶接觸流
本文所述的實施例大致上關於用於形成半導體裝置的方法，並且更具體而言關於用於形成鰭式場效電晶體(FinFET)的方法。
隨著下一代裝置的電路密度增加，互連件（例如穿孔、溝槽、接觸(contact)、閘極結構及其他特徵）之寬度以及介於其間的介電材料減小至22 nm或更小的尺度，而介電層之厚度維持實質上恆定，結果為增加特徵之高寬比(aspect ratio)。近來，互補式金屬氧化物半導體(CMOS) FinFET裝置已廣泛用於許多邏輯及其他應用中並且被整合至各種不同類型的半導體裝置中。
FinFET裝置一般包含具有高的高寬比的半導體鰭片，其中電晶體的通道及源極/汲極區域形成於該等鰭片上。隨後閘極電極形成於鰭片裝置上方且沿鰭片裝置之一部分之側面形成，利用通道及源極/汲極區域之增加的表面積之優點，以產生更快、更可靠及更好控制的半導體電晶體裝置。FinFET之進一步優點包含減少短通道效應以及提供更高的電流。
為了改進電晶體效能，應力源(stressor)材料可填充源極/汲極區域，且應力源材料可藉由磊晶於源極/汲極區域中生長。磊晶膜具有(111)平面的刻面(facet)，且沿著電晶體通道方向具有鑽石(diamond)形狀。換言之，磊晶膜可側向延伸且形成刻面。隨著電晶體規模縮小，鰭片間距（相鄰鰭片之間的距離）變得更小。此舉可能導致在鰭片上生長的磊晶膜與在相鄰鰭片上生長的磊晶膜之間的距離減少，此可能導致相鄰的磊晶膜融合(merge)。融合的磊晶膜減少電晶體通道中磊晶膜對應變的效應，且缺陷可能容易形成在融合區域之接面。
因此，需要用於形成FinFET的改進方法。
提供用於形成半導體裝置（例如FinFET）的方法。在一個實施例中，方法包含：移除形成於半導體基板上的複數個鰭片中之每個鰭片之一部分，以暴露每個鰭片之剩餘部分之表面，其中該表面從鄰近每個鰭片處形成的第一介電材料之表面凹陷；於每個鰭片之該剩餘部分之該表面上形成特徵；藉由第二介電材料填充在相鄰特徵之間的數個間隙；移除該等特徵，以在該第二介電材料中形成複數個開口，其中每個鰭片之該剩餘部分之該表面被暴露出。
在另一個實施例中，方法包含：在半導體表面之複數個暴露的部分之每個暴露的部分上以磊晶方式形成特徵，其中該特徵包括化合物半導體材料，其中該等暴露的部分由設置於該半導體表面之覆蓋的部分上的第一介電材料所分隔；藉由第二介電材料填充相鄰特徵之間的數個間隙；移除該等特徵，以在該第二介電材料中形成複數個開口，其中該半導體表面之該等暴露的部分之該表面未被覆蓋；及在每個開口內沉積填充材料。
在另一個實施例中，方法包含：移除數個半導體柱(pillar)以在鄰近該等半導體柱處形成的介電材料中形成複數個溝槽，其中在每個溝槽中暴露出包括鰭片材料的半導體表面；在每個暴露的半導體表面上形成導電源極或汲極材料，其中每個源極或汲極材料形成於該複數個溝槽之對應溝槽內；及在每個源極或汲極材料上方形成金屬接觸，其中該金屬接觸與對應的源極或汲極材料在該複數個溝槽之對應溝槽內對準。
提供用於形成半導體裝置（例如FinFET）的方法。在一個實施例中，用於形成FinFET裝置的方法包含移除複數個鰭片中之每個鰭片之一部分，並且每個鰭片之剩餘部分從介電表面凹陷。方法進一步包含在每個鰭片之剩餘部分上形成特徵，藉由介電材料填充在相鄰特徵之間形成的間隙，移除該等特徵，以及在每個鰭片之剩餘部分上形成填充材料。因為特徵之形狀受控制，所以可控制填充材料之形狀。
第1圖為根據本文所述的一個實施例的半導體結構100之透視圖。半導體結構100可包含基板101、複數個鰭片102（僅圖示兩個，但該結構可具有多於兩個鰭片）、介電材料104及閘極電極110，介電材料104設置於基板101上的相鄰鰭片102之間，閘極電極110設置於介電材料104上並且在每個鰭片102之一部分上方。基板101可為塊材(bulk)矽基板，並且可摻雜有p型或n型雜質。其他基板材料包含但不限於鍺、矽鍺及其他類似材料。複數個鰭片102可由與基板101相同的材料製成。介電材料104可形成隔離區域，如淺溝槽隔離(STI)區域，並且可包含氧化矽、氮化矽、氮氧化矽、碳氮化矽或任何其他適合的介電材料。如第1圖所示，該複數個鰭片102中之每一者在介電材料104之上表面上方延伸一段距離。閘極介電質108形成於閘極電極110與該複數個鰭片102之間。閘極介電質108促進閘極電極110與該複數個鰭片102之間的電隔離。閘極介電質108可由氮化矽、氧化矽、氧化鉿、氮氧化鉿矽、矽酸鉿、氧化鉿矽或任何其他方便的閘極介電質材料製成。閘極電極110可由多晶矽、非晶矽、鍺、矽鍺、金屬或金屬合金製成。
第2A圖~第2H圖繪示根據本文所述的一個實施例的形成半導體裝置的製程。第2A圖為半導體基板100之側視圖。半導體基板100包含在介電材料104之上表面201上方延伸的複數個鰭片102（圖示三個）及閘極電極110。為了清楚起見，省略了閘極介電質108及基板101。下一步，如第2B圖所示，移除每個鰭片102之一部分以暴露鰭片102之剩餘部分204之表面202。每個鰭片102之部分之移除可藉由選擇性蝕刻製程，使得閘極電極110及介電材料104不受影響。換言之，由於鰭片102、閘極電極110及介電材料104是由不同的材料製成，蝕刻化學物經選擇使得鰭片102之蝕刻速率比閘極電極110及介電材料104之蝕刻速率更快。每個鰭片102之剩餘部分204之表面202從介電材料之上表面201凹陷。
如第2C圖所示，於每個鰭片102之剩餘部分204之表面202上形成特徵206，如柱(pillar)或脊(ridge)。根據第2C圖，特徵206在前景中出現，而閘極電極110在背景中出現。在形成特徵206之前，任何形成在表面201及202上的原生氧化物可藉由預清洗製程來移除。特徵206可於磊晶沉積腔室中形成。在一個實施例中，每個特徵206藉由首先在每個鰭片102之剩餘部分204之表面202上形成成核層而形成。基板101（第1圖）可具有於從約攝氏300度至約攝氏400度的範圍中的溫度，且磊晶沉積腔室在形成成核層期間可具有小於約100托的壓力。成核層可具有於從約50埃至約100埃的範圍中的厚度。在形成成核層之後，將基板101（第1圖）加熱至在從約攝氏500度至約攝氏600度的範圍中的溫度，將磊晶沉積腔室之壓力降低至從約10托至約40托，並且形成特徵206。用於形成成核層及特徵206的材料包含III-V族半導體材料，例如GaAs、InGaAs、InAs、GaP、InP、InGaP、GaSb、InSb、GaAsSb、InAsSb及其他適合的材料。在一些實施例中，可使用II-VI族半導體材料來形成特徵206。與由於在不同表面平面上的不同生長速率而形成鑽石形狀的基於矽或鍺的應力源材料不同，用以形成特徵206的材料並不形成鑽石形狀。特徵206之高度、寬度及刻面可藉由溫度、壓力及/或前驅物流量來控制。如第2C圖所示，每個特徵206在每個鰭片102之剩餘部分204之表面201上方可具有矩形剖面及實質上定值的寬度W1 。寬度W1 可大於鰭片102之剩餘部分204之寬度W2 。在一個實施例中，寬度W1 比寬度W2 寬約1 nm至約10 nm。
下一步，如第2D圖所示，介電材料208形成於相鄰特徵206之間。在一個實施例中，介電材料208與特徵206在介電材料208之沉積製程結束時共平面。在另一個實施例中，介電材料208亦形成於特徵206與閘極電極110上。介電材料208可為與介電材料104相同的材料。在一個實施例中，介電材料208為氧化矽並且藉由可流動化學氣相沉積(FCVD)製程來沉積。隨後於介電材料208上實行化學機械平坦化(CMP)製程以暴露特徵206，如第2E圖所示。暴露出每個特徵206之表面210，且表面210與介電材料208之表面212共平面。
下一步，如第2F圖所示，移除特徵206以暴露剩餘部分204之表面202。閘極介電質108及閘極電極110應於背景中出現，但為了清楚起見而將之省略。特徵206可藉由選擇性蝕刻製程來移除，所以介電材料208不受影響。換言之，由於特徵206與介電材料208是由不同的材料製成，特徵206之蝕刻速率比介電材料208之蝕刻速率快得多。作為移除製程之結果，在介電材料208中形成複數個開口214，如溝槽或穿孔。每個開口214具有與特徵206相同的形狀。隨後將填充材料216（如應力源材料）沉積於每個鰭片102之剩餘部分204之表面202上的每個開口214中，如第2G圖所示。填充材料亦可沉積於介電材料208之表面212上，並且可實行回蝕製程以移除沉積於介電材料208之表面212上的填充材料。填充材料216可為FinFET裝置之源極或汲極並且可為基於矽及/或鍺的材料。在一個實施例中，填充材料216為導電材料。填充材料216可藉由在可從應用材料公司獲得的磊晶沉積腔室中的磊晶沉積製程來形成。磊晶沉積製程通常藉由將磊晶前驅物（例如矽烷(silane)、鍺烷(germane)、磷化氫(phosphine)及砷化氫(arsine)）流入磊晶沉積腔室中並且將基板加熱至例如攝氏300度至攝氏600度的溫度來實行，此造成基板上磊晶沉積。對於III-V族半導體材料，III族元素的前驅物包含鹵化物，鹵化物可與例如砷化氫、磷化氫及二苯乙烯(stilbene)的材料反應。在一個實施例中，填充材料216為摻雜磷的矽，並且FinFET裝置為n型FET。在另一個實施例中，填充材料216為摻雜硼或鎵的矽鍺，並且FinFET裝置為p型FET。填充材料216之形狀由其中形成填充材料216的開口214所限制。因此，並非具有鑽石形狀，填充材料216具有矩形剖面，並且相鄰填充材料216之間的距離增加。每個填充材料216具有從介電材料208之表面212凹陷的表面213。
形成複數個開口214之另一個益處在於，於開口214內的填充材料216之表面213上沉積的任何材料為自對準的。在一個實施例中，如第2H圖所示，於開口214內的填充材料216上方沉積金屬接觸222。由於金屬接觸222及填充材料216兩者皆形成於開口214內，因此金屬接觸222與填充材料216（亦即，源極或汲極）自對準。金屬接觸222可由金屬（例如鈷或鎢）所製造。在沉積金屬接觸222之前可在填充材料216上形成另外的材料。舉例而言，矽化物或鍺化物層218可藉由矽化製程形成於填充材料216上。襯裡(liner) 220可藉由原子層沉積(ALD)製程保形地形成於開口214中。隨後將金屬接觸222沉積於襯裡220上。可實行CMP製程以將表面平坦化。
第3A圖~第3C圖繪示根據本文所述的另一個實施例的形成半導體裝置的製程。第3A圖為半導體結構300之側視圖。半導體結構300包含具有半導體表面305的基板302。半導體表面305包含由複數個覆蓋的部分306所分隔的複數個暴露的部分304。在一個實施例中，基板302為矽基板，並且半導體表面305為矽表面。第一介電材料308設置於半導體表面305之覆蓋的部分306上。第一介電材料308可為氧化矽、氮化矽、氮氧化矽、碳氮化矽或任何其他適合的介電材料。下一步，如第3B圖所示，特徵310形成於半導體表面305之每個暴露的部分304上。特徵310可與特徵206相同。在形成特徵310之前，任何形成在半導體表面305上的原生氧化物可藉由預清洗製程來移除。特徵310可於磊晶沉積腔室中形成。在一個實施例中，每個特徵310藉由首先在半導體表面305之對應的暴露的部分304上形成成核層而形成。成核層及特徵310可在與成核層及特徵206相同的製程條件下形成。與由於在不同表面平面上的不同生長速率而形成鑽石形狀的基於矽或鍺的材料不同，用以形成特徵310的材料並不形成鑽石形狀。特徵310之高度、寬度及刻面可藉由溫度、壓力及/或前驅物流量來控制。
下一步，如第3C圖所示，在相鄰特徵310之間形成第二介電材料312。在一個實施例中，第二介電材料312與特徵310在第二介電材料312之沉積製程結束時共平面。在另一個實施例中，第二介電材料312亦形成於特徵310上，並且於第二介電材料312上實行CMP製程以暴露出特徵310。第二介電材料312可為與介電材料208相同的材料。
隨後於半導體基板300上實行在第2F圖、第2G圖及第2H圖中所示的製程步驟，以在第二介電材料312中形成複數個開口，在該複數個開口中沉積填充材料，並且在該複數個開口中沉積金屬。填充材料可與填充材料216相同，並且金屬可與金屬接觸222相同。由於填充材料與金屬兩者形成於相同的開口中，填充材料與金屬為自對準的。
儘管前述是針對本揭示案之實施例，但在不脫離本揭示案之基本範疇下，可設計其他及進一步實施例，且本揭示案之範疇由以下的申請專利範圍所決定。
100‧‧‧半導體結構
101‧‧‧基板
102‧‧‧鰭片
104‧‧‧介電材料
108‧‧‧閘極介電質
110‧‧‧閘極電極
201‧‧‧介電材料之上表面
202‧‧‧鰭片之剩餘部分之表面
204‧‧‧鰭片之剩餘部分
206‧‧‧特徵
208‧‧‧介電材料
210‧‧‧特徵之表面
212‧‧‧介電材料之表面
213‧‧‧填充材料之表面
214‧‧‧開口
216‧‧‧填充材料
218‧‧‧矽化物或鍺化物層
220‧‧‧襯裡
222‧‧‧金屬接觸
300‧‧‧半導體結構
302‧‧‧基板
304‧‧‧暴露的部分
305‧‧‧半導體表面
306‧‧‧覆蓋的部分
308‧‧‧第一介電材料
310‧‧‧特徵
312‧‧‧第二介電材料
W1‧‧‧ 寬度
W2‧‧‧ 寬度
可藉由參照實施例，該等實施例中之一些實施例繪示於附圖中，可得到以上簡要總結的本揭示案之更特定敘述，如此可得到詳細地瞭解本揭示案之上述特徵的方式。然而，應注意到，附圖僅繪示此揭示案之典型實施例，且因此不應被視為限制本揭示案之範疇，因為本揭示案可容許其他等效實施例。
第1圖為根據本文所述的一個實施例的半導體結構之透視圖。
第2A圖~第2H圖繪示根據本文所述的一個實施例的形成半導體裝置的製程。
第3A圖~第3C圖繪示根據本文所述的另一個實施例的形成半導體裝置的製程。
為了促進瞭解，已儘可能使用相同的元件符號來指稱圖式中共用的相同元件。預期一個實施例之元件及特徵在沒有進一步敘述的情況下可有利地併入其他實施例。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無

Claims (20)

  1. 一種方法，包括以下步驟： 移除形成於一半導體基板上的複數個鰭片中之每個鰭片之一部分，以暴露該每個鰭片之一剩餘部分之一表面，其中該表面從鄰近該每個鰭片處形成的一第一介電材料之一表面凹陷；於每個鰭片之該剩餘部分之該表面上形成一特徵；藉由一第二介電材料填充在相鄰特徵之間的數個間隙；及移除該等特徵，以在該第二介電材料中形成複數個開口，其中該每個鰭片之該剩餘部分之該表面被暴露出。
  2. 如請求項1所述之方法，進一步包括以下步驟：於該每個鰭片之該剩餘部分之該表面上形成一填充材料，其中每個填充材料形成於該複數個開口之一對應開口內。
  3. 如請求項1所述之方法，其中該等特徵為在一磊晶沉積腔室中形成。
  4. 如請求項1所述之方法，其中該等特徵藉由一選擇性蝕刻製程來移除。
  5. 如請求項2所述之方法，其中該填充材料為在一磊晶沉積腔室中形成。
  6. 如請求項1所述之方法，其中該每個特徵由一III-V族半導體材料或一II-VI族半導體材料製成。
  7. 如請求項1所述之方法，其中該每個特徵具有一第一寬度並且每個鰭片具有一第二寬度，其中該第一寬度大於該第二寬度。
  8. 一種方法，包括以下步驟： 在一半導體表面之複數個暴露的部分之每個暴露的部分上以磊晶方式形成一特徵，其中該特徵包括一化合物半導體材料，其中該等暴露的部分由設置於該半導體表面之覆蓋的部分上的一第一介電材料所分隔；藉由一第二介電材料填充相鄰特徵之間的數個間隙；移除該等特徵，以在該第二介電材料中形成複數個開口，其中該半導體表面之該等暴露的部分未被覆蓋；及在每個開口內沉積一填充材料。
  9. 如請求項8所述之方法，進一步包括以下步驟：在形成該等特徵之前，在該半導體表面之該等暴露的部分上實行一預清潔製程。
  10. 如請求項8所述之方法，其中該等特徵在一磊晶沉積腔室中形成。
  11. 如請求項8所述之方法，其中該等特徵藉由一選擇性蝕刻製程來移除。
  12. 如請求項8所述之方法，其中該填充材料在一磊晶沉積腔室中形成。
  13. 如請求項8所述之方法，其中該填充材料包括一半導體材料或一導電材料。
  14. 一種方法，包括以下步驟： 移除數個半導體柱以在鄰近該等半導體柱處形成的一介電材料中形成複數個溝槽，其中在該每個溝槽中暴露出包括一鰭片材料的一半導體表面； 在該每個暴露的半導體表面上形成一導電源極或汲極材料，其中該每個源極或汲極材料形成於該複數個溝槽之一對應溝槽內；及 在該每個源極或汲極材料上方形成一金屬接觸，其中該金屬接觸與一對應的源極或汲極材料在該複數個溝槽之一對應溝槽內對準。
  15. 如請求項14所述之方法，進一步包括以下步驟：在每個源極或汲極材料上方形成該金屬接觸之前，在每個源極或汲極材料上形成一矽化物或鍺化物層。
  16. 如請求項15所述之方法，進一步包括以下步驟：在每個源極或汲極材料上方形成該金屬接觸之前，在該矽化物或鍺化物層上形成一襯裡。
  17. 如請求項16所述之方法，其中該金屬接觸形成於該襯裡上。
  18. 如請求項16所述之方法，其中該金屬接觸包括鈷或鎢。
  19. 如請求項14所述之方法，其中該等半導體柱藉由一選擇性蝕刻製程來移除。
  20. 如請求項14所述之方法，其中該源極或汲極材料為在一磊晶沉積腔室中形成。
TW107102011A 2017-01-20 2018-01-19 自對準磊晶接觸流 TWI782945B (zh)

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