CN110419110B - 自对准外延接触流 - Google Patents

自对准外延接触流 Download PDF

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CN110419110B
CN110419110B CN201880017658.XA CN201880017658A CN110419110B CN 110419110 B CN110419110 B CN 110419110B CN 201880017658 A CN201880017658 A CN 201880017658A CN 110419110 B CN110419110 B CN 110419110B
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feature
fin
forming
dielectric material
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CN110419110A (zh
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张郢
舒伯特·S·楚
鲍新宇
瑞加娜.杰曼尼.弗雷德
华·春
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Applied Materials Inc
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Abstract

提供用于形成诸如FinFET的半导体器件的方法。在一个实施方式中，用于形成FinFET器件的方法包含移除多个鳍片中的每个鳍片的一部分，且每个鳍片的剩余部分从介电表面凹陷。方法进一步包含在每个鳍片的剩余部分上形成特征，利用介电材料填充在相邻特征之间形成的间隙，移除特征，和在每个鳍片的剩余部分上形成填充材料。因为特征的形状受控制，所以可控制填充材料的形状。

Description

自对准外延接触流
技术领域
本文所述的实施方式一般地涉及用于形成半导体器件的方法，并且尤其是，涉及用于形成鳍式场效晶体管(FinFET)的方法。
背景技术
随着下一代装置的电路密度增加，诸如穿孔、沟槽、接触(contact)、栅极结构及其他特征之类的互连件的宽度以及介于其间的介电材料减小至22nm或更小的尺度，而介电层的厚度维持实质上恒定，结果为增加特征的深宽比(aspect ratio)。近来，互补式金属氧化物半导体(CMOS)FinFET器件已广泛用于许多逻辑及其他应用中并且被整合至各种不同类型的半导体器件中。
FinFET器件一般包含具有高的深宽比的半导体鳍片，其中晶体管的通道及源极/漏极区域形成于这些鳍片上。随后栅极电极形成于鳍片器件上方且沿鳍片器件的一部分的侧面形成，利用通道及源极/漏极区域的增加的表面积的优点，以产生更快、更可靠及更好控制的半导体晶体管器件。FinFET的进一步优点包含减少短通道效应以及提供更高的电流。
为了改进晶体管效能，应力源(stressor)材料可填充源极/漏极区域，且应力源材料可通过外延于源极/漏极区域中生长。外延膜具有(111)平面的刻面(facet)，且沿着晶体管通道方向具有金刚石(diamond)形状。换言之，外延膜可侧向延伸且形成刻面。随着晶体管规模缩小，鳍片间距(相邻鳍片之间的距离)变得更小。此举可能导致在鳍片上生长的外延膜与在相邻鳍片上生长的外延膜之间的距离减少，此可能导致相邻的外延膜融合(merge)。融合的外延膜减少晶体管通道中外延膜对应变的效应，且缺陷可能容易形成在融合区域的接合处。
因此，需要用于形成FinFET的改进方法。
发明内容
提供用于形成半导体器件(例如FinFET)的方法。在一个实施方式中，方法包含：移除形成于半导体基板上的多个鳍片中的每个鳍片的一部分，以暴露每个鳍片的剩余部分的表面，其中该表面从邻近每个鳍片处形成的第一介电材料的表面凹陷；于每个鳍片的该剩余部分的该表面上形成特征；利用第二介电材料填充在相邻特征之间的数个间隙；移除所述特征，以在该第二介电材料中形成多个开口，其中每个鳍片的该剩余部分的该表面被暴露出。
在另一个实施方式中，方法包含：在半导体表面的多个暴露的部分中的每个暴露的部分上以外延方式形成特征，其中该特征包括化合物半导体材料，其中所述暴露的部分由设置于该半导体表面的覆盖的部分上的第一介电材料所分隔；利用第二介电材料填充相邻特征之间的数个间隙；移除所述特征，以在该第二介电材料中形成多个开口，其中该半导体表面的所述暴露的部分的表面未被覆盖；及在每个开口内沉积填充材料。
在另一个实施方式中，方法包含：移除数个半导体柱(pillar)以在邻近所述半导体柱处形成的介电材料中形成多个沟槽，其中在每个沟槽中暴露出包括鳍片材料的半导体表面；在每个暴露的半导体表面上形成导电源极或漏极材料，其中每个源极或漏极材料形成于所述多个沟槽中的对应沟槽内；及在每个源极或漏极材料上方形成金属接触，其中该金属接触与对应的源极或漏极材料在所述多个沟槽中的对应沟槽内对准。
附图说明
以上简要概述本公开内容的上述详述特征可以被详细理解的方式、以及本公开内容的更特定描述，可通过参照实施方式来获得，实施方式中的一些实施方式绘示于附图中。然而，应注意到，附图仅绘示本公开内容的典型实施方式，因而不应被视为对本公开内容的范围的限制，因为本公开内容可允许其他等同有效的实施方式。
图1为根据本文所述的一个实施方式的半导体结构的透视图。
图2A-图2H图示根据本文所述的一个实施方式的形成半导体器件的工艺。
图3A-图3C图示根据本文所述的另一个实施方式的形成半导体器件的工艺。
为了促进了解，已尽可能使用相同的附图符号来标示图式中共通的相同元件。考虑到，在没有进一步描述下一个实施方式中的元件及特征可有利地并入其他实施方式。
具体实施方式
提供用于形成诸如FinFET的半导体器件的方法。在一个实施方式中，用于形成FinFET器件的方法包含移除多个鳍片中的每个鳍片的一部分，并且每个鳍片的剩余部分从介电表面凹陷。方法进一步包含在每个鳍片的剩余部分上形成特征，利用介电材料填充在相邻特征之间形成的间隙，移除特征，以及在每个鳍片的剩余部分上形成填充材料。因为特征的形状受控制，所以可控制填充材料的形状。
图1为根据本文所述的一个实施方式的半导体结构100的透视图。半导体结构100可包括基板101、多个鳍片102(仅示出两个，但该结构可具有多于两个鳍片)、介电材料104及栅极电极110，介电材料104设置于基板101上的相邻鳍片102之间，栅极电极110设置于介电材料104上并且在每个鳍片102的一部分上方。基板101可为块材(bulk)硅基板，并且可掺杂有p型或n型杂质。其他基板材料包含但不限于锗、硅锗及其他类似材料。多个鳍片102可由与基板101相同的材料制成。介电材料104可形成隔离区域，诸如浅沟槽隔离(STI)区域，并且介电材料104可包含氧化硅、氮化硅、氮氧化硅、碳氮化硅或任何其他适合的介电材料。如图1所示，多个鳍片102中的每一鳍片在介电材料104的上表面上方延伸一段距离。栅极介电质108形成于栅极电极110与多个鳍片102之间。栅极介电质108促进栅极电极110与多个鳍片102之间的电隔离。栅极介电质108可由氮化硅、氧化硅、氧化铪、氮氧化铪硅、硅酸铪、氧化铪硅或任何其他方便的栅极介电质材料制成。栅极电极110可由多晶硅、非晶硅、锗、硅锗、金属或金属合金制成。
图2A-图2H图示根据本文所述的一个实施方式的形成半导体器件的工艺。
图2A为半导体结构100的侧视图。半导体结构100包含在介电材料104的上表面201上方延伸的多个鳍片102(示出三个)与栅极电极110。为了清楚起见，省略了栅极介电质108及基板101。下一步，如图2B所示，移除每个鳍片102的一部分以暴露鳍片102的剩余部分204的表面202。每个鳍片102的部分的移除可由选择性蚀刻工艺，使得栅极电极110及介电材料104不受影响。换言之，由于鳍片102、栅极电极110及介电材料104是由不同的材料制成，蚀刻化学物经选择使得鳍片102的蚀刻速率比栅极电极110及介电材料104的蚀刻速率更快。每个鳍片102的剩余部分204的表面202从介电材料的上表面201凹陷。
如图2C所示，于每个鳍片102的剩余部分204的表面202上形成特征206，例如柱(pillar)或脊(ridge)。根据图2C，特征206在前景中出现，而栅极电极110在背景中出现。在形成特征206之前，任何形成在表面201及202上的原生氧化物可由预清洗工艺来移除。特征206可于外延沉积腔室中形成。在一个实施方式中，每个特征206通过首先在每个鳍片102的剩余部分204的表面202上形成成核层而形成。基板101(图1)可具有于从约300摄氏度至约400摄氏度的范围中的温度，且外延沉积腔室在形成成核层期间可具有小于约100托的压力。成核层可具有于从约50埃至约100埃的范围中的厚度。在形成成核层之后，将基板101(图1)加热至在从约500摄氏度至约600摄氏度的范围中的温度，将外延沉积腔室的压力降低至从约10托至约40托，并且形成特征206。用于形成成核层及特征206的材料包含III-V族半导体材料，例如GaAs、InGaAs、InAs、GaP、InP、InGaP、GaSb、InSb、GaAsSb、InAsSb及其他适合的材料。在一些实施方式中，可使用II-VI族半导体材料来形成特征206。与由于在不同表面平面上的不同生长速率而形成金刚石形状的基于硅或锗的应力源材料不同，用以形成特征206的材料并不形成金刚石形状。特征206的高度、宽度及刻面可由温度、压力及/或前驱物流量来控制。如图2C所示，每个特征206可具有矩形横截面及跨每个鳍片102的剩余部分204的表面201具有实质上恒定的宽度W1。宽度W1可大于鳍片102的剩余部分204的宽度W2。在一个实施方式中，宽度W1比宽度W2宽约1nm至约10nm。
下一步，如图2D所示，介电材料208形成于相邻特征206之间。在一个实施方式中，介电材料208与特征206在介电材料208的沉积工艺结束时共平面。在另一个实施方式中，介电材料208亦形成于特征206与栅极电极110上。介电材料208可为与介电材料104相同的材料。在一个实施方式中，介电材料208为氧化硅并且通过可流动化学气相沉积(FCVD)工艺来沉积。随后于介电材料208上执行化学机械平坦化(CMP)工艺以暴露特征206，如图2E所示。暴露出每个特征206的表面210，且表面210与介电材料208的表面212共平面。
下一步，如图2F所示，移除特征206以暴露剩余部分204的表面202。栅极介电质108与栅极电极110应于背景中出现，但为了清楚起见而将之省略。特征206可由选择性蚀刻工艺来移除，所以介电材料208不受影响。换言之，由于特征206与介电材料208是由不同的材料制成，特征206的蚀刻速率比介电材料208的蚀刻速率快得多。作为移除工艺的结果，在介电材料208中形成多个开口214，诸如沟槽或穿孔。每个开口214具有与特征206相同的形状。随后于每个鳍片102的剩余部分204的表面202上的每个开口214中沉积填充材料216，例如应力源材料，如图2G所示。填充材料亦可沉积于介电材料208的表面212上，并且可执行回蚀工艺以移除沉积于介电材料208的表面212上的填充材料。填充材料216可为FinFET器件的源极或漏极并且可为基于硅和/或锗的材料。在一个实施方式中，填充材料216为导电材料。填充材料216可在可购自应用材料公司的外延沉积腔室中由外延沉积工艺来形成。外延沉积工艺通常通过如下方式执行：将例如硅烷(silane)、锗烷(germane)、磷化氢(phosphine)及砷化氢(arsine)的外延前驱物流入外延沉积腔室中并且将基板加热至例如300摄氏度至600摄氏度的温度，此造成基板上外延沉积。对于III-V族半导体材料，III族元素的前驱物包含卤化物，卤化物可与例如砷化氢、磷化氢及二苯乙烯(stilbene)的材料反应。在一个实施方式中，填充材料216为掺杂磷的硅，并且FinFET器件为n型FET。在另一个实施方式中，填充材料216为掺杂硼或镓的硅锗，并且FinFET器件为p型FET。填充材料216的形状由其中形成填充材料216的开口214所限制。因此，并非具有金刚石形状，填充材料216具有矩形横截面，并且相邻填充材料216之间的距离增加。每个填充材料216具有从介电材料208的表面212凹陷的表面213。
形成多个开口214的另一个益处在于，于开口214内的填充材料216的表面213上沉积的任何材料为自对准的。在一个实施方式中，如图2H所示，于开口214内的填充材料216上方沉积金属接触222。由于金属接触222及填充材料216两者皆形成于开口214内，因此金属接触222与填充材料216自对准，即，与源极或漏极自对准。金属接触222可由金属所制造，所述金属例如钴或钨。在沉积金属接触222之前可在填充材料216上形成另外的材料。举例而言，硅化物或锗化物层218可由硅化工艺形成于填充材料216上。衬里(liner)220可由原子层沉积(ALD)工艺保形地(conformally)形成于开口214中。随后将金属接触222沉积于衬里220上。可执行CMP工艺以将表面平坦化。
图3A-图3C图示根据本文所述的另一个实施方式的形成半导体器件的工艺。图3A为半导体结构300的侧视图。半导体结构300包括具有半导体表面305的基板302。半导体表面305包含由多个覆盖的部分306所分隔的多个暴露的部分304。在一个实施方式中，基板302为硅基板，并且半导体表面305为硅表面。第一介电材料308设置于半导体表面305的覆盖的部分306上。第一介电材料308可为氧化硅、氮化硅、氮氧化硅、碳氮化硅或任何其他适合的介电材料。下一步，如图3B所示，特征310形成于半导体表面305的每个暴露的部分304上。特征310可与特征206相同。在形成特征310之前，任何形成在半导体表面305上的原生氧化物可由预清洗工艺来移除。特征310可于外延沉积腔室中形成。在一个实施方式中，每个特征310通过首先在半导体表面305的对应的暴露的部分304上形成成核层而形成。成核层及特征310可在与成核层及特征206相同的工艺条件下形成。与由于在不同表面平面上的不同生长速率而形成金刚石形状的基于硅或锗的材料不同，用以形成特征310的材料并不形成金刚石形状。特征310的高度、宽度及刻面可由温度、压力和/或前驱物流量来控制。
下一步，如图3C所示，在相邻特征310之间形成第二介电材料312。在一个实施方式中，第二介电材料312与特征310在第二介电材料312的沉积工艺结束时共平面。在另一个实施方式中，第二介电材料312亦形成于特征310上，并且于第二介电材料312上执行CMP工艺以暴露出特征310。第二介电材料312可为与介电材料208相同的材料。
随后于半导体结构300上执行在图2F、图2G及图2H中所示的工艺步骤，以在第二介电材料312中形成多个开口，在所述多个开口中沉积填充材料，并且在所述多个开口中沉积金属。填充材料可与填充材料216相同，并且金属可与金属接触222相同。由于填充材料与金属两者形成于相同的开口中，填充材料与金属为自对准的。
尽管前述针对本公开内容的实施方式，但在不脱离本公开内容的基本范围下，可设计其他及进一步实施方式，且本公开内容的范围由随附的权利要求来确定。

Claims (20)

1.一种用于形成半导体器件的方法，包括以下步骤：
移除形成于半导体基板上的多个鳍片中的每个鳍片的一部分，以暴露每个鳍片的剩余部分的表面，其中所述表面从邻近每个鳍片处形成的第一介电材料的表面凹陷；
于每个鳍片的所述剩余部分的所述表面上形成特征；
利用第二介电材料填充在相邻特征之间的数个间隙；及
移除所述特征，以在所述第二介电材料中形成多个开口，其中每个鳍片的所述剩余部分的所述表面被暴露出。
2.如权利要求1所述的方法，进一步包括以下步骤：于每个鳍片的所述剩余部分的所述表面上形成填充材料，其中每个填充材料形成于所述多个开口中的对应开口内。
3.如权利要求1所述的方法，其中所述特征在外延沉积腔室中形成。
4.如权利要求1所述的方法，其中所述特征由选择性蚀刻工艺来移除。
5.如权利要求1所述的方法，其中每个特征由III-V族半导体材料或II-VI族半导体材料制成。
6.如权利要求1所述的方法，其中每个特征具有第一宽度并且每个鳍片具有第二宽度，其中所述第一宽度大于所述第二宽度。
7.如权利要求2所述的方法，其中所述填充材料在外延沉积腔室中形成。
8.一种用于形成半导体器件的方法，包括以下步骤：
在半导体表面的多个暴露的部分中的每个暴露的部分上以外延方式形成特征，其中所述特征包括化合物半导体材料，其中所述暴露的部分由设置于所述半导体表面的覆盖的部分上的第一介电材料所分隔；
利用第二介电材料填充相邻特征之间的数个间隙；
移除所述特征，以在所述第二介电材料中形成多个开口，其中所述半导体表面的所述暴露的部分未被覆盖；及
在每个开口内沉积填充材料。
9.如权利要求8所述的方法，进一步包括以下步骤：在形成所述特征之前，在所述半导体表面的所述暴露的部分上执行预清洁工艺。
10.如权利要求8所述的方法，其中所述特征由选择性蚀刻工艺来移除。
11.如权利要求8所述的方法，其中所述填充材料在外延沉积腔室中形成。
12.如权利要求8所述的方法，其中所述填充材料包括半导体材料或导电材料。
13.如权利要求8所述的方法，其中所述特征在外延沉积腔室中形成。
14.一种用于形成半导体器件的方法，包括以下步骤：
移除数个半导体柱以在邻近所述半导体柱处形成的介电材料中形成多个沟槽，其中在每个沟槽中暴露出包括鳍片材料的半导体表面；
在每个暴露的半导体表面上形成导电源极或漏极材料，其中每个源极或漏极材料形成于所述多个沟槽中的对应沟槽内；及
在每个源极或漏极材料上方形成金属接触，其中所述金属接触与对应的源极或漏极材料在所述多个沟槽中的对应沟槽内对准，且其中每个源极或漏极材料接近所述金属接触的一部分具有矩形横截面。
15.如权利要求14所述的方法，进一步包括以下步骤：在每个源极或漏极材料上方形成所述金属接触之前，在每个源极或漏极材料上形成硅化物或锗化物层。
16.如权利要求15所述的方法，进一步包括以下步骤：在每个源极或漏极材料上方形成所述金属接触之前，在所述硅化物或锗化物层上形成衬里。
17.如权利要求16所述的方法，其中所述金属接触形成于所述衬里上。
18.如权利要求16所述的方法，其中所述金属接触包括钴或钨。
19.如权利要求14所述的方法，其中所述数个半导体柱通过选择性蚀刻工艺来移除。
20.如权利要求14所述的方法，其中所述源极或漏极材料在外延沉积腔室中形成。
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