TW201839913A - 內連線結構的形成方法、半導體結構的形成方法以及積體電路 - Google Patents
內連線結構的形成方法、半導體結構的形成方法以及積體電路 Download PDFInfo
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- TW201839913A TW201839913A TW106139896A TW106139896A TW201839913A TW 201839913 A TW201839913 A TW 201839913A TW 106139896 A TW106139896 A TW 106139896A TW 106139896 A TW106139896 A TW 106139896A TW 201839913 A TW201839913 A TW 201839913A
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- Prior art keywords
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- metal oxide
- oxide layer
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- 238000000034 method Methods 0.000 title claims abstract description 113
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 347
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- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/4828—Etching
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
半導體結構的形成方法包含在基底上形成蝕刻停止層,在蝕刻停止層上方形成金屬氧化物層以及在金屬氧化物層上形成層間介電層。此方法更包含在層間介電層上方形成溝槽蝕刻開口,在溝槽蝕刻開口上方形成覆蓋層,以及在覆蓋層上方形成通孔蝕刻開口。
Description
本發明實施例係有關於半導體技術,且特別是有關於內連線結構和半導體結構的形成方法以及積體電路。
隨著半導體技術的進步,對更高的儲存容量、更快的處理系統、更高的效能以及更低的成本的需求日益增加。為了滿足這些需求,半導體工業持續縮減半導體裝置(例如金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistors,MOSFETs)、平面型金屬氧化物半導體場效電晶體以及鰭式場效電晶體(fin field effect transistors,FinFETs))的尺寸。此微縮化增加了半導體製造過程的複雜性。
在一些實施例中,提供一種內連線結構的形成方法,此方法包含在基底上形成蝕刻停止層;在蝕刻停止層上方形成金屬氧化物層;在金屬氧化物層上形成層間介電層;在層間介電層上方形成低溫氧化物層;在低溫氧化物層上方形成覆蓋層;以及在覆蓋層中形成通孔蝕刻開口。
在一些其他實施例中,提供一種半導體結構的形成方法,此方法包含在基底上形成蝕刻停止層;在蝕刻停止層 上方形成金屬氧化物層;在金屬氧化物層上形成層間介電層;在層間介電層上方形成溝槽蝕刻開口;在溝槽蝕刻開口上方形成覆蓋層;以及在覆蓋層上方形成通孔蝕刻開口。
在另外一些實施例中,提供一種積體電路,積體電路包含半導體裝置,包括接點結構;以及內連線結構,耦接至接點結構,內連線結構包含蝕刻停止層,位於半導體裝置上方;金屬氧化物層,位於蝕刻停止層上方;層間介電層,位於金屬氧化物層上;以及導通孔,位於金屬氧化物層和層間介電層中。
100‧‧‧積體電路
102、302‧‧‧基底
104、1400‧‧‧內連線結構
104.1、104.2、104.3、104.4、104.5‧‧‧層
106、320‧‧‧層間介電層
108、108*、1408‧‧‧金屬線
110、110*、1410‧‧‧導通孔
112、312‧‧‧蝕刻停止層
114‧‧‧區域
122、322‧‧‧接點結構
200‧‧‧方法
210、220、230、240、250‧‧‧操作
316‧‧‧襯墊
318‧‧‧金屬氧化物層
324‧‧‧無氮抗反射層
326‧‧‧第一硬遮罩層
328‧‧‧第二硬遮罩層
430、432、434‧‧‧溝槽蝕刻開口
536‧‧‧第一有機層
538‧‧‧低溫氧化物層
540‧‧‧第一矽基層
542‧‧‧覆蓋層
544‧‧‧第二有機層
546‧‧‧第二矽基層
548‧‧‧光阻層
650、652、750、752、750*、752*‧‧‧通孔蝕刻開口
950、952‧‧‧部分通孔
1030、1032、1034‧‧‧部分溝槽
1230、1232、1234‧‧‧溝槽
1250、1252、1250*、1252*‧‧‧通孔
312t、316t、318t、320t、324t、326t、328t、536t、538t、540t、542t、546t、548t‧‧‧厚度
650w、652w、750w、752w、W1、W2、W3、W4、W5、W6、W7、W8、W9、W10‧‧‧寬度
A1、A2、A3、A4、A5、A6、A7、A8‧‧‧角度
H1、H2、H3‧‧‧高度
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是,根據本產業的標準慣例,圖示中的各種部件(feature)並未必按照比例繪製。事實上,可能任意的放大或縮小各種部件的尺寸,以做清楚的說明。
第1A圖為依據一些實施例之積體電路的剖面示意圖。
第1B圖為依據一些實施例之內連線結構的剖面示意圖。
第1C圖為內連線結構的剖面示意圖。
第2圖為依據一些實施例之製造內連線結構的方法的流程圖。
第3-7圖為依據一些實施例之積體電路在製造過程中各種階段的剖面示意圖。
第8圖為部分形成的內連線結構的剖面示意圖。
第10-12圖為依據一些實施例之積體電路在製造過程中各種階段的剖面示意圖。
第13圖為部分形成的內連線結構的剖面示意圖。
第14圖為依據一些實施例之積體電路的剖面示意圖。
現在將參照附圖描述顯示的實施例。在圖式中,相似的參考符號通常表示相同、功能上相似及/或結構上相似的元件。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例,以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例,以求簡化揭露內容的說明。當然,這些僅為範例並非用以限定本發明。例如,以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方,即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例,亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間,而使上述第一部件與上述第二部件可能未直接接觸的實施例。
再者,為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係,可使用空間相關用語,例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外,空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如,旋轉90度或者位於其他方位),並對應地解讀所使用的空間相關用語的描述。
鰭可透過任何合適的方法圖案化。舉例來說,鰭可透過使用一個或多個光微影製程圖案化,包含雙重圖案化製程或多重圖案化製程。雙重圖案化製程或多重圖案化製程可結 合光微影製程和自對準製程,以創造具有較小間距的圖案,舉例來說,此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說,在一些實施例中,犧牲層形成於基底上方並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著,移除犧牲層,且可接著使用餘留的間隔物將鰭圖案化。
應當理解的是,本文的措辭或術語是為了描述而非限制的目的,使得本說明書的措辭或術語將可由本發明所屬技術領域者所詮釋。
如本文所用,術語“選擇性”是指在相同蝕刻條件下兩種材料的蝕刻速率的比率。
除非另有說明,否則本文所用的術語“大約”是指定量的值改變±10%的值。
如本文所用,術語“基底”描述後續材料層添加於其上的材料。可圖案化基底本身。添加在基底頂部的材料可被圖案化或可保持未圖案化。再者,基底可為大範圍的半導體材料,例如矽、鍺、砷化鎵、磷化銦等。或者,基底可由不導電材料製成,例如玻璃或藍寶石晶圓。
如本文所用,術語“高的k值(high-k)”是指高介電常數。在半導體裝置結構和製造過程的領域中,高介電常數是指大於SiO2的介電常數(例如大於3.9)。
如本文所用,術語“低的k值(low-k)”是指低介電常數。在半導體裝置結構和製造過程的領域中,低介電常數是指小於SiO2的介電常數(例如小於3.9)。
如本文所用,術語“p型”定義為摻雜了p型摻雜劑(例如硼)的結構、層別及/或區域。
如本文所用,術語“n型”定義為摻雜了n型摻雜劑(例如磷)的結構、層別及/或區域。
如本文所用,術語“垂直”是指名義上垂直基底的表面。
如本文所用,術語“臨界尺寸”是指鰭式場效電晶體及/或積體電路的元件的最小部件尺寸(例如線寬)。
本發明實施例提供了用於改善後段製程(back end of the line,BEOL)之部件(例如在製造積體電路(integrated circuit,IC)的後段製程中製造的內連線結構中的通孔(via))的蝕刻輪廓的例示性方法。本文揭露的例示性方法相較於使用其他方法形成的通孔,形成有著更垂直的蝕刻輪廓的通孔,且通孔的頂部開口與底部開口之間具有更小的比率。改善的通孔的蝕刻輪廓幫助防止內連線結構中通孔與金屬線之間的漏電及/或接觸,並因此改善積體電路中裝置的效能。
積體電路製造過程可分為三個階段:前段製程(front end of the line,FEOL)、中段製程(middle of the line,MOL)及後段製程(BEOL)。在前段製程中,可形成功能性裝置(例如場效電晶體(field effect transistors,FETs))。在中段製程中,可形成低階內連線結構(例如場效電晶體的源極/汲極接點結構及/或閘極接點結構),以將功能性裝置電性連接至後段製程中的高階內連線結構。
高階內連線結構可提供在前段製程中形成的功能 性裝置及/或積體電路的元件之間的電性連接。在後段製程中,高階內連線結構可形成於層間介電(interlayer dielectric,ILD)層中,此層間介電層可在中段製程階段之後沉積於積體電路結構上方。高階內連線結構可包含兩種類型的導電結構:垂直內連線結構(也被稱為“導通孔(conductive via)”或“通孔”)和橫向內連線結構(也被稱為“金屬線”)。導通孔可在垂直方向上穿過後段製程的層間介電層,且可創造至後段製程的層間介電層之上或之下的層別的電性連接。金屬線可在橫向方向上穿過層間介電層,且可連接後段製程的層間介電層中的組件。高階內連線結構可包含後段製程的層間介電層中的多層導通孔和金屬線。除了在相鄰層之間有著電性連接的區域之外,這些多層的每一者可透過蝕刻停止層與相鄰層分開。
第1A圖為依據一些實施例之在後段製程階段之後的積體電路(IC)100的剖面示意圖。積體電路100可包含基底102和內連線結構104。在一些實施例中,基底102可代表在前段製程中形成的一個或多個功能性裝置。功能性裝置可具有接點結構122,接點結構122可在中段製程階段中形成。在一些實施例中,內連線結構104可包含層104.1至層104.5。層104.1至層104.5的每一者可包含層間介電層112、導通孔110和金屬線108。導通孔110和金屬線108可被配置為提供在前段製程階段中形成的基底102的功能性裝置之間的電性連接。
第1B圖為依據一些實施例之內連線結構100的一部份的剖面示意圖。如第1B圖所示,導通孔110可具有大致垂直的輪廓。下面的實施例描述了實現此種垂直通孔輪廓的方 法,以防止當導通孔輪廓如第1C圖所示為錐狀時,導通孔與金屬線之間的漏電及/或接觸。導通孔110*可透過使用其他方法形成。由於導通孔110*的錐形輪廓,導通孔110*可能與區域114中的金屬線108*發生短路,並因此對積體電路中的裝置的效能具有負面影響。
第14圖顯示依據一些實施例之具有導通孔1410的內連線結構1400的剖面示意圖。導通孔1410可具有與上述參照第1A圖和第1B圖之導通孔110的大致垂直輪廓相似的輪廓。
第2圖為依據一些實施例之製造如第14圖所示的內連線結構1400的例示性方法200的流程圖。依據特定的應用,可以不同的順序進行這些操作或不進行這些操作。應當注意的是,方法200不產生如第14圖所示的完整的內連線結構。因此,可以理解的是,可在方法200之前、期間及/或之後提供額外的製程,且本文簡要地描述一些製程。
為了說明的目的,將參照第3-7圖、第10-12圖和第14圖顯示的例示性製造過程描述第2圖顯示的操作。第3-7圖、第10-12圖和第14圖為依據一些實施例內連線結構在製造過程中各種階段的剖面示意圖。本發明所屬技術領域中具通常知識者將理解第3-7圖、第10-12圖和第14圖顯示的示意圖為顯示目的,且可不按比例繪製。依據一些實施例,內連線結構1400可代表參照第1A圖描述的內連線結構104的一部份。內連線結構104和內連線結構104的導通孔110、金屬線108、層間介電層106和蝕刻停止層112的上述討論應用參照第2-7圖、第10-12圖和第14圖的導通孔、金屬線、層間介電層和蝕刻停止層的以下討論。
在操作210中,在基底上沉積蝕刻停止層(etch stop layer,ESL)。舉例來說,如第3圖所示,蝕刻停止層312可沉積於基底302上。在一些實施例中,基底302可代表具有接點結構322(有時也被稱為金屬線,或被稱為導電結構)的高階內連線結構的一層,內連線結構1400(顯示於第14圖中)的導通孔1410可電性連接至此接點結構322。在一些實施例中,基底302可代表在前段製程階段中形成的一個或多個功能性裝置。功能性裝置可具有在中段製程階段中形成的接點結構322,內連線結構1400的導通孔1410可電性連接至此接點結構322。在一些實施例中,基底302可代表具有接點結構322的半導體材料(例如矽,但不限於此),內連線結構1400的導通孔1410可電性連接至此接點結構322。
在一些實施例中,基底302可包含結晶矽基底(例如晶圓)。在一些實施例中,基底302可包含元素半導體(例如鍺)、化合物半導體(包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包含碳化矽鍺、矽鍺、磷化砷鎵、磷化銦鎵、砷化銦鎵、磷化砷銦鎵、砷化銦鋁及/或砷化鎵鋁)或前述之組合。再者,基底302可依據設計需求摻雜(例如p型基底或n型基底)。在一些實施例中,基底302可摻雜p型摻雜劑(例如硼、銦、鋁或鎵)或n型摻雜劑(例如磷或砷)。基於本文揭露的內容,本發明所屬技術領域中具通常知識者將理解用於基底302的其他材料在本發明實施例的範圍和精神中。
在一些實施例中,接點結構322可包含合適的導電材料,例如鈦(Ti)、鎢(W)、銅(Cu)、鈷(Co)、鎳(Ni)、銀(Ag)、 鋁(Al)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮化矽鉭(TaSiN)、錳(Mn)、鋯(Zr)、氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、氮化鎢(WN)、碳化鈦(TiC)、碳化鋁鈦(TiAlC)、碳化鋁鉭(TaAlC)、金屬合金及/或前述之組合。基於本文揭露的內容,本發明所屬技術領域中具通常知識者將理解用於接點結構322的其他材料在本發明實施例的範圍和精神中。
蝕刻停止層312可被配置為例如在形成內連線結構1400的期間保護基底312和接點結構322。在一些實施例中,蝕刻停止層312可包含例如氮化矽(SiNx)、氧化矽(SiOx)、氮氧化矽(SiON)、碳化矽(SiC)、氮碳化矽(SiCN)、氮化硼(BN)、氮化矽硼(SiBN)、氮化矽碳硼(SiCBN)或前述之組合。在一些實施例中,蝕刻停止層312可包含透過低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)、化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)形成的氮化矽或氧化矽或透過高深寬比填溝製程(high-aspect-ratio process,HARP)形成的氧化矽。在一些實施例中,蝕刻停止層312具有在約1nm至約3nm的範圍中的厚度312t。基於本文揭露的內容,本發明所屬技術領域中具通常知識者將理解用於蝕刻停止層312的其他材料、形成方法和厚度在本發明實施例的範圍和精神中。
在一些實施例中,具有摻雜氧的碳化物材料的襯墊316可沉積於蝕刻停止層312上。在一些實施例中,襯墊316 具有在約3nm至約8nm的範圍中的厚度316t,且可用作另一個蝕刻停止層。在一些實施例中,襯墊316可透過低壓化學氣相沉積、電漿增強化學氣相沉積或化學氣相沉積形成。
請參照第2圖,在操作220中,在蝕刻停止層上方沉積金屬氧化物層和層間介電(ILD)層。舉例來說,如第3圖所示,金屬氧化物層318可沉積於襯墊316上,接著層間介電層320沉積於金屬氧化物層318上。金屬氧化物層318可幫助改善通孔的蝕刻輪廓,其將於以下進一步詳細討論。在一些實施例中,金屬氧化物層318可包含合適金屬(例如鉻(Cr)、鋁(Al)、鈦(Ti)、錫(Sn)、鋅(Zn)、鎂(Mg)、銀(Ag)、鎳(Ni)、鉬(Mo)或前述之組合)的氧化物。金屬氧化物層318可透過使用合適的金屬氧化物沉積製程(例如化學氣相沉積)沉積。
在一些實施例中,可使用具有金屬氮化物或金屬碳化物的一層取代金屬氧化物層318。在一些實施例中,可使用具有金屬氧化物、金屬氮化物、金屬碳化物或前述之組合的一層或多層的堆疊取代金屬氧化物層318來製造內連線結構1400(顯示於第14圖中)。
層間介電層320可在結構和功能上相似於上述參照第1A圖的內連線結構104的層間介電層106。在一些實施例中,層間介電層320可包含低介電常數介電材料。低介電常數材料可具有小於3.9的介電常數。在層間介電層320中的低介電常數材料可幫助降低不想要的寄生電容並最小化電阻電容(resistance-capacitance,RC)延遲。在一些實施例中,層間介電層320可透過合適的介電質沉積製程形成,例如化學氣相沉 積或原子層沉積。層間介電層320可具有在約90nm至約150nm的範圍中的厚度320t。層間介電層320可幫助提供可形成於層間介電層320中之內連線結構1400的相鄰導通孔1410之間及/或相鄰金屬線1408之間的電性隔離。導通孔1410沿例如層間介電層320中的Z軸垂直延伸,且金屬線1408可沿例如層間介電層320中的Y軸橫向延伸。
如第3圖所示,在沉積層間介電層320之後,可沉積遮罩層的堆疊。遮罩層的堆疊可包含無氮抗反射層(nitrogen free anti-reflective layer,NFARL)324、第一硬遮罩層326和第二硬遮罩層328。無氮抗反射層324可幫助在後續圖案化第一硬遮罩層326和第二硬遮罩層328的期間保護層間介電層320。第一硬遮罩層326和第二硬遮罩層328的圖案化可涉及如果不被遮罩層(例如無氮抗反射層324)保護時,可蝕刻層間介電層320的氯基製程。在一些實施例中,無氮抗反射層324可包含介電材料,且可透過使用合適的沉積方法(例如化學氣相沉積)形成。在一些實施例中,在無氮抗反射層324的沉積中,可使用包含矽烷和二氧化碳的氣體混合物。無氮抗反射層324可具有在約20nm至約30nm的範圍中的厚度324t。
在一些實施例中,第一硬遮罩層326可透過使用例如物理氣相沉積(physical vapor deposition,PVD)來沉積,且可包含氮化矽、氮化鈦或前述之組合。第一硬遮罩層326可具有在約25nm至約40nm的範圍中的厚度326t。依據一些實施例,第二硬遮罩層328可包含例如透過化學氣相沉積形成的四乙氧基矽烷(tetraethoxysilane,TEOS)。第二硬遮罩層328可具有在 約25nm至約40nm的範圍中的厚度328t。
請參照第2圖,在操作230中,圖案化層間介電層上方的硬遮罩層。舉例來說,如第4圖所示,可圖案化第一硬遮罩層326和第二硬遮罩層328,以形成溝槽蝕刻開口430、432和434。這些溝槽蝕刻開口可定義後續在層間介電層320中形成溝槽的區域。這些溝槽可後續形成內連線結構1400的金屬線1408(第14圖),其將於以下進一步詳細描述。個別溝槽蝕刻開口430、432和434的寬度W1、W2和W3可定義在後續加工中在層間介電層320中形成的溝槽的寬度。第一硬遮罩層326和第二硬遮罩層328的圖案化可透過光微影製程和乾蝕刻製程進行。在一些實施例中,乾蝕刻製程可為氯基製程。
請參照第2圖,在操作240中,在層間介電層中形成通孔和溝槽。舉例來說,如第5-7圖和9-12圖所示,通孔1250和1252以及溝槽1230、1232和1234可形成於層間介電層320中。在一些實施例中,如第5圖所示,層的堆疊可沉積於第4圖的結構上。層的堆疊可包含第一有機層536和第二有機層544、低溫氧化物(low temperature oxide,LTO)層538、第一矽基層540和第二矽基層546、覆蓋層542以及光阻層548。依據一些實施例,層的堆疊中這些層的每一者可如第5圖所示的順序排列。這些層的堆疊可幫助形成通孔蝕刻開口650、652、750和752(顯示於第6-7圖),通孔蝕刻開口650、652、750和752可定義後續在層間介電層320中形成通孔1250和1252(顯示於第12圖)的區域。這些層的堆疊也可幫助控制通孔1250和1252在其形成期間的蝕刻輪廓。
在一些實施例中,第一有機層536和第二有機層544可在相似的製程(例如分別在第4圖的結構上和覆蓋層542上在約100℃至約300℃的範圍中的溫度旋塗合適的高分子材料)中形成。第一有機層536和第二有機層544可具有在約150nm至約300nm的範圍中的個別厚度536t和542t。
依據一些實施例,低溫氧化物層538可包含例如使用具有矽烷和氧氣的氣體混合物的化學氣相沉積形成的氧化矽。低溫氧化物層538可在約50℃至約200℃的範圍中的低溫沉積。低溫氧化物層538可具有在約10nm至約30nm的範圍中的厚度538t。
依據一些實施例,第一矽基層540和第二矽基層546可包含不同的材料,且可在不同的沉積製程中形成。第一矽基層540可例如透過使用具有矽、氧和碳之元素的氣體混合物的化學氣相沉積或物理氣相沉積形成。在一些實施例中,第一矽基層540可具有在約10nm至約30nm的範圍中的厚度540t。第二矽基層546可例如透過在約50℃至約200℃的範圍中的溫度在第二有機層544上旋塗矽氧烷沉積。在一些實施例中,第二矽基層546可具有在約30nm至約40nm的範圍中的厚度546t。在一些實施例中,第一矽基層540和第二矽基層546可包含相同的材料。
在一些實施例中,覆蓋層542可包含例如透過在約200℃至約500℃的範圍中的溫度使用具有矽烷和氧氣的氣體混合物的化學氣相沉積形成的氧化矽。覆蓋層542可具有在約30nm至約40nm的範圍中的厚度542t。
在第4圖的結構上沉積層的堆疊之後,可圖案化光阻層548以形成如第6圖所示的第一對通孔蝕刻開口650和652。第一對通孔蝕刻開口650和652形成之後是一個或多個蝕刻製程,蝕刻製程透過第一對通孔蝕刻開口650和652蝕刻第二矽基層546和第二有機層544以形成如第7圖所示的第二對通孔蝕刻開口750和752。在一些實施例中,第二矽基層546可透過使用具有氟碳化物(CxFy)、氮和氬的氣體混合物在乾蝕刻製程(例如反應性離子蝕刻製程)中蝕刻。此氣體混合物可具有約10%至約70%的CxFy。CxFy的流量可在約100sccm至約400sccm的範圍中,且氮和氬的流量可在約50sccm至約300sccm的範圍中。此蝕刻製程可在約10℃至約90℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行在約10秒至約90秒。
在一些實施例中,第二有機層544可透過使用具有氫、氮和氬的氣體混合物在乾蝕刻製程(例如反應性離子蝕刻製程)中蝕刻。此氣體混合物可具有約5%至約20%的氫。氫的流量可在約20sccm至約100sccm的範圍中,且氮和氬的流量可在約100sccm至約400sccm的範圍中。此蝕刻製程可在約10℃至約90℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行在約10秒至約90秒。
在透過通孔蝕刻開口650和652蝕刻第二矽基層546和第二有機層544之後,通孔蝕刻開口650和652的圖案可轉移至第二有機層546。由於存在第二矽基層546,因此在第二有機層544中被轉移的蝕刻圖案(未顯示)的寬度可能小於寬度 650w和652w。這可能是由於在第二矽基層546的蝕刻製程期間,氟化矽基的材料沉積於形成在第二矽基層546中的通孔蝕刻開口(未顯示)的側壁上。因此,蝕刻第二有機層544所通過的第二矽基層546中的通孔蝕刻開口的寬度可比寬度650w和652w更窄。因此,與光阻層548中圖案化的通孔蝕刻開口650和652的寬度相比,第二矽基層546可幫助收縮在層間介電層320中後續第12圖的通孔1250和1252。
在蝕刻第二有機層544之後,可蝕刻覆蓋層542、第一矽基層540和低溫氧化物層538以形成第二對通孔蝕刻開口750和752,如第7圖所示。在一些實施例中,覆蓋層542可透過使用具有在約100sccm至約400sccm的範圍中的流量的CxFy在乾蝕刻製程(例如反應性離子蝕刻製程)中蝕刻。此蝕刻製程可在約10℃至約90℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行在約10秒至約90秒。此蝕刻製程將通孔蝕刻開口(未顯示)從第二有機層544轉移至覆蓋層542。在蝕刻覆蓋層542期間,第二矽基層546和第二有機層544可從覆蓋層542的頂表面被蝕刻掉。
在一些實施例中,上述第5圖的層的堆疊可不包含第二有機層544和第二矽基層546。替代地,光阻層548可沉積於覆蓋層542上。在此實施例中,形成通孔蝕刻開口650和652之後,可蝕刻覆蓋層542。
第一矽基層540和低溫氧化物層538可透過在覆蓋層542中轉移的通孔蝕刻開口(未顯示)蝕刻。在一些實施例中,第一矽基層540可透過使用具有CxHyFz氣體、氧、氮和氬的氣 體混合物在乾蝕刻製程(例如反應性離子蝕刻製程)中蝕刻。此氣體混合物可具有約5%至約10%的CxHyFz以及約1%至約5%的氧。CxHyFz的流量可在約5sccm至約100sccm的範圍中,氧的流量可在約5sccm至約30sccm的範圍中,且氮和氬的流量可在約50sccm至約300sccm的範圍中。此蝕刻製程可在約10℃至約90℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行在約10秒至約90秒。
在一些實施例中,低溫氧化物層538可透過使用具有氟碳化物(CxFy)、氮和氬的氣體混合物在乾蝕刻製程(例如反應性離子蝕刻製程)中蝕刻。此氣體混合物可具有約1%至約20%的CxFy。CxFy的流量可在約10sccm至約30sccm的範圍中,且氮和氬的流量可在約600sccm至約1500sccm的範圍中。此蝕刻製程可在約10℃至約90℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行在約10秒至約90秒。
如第7圖所示,在蝕刻第一矽基層540和低溫氧化物層538期間,覆蓋層542可從第一矽基層540的頂表面被蝕刻掉。如上所述,因為在第二有機層544中轉移的通孔蝕刻開口的寬度較窄,第二對通孔蝕刻開口750和752的寬度750w和752w可比寬度650w和652w更窄。
相較於在不使用覆蓋層(例如覆蓋層542)的方法中形成的通孔蝕刻開口750*和752(如第8圖所示)中的蝕刻輪廓,覆蓋層542的存在可幫助實現在通孔蝕刻開口750和752中大致垂直的蝕刻輪廓。在個別的通孔蝕刻開口750和752中的蝕刻輪 廓中的角度A1和A2大於在個別的通孔蝕刻開口750*和752*中的蝕刻輪廓中的角度A3和A4。在一些實施例中,角度A1和A2可在約83°至約90°的範圍中,且角度A3和A4可在約65°至約70°的範圍中。角度A1和A2可為在通孔蝕刻開口750和752的個別側壁與X軸之間的角度。角度A3和A4可為在通孔蝕刻開口750*和752*的個別側壁與X軸之間的角度。因此,因為覆蓋層542在低溫氧化物層538和第一矽基層540的蝕刻製程期間幫助保護在低溫氧化物層538上的第一矽基層540,通孔蝕刻開口750和752在覆蓋層542的幫助下可實現大致垂直的蝕刻輪廓。第一矽基層540幫助防止低溫氧化物層538在橫向(例如X方向)的過蝕刻。如第8圖所示,在低溫氧化物層538中的通孔蝕刻開口750*和752*的形成期間,蝕刻掉第一矽基層540。
在通孔蝕刻開口中實現大致垂直的蝕刻輪廓可導致後續在層間介電層320中形成的通孔1250和1252(第14圖)的相似蝕刻輪廓。如上所述,通孔的大致垂直的蝕刻輪廓可幫助防止內連線結構中通孔與金屬線之間的漏電及/或接觸。
通孔蝕刻開口750和752的形成可用以形成如第9圖所示之層間介電層320中的部分通孔950和952。這些部分通孔950和952可在透過通孔蝕刻開口750和752蝕刻第一有機層536、無氮抗反射層324和層間介電層320之後形成。在一些實施例中,可在相似於第二有機層544的蝕刻製程的製程中蝕刻第一有機層536。在此蝕刻製程期間,具有相似於通孔蝕刻開口750和752的輪廓的通孔蝕刻開口(未顯示)可形成於第一有機層536和第一矽基層540中。在此蝕刻製程期間,低溫氧化物層 538可從第一有機層536的頂表面被蝕刻掉。
接著,可透過形成於第一有機層536中的通孔蝕刻開口蝕刻無氮抗反射層342和層間介電層320。在一些實施例中,無氮抗反射層342和層間介電層320可透過使用具有CxFy氣體、氧、氮和氬的氣體混合物在乾蝕刻製程(例如反應性離子蝕刻製程)中蝕刻。此氣體混合物可具有約5%至約10%的CxFy以及約1%至約5%的氧。CxFy的流量可在約10sccm至約60sccm的範圍中,氧的流量可在約5sccm至約30sccm的範圍中,且氮和氬的流量可在約5sccm至約1000sccm的範圍中。此蝕刻製程可在約10℃至約90℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行在約10秒至約90秒。
在形成部分通孔950和952之後,第一有機層536可從第一硬遮罩層328和無氮抗反射層324的頂表面移除。在移除第一有機層536之後,可繼續蝕刻層間介電層320,以將部分通孔950和952延伸至金屬氧化物層318的頂表面,如第10圖所示。在繼續蝕刻層間介電層320的期間,蝕刻第一硬遮罩層328和無氮抗反射層342以形成部分溝槽1030、1032和1034,如第10圖所示。個別部分溝槽1030、1032和1034的寬度W4、W5和W6可由上述個別溝槽蝕刻開口430、432和434的寬度W1、W2和W3所定義。在一些實施例中,溝槽寬度W4可在約85nm至約100nm的範圍中,且溝槽高度H1可在約50nm至約80nm的範圍中。
在一些實施例中,在形成部分溝槽1030、1032和1034之後,可移除第二硬遮罩層326和透過部分通孔950和952 暴露出的金屬氧化物層318的部份,如第11圖所示。第二硬遮罩層326和暴露出的金屬氧化物層318的部份可例如透過在約30℃至約10℃的範圍中的溫度使用過氧化氫的濕蝕刻製程移除。此濕蝕刻製程的蝕刻速率可在約0.2nm/sec至約0.5nm/sec的範圍中。
在移除第二硬遮罩層326和金屬氧化物層318的一部份之後,可蝕刻在層間介電層320上的無氮抗反射層324的餘留部分以及透過部分通孔950和952暴露出的襯墊316的部分。此蝕刻可導致形成如第12圖所示的溝槽1230、1232和1234以及通孔1250和1252。在一些實施例中,此蝕刻可透過使用具有CxFy氣體、氧、二氧化碳、氮和氬的氣體混合物在乾蝕刻製程(例如反應性離子蝕刻製程)中進行。此氣體混合物可具有約1%至約5%的CxFy、約1%至約5%的氧以及約1%至約5%的二氧化碳。此蝕刻製程可在約20℃至約60℃的範圍中的溫度中以及在約15mTorr至約100mTorr的範圍中的壓力下進行。在一些實施例中,可蝕刻蝕刻停止層312的一部份,以將通孔1250和1252打開至接點結構322。
第13圖顯示在不使用金屬氧化物層(例如金屬氧化物層318)的方法中形成的通孔1250*和1252*的錐形輪廓。金屬氧化物層318的存在可幫助實現通孔1250和1252的大致垂直輪廓。個別通孔1250和1252的輪廓中的角度A5和A6大於個別通孔1250*和1252*的輪廓中的角度A7和A8。在一些實施例中,A5和A6可在約70°至約80°的範圍中,且A7和A8可在約50°至約60°的範圍中。角度A7和A8可為在通孔1250和1252的個別側壁與X 軸之間的角度。角度A7和A8可為在通孔1250*和1252*的個別側壁與X軸之間的角度。
在一些實施例中,通孔1250可具有頂部寬度W7與底部寬度W8的比值在約2至約3的範圍中,且通孔1250*可具有頂部寬度W9與底部寬度W10的比值在約3至約4的範圍中,通孔1250*之頂部寬度W9與底部寬度W10的比值大於通孔1250之頂部寬度W7與底部寬度W8的比值。在一些實施例中,通孔1250可具有底部寬度W8與高度H2的比值在約45至約55的範圍中,且通孔1250*可具有底部寬度W10與高度H3的比值在約55至約65的範圍中,通孔1250*之底部寬度W10與高度H3的比值大於通孔1250之底部寬度W8與高度H2的比值。在一些實施例中,通孔1250可具有高度H2與頂部寬度W7的比值在約65至約75的範圍中,且通孔1250*可具有高度H3與頂部寬度W9的比值在約40至約50的範圍中,通孔1250*之高度H3與頂部寬度W9的比值小於通孔1250之高度H2與頂部寬度W7的比值。因此,相較於通孔1250的輪廓,通孔1250具有錐形通孔輪廓。
請參照第2圖,在操作250中,在通孔和溝槽中沉積導電材料以形成導通孔和金屬線。舉例來說,如第14圖所示,形成內連線結構1400的導通孔1410和金屬線1408。依據一些實施例,導通孔1410和金屬線1408的形成可涉及在通孔1250和1252以及溝槽1230、1232和1234中透過使用例如物理氣相沉積、化學氣相沉積或原子層沉積來沉積導電材料(例如W、Al、Co、Cu或合適的導電材料)。
上述的實施例描述實現內連線結構(例如內連線結 構1400)的通孔(例如通孔1250和1252)的大致垂直輪廓的方法。實現通孔的大致垂直輪廓可幫助防止內連線結構中通孔與金屬線之間的漏電及/或接觸。在一些實施例中,在形成通孔蝕刻開口(例如通孔蝕刻開口750和752)的期間使用氧化物覆蓋層(例如覆蓋層542)幫助實現通孔蝕刻開口的大致垂直蝕刻輪廓,進而幫助實現通孔的大致垂直輪廓。在一些實施例中,相較於在不使用金屬氧化物層的方法中形成的通孔,內連線結構的層間介電層下方存在金屬氧化物層幫助形成通孔的大致垂直輪廓。舉例來說,在內連線結構中使用金屬氧化物層形成的通孔可具有與水平軸呈約70°至約80°的範圍中之角度的通孔輪廓側壁。此角度大於不用金屬氧化物層所形成之通孔的通孔輪廓側壁的角度,不用金屬氧化物層所形成之通孔的通孔輪廓側壁的角度在約50°至約60°的範圍中。以下描述一些實施例。
在一些實施例中,半導體結構的形成方法包含在基底上形成蝕刻停止層,在蝕刻停止層上方形成金屬氧化物層,以及在金屬氧化物層上形成層間介電(ILD)層。此方法更包含在層間介電層上方形成溝槽蝕刻開口,在溝槽蝕刻開口上方形成覆蓋層,以及在覆蓋層上方形成通孔蝕刻開口。
在一些實施例中,內連線結構的形成方法包含在基底上形成蝕刻停止層,在蝕刻停止層上方形成金屬氧化物層,以及在金屬氧化物層上形成層間介電(ILD)層。此方法更包含在層間介電層上方形成低溫氧化物層,在低溫氧化物層上方形成覆蓋層,以及在覆蓋層中形成通孔蝕刻開口。
在一些實施例中,內連線結構的形成方法包含在 基底上形成蝕刻停止層,在蝕刻停止層上方形成金屬氧化物層,以及在金屬氧化物層上形成層間介電(ILD)層。此方法更包含在層間介電層中形成第一導電結構沿第一方向延伸,以及在層間介電層中和金屬氧化物層中形成第二導電結構沿第二方向延伸,第二方向垂直於第一方向。
在一些實施例中,內連線結構包含蝕刻停止層位於基底上,金屬氧化物層位於蝕刻停止層上方,層間介電(ILD)層位於金屬氧化物層上,以及導電結構位於層間介電層中,導電結構位於金屬氧化物層中和蝕刻停止層中。
在一些實施例中,積體電路包含半導體裝置和內連線結構,半導體裝置包含接點結構和耦接至接點結構的內連線結構。內連線結構包含蝕刻停止層位於半導體裝置上方,金屬氧化物層位於蝕刻停止層上方,層間介電(ILD)層位於金屬氧化物層上,以及導通孔位於金屬氧化物層和層間介電層中。
在一些實施例中,半導體結構包含蝕刻停止層位於基底上方,金屬氧化物層位於蝕刻停止層上方,以及層間介電(ILD)層位於金屬氧化物層上。半導體結構更包含第一導電結構在層間介電層中沿第一方向延伸,以及第二導電結構在層間介電層中和金屬氧化物層中沿第二方向延伸,第二方向垂直於第一方向。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解,且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構,並以此達到 相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下,可對本發明進行各種改變、置換或修改。
Claims (20)
- 一種內連線結構的形成方法,包括:在一基底上形成一蝕刻停止層;在該蝕刻停止層上方形成一金屬氧化物層;在該金屬氧化物層上形成一層間介電層;在該層間介電層上方形成一低溫氧化物層;在該低溫氧化物層上方形成一覆蓋層;以及在該覆蓋層中形成一通孔蝕刻開口。
- 如申請專利範圍第1項所述之內連線結構的形成方法,其中在該覆蓋層中形成該通孔蝕刻開口的步驟包括:在該覆蓋層上沉積一光阻層;以及透過該光阻層中的一圖案蝕刻該覆蓋層。
- 如申請專利範圍第1項所述之內連線結構的形成方法,更包括:在該層間介電層中和該金屬氧化物層上形成一通孔;以及透過該通孔蝕刻該金屬氧化物層的一部份。
- 如申請專利範圍第3項所述之內連線結構的形成方法,更包括在該通孔中沉積一導電材料。
- 如申請專利範圍第3項所述之內連線結構的形成方法,其中該通孔的側壁與一水平軸形成一角度在約70°至約80°的範圍內。
- 如申請專利範圍第1項所述之內連線結構的形成方法,其中該覆蓋層包括氧化物材料。
- 如申請專利範圍第1項所述之內連線結構的形成方法,其 中該金屬氧化物層包括鉻、鋁、鈦、錫、鋅、鎂或銀。
- 一種半導體結構的形成方法,包括:在一基底上形成一蝕刻停止層;在該蝕刻停止層上方形成一金屬氧化物層;在該金屬氧化物層上形成一層間介電層;在該層間介電層上方形成一溝槽蝕刻開口;在該溝槽蝕刻開口上方形成一覆蓋層;以及在該覆蓋層上方形成一通孔蝕刻開口。
- 如申請專利範圍第8項所述之半導體結構的形成方法,更包括在該覆蓋層與該溝槽蝕刻開口之間形成一低溫氧化物層。
- 如申請專利範圍第8項所述之半導體結構的形成方法,更包括分別在該溝槽蝕刻開口上方和該覆蓋層上方形成一第一矽基層和一第二矽基層。
- 如申請專利範圍第8項所述之半導體結構的形成方法,更包括分別在該溝槽蝕刻開口上方和該覆蓋層上方形成一第一有機層和一第二有機層。
- 如申請專利範圍第8項所述之半導體結構的形成方法,其中形成該溝槽蝕刻開口的步驟包括:在該層間介電層上沉積一無氮介電層;以及將在該無氮介電層上的一矽基層和一氮化物層圖案化。
- 如申請專利範圍第8項所述之半導體結構的形成方法,更包括:在該溝槽蝕刻開口上方形成一低溫氧化物層;以及 在該低溫氧化物層中形成一另一通孔蝕刻開口,該另一通孔蝕刻開口的寬度小於該蝕刻開口的寬度。
- 如申請專利範圍第8項所述之半導體結構的形成方法,其中該覆蓋層包括氧化物材料。
- 如申請專利範圍第8項所述之半導體結構的形成方法,更包括在該層間介電層和該金屬氧化物層中形成一通孔。
- 如申請專利範圍第8項所述之半導體結構的形成方法,更包括在該層間介電層、該金屬氧化物層和該蝕刻停止層中形成一通孔。
- 如申請專利範圍第8項所述之半導體結構的形成方法,其中該金屬氧化物層包括鉻、鋁、鈦、錫、鋅、鎂或銀。
- 一種積體電路,包括:一半導體裝置,包括一接點結構;以及一內連線結構,耦接至該接點結構,該內連線結構包括:一蝕刻停止層,位於該半導體裝置上方;一金屬氧化物層,位於該蝕刻停止層上方;一層間介電層,位於該金屬氧化物層上;以及一導通孔,位於該金屬氧化物層和該層間介電層中。
- 如申請專利範圍第18項所述之積體電路,更包括一碳層位於該金屬氧化物層與該蝕刻停止層之間。
- 如申請專利範圍第18項所述之積體電路,其中該導通孔的側壁與一水平軸形成一角度在約70°至約80°的範圍內。
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