TW201828363A - 用於三維nand硬遮罩應用的奈米結晶鑽石碳膜 - Google Patents

用於三維nand硬遮罩應用的奈米結晶鑽石碳膜 Download PDF

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TW201828363A
TW201828363A TW107102838A TW107102838A TW201828363A TW 201828363 A TW201828363 A TW 201828363A TW 107102838 A TW107102838 A TW 107102838A TW 107102838 A TW107102838 A TW 107102838A TW 201828363 A TW201828363 A TW 201828363A
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diamond layer
nanocrystalline diamond
layer
element layers
substrate
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TWI656575B (zh
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陳咏梅
倪克里斯多夫S
劉菁菁
薛君
殷正操
葛迪魯多維
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美商應用材料股份有限公司
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Abstract

本文揭露在形成半導體元件中使用的奈米結晶鑽石層以及用於形成該奈米結晶鑽石層的方法。該元件可包括:基板,該基板具有處理表面與支撐表面;元件層,該元件層形成於該處理表面上;以及奈米結晶鑽石層,該奈米結晶鑽石層形成於該處理層上,該奈米結晶鑽石層具有介於2nm至5nm之間的平均晶粒尺寸。該方法可包括:將基板定位於處理腔室中,於處理表面上沉積元件層;於該元件層上沉積奈米結晶鑽石層,該奈米結晶鑽石層具有介於2nm至5nm之間的平均晶粒尺寸;圖案化及蝕刻該奈米結晶鑽石層;蝕刻該元件層以形成特徵;以及從該元件層之表面灰化該奈米結晶鑽石層。

Description

用於三維NAND硬遮罩應用的奈米結晶鑽石碳膜
本文所揭露之實施例大體上關於包括惰性碳膜的元件。更詳言之,實施例大體上關於奈米結晶鑽石膜。
隨著半導體工業導入新一代的具有更高性能與更大功能性的積體電路(IC),形成該等IC的構件的密度增加,同時個別部件或構件之間的尺寸(dimension)、大小(size)、與間距減少。雖然在過去這樣的減少僅受限於使用光微影術界定結構的能力,但尺寸是以μm或nm測量的元件幾何特徵已產生新的限制因子,該等限制因子諸如為金屬構件的導電率、在構件之間所用的絕緣材料之介電常數、或是三維NAND或DRAM製程中的挑戰。這些限制可受惠於更耐久且更高硬度的硬遮罩。
厚的碳硬遮罩廣為所知,且常用作POR膜。然而,隨著DRAM與NAND將其規模持續縮小降至低於10nm的製程必要條件時,預料當前的碳硬遮罩組成物是不足夠的。此規模縮小將要求更高深寬比的深接觸孔或溝槽蝕刻。高深寬比蝕刻問題包括阻塞、孔洞形狀扭曲、與圖案變形、頂部關鍵尺寸膨大、線彎折、輪廓弓形化,上述問題大體上在這些應用中觀察到。許多蝕刻挑戰取決於硬遮罩材料性質。深接觸孔變形是由於硬遮罩較低密度與不良的熱導率。狹縫圖案變形或線彎折是由於硬遮罩材料較低的選擇性與應力。所以,期望有一種蝕刻硬遮罩具有更高的密度、更高的蝕刻選擇性、較低的應力、與絕佳的熱導率。
奈米結晶鑽石已知是高硬度材料。由於奈米結晶鑽石材料有諸如極高的硬度、化學惰性、及高熱導率之類的非常見之性質,所以奈米結晶鑽石材料可用於抗磨耗塗層、光學窗、表面聲波元件、與熱散播件。但是,奈米結晶鑽石膜尚未被應用於半導體製造程序。
因此,需要更高硬度的膜以用於半導體元件。
本文所揭露的實施例大體上關於奈米結晶鑽石層。藉由將晶粒尺寸控制在2nm至5nm之間,可在半導體元件相關方面利用奈米結晶鑽石膜。這些奈米結晶鑽石膜可用在各式各樣應用中,諸如奈米結晶鑽石層用作為蝕刻製程期間的硬遮罩。一個實施例中,一種元件可包括:基板,具處理表面與支撐表面;元件層,形成在該處理表面上;以及奈米結晶鑽石層,形成於該處理層上,該奈米結晶鑽石層具有介於2nm至5nm之間的平均晶粒尺寸。
另一實施例中,一種用於處理基板的方法可包括:將基板定位在處理腔室中,該基板具有處理表面與支撐表面;在該處理表面上沉積元件層;在該元件層上沉積奈米結晶鑽石層,該奈米結晶鑽石層具有介於2nm至5nm之間的平均晶粒尺寸;圖案化該奈米結晶鑽石層;蝕刻該元件層以形成特徵;以及從該元件層之表面移除任何殘留的奈米結晶鑽石層。
另一實施例中,一種元件可包括:基板,具處理表面與支撐表面;複數個元件層,形成於該處理表面上,該元件層形成三維NAND結構的一或多個部件;複數個通道,形成為穿過該元件層,該複數個通道之每一者連接該一或多個部件的至少一者;以及奈米結晶鑽石層,形成在該處理層上,該奈米結晶鑽石層具有介於2nm至5nm之間的平均晶粒尺寸。
本文揭露的實施例大體上關於基板上所形成的奈米結晶鑽石層。奈米結晶鑽石層提供更高密度、更高蝕刻選擇性、更低應力、與絕佳熱導率,上述性質是處理基板中低於10nm邊界的特徵所需。下文中,參考圖式而更清楚地描述實施例。
第1圖是CVD處理腔室100之概略剖面視圖,該CVD處理腔室100可用於根據本文所述之實施例沉積以碳為基礎之層。可適於執行本文所述之碳層沉積方法的處理腔室是PRODUCER® 化學氣相沉積腔室,該腔室可購自美國加州Santa Clara的應用材料公司。應瞭解下文所述之腔室為示範性腔室,而其他腔室(包括來自其他製造商的腔室)可與本案揭露內容之態樣一併使用或經修飾而完成本案揭露內容之態樣。
處理腔室100可為處理系統(圖中未示)的一部分,該處理系統包括多個處理腔室,該等處理腔室連接中央移送室(圖中未示)且由機器人(圖中未示)所服務。處理腔室100包括界定處理空間112的壁106、底部108、與蓋110。壁106與底部108可由單一塊鋁所製造。處理腔室100也可包括泵送環114,該泵送環114將處理空間112流體連通式(fluidly)耦接排氣口116及其他泵送部件(圖中未示)。
基板支撐組件138可被加熱,且該基板支撐組件138可置中配置在處理腔室100內。基板支撐組件138於沉積製程期間支撐基板103。基板支撐組件138大體上由鋁、陶瓷、或鋁與陶瓷之組合所製造,且包括至少一個偏壓電極132。
真空通口可用於在基板103與基板支撐組件138之間施加真空,以於沉積製程期間將基板103固定到基板支撐組件138。偏壓電極132可例如配置在基板支撐組件138中,且耦接偏壓電源130A與130B,以在處理的同時將基板支撐組件138及定位在基板支撐組件138上的基板103偏壓至預定的偏壓電力水準。
可獨立地裝設偏壓電源130A與130B,以於各種頻率將電力遞送到基板103與基板支撐組件138,該頻率諸如約1MHz至約60MHz的頻率。可不偏離本文所述之實施例而運用本文所述之頻率的各種排列組合。
大體上,基板支撐組件138耦接心柱142。心柱142提供基板支撐組件138與處理腔室100的其他部件之間的電導線、真空、與氣體供應線路所用之導管。此外,心柱142將基板支撐組件138耦接升舉系統144,該升舉系統144於升高位置(如第1圖所示)與降下位置(圖中未示)之間移動基板支撐組件138,以助於自動機械式傳送。波紋管146提供處理空間112與處理腔室100外的大氣之間的真空密封,同時助於基板支撐組件138的移動。
噴頭118可大體上耦接蓋110的內側120。進入處理腔室100的氣體(即,處理氣體與其他氣體)通過噴頭118且進入處理腔室100。噴頭118可裝設成提供均勻氣流給處理腔室100。均勻的氣流是促進基板103上均勻的層形成所期望的。包括氣體源104的遠端電漿源105可耦接處理空間112。如本文所示,諸如遠端電漿產生器之類的遠端活化源用於生成活性物種之電漿,該等活性物種之後被遞送至處理空間112中。示範性的遠端電漿產生器可購自諸如MKS Instruments公司及Advanced Energy Industries公司之類的販售商。
此外,電漿電源160可耦接噴頭118以使通過噴頭118朝向基板支撐組件138上配置的基板103的氣體賦有能量。電漿電源160可提供射頻電力。
處理腔室100之功能可由運算裝置154所控制。運算裝置154可以是任何形式的通用電腦之其中一種,該通用電腦可用在工業設施中以控制各種腔室與次處理器。運算裝置154可包括電腦處理器156與記憶體158。記憶體158可包括任何適合的記憶體,諸如隨機存取記憶體、唯讀、快閃記憶體、硬碟、或其他形式的遠端或本地端數位儲存裝置。運算裝置154可包括各種支援電路162,支援電路162可耦接電腦處理器156以用習知方式支援電腦處理器156。如需要,軟體常式可儲存於記體體158中或由位在遠端之第二運算裝置(圖中未示)所實行。
運算裝置154可進一步包括一或多個電腦可讀媒體(圖中未示)。電腦可讀媒體大體上包括任何位在遠端或本地端之裝置,該裝置能夠儲存可由運算裝置擷取之資訊。可與本文所述之實施例一併使用的電腦可讀媒體之範例包括固態記憶體、軟碟、外接或內部硬碟、與光學記憶體(例如CD、DVD、BR-D等)。一個實施例中,記憶體158可以是電腦可讀媒體。軟體常式可儲存在電腦可讀媒體上,以由運算裝置實行。
軟體常式在實行時會將通用電腦轉換成特定處理電腦,該專用處理電腦控制腔室操作而執行腔室製程。或者,軟體常式可於硬體中執行如應用專一的積體電路或其他類型的硬體實施方式,或是軟體與硬體的組合。
第2圖是根據一個實施例的上面形成有奈米結晶鑽石層的元件200,該實施例中,該元件200是NAND元件。元件200包括基板202、複數個元件層204、與奈米結晶鑽石層206。
基板202可以是此技術中已知的任何半導體基板,諸如單晶矽、四四族化合物(諸如矽鍺或矽鍺碳)、三五族化合物、二六族化合物、此類基板上的磊晶層、或任何其他半導體或非半導體材料(諸如氧化矽、玻璃、塑膠、金屬、或陶瓷基板)。基板202可包括於該基板202上製造的積體電路,諸如記憶體元件(圖中未示)用的驅動器電路。
複數個元件層204可形成於基板202之表面上。該複數個元件層204可為形成三維垂直NAND結構之部件的沉積層。由複數個元件層(例如介電質或分離式電荷儲存區段)的全部或部分所形成的部件。介電質部分可獨立地選自任何一或多種相同或不同的電絕緣材料,諸如氧化矽、氮化矽、氮氧化矽、或其他高k絕緣材料。一個實施例中,該結構可由以交替方式沉積的成對的氧化矽/氮化矽所構成。該對氧化矽/氮化矽之總寬度可介於100至600埃之間。該對氧化矽/氮化矽之數目可大於10對,諸如32對、64對、或更多對。一個實施例中,該對氧化矽/氮化矽之數目介於10至64對之間。總厚度可介於約2微米至約4微米之間。
分離式電荷儲存區段可包括導電(例如,金屬或金屬合金,諸如鈦、鉑、釕、氮化鈦、氮化鉿、氮化鉭、氮化鋯、或諸如矽化鈦、矽化鎳、矽化鈷之類的金屬矽化物、或前述材料之組合)或半導體(例如多晶矽)浮置閘極、導電奈米粒子、或分離式電荷儲存介電質(例如氮化矽或其他介電質)特徵。然而,應了解可使用介電質電荷儲存特徵或其他浮置閘極材料取代上述材料。
奈米結晶鑽石層206是結晶碳層,具有高sp3含量與小型結晶尺寸。非晶形與奈米結晶碳中最常見的化學鍵是三配位(sp2鍵結)與四配位(sp3鍵結)。sp3組態中,碳原子形成四個sp3軌域,產生對相鄰原子的強σ键。高sp3含量的碳膜中,sp3含量大於80%,諸如大於約90%、或大於約95%。本文所示之奈米結晶鑽石層206具有高sp3含量(例如,奈米結晶鑽石晶粒)且由sp2基質(例如石墨)所支撐。小結晶尺寸是小於6nm之結晶尺寸,諸如介於2nm至5nm之間。奈米結晶鑽石層可具有方均根高度差小於6nm的表面粗糙度。奈米結晶鑽石層可具有介於2.5g/cm3 至3.5g/cm3 之間的密度,諸如3g/cm3 。奈米結晶鑽石層具有介於-50MPa至-150MPa之間的應力,諸如介於-80MPa至-120MPa之間的應力。相較於當前可得的類似鑽石的碳膜,奈米結晶鑽石層可具有介於2至4之間的全面蝕刻選擇性。
元件200包括通道208。本文所示之通道208形成為穿過奈米結晶鑽石層206與複數個元件層204。通道208可實質上垂直基板202之第一表面210。例如,通道208可具有柱狀形狀。通道208可實質上垂直基板202之第一表面210延伸。視情況任選的主體接觸電極(圖中未示)可配置在基板202中,以從下方提供對通道208的連接部分的主體接觸。一些實施例中,通道208可為填充的特徵。一些其他實施例中,通道208可以是中空的。在這些實施例中,可形成絕緣填充材料212以填充由通道208所環繞的中空部分。絕緣的填充材料212可包括任何電絕緣材料,諸如氧化矽、氮化矽、氮氧化矽、或其他高k絕緣材料。
任何適合的半導體材料可用於通道208,所述材料例如矽、鍺、矽鍺、或其他化合半導體材料,諸如三五族、二六族、或者是導電(或半導體)氧化物,或是其他材料。半導體材料可為非晶形、多晶、或單晶。半導體通道材料可藉由任何適合的沉積方法形成。例如,一個實施例中,半導體通道材料是由低壓化學氣相沉積(LPCVD)所沉積。一些其他實施例中,半導體通道材料可以是藉由將最初沉積的非晶形半導體材料再結晶而形成的再結晶多晶半導體材料。
第3圖是根據一或多個實施例的方法300之流程圖,該方法300用於以奈米結晶鑽石層處理基板。用於元件層的蝕刻化學條件(etching chemistry)實質上是對奈米結晶鑽石呈惰性。就此而言,本文所述之實施例使用包括奈米結晶鑽石層的硬遮罩,而非傳統的硬遮罩。傳統的硬遮罩具有許多限制條件,這些限制條件會容許上文所述之結構性缺陷。一個範例中,頂部關鍵尺寸膨大部分是由於較少硬遮罩殘留,這是由傳統硬遮罩與下面的層之間不良的蝕刻選擇性所引發。另一範例中,深接觸孔變形是由於硬遮罩較低的密度與不良熱導率所造成。狹縫圖案變形或線彎折是由於HM材料較低的選擇性與應力所造成。奈米結晶鑽石層容許高深寬比特徵得以形成,同時避免特徵的非圓形蝕刻的弓形化與彎折以及避免上文所述之圖案崩潰,上述現象與傳統硬遮罩有關連。奈米結晶鑽石層因具高物理抵抗性、呈化學惰性、且有高熱導率而達成這些優勢。擁有高物理抵抗性及呈化學惰性容許有優於先前已知的硬遮罩更為改善的蝕刻選擇性。改良的蝕刻選擇性使良好的蝕刻輪廓得以維持。進一步而言,奈米結晶鑽石層比標準碳硬遮罩更接近鑽石,而給予層高熱導率。蝕刻製程期間,累積顯著量的熱。此熱若仍堵塞(trap)在下面的層中,會產生翹曲。奈米結晶鑽石層容許有效的熱傳,而阻止翹曲或其他與熱相關的扭曲。奈米結晶鑽石層之後可透過在含氧氣體或含氮氣體的存在下灰化而輕易且選擇性地移除。
方法300開始於302,步驟為將基板定位在處理腔室中,該基板具有處理表面與支撐表面。該基板可具任何組成,諸如結晶矽基板。該基板也可包括一或多個特徵,諸如介層窗或互連件。該基板可支撐在基板支撐件上。基板支撐件可維持在特定的溫度範圍。一個實施例中,該基板支撐件維持在介於約攝氏500度至約攝氏650度的溫度範圍中。
與一或多個實施例一併使用的處理腔室可為任何具遠端電漿源之CVD處理腔室,諸如上文所述之處理腔室100或來自其他製造商的腔室。下文所述之流速與其他處理參數是針對300mm之基板。應了解,可根據受處理之基板的尺寸以及所用的腔室類型調整這些參數但不可背離本文揭露之實施例。
如本文所用之「基板表面」是指形成於基板上且在上面可執行膜處理的任何基板或材料表面。例如,可在上面執行處理的基板表面取決於應用而包括諸如下述之材料:矽、氧化矽、氮化矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石、以及任何其他材料,諸如金屬、金屬氮化物、金屬合金、以及其他導電材料。基板表面也可包括介電材料,諸如二氧化矽以及碳摻雜的氧化矽。基板可具有各種尺寸,諸如200mm、300mm、或其他直徑的晶圓,以及矩形或方形嵌板(pane)。
於304,元件層隨後可沉積於處理表面上。元件層可以是參考第2圖所述之元件層。進一步而言,元件層可以是複數個元件層之其中一層。該等元件層可協同作用,以形成一或多個特徵或部件,諸如三維NAND元件之部件。
於306,奈米結晶鑽石層隨後沉積在元件層上。奈米結晶鑽石層可具有小於6nm之平均晶粒尺寸。一個範例中,奈米結晶鑽石層具有介於2nm至5nm之間的平均晶粒尺寸。小晶粒尺寸(諸如低於6nm)容許更好地控制硬遮罩層(諸如奈米結晶鑽石層)與下面的層之間的黏著及容許硬遮罩層有更小尺寸。沉積期間較大的晶粒尺寸的隨機定位將會增加硬遮罩層與下面的層之間的非接觸空間的數目。非接觸空間是硬遮罩層與下面的層之間硬遮罩層不直接接觸下面的層的空間,這是由於硬遮罩層的晶粒形狀與尺寸所致,且也是由於下面的層本身的粗糙度所致。較大的非接觸空間減少層的黏著,且減少硬遮罩層與下面的層之間的熱傳。非接觸空間的尺寸因較小的晶粒而減少,因為較小的晶粒在沉積為層的一部分時可比較大的晶粒更為緊密地堆積。另外,由於較小的晶粒尺寸,該層可製作得比較大的晶粒尺寸之層還要薄,同時維持與下面的層有良好的接觸。
最後,較小的晶粒尺寸容許硬遮罩層中較小的粗糙度。線寬粗糙度(LWR)亦已知為線邊緣粗糙度(LER),該線寬粗糙度是硬遮罩地勢或特徵之寬度上的過量變化。由於LWR或LER所致之粗糙度與變化可能是不利的,因為該變化可能在蝕刻期間轉移到溝槽上且最終轉移到電路。隨著硬遮罩地勢的特徵尺寸減少,這些變化變得更為顯著。從硬遮罩層形成的特徵的關鍵尺寸可透過減少LER或LWR之效應而製作得更小。可透過擁有較小的晶粒尺寸從而擁有較小粗糙度而減少LER或LWR。
奈米結晶鑽石層的沉積可開始於在第一壓力下遞送沉積氣體至遠端電漿腔室。該沉積氣體包括含碳前驅物與含氫氣體。此實施例中,含碳前驅物是烷類前驅物。該烷類前驅物可為飽和的非分支碳氫化合物,諸如甲烷、乙烷、丙烷、及前述物質之組合。其他烷類前驅物包括正丁烷、正戊烷、正己烷、正庚烷、正辛烷、及前述物質之組合。該含氫氣體可包括H2 、H2 O、NH3 、或其他含氫分子。該沉積氣體可進一步包括惰氣。該惰氣可以是稀有氣體,諸如氬氣。
沉積氣體隨後遞送至遠端電漿腔室。該沉積氣體可於腔室內混合或是在進入腔室之前先混合。沉積氣體於相對高的壓力下遞送,該壓力諸如為大於5托耳。一個實施例中,該沉積氣體是在介於約10托耳至100托耳(諸如約50托耳)之間遞送。
沉積氣體隨後可活化而產生活化的沉積氣體。沉積氣體可藉由使用電源形成電漿而活化。可使用能夠將氣體活化成反應性物種且維持反應性物種之電漿的任何電源。例如,可使用以射頻(RF)、直流(DC)、或微波(MW)為基礎的放電技術。電源產生源電漿電力,該源電漿電力被施加到遠端電漿腔室以生成且維持沉積氣體之電漿。在使用射頻電力用於源電漿電力的實施例中,對於300mm基板而言,可在從約2MHz至約170MHz的頻率及介於500瓦至5000瓦的功率水準下遞送源電漿電力(介於基板頂部表面處0.56W/cm2 至基板頂部表面處5.56W/cm2 之間)。其他實施例包括,對於300mm基板而言,在介於1000瓦至3000瓦的功率水準下遞送源電漿電力(介於基板頂部表面處1.11W/cm2 至基板頂部表面處3.33W/cm2 之間)。可根據受處理之基板的大小調整施加的功率。
根據遠端電漿腔室中的高壓及其他因素,離子化物種的形成將會最小化,同時自由基的形成會最大化。不希望受理論所限制,相信奈米結晶鑽石層應主要為sp3鍵而非sp2鍵。進一步而言,相信可藉由在沉積該層期間使自由基物種之數目增加超過離子化物種,而達成更多的sp3鍵結。離子化物種具高能量,可相較於自由基需要更多的移動空間。藉由增加壓力,電子能量減少,同時與其他分子碰撞的可能性增加。電子能量的減少及碰撞數目的增加使自由基的形成比離子形成更為有利。
一旦活化,該活化的沉積氣體隨後遞送通過具有第二壓力的第二空間。該第二空間可以是第二腔室或是處理空間與遠端電漿腔室之間的另一受限區域。一個範例中,第二空間是遠端電漿腔室與處理空間之間的連接件。
第二壓力小於第一壓力。根據流速、總體積之改變、或前述之組合的從遠端電漿腔室到第二空間的移動造成活化沉積氣體在第二空間中壓力減少。該壓力減少而容許從自由基物種更好地沉積,同時減少離子化物種與沉積層之碰撞。一個實施例中,第二壓力介於約1托耳至約5托耳之間。
活化的沉積氣體隨後遞送到處理腔室之處理空間中的基板。該基板可具任何組成,諸如結晶矽基板。該基板也可包括一或多個特徵,諸如介層窗或互連件。該基板可支撐在基板支撐件上。基板支撐件可維持在特定的溫度範圍。一個實施例中,該基板支撐件維持在介於約攝氏500度至約攝氏650度的溫度範圍中。
該基板可預先種晶(preseed)以沉積奈米結晶層。一個實施例中,該基板於種晶溶液中浸潤或以其他方式於種晶溶液中塗布。種晶溶液是以乙醇為基礎的奈米鑽石懸浮液。該基板於超音波處理期間在該懸浮液中浸潤,而使懸浮的奈米鑽石中的一些奈米鑽石黏著到基板表面。可運用其他的預先種晶技術,但不可背離本文所述之實施例。
與一或多個實施例一併使用的處理腔室可以是具遠端電漿源的任何CVD處理腔室,諸如上文所述之處理腔室100或購自其他製造商的腔室。下文所描述之流速與其他處理條件處理參數是針對300mm之基板。應了解,可根據受處理之基板的尺寸以及所用的腔室類型調整這些參數但不可背離本文揭露之實施例。
如本文所用之「基板表面」是指形成於基板上且在上面可執行膜處理的任何基板或材料表面。例如,可在上面執行處理的基板表面取決於應用而包括諸如下述之材料:矽、氧化矽、氮化矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石、以及任何其他材料,諸如金屬、金屬氮化物、金屬合金、以及其他導電材料。基板表面也可包括介電材料,諸如二氧化矽以及碳摻雜的氧化矽。基板可具有各種尺寸,諸如200mm、300mm、或其他直徑的晶圓,以及矩形或方形嵌板(pane)。
處理空間於第三壓力接收活化的沉積氣體,該第三壓力小於第二壓力。該第三壓力可以是低於2托耳之壓力,諸如介於約500毫托耳至1托耳之間的壓力。
奈米結晶鑽石層之後沉積於基板表面上。來自先前形成的活化沉積氣體之自由基沖射於基板表面上,以形成奈米結晶鑽石層。相信低壓對於從遠端形成之自由基在奈米結晶鑽石層中形成sp3鍵結是有利的。遠端電漿源中較高的壓力容許優先形成自由基,而處理空間中的低壓容許從先前形成的自由基中有更均勻的沉積。
一旦沉積奈米結晶鑽石層,則將含氫氣體遞送到遠端電漿腔室。含氫氣體可於各別的時間遞送,或可從前一步驟維持該氣體流動。此部分無烷類前驅物存在。含氫氣體可以惰氣遞送,或作為多種含氫氣體的組合的一部分。
含氫氣體隨後活化而產生活化含氫氣體。使用相同的壓力、溫度、功率類型、功率範圍、與其他形成電漿之參數(如參考形成活化沉積氣體所討論之參數),可將含氫氣體轉換成電漿。
一旦形成活化的含氫氣體,該氣體可遞送至處理空間中的基板。該處理空間與基板可維持在相同壓力、溫度、及前文所述之其他參數。沉積製程期間,相信聚合物可形成於沉積的奈米結晶鑽石層之表面上。該等聚合物可影響進一步之沉積,且另外劣化沉積之層的性能。藉由將活化的含氫氣體遞送到沉積之層,該等聚合物成為揮發性,且可隨後從腔室移除,使得他們不會影響後續的沉積製程。
之後可重覆上述構件以沉積期望厚度的奈米結晶鑽石堆疊。每一沉積循環產生介於約20埃至約200埃的厚度,諸如約100埃。藉由重覆上述步驟,先前的層作為下一沉積之種晶層,而容許總體期望厚度得以沉積。一個實施例中,奈米結晶鑽石堆疊沉積達1µm厚。
元件層可預先種晶以供沉積奈米結晶鑽石層。一個實施例中,基板於種晶溶液中浸潤或以其他方式於種晶溶液中塗布。種晶溶液是以乙醇為基礎的奈米鑽石懸浮液。該基板於超音波處理期間在該懸浮液中浸潤,而使懸浮的奈米鑽石中的一些奈米鑽石黏著到基板表面。可運用其他的預先種晶技術,但不可背離本文所述之實施例。
可使用沉積氣體沉積奈米結晶鑽石層。該沉積氣體包括含碳前驅物與含氫氣體。此實施例中,含碳前驅物可以是烷類、烯類、或炔類前驅物。烷類前驅物可以是飽和的非分支碳氫化合物,諸如甲烷、乙烷、丙烷、及前述物質之組合。其他烷類前驅物包括正丁烷、正戊烷、正己烷、正庚烷、正辛烷、及前述物質之組合。該含氫氣體可包括H2 、H2 O、NH3 、或其他含氫分子。該沉積氣體可進一步包括惰氣。該惰氣可以是稀有氣體,諸如氬氣。
於308,隨後可圖案化及蝕刻奈米結晶鑽石層。圖案化可包括於奈米結晶鑽石層上沉積光阻。該光阻隨後暴露至適當波長的輻射,以產生圖案。之後將該圖案蝕刻進入光阻、再進入奈米結晶鑽石層。
於構件310,之後可蝕刻元件層以形成特徵。以形成於奈米結晶鑽石層中的圖案,之後可蝕刻元件層。元件層是藉由蝕刻劑蝕刻,該蝕刻劑對元件層有優於奈米結晶鑽石層的選擇性。元件層是以此技術中廣為所知的化學條件與技術所蝕刻。一個實施例中,蝕刻劑是含氯蝕刻劑。
於構件312,奈米結晶鑽石層隨後可從元件層之表面移除。奈米結晶鑽石層可例如透過使用電漿灰化製程從元件層表面灰化。電漿灰化製程可包括活化含氧氣體(諸如O2 )。當使用O2 時,灰化速率為約900埃/分或更高。奈米結晶鑽石層可使用高深寬比蝕刻系統灰化,該系統諸如Centura Avatar蝕刻系統,可購自位在美國加州Santa Clara的應用材料公司。
表1顯示非晶形碳硬遮罩(ACH)與奈米結晶鑽石硬遮罩之間的蝕刻選擇性比較及伴隨的膜性質。 1
該等膜在矽基板上沉積至均勻厚度。所沉積的第一膜是ACH膜。該ACH膜是使用CVD製程從甲烷與含氫前驅物沉積。在攝氏550度的沉積溫度下,沉積速率是約2500埃/分。RMS粗糙度為約0.46。密度為1.45g/cm3 。應力為約50MPa,且熱導率為低於1W/(m*K)。經標準化至標準ACH膜的ACH之全面蝕刻選擇性為約1。ACH膜可由O2 與N2 電漿處理移除。
沉積的第二膜是NCD膜。NCD膜是使用MWCVD製程從甲烷與含氫前驅物沉積。在攝氏600度的沉積溫度下,沉積速率是約170埃/分。RMS粗糙度為約7.54。密度為3.2g/cm3 。應力為約-207MPa,且熱導率為約12W/(m*K)。經標準化至標準ACH膜的NCD之全面蝕刻選擇性為約2.4。NCD膜可由O2 與N2 電漿處理移除。
上表呈現ACH與NCD膜之全面膜性質(諸如蝕刻速率、選擇性、與可剝除性)之間的比較。如本文所示,NCD膜具有比ACH膜高得多的蝕刻選擇性。進一步而言,NCD可由相同蝕刻製程蝕刻及剝除。
雖然前述內容涉及設備與方法之實施例,但可不背離該設備與方法之基本範疇而設計其他與進一步的實施例,且該設備與方法之範疇由隨後的申請專利範圍所決定。
100‧‧‧處理腔室
103‧‧‧基板
104‧‧‧氣體源
105‧‧‧遠端電漿源
106‧‧‧壁
110‧‧‧蓋
112‧‧‧處理空間
114‧‧‧泵送環
116‧‧‧排氣口
118‧‧‧噴頭
130A‧‧‧偏壓電源
130B‧‧‧偏壓電源
132‧‧‧偏壓電極
138‧‧‧基板支撐組件
142‧‧‧心柱
144‧‧‧升舉系統
146‧‧‧波紋管
154‧‧‧運算裝置
156‧‧‧電腦處理器
158‧‧‧記憶體
160‧‧‧電源
162‧‧‧支援電路
200‧‧‧元件
202‧‧‧基板
204‧‧‧元件層
206‧‧‧奈米結晶鑽石層
208‧‧‧通道
210‧‧‧第一表面
212‧‧‧絕緣填充材料
300‧‧‧方法
302-312‧‧‧構件
透過參考其中一些繪示於附圖中的實施例,可得到上文簡要總結的實施例之更詳細之敘述,如此可得到詳細地瞭解本案之實施例之上述特徵的方式。然而,應注意附圖僅繪示典型實施例,因此不應被視為限制實施例之範疇。
第1圖是根據一或多個實施例所裝設的CVD處理腔室之概略剖面視圖;
第2圖是根據一或多個實施例的奈米結晶鑽石層的側視圖;以及
第3圖是根據一或多個實施例的以奈米結晶鑽石層處理基板的方法的流程圖。
為了助於瞭解,如可能則已使用相同的元件符號指定各圖共通的相同元件。此外,一個實施例中揭露的構件可有利地用在其他實施例上而無需贅述。
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Claims (20)

  1. 一種處理基板之方法,包括下述步驟: 在複數個元件層上沉積一奈米結晶鑽石層,包括下述步驟:藉由使用一微波電源形成一電漿,而活化一沉積氣體,其中該沉積氣體包括一含碳前驅物與一含氫氣體;以及將該複數個元件層暴露至經活化的該沉積氣體,以在該複數個元件層上沉積該奈米結晶鑽石層,其中該奈米結晶鑽石層接觸該複數個元件層的至少一個元件層,且該奈米結晶鑽石層具有小於6奈米的平均晶粒尺寸。
  2. 如請求項1所述之方法,進一步包括下述步驟: 圖案化及蝕刻該奈米結晶鑽石層; 蝕刻該複數個元件層以形成一特徵,其中該特徵形成在該複數個元件層與該奈米結晶鑽石層中;以及移除該奈米結晶鑽石層。
  3. 如請求項2所述之方法,其中該特徵之深寬比大於50:1。
  4. 如請求項1所述之方法,其中該複數個元件層包括氧化矽、氮化矽、氮氧化矽、或前述材料之組合。
  5. 如請求項1所述之方法,其中該複數個元件層形成一3D NAND結構的多個部件。
  6. 如請求項5所述之方法,其中該複數個元件層包括以交替方式沉積的氧化矽/氮化矽對。
  7. 如請求項1所述之方法,其中該含碳前驅物是一烷類前驅物,該烷類前驅物選自甲烷、乙烷、丙烷、正丁烷、正戊烷、正己烷、正庚烷、正辛烷、及前述物質之組合的群組。
  8. 如請求項7所述之方法,其中該含氫氣體選自H2 、H2 O、及NH3
  9. 一種處理基板之方法,包括下述步驟: 在複數個元件層上沉積一奈米結晶鑽石層,包括下述步驟:將一沉積氣體遞送至處於第一壓力的一遠端電漿腔室,其中該沉積氣體包括一含碳前驅物與一含氫氣體;藉由使用一微波電源形成一電漿,而活化該沉積氣體;將經活化的該沉積氣體遞送到處於第二壓力的一第二空間(volume),其中該第二壓力小於該第一壓力;將經活化的該沉積氣體遞送到該複數個元件層,該複數個元件層定位在處於第三壓力的一處理空間中,其中該第三壓力小於該第二壓力;以及在該複數個元件層的至少一個元件層上沉積該奈米結晶鑽石層,其中該奈米結晶鑽石層接觸該至少一個元件層,且該奈米結晶鑽石層具有小於6奈米的平均晶粒尺寸。
  10. 如請求項9所述之方法,進一步包括下述步驟: 圖案化及蝕刻該奈米結晶鑽石層; 蝕刻該複數個元件層以形成一通道,其中該通道形成在該複數個元件層與該奈米結晶鑽石層中;以及移除該奈米結晶鑽石層。
  11. 如請求項10所述之方法,其中該通道之深寬比大於50:1。
  12. 如請求項9所述之方法,其中該複數個元件層包括氧化矽、氮化矽、氮氧化矽、或前述材料之組合。
  13. 如請求項9所述之方法,其中該複數個元件層形成一3D NAND結構的多個部件。
  14. 如請求項13所述之方法,其中該複數個元件層包括以交替方式沉積的氧化矽/氮化矽對。
  15. 如請求項9所述之方法,其中該沉積氣體進一步包括氬氣。
  16. 如請求項9所述之方法,其中該第一壓力介於約10托耳及約100托耳之間。
  17. 如請求項16所述之方法,其中該第二壓力介於約1托耳及約5托耳之間。
  18. 如請求項17所述之方法,其中該第一壓力介於約500毫托耳及約1托耳之間。
  19. 如請求項1所述之方法,其中該含碳前驅物是一烷類前驅物,該烷類前驅物選自甲烷、乙烷、丙烷、正丁烷、正戊烷、正己烷、正庚烷、正辛烷、及前述物質之組合的群組。
  20. 如請求項19所述之方法,其中該含氫氣體選自H2 、H2 O、及NH3
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI697104B (zh) * 2018-10-26 2020-06-21 大陸商長江存儲科技有限責任公司 3d nand記憶體元件的結構及其形成方法
TWI723856B (zh) * 2020-04-28 2021-04-01 逢甲大學 大氣常壓低溫電漿沉積抗刮疏水層的方法
TWI725430B (zh) * 2019-03-29 2021-04-21 大陸商長江存儲科技有限責任公司 具有氮化矽的閘極到閘極介電質層的記憶堆疊體及其形成方法
US11373865B2 (en) 2020-03-11 2022-06-28 Kioxia Corporation Method for manufacturing semiconductor device having a film with layers of different concentrations of elements

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10249495B2 (en) * 2016-06-28 2019-04-02 Applied Materials, Inc. Diamond like carbon layer formed by an electron beam plasma process
US10760157B2 (en) * 2016-08-09 2020-09-01 Akhan Semiconductor, Inc. Thin film diamond coating system and method
US10858727B2 (en) 2016-08-19 2020-12-08 Applied Materials, Inc. High density, low stress amorphous carbon film, and process and equipment for its deposition
US11043372B2 (en) * 2017-06-08 2021-06-22 Applied Materials, Inc. High-density low temperature carbon films for hardmask and other patterning applications
KR102227347B1 (ko) * 2017-09-05 2021-03-11 어플라이드 머티어리얼스, 인코포레이티드 3d 메모리 구조들에서의 고종횡비 홀 형성에 대한 상향식 접근법
CN107946311B (zh) * 2017-11-21 2020-09-25 长江存储科技有限责任公司 控制3d nand闪存结构中沟道关键尺寸的方法
KR20220143158A (ko) * 2018-01-15 2022-10-24 어플라이드 머티어리얼스, 인코포레이티드 원격 플라즈마 산화에 대한 아르곤 추가
CN108315818A (zh) * 2018-05-02 2018-07-24 苏州贝莱克晶钻科技有限公司 单晶金刚石合成装置和方法
KR20200086141A (ko) * 2019-01-08 2020-07-16 삼성전자주식회사 실리콘 질화물용 식각제 조성물 및 반도체 소자의 제조 방법
JP2020191427A (ja) 2019-05-23 2020-11-26 東京エレクトロン株式会社 ハードマスク、基板処理方法及び基板処理装置
US11384428B2 (en) * 2019-07-19 2022-07-12 Applied Materials, Inc. Carbon layer covered mask in 3D applications
TW202201483A (zh) 2020-02-19 2022-01-01 日商東京威力科創股份有限公司 基板處理方法及基板處理系統
US20230142791A1 (en) 2020-03-31 2023-05-11 Toray Industries, Inc. Inorganic solid object pattern manufacturing method and inorganic solid object pattern
US11594416B2 (en) 2020-08-31 2023-02-28 Applied Materials, Inc. Tribological properties of diamond films
US20220127721A1 (en) * 2020-10-23 2022-04-28 Applied Materials, Inc. Depositing Low Roughness Diamond Films
KR102528990B1 (ko) * 2020-12-28 2023-05-03 알에프에이치아이씨 주식회사 다이아몬드 기판, 다이아몬드 커버, 다이아몬드 플레이트 및 반도체 패키지의 제조 공정, 및 이를 이용하여 제조된 반도체 패키지
US11521926B2 (en) 2021-03-10 2022-12-06 Nanya Technology Corporation Semiconductor device structure with serpentine conductive feature and method for forming the same
US11946134B2 (en) * 2022-01-27 2024-04-02 Applied Materials, Inc. In situ nucleation for nanocrystalline diamond film deposition
US20230260800A1 (en) * 2022-02-15 2023-08-17 Applied Materials, Inc. Methods to reduce uncd film roughness
CN115632048B (zh) * 2022-09-23 2023-08-01 北京科技大学 一种具有纳米金刚石钝化层的TaN薄膜电阻器及其制备方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2666172B1 (fr) * 1990-08-24 1997-05-16 Thomson Csf Transistor de puissance et procede de realisation.
US6811612B2 (en) * 2000-01-27 2004-11-02 The University Of Chicago Patterning of nanocrystalline diamond films for diamond microstructures useful in MEMS and other devices
US6673684B1 (en) * 2002-07-31 2004-01-06 Advanced Micro Devices, Inc. Use of diamond as a hard mask material
JP2004111704A (ja) 2002-09-19 2004-04-08 Mitsubishi Electric Corp メンブレンマスクの製法および該製法を用いたメンブレンマスク
JP2004176132A (ja) * 2002-11-27 2004-06-24 Toppan Printing Co Ltd ナノダイヤモンド膜及びその製造方法
US7306778B2 (en) * 2003-06-19 2007-12-11 Nanotech Llc Diamond films and methods of making diamond films
US7128889B2 (en) * 2003-06-26 2006-10-31 Carlisle John A Method to grow carbon thin films consisting entirely of diamond grains 3-5 nm in size and high-energy grain boundaries
JP2005039082A (ja) * 2003-07-16 2005-02-10 Toppan Printing Co Ltd マスクブランクス及びステンシルマスク及びその製造方法及びその露光方法
WO2005116306A1 (ja) * 2004-05-27 2005-12-08 Toppan Printing Co., Ltd. ナノクリスタルダイヤモンド膜、その製造方法、及びナノクリスタルダイヤモンド膜を用いた装置
US7394103B2 (en) * 2004-09-13 2008-07-01 Uchicago Argonne, Llc All diamond self-aligned thin film transistor
EP1929064A1 (en) * 2005-09-29 2008-06-11 UAB Research Foundation Ultra smooth nanostructured diamond films and compositions and methods for producing same
TWI395335B (zh) * 2006-06-30 2013-05-01 Applied Materials Inc 奈米結晶的形成
JP2009091234A (ja) * 2007-09-18 2009-04-30 Tokyo Univ Of Science 導電性ダイヤモンド膜が形成された基板及び導電性ダイヤモンド膜が形成された基板の製造方法
US8008095B2 (en) * 2007-10-03 2011-08-30 International Business Machines Corporation Methods for fabricating contacts to pillar structures in integrated circuits
US8793866B1 (en) * 2007-12-19 2014-08-05 Western Digital (Fremont), Llc Method for providing a perpendicular magnetic recording head
US8470701B2 (en) 2008-04-03 2013-06-25 Advanced Diamond Technologies, Inc. Printable, flexible and stretchable diamond for thermal management
KR20110120661A (ko) * 2010-04-29 2011-11-04 주식회사 하이닉스반도체 비휘발성 메모리 장치 및 그의 제조 방법
JP2013534058A (ja) * 2010-06-30 2013-08-29 サンディスク テクノロジィース インコーポレイテッド 超高密度垂直nandメモリデバイスおよびそれを作る方法
JP2012151187A (ja) * 2011-01-17 2012-08-09 Toshiba Corp 半導体記憶装置の製造方法
JP2012227326A (ja) * 2011-04-19 2012-11-15 Toshiba Corp 不揮発性半導体記憶装置とその製造方法
US20130175546A1 (en) 2012-01-06 2013-07-11 Akhan Technologies, Inc. Diamond Semiconductor System and Method
KR102015578B1 (ko) * 2012-09-11 2019-08-28 삼성전자주식회사 불휘발성 메모리 장치 및 그 형성방법
JP5951442B2 (ja) * 2012-10-17 2016-07-13 株式会社半導体エネルギー研究所 半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI697104B (zh) * 2018-10-26 2020-06-21 大陸商長江存儲科技有限責任公司 3d nand記憶體元件的結構及其形成方法
US11856776B2 (en) 2018-10-26 2023-12-26 Yangtze Memory Technologies Co., Ltd. Structure of 3D NAND memory device and method of forming the same
TWI725430B (zh) * 2019-03-29 2021-04-21 大陸商長江存儲科技有限責任公司 具有氮化矽的閘極到閘極介電質層的記憶堆疊體及其形成方法
US11373865B2 (en) 2020-03-11 2022-06-28 Kioxia Corporation Method for manufacturing semiconductor device having a film with layers of different concentrations of elements
TWI785338B (zh) * 2020-03-11 2022-12-01 日商鎧俠股份有限公司 半導體裝置的製造方法
TWI723856B (zh) * 2020-04-28 2021-04-01 逢甲大學 大氣常壓低溫電漿沉積抗刮疏水層的方法

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