TW201743384A - 使用導線架條製造晶圓級封裝及相關裝置 - Google Patents
使用導線架條製造晶圓級封裝及相關裝置 Download PDFInfo
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- TW201743384A TW201743384A TW106104872A TW106104872A TW201743384A TW 201743384 A TW201743384 A TW 201743384A TW 106104872 A TW106104872 A TW 106104872A TW 106104872 A TW106104872 A TW 106104872A TW 201743384 A TW201743384 A TW 201743384A
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- Prior art keywords
- mold
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- polymer layer
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- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 150000001875 compounds Chemical class 0.000 claims abstract description 34
- 229920000642 polymer Polymers 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 238000000465 moulding Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- 239000011253 protective coating Substances 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000002519 antifouling agent Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002611 lead compounds Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012766 organic filler Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
提供一種使用嵌埋式導線架條製造晶圓級封裝之方法及其產生的裝置。具體實施例包括將晶粒置放到模具內並使各晶粒之主動側面向該模具之表面;將導線架條置放於該模具上,其中該導線架條包括安置於各晶粒間的已蝕刻部分及半蝕刻部分;將模具蓋置放於該模具及晶粒上方;以及在介於該等晶粒與模具蓋之間的空間中添加成型化合物。
Description
本揭露係關於半導體封裝。特別的是,本揭露係關於多晶片晶圓級封裝。
三維晶圓級晶片尺度封裝(3D-WLCSP)是一種開發中的技術,在行動與射頻(RF)領域中有具備顯著效益的潛能。然而,從扇出WLCSP封裝件頂端安裝之晶片或封裝件到印刷電路板(PCB)有不良的熱轉移路徑,對於手機應用而言,由於沒有氣流且散熱有限制,這是主要的熱轉移路徑。
習知的程序一直嘗試著解決熱轉移問題。有一些程序是將電氣絕緣材料置放於晶片週圍,並包封於成型化合物(mold compound)中。電氣貫孔是在電氣絕緣材料中形成,而不是在成型化合物中形成。其它程序利用以導線架為基礎之打線接合組合件,具有自封裝件的底側延展之曝露的散熱片接腳。輸入/輸出(I/O)需要打線接合。另外的程序利用以導線架為基礎之覆晶組合件,具有自中心至曝露之底端封裝件表面提供直接熱路徑之散熱片。其它
程序利用介於頂端上所堆疊之晶片與PCB之間的貫穿模具貫孔(TMV)。然而,這些習知的程序並未提供充分的熱處理路徑。
因此,需要能夠改善頂端封裝件與PCB之間的熱轉移之方法及其產生的裝置。
本揭露之一態樣是一種提供嵌埋式導線架條之方法,其改善頂端封裝件與PCB之間的熱轉移。
本揭露之另一態樣是一種包括嵌埋式導線架條之裝置,其改善頂端封裝件與PCB之間的熱轉移。
本揭露之附加態樣及其它特徵將會在以下說明中提出,並且對於審查以下內容之所屬技術領域中具有通常知識者部分將會顯而易見,或可經由實踐本揭露來學習。可如隨附申請專利範圍中特別指出的內容來實現並且獲得本揭露的優點。
根據本揭露,一些技術功效可藉由一種方法來部分達成,其包括將晶粒置放到模具內並使各晶粒之主動側面向該模具之表面;將導線架條置放於該模具上,其中該導線架條包括安置於各晶粒間的已蝕刻部分及半蝕刻部分;將模具蓋置放於該模具及晶粒上方;以及在介於該等晶粒與模具蓋之間的空間中添加成型化合物。
本揭露之態樣包括將該模具翻轉180度;以及固化該成型化合物,其中該導線架條包括銅、或以保護性塗料塗佈之銅。其它態樣包括將含有該等晶粒之該已固
化成型化合物從該模具及模具蓋移除。附加態樣包括在該等晶粒之非主動側上形成第一聚合物層;以及固化該聚合物層。其它態樣包括圖型化該第一聚合物層。又進一步態樣包括該第一聚合物層含有聚亞醯胺。態樣包括在該圖型化第一聚合物層上方形成金屬層;以及圖型化該金屬層。其它態樣包括在該金屬層上方形成第二聚合物層;以及固化該第二聚合物層。附加態樣包括該金屬層包括銅、及含有聚亞醯胺之第二聚合物層。進一步態樣包括圖型化該第二聚合物層。又其它態樣包括在該圖型化第二聚合物層上方形成凸塊下敷金屬(UBM);將該等晶粒翻轉180度;在該等晶粒之間的該成型化合物中形成貫孔;在該等貫孔中形成金屬;以及在該等成型化合物、貫孔及導線架條上方形成背面金屬層並予以圖型化。其它態樣包括在該背面金屬層上方形成第三聚合物層並予以圖型化;在該圖型化第三聚合物層上方形成球柵陣列(BGA)接墊;對該UBM塗敷焊球;對該等BGA接墊塗敷焊球;將印刷電路板附接至對該UBM塗敷之該等焊球;以及將封裝件附接至對該等BGA接墊塗敷之該等焊球。
本揭露之另一態樣是一種裝置,其包括附接至模具之晶粒;附接至該模具之導線架條,其中該導線架條包括安置於各晶粒間的已蝕刻部分及半蝕刻部分;該模具及晶粒上方所形成之模具蓋;以及該等晶粒與模具蓋之間的空間中所形成之成型化合物,其中該導線架條之該等已蝕刻部分接觸該模具及模具蓋。
態樣包括該成型化合物是在該導線架條之該半蝕刻部分之上表面上形成。其它態樣包括該導線架條包括金屬。進一步態樣包括該導線架條之該等半蝕刻部分相鄰於該等晶粒之各側。又其它態樣包括該金屬包含銅、或以保護性塗料塗佈之銅。附加態樣包括各晶粒之主動側面向該模具之表面。
根據本揭露,一些技術功效亦可藉由一種方法來部分達成,其包括將晶粒置放到模具內並使各晶粒之主動側面向該模具之表面;將導線架條置放於該模具上;將模具蓋置放於該模具及晶粒上方;以及在該等晶粒與模具蓋之間的空間中添加聚合物成型化合物。其中該金屬導線架條包含安置於各晶粒間的已蝕刻部分及半蝕刻部分,而且該金屬導線架條之該等半蝕刻部分相鄰於該等晶粒之各側。
態樣包括將該模具翻轉180度;固化該成型化合物;將含有該等晶粒之該已固化成型化合物從該等模具及模具蓋移除,其中該金屬導線架條包括銅、或以保護性塗料塗佈之銅。
本揭露之附加態樣及技術功效經由以下詳細說明對於所屬技術領域中具有通常知識者將會輕易地變為顯而易見,其中本揭露之具體實施例單純地藉由經深思用以實行本揭露之最佳模式的說明來描述。如將會瞭解的是,本揭露能夠是其它及不同的具體實施例,而且其數項細節能夠在各種明顯方面進行修改,全都不會脫離本揭
露。因此,圖式及說明本質上要視為說明性,而不是作為限制。
101‧‧‧晶粒
103‧‧‧模具
107、109‧‧‧區域
111‧‧‧成型化合物
113‧‧‧模具蓋
117、121、133‧‧‧聚合物層
119‧‧‧金屬層
123‧‧‧開口
125‧‧‧UBM
127‧‧‧TMV
129‧‧‧金屬
131‧‧‧背面金屬層
135‧‧‧開口
137‧‧‧BGA接墊
139、141‧‧‧焊球
143‧‧‧主機板
145‧‧‧晶片封裝件
本揭露是在隨附圖式的附圖中舉例來說明,但非作為限制,圖中相同的元件符號係指類似的元件,並且其中:第1A至1Q圖根據一例示性具體實施例,示意性繪示半導體封裝程序流程。
在底下的說明中,為了解釋,提出許多特定細節以便透徹理解例示性具體實施例。然而,應顯而易知的是,沒有這些特定細節或利用均等配置也可實踐例示性具體實施例。在其它實例中,眾所周知的結構及裝置是以方塊圖形式來展示,為的是要避免不必要地混淆例示性具體實施例。另外,除非另有所指,本說明書及申請專利範圍中用來表達成分、反應條件等等之量、比率、及數值特性的所有數字都要了解為在所有實例中是以「約」一語來修飾。
本揭露因應並解決目前在晶圓級封裝中熱轉移不足的問題。根據本揭露之具體實施例,沿著封裝件之邊緣設置導線架條,以提供充分的熱轉移,並且防止對封裝件及週圍組件造成損壞。
根據本揭露之具體實施例之方法包括將晶粒置放到模具內並使各晶粒之主動側面向該模具之表面;
在該模具上形成並蝕刻導線架條,其中該導線架條之已蝕刻及半蝕刻部分是在各晶粒之間形成;將模具蓋置放於該模具及晶粒上方;以及在介於該晶粒與模具蓋之間的空間中添加成型化合物。
單純地藉由所思及之最佳模式的描述,還有其它態樣、特徵、以及技術功效經由下文的詳細說明對於所屬技術領域中具有通常知識者將顯而易知,其中表示並且說明的是較佳具體實施例。本揭露能夠是其它及不同的具體實施例,而且其數項細節能夠在各種明顯方面進行修改。因此,圖式及說明本質上要視為說明性,而不是作為限制。
言及第1A圖,在模具103上置放個別晶粒101,其是來自已被薄化並分切的已製作晶圓。將晶粒101置放並固定至該模具,並且使各晶粒之主動側面向模具103表面。言及第1B圖,所示為其中一個晶粒101的截面圖,且其主動側面向模具103表面。在將其置放於模具103上之前,先在單獨的製造程序中形成並蝕刻導線架條。該導線架條是由兩個區域107及109所構成。該導線架之區域107未經受蝕刻,而且是全厚度區域。區域109是半蝕刻區域。導線架區域107及109是由銅或其它傳導金屬所組成。該傳導金屬可用諸如鎳之保護性塗料來鍍覆。導線架區域107及109一完成,便接著將已完成的導線架條置放到模具103上,使得該導線架條安置於模具103中的晶粒101之各側週圍。
第1C圖是該導線架之俯視圖,該導線架圍繞模具103上方之晶粒101。如圖所示,區域107及109是在晶粒101週圍,以交替圖型存在於晶粒101之各側上。在第1C圖中,區域107是該導線架區域之全厚度區域,而區域109是該導線架之半蝕刻區域。
言及第1D圖,成型化合物111施配於該模具上方,而模具蓋113置放於模具103上方,以容許成型化合物111之壓縮成型。由於該導線架之半蝕刻區域109,故允許成型化合物111跨佈晶粒101並且在這些晶粒之間流動。該導線架之區域107有足以接觸該模具蓋之高度,如第1D圖所示。該成型化合物可以是有機填充物並且由矽土所組成。儘管所述為壓縮成型,但其它成型技巧也可用於扇出WLSCP。
成型化合物111一旦固化,便移除模具103及模具蓋113,並且將晶粒101翻轉180度,如第1E圖所示。言及第1E圖,對各晶粒101之主動側塗敷聚合物層117。將諸如聚亞醯胺之第一聚合物層117塗敷並固化至約略5微米至10微米之厚度。如第1F圖所示,曝露並顯影第一聚合物層117以形成圖型。言及第1G圖,在聚合物層117上方沉積並圖型化金屬層119,例如銅層。金屬層119當作重分佈層(RLD),用於使I/O接墊可用。在第1H圖中,在金屬層119上方將第二聚合物層121沉積並固化至約略5微米至10微米之厚度。正如第一聚合物層117,第二聚合物層121可以是聚亞醯胺。言及第1I圖,曝露並
顯影第二聚合物層121以向下形成開口123至金屬層119。
言及第1J圖,在開口123中及第二聚合物層121上方形成複數個UBM 125。如第1K圖所示,將晶粒101翻轉180度,並且在成型化合物111中將TMV 127向下形成至金屬層119。第1L圖是封裝之俯視圖,其繪示各晶粒101之各側上的成型化合物111中所形成之TMV 127。在第1M圖中,在TMV 127中填充金屬129,並且在該導線架條之成型化合物111、金屬填充TMV 127及區域107上方形成背面金屬層131並予以圖型化。
言及第1N圖,第三聚合物層是在背面金屬層131中的開口135上方及之間形成、曝露並顯影。在第1O圖中,BGA接墊137是在圖型化的第三聚合物層133上方、及第三聚合物層133之開口135中形成。如第1P圖所示,對UBM 125塗敷焊球139。在第1Q圖中,對BGA接墊137塗敷焊球141。PCB或主機板143是塗敷至對UBM 125塗敷之焊球139。頂端晶片封裝件145是附接至對BGA接墊137塗敷之焊球141。
本揭露之具體實施例可達到數種技術功效,包括改善結合至3D WLCSP封裝件之晶片/封裝件與PCB之間的熱轉移。本揭露之具體實施例可允許另外的RF整合,諸如加入射頻矽絕緣體(RF-SOI)功率放大器(PA)之濾波器。相較於3D貫穿矽貫孔(TSV),本揭露之具體實施例有助於降低3D WLCSP的成本,尤其是在I/O要求較低的RF領域中。利用本案的具體實施例改善熱轉移可擴大
應用空間。本案之具體實施例之導線架條為打線接合四面扁平無導線(QFN)及四面扁平封裝件(QFP)提供低成本技術,並且非常適用於以條體為基礎之整合。本揭露在各種工業應用之任一者中享有產業利用性,例如,微處理器、智慧型手機、行動電話、蜂巢式手機、機上盒、DVD錄影機與播放器、車輛導航、印表機與週邊裝置、網路與電信設備、遊戲系統、以及數位照相機。因此,本揭露在各種類型之高度整合型半導體裝置之任一者中享有產業利用性。
在前述說明中,本揭露是參照其具體例示性具體實施例來說明。然而,明顯的是,可對其實施各種修改和變更而不脫離本揭露較廣之精神與範疇,如申請專利範圍所提。本說明書及圖式從而要視為說明性而非作為限制。了解的是,本揭露能夠使用各種其它組合及具體實施例,並且如本文中所表達,能夠在本發明概念的範疇內作任何變更或修改。
101‧‧‧晶粒
103‧‧‧模具
107‧‧‧區域
111‧‧‧成型化合物
113‧‧‧模具蓋
Claims (20)
- 一種方法,包含:將晶粒置放到模具內並使各晶粒之主動側面向該模具之表面;將導線架條置放於該模具上,其中,該導線架條包括安置於各晶粒間的已蝕刻部分及半蝕刻部分;將模具蓋置放於該模具及晶粒上方;以及在介於該等晶粒與模具蓋之間的空間中添加成型化合物。
- 如申請專利範圍第1項所述之方法,還包含:將該模具翻轉180度;以及固化該成型化合物,其中,該導線架條包含銅、或以保護性塗料塗佈之銅。
- 如申請專利範圍第2項所述的方法,還包含:將含有該等晶粒之該已固化成型化合物從該模具及模具蓋移除。
- 如申請專利範圍第3項所述之方法,還包含:在該等晶粒之非主動側上形成第一聚合物層;以及固化該聚合物層。
- 如申請專利範圍第4項所述之方法,還包含:圖型化該第一聚合物層。
- 如申請專利範圍第5項所述之方法,其中,該第一聚合物層包含聚亞醯胺。
- 如申請專利範圍第5項所述之方法,還包含:在該圖型化第一聚合物層上方形成金屬層;以及圖型化該金屬層。
- 如申請專利範圍第7項所述之方法,還包含:在該金屬層上方形成第二聚合物層;以及固化該第二聚合物層。
- 如申請專利範圍第8項所述之方法,其中,該金屬層包含銅,而該第二聚合物層包含聚亞醯胺。
- 如申請專利範圍第8項所述之方法,還包含:圖型化該第二聚合物層。
- 如申請專利範圍第10項所述之方法,還包含:在該圖型化第二聚合物層上方形成凸塊下敷金屬(UBM);將該等晶粒翻轉180度;在該等晶粒之間的該成型化合物中形成貫孔;在該等貫孔中形成金屬;以及在該成型化合物、貫孔及導線架條上方形成背面金屬層並予以圖型化。
- 如申請專利範圍第11項所述之方法,還包含:在該背面金屬層上方形成第三聚合物層並予以圖型化;在該圖型化第三聚合物層上方形成球柵陣列(BGA)接墊;對該UBM塗敷焊球; 對該等BGA接墊塗敷焊球;將印刷電路板附接至對該UBM塗敷之該等焊球;以及將封裝件附接至對該等BGA接墊塗敷之該等焊球。
- 一種裝置,包含:晶粒,附接至模具;導線架條,附接至該模具,其中,該導線架條包括安置於各晶粒間的已蝕刻部分及半蝕刻部分;模具蓋,形成在該模具及晶粒上方;以及成型化合物,形成在該等晶粒與模具蓋之間的空間中,其中,該導線架條之該等已蝕刻部分接觸該模具及模具蓋。
- 如申請專利範圍第13項所述之裝置,其中:該成型化合物是在該導線架條之該半蝕刻部分之上表面上形成。
- 如申請專利範圍第13項所述之裝置,其中,該導線架條包含金屬。
- 如申請專利範圍第15項所述之裝置,其中,該導線架條之該等半蝕刻部分相鄰於該等晶粒之各側。
- 如申請專利範圍第15項所述之裝置,其中,該金屬包含銅、或以保護性塗料塗佈之銅。
- 如申請專利範圍第13項所述之裝置,其中,各晶粒之 主動側面向該模具之表面。
- 一種方法,包含:將晶粒置放到模具內並使各晶粒之主動側面向該模具之表面;將導線架條置放於該模具上;將模具蓋置放於該模具及晶粒上方;以及在該等晶粒與模具蓋之間的空間中添加聚合物成型化合物,其中,該金屬導線架條包含安置於各晶粒間的已蝕刻部分及半蝕刻部分,而且該金屬導線架條之該等半蝕刻部分相鄰於該等晶粒之各側。
- 如申請專利範圍第19項所述之方法,還包含:將該模具翻轉180度;固化該成型化合物;將含有該等晶粒之該已固化成型化合物從該模具及模具蓋移除,其中,該金屬導線架條包含銅、或以保護性塗料塗佈之銅。
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US15/175,290 | 2016-06-07 |
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US11380616B2 (en) * | 2018-05-16 | 2022-07-05 | Intel IP Corporation | Fan out package-on-package with adhesive die attach |
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US6184575B1 (en) * | 1994-08-26 | 2001-02-06 | National Semiconductor Corporation | Ultra-thin composite package for integrated circuits |
US7772036B2 (en) | 2006-04-06 | 2010-08-10 | Freescale Semiconductor, Inc. | Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing |
US9305859B2 (en) | 2006-05-02 | 2016-04-05 | Advanced Analogic Technologies Incorporated | Integrated circuit die with low thermal resistance |
US9711343B1 (en) * | 2006-12-14 | 2017-07-18 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US7842542B2 (en) * | 2008-07-14 | 2010-11-30 | Stats Chippac, Ltd. | Embedded semiconductor die package and method of making the same using metal frame carrier |
US20100133682A1 (en) | 2008-12-02 | 2010-06-03 | Infineon Technologies Ag | Semiconductor device |
US8354304B2 (en) * | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
US9064936B2 (en) * | 2008-12-12 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
US8766428B2 (en) * | 2009-12-02 | 2014-07-01 | Stats Chippac Ltd. | Integrated circuit packaging system with flip chip and method of manufacture thereof |
US8916481B2 (en) * | 2011-11-02 | 2014-12-23 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
US9159643B2 (en) * | 2012-09-14 | 2015-10-13 | Freescale Semiconductor, Inc. | Matrix lid heatspreader for flip chip package |
US8975735B2 (en) * | 2013-08-08 | 2015-03-10 | Infineon Technologies Ag | Redistribution board, electronic component and module |
US9620388B2 (en) * | 2013-08-23 | 2017-04-11 | Texas Instruments Incorporated | Integrated circuit package fabrication with die attach paddle having middle channels |
TWI651387B (zh) * | 2013-09-30 | 2019-02-21 | 漢高智慧財產控股公司 | 用於大型晶粒半導體封裝之導電黏晶薄膜及供其製備之組合物 |
US9257419B2 (en) * | 2014-03-17 | 2016-02-09 | Freescale Semiconductor Inc. | Leadframe-based system-in-packages having sidewall-mounted surface mount devices and methods for the production thereof |
US10665475B2 (en) * | 2014-06-11 | 2020-05-26 | Texas Instruments Incorporated | Quad flat no lead package and method of making |
US9263299B2 (en) * | 2014-07-02 | 2016-02-16 | Nxp B.V. | Exposed die clip bond power package |
JP6357371B2 (ja) * | 2014-07-09 | 2018-07-11 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
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US20180122730A1 (en) | 2018-05-03 |
US10304763B2 (en) | 2019-05-28 |
TWI641058B (zh) | 2018-11-11 |
CN107481943A (zh) | 2017-12-15 |
US9892999B2 (en) | 2018-02-13 |
CN107481943B (zh) | 2021-01-08 |
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