TW201737491A - 半導體開關結構 - Google Patents
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- TW201737491A TW201737491A TW106111774A TW106111774A TW201737491A TW 201737491 A TW201737491 A TW 201737491A TW 106111774 A TW106111774 A TW 106111774A TW 106111774 A TW106111774 A TW 106111774A TW 201737491 A TW201737491 A TW 201737491A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000004888 barrier function Effects 0.000 description 12
- 230000005669 field effect Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910001922 gold oxide Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K2017/6878—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors using multi-gate field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一種半導體開關結構的實施例,包含源極接觸、汲極接觸、閘極與鰭片。接觸與閘極沿著第一方向延伸並且在垂直第一方向的第二方向上彼此間隔。閘極散佈於接觸之間。鰭片位於接觸與閘極兩者之下。鰭片沿第二方向延伸並且在第一方向上彼此間隔。接觸柱延伸穿過接觸之一,並且未碰觸閘極或鰭片。閘極柱延伸穿過閘極之一,並且未碰觸接觸或鰭片。接觸-閘極柱與接觸與閘極碰觸,但未與鰭片碰觸。
Description
本發明實施例係關於半導體積體電路,更具體關於半導體開關結構。
電源閘(power gating)是低功耗應用的一種技術。藉由電源閘,高速晶片可以保持高頻率運作,但沒有使用的區段會關閉以節省功耗。這樣的技術可以藉由使用半導體場效電晶體(field effect transistor,FET)開關達到,其中需要極小的導通電阻(Ron)與高的導通電流-斷路電流比例。晶片的電阻電位降(IR drop)希望盡可能的越小越好。當元件尺寸縮小,前段製程(front-end-of-line,FEOL)因為擴散而電阻上升、接觸區域縮小。而且,後段製程(back-end-of-line,BEOL)因為縮小金屬導體的寬度與通柱尺寸而電阻上升。
本揭露的一態樣是提供半導體開關結構,包含:一接觸,接觸包含源極接觸與汲極接觸,一閘極,其中
接觸與閘極沿著第一方向延伸並在垂直於第一方向的第二方向上彼此間隔,其中閘極散佈於接觸之間,一鰭片,其位於接觸與閘極兩者之下,沿第二方向延伸並且在第一方向彼此間隔,一接觸柱,其沿伸穿過接觸之一,且未與閘極或鰭片碰觸,一閘極柱,其沿伸穿過閘極之一,且未與接觸或鰭片碰觸,以及一接觸-閘極柱,其與接觸與閘極兩者碰觸,但未與鰭片碰觸。
9‧‧‧開關
10‧‧‧開關結構
10’‧‧‧開關結構
11‧‧‧控制電路
12‧‧‧邏輯區
21‧‧‧源極接觸
22‧‧‧汲極接觸
23‧‧‧閘極
24‧‧‧鰭片
24T‧‧‧鰭片的上表面
24S‧‧‧鰭片的相對側表面
25‧‧‧通柱
30‧‧‧覆蓋區域
31‧‧‧邊緣
40、41、42‧‧‧矩形區域
40D、41D、42D‧‧‧矩形區域的縱向延伸長度
40L、41L、42L‧‧‧矩形區域縱向延伸的左邊緣
40T、41T、42T‧‧‧矩形區域橫向延伸的上邊緣
40R、41R、42R‧‧‧矩形區域縱向延伸的右邊緣
40B、41B、42B‧‧‧矩形區域橫向延伸的下邊緣
40W、41W、42W‧‧‧矩形區域的橫向延伸寬度
50‧‧‧未覆蓋區域
51‧‧‧電路的其他組件
60‧‧‧無鰭區域
S1、S2‧‧‧鰭片到鰭片的間距
121‧‧‧源極接觸
122‧‧‧汲極接觸
123‧‧‧閘極
124‧‧‧鰭片
125‧‧‧閘極柱
126‧‧‧側絕緣屏障
127‧‧‧上絕緣屏障
為了讓本案內容敘述更易懂,在讀以下描述的時候應參照圖示。要注意的是,依據實際業界的作法,許多特徵並非依照比例繪製。實際上,各種特徵的尺寸可能會任意的增大或縮小,以使所述更為清楚。所附圖式之說明如下:
第1圖與第2圖根據一些實施例繪示兩個包含例示性鰭式場效電晶體開關的例示性電路。
第3圖為根據一些實施例的例示性開關結構的透視圖。
第4圖為根據一些實施例的開關結構的上視圖。
第5圖為根據一些實施例對應第4圖線5-5的剖面圖。
第6圖為根據一些實施例對應第4圖線6-6的剖面圖。
第7圖類似於第4圖,根據一些實施例繪示了開關結構佔據的矩形區域的邊緣。
第8圖根據一些實施例繪示開關結構相對於聯絡開關結構的鄰近電路位置的例示性位置。
第9圖類似於第4圖,根據一些實施例繪示了替代開關結構的上視圖。
第10圖為側視圖,對應第6圖的線10-10,繪示開關結構的閘極柱對準開關結構的閘極中間的配置。
第11圖為類似於第10圖的側視圖,繪示開關結構的閘極柱未對準閘極中間並且碰觸開關結構的源極的配置。
第12圖為類似於第10圖的側視圖,根據一個不同的實施例,屏障材料位於源極之上與旁邊。
第13圖為類似於第12圖的側視圖,繪示閘極柱未對準準閘極中間並且藉屏障材料與源極隔開。
以下公開提供許多不同實施例,或示例,以建置所提供之標的物的不同特徵。以下敘述之成份和排列方式的特定示例是為了簡化本公開。這些當然僅是做為示例,其目的不在構成限制。舉例而言,元件的尺寸不被揭露之範圍或數值所限制,但可以取決於元件之製程條件與/或所需的特性。此外,第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接接觸的實施例,也包含有其他特徵形成在第一特徵和第二特徵之間,以致第一特徵和第二特徵沒有直接接觸的實施例。為了簡單與清晰起見,不同特徵可以任意地繪示成不同大小。
再者,空間相對性用語,例如「下方(beneath)」、「在…之下(below)」、「低於(lower)」、
「在…之上(above)」、「高於(upper)」等,是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關係。空間相對性用語除了圖式中所描繪的方向外,還包含元件在使用或操作時的不同方向。儀器可以其他方式定向(旋轉90度或在其他方向),而本文所用的空間相對性描述也可以如此解讀。
在本說明書的某些情況下,一個詞彙之後的括號中會有替代詞彙或基本相等的詞彙。
第1圖與第2圖繪示包含開關9的例示性電路,開關9由控制器11(控制電路)所控制。在此示例中,開關9為場效電晶體(field effect transistor,FET)。場效電晶體9的功能為從電源VDD選擇性導通電路至邏輯區12的開關。第1圖中,開關9在電路的頂部區域(header region),從電源電壓VDD提供電流至邏輯區12。第2圖中,邏輯區12從VDD直接獲取電流,而開關9位於電路的底部區域(footer region),從邏輯區12獲取電流至接地(Gnd)。
第3圖與第4圖依序為例示性開關9的結構10的透視圖以及上視圖。開關結構10包含源極接觸21、汲極接觸22以及閘極23。接觸21、22與閘極23在縱向延伸(第4圖中箭頭A),並且在垂直於縱向的橫向彼此間隔(第4圖中箭頭B)。縱向A與橫向B可以依序稱為第一方向與第二方向。閘極23位於源極接觸21與汲極接觸22之間。而接觸21、22位於兩閘極23之間。開關結構10包含橫向延伸的重複的閘極、源極、閘極、汲極的序列。閘極23散佈(交織)於接觸
21、22之間。
接觸21、22與閘極23電性與物理連接至位於接觸21、22與閘極23之下的一系列鰭片24。鰭片24在橫向延伸並且在縱向彼此間隔。接觸21、22與閘極23直接碰觸其下的鰭片24,其間沒有任何中間層。第5圖與第6圖繪示鰭片24的剖面圖,其中鰭片24的寬度在各圖中水平延伸。如第5圖所示,在此示例中的接觸21、22直接碰觸鰭片24的上表面24T整個寬度(或基本上整個寬度,例如超過全部寬度的95%),並且未與鰭片24的相對側表面24S碰觸。如第6圖所示,在此示例中的閘極23直接碰觸鰭片24的上表面24T整個寬度(或基本上整個寬度,例如超過全部寬度的95%),並且與鰭片24的每個相對側表面24S的整個高度(或基本上整個高度,例如超過全部高度的95%)碰觸。
如第3-4圖所示,開關結構10更包含不同的通柱25。接觸柱(源極柱或汲極柱)延伸穿過接觸21、22,且未與閘極23或鰭片24碰觸。閘極柱延伸穿過閘極23,且未與接觸21、22或鰭片24碰觸。接觸-鰭片柱與接觸21、22以及鰭片24碰觸,且未與閘極23碰觸。閘極-鰭片柱與閘極23與鰭片24碰觸,且未與接觸21、22碰觸。
接觸21、22、閘極23與鰭片24覆蓋整個覆蓋區域30,覆蓋區域30具有如第4圖虛線所示的多邊形邊緣31。
如第7圖的粗矩形輪廓所示,在這個示例中整個覆蓋區域30包括較窄的矩形區域40、第一較寬的矩形區域41以及第二較寬的矩形區域42。
每個矩形區域40、41、42由縱向延伸的左邊緣40L、41L、42L(第一側邊緣)與縱向延伸的右邊緣40R、41R、42R(第二側邊緣)界定,其中左邊緣與右邊緣一起依序界定矩形區域40、41、42的橫向延伸寬度40W、41W、42W。第一較寬的矩形區域41的寬度41W大於第二較寬的矩形區域42的寬度42W,寬度42W本身大於較窄的矩形區域40的寬度40W。每個矩形區域40、41、42更由橫向延伸的上邊緣40T、41T、42T以及橫向延伸的下邊緣40B、41B、42B界定,其上邊緣與下邊緣界定各自的矩形區域40、41、42的縱向延伸長度40D、41D、42D。
較窄的矩形區域40與第一較寬的矩形區域41鄰接較窄的矩形區域40的下邊緣40B,下邊緣40B與第一較寬的矩形區域41的上邊緣41T重合。較窄的矩形區域40與第二較寬的矩形區域42鄰接較窄的矩形區域40的上邊緣40T,上邊緣40T與第二較寬的矩形區域42的下邊緣42B重合。
第一較寬的矩形區域的左邊緣41L位於較窄的矩形區域的左邊緣40L的左側。第一較寬的矩形區域41的左突出41LP向左延伸超過較窄的矩形區域的左邊緣40L。第一較寬的矩形區域的右邊緣41R位於較窄的矩形區域的左邊緣40R的右側。第一較寬的矩形區域41的右突出41RP向右延伸超過較窄的矩形區域的右邊緣40R。
第二較寬的矩形區域的左邊緣42L與較窄的矩形區域的左邊緣40L共線。第二較寬的矩形區域的右邊緣
42R位於較窄的矩形區域的右邊緣40R的右側。第二較寬的矩形區域42的右突出42RP向右延伸超過較窄的矩形區域的右邊緣40R。
較窄的矩形區域40與第一較寬的矩形區域41一起組成開關結構佔據的T型第一覆蓋區域。較窄的矩形區域40與第二較寬的矩形區域42一起組成開關結構佔據的L型第二覆蓋區域。
一些接觸21、22與一些閘極23延伸完全(基本上完全)穿過較窄的矩形區域40與第一和第二較寬的矩形區域41、42。那些接觸21、22與閘極23因此也延伸完全(基本上完全)穿過第一與第二覆蓋區域兩者。位於較寬的矩形區域的突出41LP、41RP、42RP中的其餘的接觸21、22與其餘的閘極23並未延伸入較窄的矩形區域40。
一些鰭片24延伸完全(基本上完全)穿過較窄的矩形區域40。其餘的鰭片24延伸完全(基本上完全)穿過第一較寬的矩形區域41。還有其他的鰭片24延伸完全(基本上完全)穿過第二較寬的矩形區域42。
在此示例中,整個第一覆蓋區域(包含40與41),與整個第二覆蓋區域(包含40與42),具有以下特徵:接觸21、22的橫向延伸寬度是一致的,可以為6-30nm。閘極23的橫向延伸寬度是一致的,可以為10-30nm。鰭片24的縱向延伸寬度是一致的,可以為4-15nm。閘極23與閘極鄰近的接觸21、22之間的橫向延伸間隔是一致的,可以為6-30nm。相鄰的鰭片之間的縱向延伸間隔是一致的,可以
為10-40nm。鰭片到鰭片的間距是一致的,可以為10-40nm。上述各參數的範圍(如有關寬度、間隔、間距的參數)為例示性的範圍。減小這些參數的每一個值可能的優點為可以實現更小的電路尺寸。減小這些參數的每一個值的另一個可能的優點為實現閘極、接觸與鰭片數量增加,以及增加閘極與鰭片之間和接觸和鰭片之間的接觸面積,這些會形成較低的導通電阻。另一方面,增加這些參數的每一個值可能的優點為藉由每個組件可以相對於組件的整體尺寸定位,以實現較好的精度。因此,上述的每個參數範圍可以最佳化,以平衡小尺寸與較低的導通電阻的優點以及相對定位精準的優點。
每個突出41LP、41RP、42RP可以位於聯絡開關結構10的電路之上或之下,或向外延伸以接合或鄰近聯絡開關結構10的電路。舉例來說,第一較寬的矩形區域的左突出41LP向左延伸至控制開關結構10的控制電路11(第1-2圖)。第一較寬的矩形區域的右突出41RP可以位於開關結構控制電流流向(選擇性導通)的邏輯電路12之上或之下。第二較寬的矩形區域的右突出42RP可以位於另一個電路、邏輯單元、頂部單元與/或TAP單元區域之上或之下,或相鄰於另一個電路、邏輯單元、頂部單元與/或TAP單元區域。
開關結構10包含未覆蓋區域50(第8圖),如開關覆蓋區域未向外延伸的區域。這些未覆蓋區域50沒有開關結構10的組件,並為電路的其他組件51(例如邏輯組件)
騰出空間。
舉例來說,接觸21、22可以由一或多種選自鋁、鈷、銅、鎢或其他適合材料的材料構成。
舉例來說,閘極23可以由一或多種選自氮化鈦、鎢、銅、鈷或其他適合材料的材料構成。
舉例來說,鰭片24可以由一或多種選自矽、矽鍺、砷化矽鍺或其他適合材料的材料構成。
如果開關結構10位於頂部區域(如第1圖),開關結構10為P型金氧半場效電晶體(PMOS)。如果開關結構10位於底部區域(如第2圖),開關結構10為N型金氧半場效電晶體(NMOS)。
第8圖繪示一個半導體元件內開關結構10外面的電路位置的示例,其位置相對於開關結構10。控制電路12可以控制頂部和底部的開關結構10的開與關(第1圖與第2圖)。TAP區域(單元)可以界定阱電壓(VDD的N阱與GND的P阱)。
第9圖繪示另一個開關結構10’,其類似於第3-4圖的開關結構10,並且具有與開關結構10一樣的形狀與尺寸。開關結構10’與第3-4圖的例示性開關結構10不同的地方在於,開關結構10’具有缺乏鰭片的無鰭區域60(也就是不含鰭片)。相較於開關結構10’的其他區域(無鰭區域60之上與之下)的鰭片到鰭片的間距(S2),開關結構10’的無鰭區域60具有更大的鰭片到鰭片的間距(S1)。相反的,因為沒有無鰭區域,第3-4圖的開關結構10的鰭片到鰭片的間
距在整個開關結構中是一致的。在第9圖中,全部的閘極柱(延伸穿過閘極23的通柱25)位於無鰭區域60中。相反的,在第3-4圖的示例中,一些閘極柱25位於鰭片24的正上方,而其他在非無鰭區域內的閘極柱則位於兩鄰近鰭片24之間。第3-4圖的開關結構10具有一系列連續的鰭片,不會被無鰭區域中斷。相對於第9圖的開關結構10’,開關結構10就好像是第9圖的無鰭區域60的上下合在一起,而除去無鰭區域60。第3-4圖的開關結構10缺乏無鰭區域,這提供了相較於第9圖的開關結構10’在同樣的覆蓋區域下較大數量的鰭片。
第3-4圖的例示性鰭式場效電晶體開關結構非常適用於低電壓的應用,像是電源電壓VDD為1.1V或更小,例如0.3V-1.1V。其中一個理由為此例示性開關結構10並不具有如開關結構10’的無鰭區域。先前技術的開關結構具有無鰭區域是因為後述理由。未完全對準閘極中間的不對齊的閘極柱,可能會碰觸(接觸)鄰近的源極/汲極接觸。在先前技術中,為了避免閘極柱碰觸源極/汲極接觸,在閘極柱的附近,先前技術的源極/汲極接觸的上表面位於相對於鄰近閘極的上表面較低的水平。在閘極柱附近,接觸上表面相對於閘極上表面的降低避免了不對齊的閘極柱碰觸接觸。在先前技術中,為了幫助降低接觸的上表面,在閘極柱的附近移除了一或多個鰭片。相對於先前技術,第3-4圖的例示性鰭式場效電晶體中閘極柱的附近,鄰近的接觸21、22位於鰭片24之上。
如上述說明,第3-4圖的開關結構10缺乏無鰭區域,而是完全被鰭片覆蓋。因此,就每個區域的鰭片數量而言,第3-4圖的開關結構10較包含無鰭區域的第9圖的開關結構10’多。當第3-4圖的開關結構10的鰭片數量越多(相較於第9圖的開關結構10’),產生越大的開關覆蓋區域30的每個單位區域的鰭片接觸面積(如鰭片24碰觸接觸21、22與閘極23)。越大的鰭片接觸面積,反過來說就是產生越小的導通電阻,因為導通電阻與鰭片接觸面積呈現負相關。較低的導通電阻,可以讓第3-4圖的開關結構在較低的電源電壓下運作。這是因為降低導通電阻可以增加電流,而且因此抵消在較低的電源電壓下可能發生的電流減少。
另一個第3-4圖的鰭式場效電晶體開關結構非常適用於低電壓應用的理由是開關的覆蓋區域(由邊緣31環繞)沒有限制為單一矩形,而是沿著向外突出超過窄矩形40的基於突出的圖案(突出41LP、41RP、42RP)。突出41LP、41RP、42RP延伸進入半導體元件的小空位,這些小空位在開關覆蓋區域限制為單一矩形時,開關無法延伸進入其中。舉例來說,相較於無法延伸進入小空位的單一矩形,突出可以提供增加40%或50%以上的覆蓋區域。突出可以在頂部/底部區域外增加額外的鰭片區域。第3-4圖基於突出的開關結構10中覆蓋區域較大,所產生的導通電阻也比不包含突出的開關結構低。較低的導通電阻,也就是說,可以讓基於突出的開關結構10在相較於未含有突出的開關結構更低的電源電壓下運作。
第3-4圖開關結構10基於突出的圖案也允許與聯絡開關結構的外部電路重疊,而不是藉由一個水平距離外的金屬線來與外部電路聯絡。藉由讓開關結構10的鰭片24延伸至開關覆蓋區域30之上與其他邏輯的覆蓋區域之中(如另一個鰭式場效電晶體或非鰭式場效電晶體),可以實現非矩形的形狀。
第10圖是一部分開關結構10的側視圖,對應第6圖的線10-10。第10圖繪示源極接觸21、汲極接觸22、位於鰭片24之上的閘極23與位於閘極23之上的閘極柱25。閘極柱25準確對準閘極23的中間,並且與源極接觸21和汲極接觸22間隔開。第11圖是類似於第10圖的側視圖,其繪示閘極柱25並未準確對準閘極23中間的配置。閘極柱25相對於閘極23而言偏離中心(未對準),且碰觸源極22。
第12-13圖是類似於第10-11圖的側視圖,其根據一個有助於避免閘極柱碰觸源極與汲極的實施例繪示。類似第10圖的實施例,第12圖的實施例具有源極接觸121、汲極接觸122與位於鰭片124之上的閘極123與位於閘極123之上的閘極柱125。然而,第12圖的實施例與第10圖的實施例不同的地方如下所述。屏障材料的側絕緣屏障126配置於閘極123與接觸121、122之間。接觸121、122的上表面較閘極123的上表面低。絕緣材料的上絕緣屏障127(如與屏障126一樣的屏障材料)位於每個接觸121、122之上。上絕緣屏障127具有與接觸121、122的上表面同水平(如共平面)的上表面。如第13圖所示,如果閘極柱125沒有對齊而朝向
其中一個接觸122,閘極柱125會被接觸122的上屏障材料接觸127擋住。此外,側絕緣屏障126避免閘極柱125與接觸121、122的側面碰觸。
在一個實施例中,半導體開關結構包含源極接觸、汲極接觸、閘極與鰭片。接觸與閘極沿縱向延伸,並在垂直於縱向的橫向彼此間隔。閘極散佈於接觸之間。鰭片位於接觸與閘極兩者之下。鰭片沿橫向延伸並且在縱向彼此間隔。接觸柱延伸穿過接觸之一,且未與閘極或鰭片碰觸。閘極柱延伸穿過閘極之一,且未與接觸或鰭片碰觸。接觸-閘極柱與接觸和閘極碰觸,未與鰭片碰觸。
在另一個實施例中,半導體開關結構包含源極接觸、汲極接觸與閘極。接觸與閘極沿縱向延伸並且在垂直於縱向的橫向彼此間隔。閘極散佈於接觸之間。鰭片位於接觸與閘極兩者之下。鰭片沿橫向延伸並且在縱向彼此間隔。一覆蓋區域,其中開關結構延伸穿過覆蓋區域,覆蓋區域由鄰接在一起的較窄的矩形區域與較寬的矩形區域界定。每個較窄的矩形區域與較寬的矩形區域由界定各矩形橫向延伸寬度的縱向延伸的左邊緣與縱向延伸的右邊緣一起界定,其中較寬的矩形區域的寬度比較窄的矩形區域的寬度大。每個較窄的矩形區域與較寬的矩形區域更由界定較窄的矩形縱向延伸長度的橫向延伸的上邊緣與橫向延伸的下邊緣一起界定。較窄的矩形區域與較寬的矩形區域藉由較窄的矩形區域的橫向延伸邊緣之一鄰接在一起,較窄的矩形區域的橫向延伸邊緣之一與較寬的矩形區域的橫向延伸邊緣之一重
合。至少一接觸延伸完全穿過較窄的矩形區域與較寬的矩形區域兩者。
在另一個實施例中,半導體開關結構包含源極接觸、汲極接觸與閘極。接觸與閘極沿著縱向延伸並且在垂直於縱向的橫向上彼此間隔。閘極散佈於接觸之間。鰭片位於接觸與閘極之下。鰭片沿著橫向延伸並且在縱向上彼此間隔。每一個鰭片包含一上表面與兩相對側表面。每一個接觸沿著鰭片的上表面的全寬與鰭片的兩相對側表面的全高至少與一個鰭片直接碰觸。
前面概述了幾個實施例或示例的特徵,使得本領域之技術人員可以更好地理解本揭露的方面。本領域技術人員應當理解,他們可以容易地使用本揭露作為設計或修改用於實現與本揭露之實施例或示例的相同目的與/或實現相同優點的其他製程和結構之基礎。本領域技術人員還應當瞭解,這樣的等同結構不脫離本揭露的精神和範圍,在不脫離本揭露之精神和範圍內,當可作各種之更動、替換和更改。
10‧‧‧開關結構
21‧‧‧源極接觸
22‧‧‧汲極接觸
23‧‧‧閘極
24‧‧‧鰭片
25‧‧‧通柱
Claims (1)
- 一種半導體開關結構,包含:一接觸,該接觸包含源極接觸與汲極接觸;一閘極,其中該接觸與該閘極沿一第一方向延伸並在垂直於該第一方向的一第二方向上彼此間隔,其中該閘極散佈於該接觸之間;一鰭片,其位於該接觸與該閘極兩者之下,沿該第二方向延伸並且在該第一方向彼此間隔;一接觸柱,沿伸穿過該接觸之一,且未與該閘極或該鰭片碰觸;一閘極柱,沿伸穿過該閘極之一,且未與該接觸或該鰭片碰觸;以及一接觸-閘極柱,與該接觸與該閘極兩者碰觸,但未與該鰭片碰觸。
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