TW201737471A - Memory structure and manufacturing method of the same - Google Patents

Abstract

A memory structure and a manufacturing method of the same are provided. The memory structure includes a bottom oxide layer, a first conductive layer, a first insulation recess, a plurality of insulating layers, a plurality of second conductive layers, a second insulation recess, a channel layer, and a memory layer. The first conductive layer is located on the bottom oxide layer. The first insulation recess penetrates through the first conductive layer and is located on the bottom oxide layer, the first insulation recess having a first width. The insulating layers are located on the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess penetrates through the insulating layers and the second conductive layers and located on the first insulation recess, the second insulation recess having a second width larger than the first width. The channel layer is located on at least a sidewall of the second insulation recess. The memory layer is located between the channel layer and the second conductive layers.

Description

Memory structure and manufacturing method thereof

The present disclosure relates to a memory structure and a method of fabricating the same, and more particularly to a three-dimensional memory structure and a method of fabricating the same.

The non-volatile memory component has the characteristics that the data stored in the component does not disappear due to the interruption of the power supply, and thus becomes one of the memory components currently commonly used for storing data. Flash memory is a typical non-volatile memory technology.

A method for fabricating a non-volatile memory component having a vertical channel, such as a vertical channel NAND flash memory, is generally formed by stacking a plurality of insulating layers and a polysilicon layer on a semiconductor substrate to form a multilayer stacked structure, and then stacking the multilayer structure. Forming a through opening to expose the substrate to the outside; and sequentially blanketing the memory layer on the sidewall of the through opening, such as a 矽-矽 oxide-tantalum nitride-矽 oxide-矽 (SONOS) memory layer and a polysilicon channel The layer is used to define a plurality of memory cells on the memory layer, the channel layer, and the polysilicon layer.

However, as the use of memory components has increased, the demand for memory components has also tended to be smaller in size and larger in memory capacity. In response to this demand, it is necessary to manufacture a memory device having a high component density and a small size, and thus the difficulty of the process is improved.

Accordingly, it would be desirable to provide a vertical channel flash memory component and method of fabricating the same that addresses the problems faced by the prior art.

The disclosure relates to a memory structure and a method of fabricating the same. In the embodiment, in the memory structure, two grooves are respectively formed by two etching processes, so that the depth of the entire groove can be easily controlled, and the width of the second insulating groove is larger than the width of the first insulating groove, so The etching process of the second insulating recess can be easily aligned with the position of the first insulating recess.

According to one embodiment of the present disclosure, a memory structure is proposed. The memory structure includes a bottom oxide layer, a first conductor layer, a first insulating recess, a plurality of insulating layers, a plurality of second conductor layers, a second insulating recess, a channel layer, and a memory layer. The first conductor layer is on the bottom oxide layer. The first insulating recess passes through the first conductor layer and is located on the bottom oxide layer, and the first insulating recess has a first width. The insulating layer is on the first conductor layer. The second conductor layer and the insulating layer are alternately stacked, and the second conductor layer and the first conductor layer are electrically isolated. The second insulating groove passes through the insulating layer and the second conductor layer and is located on the first insulating groove, the second insulating groove has a second width, and the second width is greater than the first width. The channel layer is located on at least one sidewall of the second insulating recess. The memory layer is between the channel layer and the second conductor layer.

According to another embodiment of the present disclosure, a method of fabricating a memory structure is presented. The method for fabricating a memory structure includes the steps of: forming a bottom oxide layer; forming a first conductor layer on the bottom oxide layer; forming a first insulating recess, the first insulating recess passing through the first conductor layer and located at the bottom The first insulating recess has a first width on the oxide layer; forming a plurality of insulating layers on the first conductor layer; forming a plurality of second conductor layers, the second conductor layer and the insulating layer are alternately stacked, and the first conductor Electrically isolating; forming a second insulating recess, the second insulating recess passes through the insulating layer and the second conductor layer and is located on the first insulating recess, the second insulating recess has a second width, the second width Greater than the first width; forming a channel layer on at least one sidewall of the second insulating recess; and forming a memory layer between the channel layer and the second conductor layer.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

In the embodiments disclosed herein, a memory structure and a method of fabricating the same are presented. In the embodiment, in the memory structure, two grooves are respectively formed by two etching processes, so that the depth of the entire groove can be easily controlled, and the width of the second insulating groove is larger than the width of the first insulating groove, so The etching process of the second insulating recess can be easily aligned with the position of the first insulating recess. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

Please refer to FIG. 1 , which is a schematic diagram of a memory structure according to an embodiment of the disclosure. As shown in FIG. 1, the memory structure 10 includes a bottom oxide layer 100, a first conductor layer 200, a first insulating recess 300, a plurality of insulating layers 400, a plurality of second conductor layers 500, and a second An insulating groove 600, a channel layer 700, and a memory layer 800.

As shown in FIG. 1, the first conductor layer 200 is located on the bottom oxide layer 100. The first insulating recess 300 passes through the first conductive layer 200 and is located on the bottom oxide layer 100, and the first insulating recess 300 has a first width W1. The insulating layer 400 is located on the first conductor layer 200. The second conductor layer 500 and the insulating layer 400 are alternately stacked, and the second conductor layer 500 and the first conductor layer 200 are electrically isolated. The second insulating recess 600 passes through the insulating layer 400 and the second conductive layer 500 and is located on the first insulating recess 300. The second insulating recess 600 has a second width W2, and the second width W2 is greater than the first width W1. . The channel layer 700 is located on at least one sidewall of the second insulating recess 600. The memory layer 800 is located between the channel layer 700 and the second conductor layer 500.

According to an embodiment of the present disclosure, the memory structure 10 can be the primary structure of a three-dimensional vertical channel NAND flash memory device, wherein the first conductor layer 200 is, for example, an inversion gate, and the second conductor layer 500 is, for example. Is the word line.

According to an embodiment of the present disclosure, two grooves 300/600 are separately formed by two etching processes, so that the depth of the entire groove can be easily controlled; and the second width W2 of the second insulating groove 600 is greater than the first insulation. The first width W1 of the recess 300, and thus the etching process of the second insulating recess 600, can be easily aligned with the position of the first insulating recess 300.

Further, as shown in FIG. 1 , according to an embodiment of the present disclosure, the channel layer 700 is located on the sidewalls and the bottom surface of the second insulating recess 600 to form the U-shaped region 700 a in the first conductive layer 200. Even though the U-shaped region 700a of the channel layer 700 can be close to the first conductor layer 200, a relatively large range of the channel layer 700 can be controlled by the gate (via the first conductor layer 200), and the channel can be effectively reduced. The layer is not controlled by the gate, thereby reducing the large resistance of the channel layer not affected by the gate and the small current has an adverse effect on the operational performance of the memory device.

Furthermore, as shown in FIG. 1, according to an embodiment of the present disclosure, the channel layer 700 is located on the memory layer 800. In other words, the channel layer 700 is not buried in the memory layer 800, covered by other film layers, or buried. It is placed in some pipelines, so that it is easier to perform various treatments on the channel layer 700. For example, the channel layer 700 can be more easily heat-treated to increase the grain size, reduce the grain boundaries, and increase the current.

As shown in FIG. 1 , in the embodiment, the memory structure 10 further includes a top oxide layer 900 on the insulating layer 400 and the second conductor layer 500 .

In the embodiment shown in FIG. 1, the first insulating recess 300 and the second insulating recess 600 are filled with an oxide, and the top oxide layer 900 covers the upper of the channel layer 700 and the second insulating recess 600.

In the embodiment, as shown in FIG. 1, the first conductor layer 200 has a thickness T1, and the thickness T1 is, for example, 1500 to 4000 angstroms. In detail, according to an embodiment of the present disclosure, the first conductor layer 200 has a relatively large thickness T1, so that two recesses 300/600 can be respectively fabricated by two etching processes to make the two recesses 300/600 The connection is located in the first conductor layer 200, which makes it easier to control the depth of the overall groove, and thus facilitates the patterning of the second conductor layer 500 (character line) in the process.

In the embodiment, as shown in FIG. 1, the first width W1 of the first insulating groove 300 is, for example, 10 to 30 nm, and the second width W2 of the second insulating groove 600 is, for example, 50 to 150 nm.

In an embodiment, the first conductor layer 200 and the second conductor layer 500 may respectively comprise polysilicon, tungsten or a combination of the two.

Please refer to FIG. 2 , which is a schematic diagram of a memory structure according to another embodiment of the disclosure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 2, in the memory structure 20, the channel layer 700 has a vertical extension 700v and a horizontal extension 700h, the vertical extension 700v and the horizontal extension 700h are connected, and the horizontal extension 700h is located at the second. Above the conductor layer 500.

As shown in FIG. 2 , in the embodiment, the memory structure 20 further includes a hard mask layer 910 , and the hard mask layer 910 is located on the channel layer 700 . The hard mask layer 910 has an extension 910a on the horizontal extension 700h of the channel layer 700, and the extension L1 of the extension 910a of the hard mask layer 910 is greater than the extension of the horizontal extension 700h of the channel layer 700. Length L2. In an embodiment, the horizontal extension 700h of the channel layer 700 is used to electrically connect to the bit line of the memory device.

Please refer to FIG. 3 , which is a schematic diagram of a memory structure according to still another embodiment of the disclosure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 3, in the embodiment, the memory structure 30 may further include a low-temperature oxide 920. The low temperature oxide layer 920 is on the hard mask layer 910 and the low temperature oxide layer 920 completely covers the extension 910a of the hard mask layer 910.

As shown in FIG. 3, in the embodiment, the upper portion of the low temperature oxide layer 920 has a protruding outer edge, the side surface 920s of the protruding outer edge exceeds the side surface 910s of the extended portion 910a, and the side surface 910s of the extended portion 910a exceeds the side of the horizontal extended portion 700h. 700s.

Please refer to FIG. 4 , which is a schematic diagram of a memory structure according to still another embodiment of the disclosure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 4, in the embodiment, the memory structure 40 further includes a through opening 950. The through opening 950 passes through the insulating layer 400, the second conductor layer 500, and the first conductor layer 200, and the through opening 950 is located on the bottom oxide layer 100.

Please refer to FIG. 5, which is a schematic diagram of a memory structure according to a further embodiment of the present disclosure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 5, in an embodiment, the first conductor layer 200 of the memory structure 50 can include two conductor portions 210 and 220, and the conductor portion 210 and the conductor portion 220 can be made, for example, of different materials. For example, the conductor portion 210 adjoining the first insulating recess 300 is made of polysilicon, and the conductor portion 220 adjoining the through opening 950 is made of tungsten.

As shown in FIG. 5, the conductor portion 210 is substantially located between the second insulating recess 600 and the bottom oxide layer 100, and the conductor portion 220 is substantially located between the insulating layer 400 and the bottom oxide layer 100.

Please refer to FIG. 6 , which is a schematic diagram of a memory structure according to still another embodiment of the disclosure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 6, in the embodiment, the first conductor layer 200 of the memory structure 60 may include two conductor portions 210 and 220, and the conductor portion 210 adjacent to the first insulating recess 300 is made of polysilicon, and the abutment is continuous. The conductor portion 220 of the opening 950 is made of tungsten.

As shown in Fig. 6, the conductor portion 210 made of polycrystalline germanium occupies a larger volume than the conductor portion 220 made of tungsten.

7A-7F are schematic views showing a method of fabricating a memory structure in accordance with an embodiment of the present invention. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 7A, a bottom oxide layer 100 is formed, and a first conductor layer 200 is formed on the bottom oxide layer 100. In the embodiment, the first conductor layer 200 is, for example, a polysilicon layer, and has a thickness T1 of, for example, 1500 to 4000 angstroms. The first conductor layer 200 can function as a gate in a memory device.

As shown in FIG. 7B, a first insulating recess 300 is formed. The first insulating recess 300 passes through the first conductive layer 200 and is located on the bottom oxide layer 100. The first insulating recess 300 has a first width W1, and the first width W1 is, for example, 10 to 30 nm. In an embodiment, for example, the first conductor layer 200 is etched and stopped on the bottom oxide layer 100 to form a first insulating recess 300. The etching process has a high selectivity ratio to the bottom oxide layer 100 and the first conductor layer 200.

As shown in FIG. 7C, the insulating material is filled in the first insulating recess 300. In an embodiment, for example, an oxide is first deposited in the first insulating recess 300, and then the surface of the oxide is planarized to the upper surface of the first conductor layer 200 by, for example, chemical mechanical polishing.

As shown in FIG. 7D, a plurality of insulating layers 400 are formed on the first conductor layer 200, and a plurality of second conductor layers 500 are formed, the second conductor layer 500 and the insulating layer 400 are alternately stacked, and the second conductor layer 500 and The first conductor layers 200 are electrically isolated from each other. In the embodiment, the insulating layer 400 is, for example, an oxide layer, and the second conductive layer 500 is, for example, a polysilicon layer or a doped polysilicon layer, which can be used as a word line in a memory device.

As shown in FIG. 7E, a second insulating recess 600 is formed, and the second insulating recess 600 passes through the insulating layer 400 and the second conductive layer 500 and is located on the first insulating recess 300. The second width W2 of the second insulating groove 600 is greater than the first width W1 of the first insulating groove 300. In an embodiment, the second width W2 of the second insulating groove 600 is, for example, 50 to 150 nm.

In an embodiment, for example, the insulating material 400, the second conductive layer 500, and a portion of the first conductive layer 200 and a portion of the insulating material of the first insulating recess 300 are etched and stopped in the first conductive layer 200 to form The second insulating groove 600 is on the first insulating groove 300. The relatively large thickness T1 of the first conductor layer 200 facilitates the control of the etch depth of the etch process.

According to an embodiment of the present disclosure, two grooves 300/600 are formed by two etching processes, and the connection of the two grooves 300/600 is located in the first conductor layer 200, so that it is easier to control the depth of the entire groove; The second width W2 of the second insulating recess 600 is greater than the first width W1 of the first insulating recess 300, so that the etching process of the second insulating recess 600 can easily align the position of the first insulating recess 300.

As shown in FIG. 7F, the channel layer 700 is formed on at least one sidewall of the second insulating recess 600, and the memory layer 800 is formed between the via layer 700 and the second conductor layer 500. In an embodiment, the channel layer 700 is, for example, a polysilicon layer or a germanium (Ge)/germanium telluride (SiGe)/germanium indium tin oxide (GIZO) layer, and the memory layer 800 may have, for example, hafnium oxide-tantalum nitride-yttria ( Oxide-Nitride-Oxide, ONO), Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) or Cerium Oxide-Nttrium Nitride-Oxide-Nitride A composite layer of the structure of Oxide-Nitride-Oxide-Nitride-Oxide-Nitride-Oxide (ONONONO) (but not limited thereto).

As shown in FIG. 7F, the channel layer 700 may be formed on the bottom surface of the second insulating groove 600. As a result, most of the area of the channel layer 700 is close to the first conductor layer 200 or the second conductor layer 500, and the channel layer 700 can be prevented from being affected by the gate and/or the area controlled by the word line. The small current has an adverse effect on the operational performance of the memory device.

Next, referring to FIG. 1, a top oxide layer 900 is formed on the insulating layer 400 and the second conductor layer 500. Thus far, the memory structure 10 as shown in Fig. 1 is formed.

Please refer to FIG. 7A to FIG. 7F and FIG. 8A to FIG. 8H simultaneously, which illustrate a manufacturing method of a memory structure according to another embodiment of the present invention. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

After the steps of FIGS. 7A to 7F are performed, next, as shown in FIG. 8A, a hard mask layer 910 is formed on the channel layer 700. In an embodiment, the hard mask layer 910 is, for example, a tantalum nitride layer or a tantalum oxide layer. The hard mask layer 910 at this stage can be used to protect the channel layer 700.

As shown in FIG. 8B, an organic dielectric layer 930 is formed on the hard mask layer 910 and fills the second insulating recess 600, and another hard mask layer 940 is formed on the organic dielectric layer 930. In the embodiment, as shown in FIG. 8B, the organic dielectric layer 930 has a flat upper surface, and the hard mask layer 940 is formed on the flat upper surface of the organic dielectric layer 930.

In an embodiment, the organic dielectric layer 930 includes, for example, an organic dielectric material or a Topaz material (developed by Applied Materials), and the hard mask layer 940 includes, for example, a hard mask-containing anti-reflective coating (silicon- Containing hard-mask bottom anti-reflection coating (SHB), low-temperature oxide (LTO), or DARC layer (developed by Applied Materials).

As shown in FIG. 8C, a patterned mask layer 960 is disposed over the hard mask layer 940 for subsequent patterning processes. The patterned mask layer 960 has at least one opening 960a corresponding to a predetermined second insulating groove 600. As shown in FIG. 8C, in the embodiment, the structure may also have another second insulating groove 600, and the opening 960a only corresponds to the predetermined second insulating groove 600, and the other second insulating groove 600 is completely The patterned mask layer 960 is covered.

As shown in FIG. 8D, the removed portion of the organic dielectric layer 930 and the hard mask layer 940 are etched according to the patterned mask layer 960, exposing the hard mask layer 910 in the second insulating recess 600 and the underlying The channel layer 700 is simultaneously etched away to remove the patterned mask layer 960. Since the material of the organic dielectric layer 930 has a high etching selectivity with respect to the hard mask layer 910, the channel layer 700, the insulating layer 400, and the second conductor layer 500, etching removes the hard mask left by the organic dielectric layer 930. The cover layer 910 and the underlying channel layer 700 retain a complete structure and are not damaged by the etching process.

As shown in FIG. 8E, a low temperature oxide layer 920 is formed over the organic dielectric layer 930 and the hard mask layer 940 and filled in the second insulating recess 600. In an embodiment, the low temperature oxide layer 920 is formed, for example, by atomic layer deposition (ALD). The low temperature oxide layer 920 can protect the hard mask layer 910 and the channel layer 700 from subsequent destruction by an iso-tropical etching process.

As shown in FIG. 8F, a portion of the low temperature oxide layer 920 and the hard mask layer 940 are etched away to expose the organic dielectric layer 930.

As shown in FIG. 8G, the organic dielectric layer 930 is removed by etching, and the low temperature oxide layer 920, the hard mask layer 910, and the channel layer 700 are retained. For example, as shown in FIG. 8G, in the embodiment, the organic dielectric layer 930 located in the other second insulating recess 600 is etched away in this step.

Next, as shown in FIG. 8H, a portion of the hard mask layer 910 and a portion of the channel layer 700 are removed by an iso-tropical etching process to form an upper portion of the low temperature oxide layer 920. The side 920s of the rim exceeds the side 910s of the extended section 910a of the hard mask layer 910, and the side 910s of the extended section 910a exceeds the side 700s of the horizontally extending section 700h of the channel layer 700.

In an embodiment, the isotropic etching process includes, for example, etching a hard mask layer 910 using a hot phosphoric acid (H ₃ PO ₄ ) etching solution or a chemical dry etch (CDE) process, and using ammonia water (NH ₄ OH). Or a tetramethylammonium hydroxide (TMAH) etchant or a chemical dry etch (CDE) process to etch the via layer 700.

Next, referring to FIG. 3, a top oxide layer 900 is formed on the insulating layer 400, the second conductor layer 500, and the low temperature oxide layer 920. Thus far, the memory structure 30 as shown in FIG. 3 is formed.

According to the manufacturing method of the embodiment of the present disclosure, the horizontal extension 700h can be formed to electrically connect to the bit line of the memory device without etching the memory layer 800. In this way, the integrity of the memory layer 800 can be maintained, the uniformity of the electric field distribution of the memory layer 800 can be maintained, and the edge effect which may be generated by uneven electric field distribution can be reduced, and the programming/wiping of the memory device can be effectively maintained and improved. In addition to operational performance and operating speed.

Please refer to FIG. 7A to FIG. 7F and FIG. 9A to FIG. 9B simultaneously, which illustrate a manufacturing method of a memory structure according to still another embodiment of the present invention.

After the steps of FIGS. 7A to 7F are performed, next, as shown in FIG. 9A, a hard mask layer 910 is formed on the channel layer 700. In an embodiment, the hard mask layer 910 is, for example, a tantalum nitride layer. The hard mask layer 910 at this stage can be used to protect the channel layer 700.

Next, as shown in FIG. 9B, a portion of the hard mask layer 910 and a portion of the channel layer 700 are removed by an isotropic etching process, and the side 910s of the extended portion 910a forming the hard mask layer 910 exceeds the channel layer 700. The side of the horizontal extension 700h is 700s. In the embodiment, for example, a structure including the low temperature oxide layer 920 as shown in FIG. 8H may be formed first, and the low temperature oxide layer 920 may be removed by diluted hydrofluoric acid (DHF).

In an embodiment, the isotropic etching process includes, for example, etching a hard mask layer 910 using a hot phosphoric acid (H ₃ PO ₄ ) etching solution or a chemical dry etching process, and using ammonia water (NH ₄ OH) or hydrogen. The channel layer 700 is etched by oxidizing a tetramethylammonium (TMAH) etchant or by a chemical dry etch process.

Next, referring to FIG. 2, a top oxide layer 900 is formed on the insulating layer 400 and the second conductor layer 500. Thus far, the memory structure 20 as shown in Fig. 2 is formed.

10A to 10K are schematic views showing a method of fabricating a memory structure in accordance with still another embodiment of the present invention. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 10A, a bottom oxide layer 100 is formed, and an insulating layer 200A is formed on the bottom oxide layer 100. In the embodiment, the insulating layer 200A is, for example, a tantalum nitride layer, and has a thickness T1 of, for example, 1,500 to 4,000 angstroms.

As shown in Fig. 10B, a groove 300A is formed. The groove 300A passes through the insulating layer 200A and is located on the bottom oxide layer 100, and the groove 300A has a width W3 of, for example, 70 to 150 nm. In the embodiment, for example, the insulating layer 200A is etched and stopped on the underlying oxide layer 100 to form the recess 300A.

As shown in Fig. 10C, the conductor portion 210 is formed on the side wall of the recess 300A, and the first insulating recess 300 is defined. In an embodiment, the recess 300A is filled with a conductor material, for example, and then the conductor material of the recess 300A is etched to form a first insulating recess 300 and a conductor portion 210. The first insulating recess 300 has a first width W1 of 10-30. Nano. In the embodiment, the conductor material is, for example, polysilicon.

As shown in FIG. 10D, an insulating material is filled in the first insulating recess 300.

As shown in FIG. 10E, a plurality of insulating layers 400 are formed on the first insulating recess 300, the conductor portion 210, and the insulating layer 200A, and a plurality of sacrificial layers 500A are formed, and the sacrificial layer 500A and the insulating layer 400 are alternately stacked. In the embodiment, the insulating layer 400 is, for example, a hafnium oxide layer, and the sacrificial layer 500A is, for example, a tantalum nitride layer.

As shown in FIG. 10F, a second insulating recess 600 is formed, and the second insulating recess 600 passes through the insulating layer 400 and the sacrificial layer 500A and is located on the first insulating recess 300. The second width W2 of the second insulating groove 600 is greater than the first width W1 of the first insulating groove 300. In an embodiment, the second width W2 of the second insulating groove 600 is, for example, 50 to 150 nm.

As shown in FIG. 10G, a channel layer 700 is formed on at least one sidewall of the second insulating recess 600, and a memory layer 800 is formed between the via layer 700 and the sacrificial layer 500A.

As shown in FIG. 10H, a top oxide layer 900 is formed on the insulating layer 400 and the sacrificial layer 500A.

As shown in FIG. 10I, a through opening 950 is formed. The through opening 950 passes through the top oxide layer 900, the channel layer 700, the memory layer 800, the insulating layer 400, the sacrificial layer 500A, and the insulating layer 200A, and is located on the bottom oxide layer 100.

As shown in FIG. 10J, the sacrificial layer 500A and the insulating layer 200A are removed. In the embodiment, the etching liquid is introduced, for example, through the through opening 950 to etch away the sacrificial layer 500A and the insulating layer 200A.

As shown in Fig. 10K, the conductor portion 220 and the second conductor layer 500 are formed. In the embodiment, the space left by etching the sacrificial layer 500A and the insulating layer 200A is filled, for example, via the through opening 950, and then the conductive material passing through the opening 950 is etched apart by introducing an etching solution through the through opening 950. Thus far, the memory structure 50A as shown in Fig. 10K is formed.

In another embodiment, referring to FIG. 5, FIG. 8A to FIG. 8H, and FIGS. 10A to 10K, after performing the steps as shown in FIG. 10G, the steps as shown in FIGS. 8A to 8H are performed to form. The structure of the low temperature oxide layer 920, the extension 910a of the hard mask layer 910, and the horizontal extension 700h of the channel layer 700, as shown in Fig. 5, is followed by the steps shown in Figs. 10H to 10K, and finally coated. The oxide material is formed on the top oxide layer 900 and through the opening 950 to form the memory structure 50 as shown in FIG.

The manufacturing method of the memory structure 40 as shown in FIG. 4 differs from the manufacturing method of the memory structure 50 as shown in FIG. 5 in the steps shown in FIGS. 10B to 10C in which the groove 300A is not formed and The conductor portion 210, but directly forming the first insulating groove 300 having the first width W1 of 10 to 30 nm directly in the insulating layer 200A, the subsequent manufacturing steps are similar to the steps shown in Figs. 10D to 10K.

The manufacturing method of the memory structure 60 as shown in FIG. 6 differs from the manufacturing method of the memory structure 50 as shown in FIG. 5 in the steps shown in FIGS. 10B to 10C in which the width of the groove 300A is adjusted. W3, the width W3 is made larger than the predetermined second width W2 of the second insulating groove 600, and the subsequent manufacturing steps are similar to the steps shown in Figs. 10D-10K.

11A to 11K-1 are schematic views showing a method of manufacturing a memory structure in accordance with still another embodiment of the present invention. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 11A, a bottom oxide layer 100 is formed on the substrate 100A, and a first conductor layer 200 is formed on the bottom oxide layer 100. Then, a plurality of insulating layers 400 are formed on the first conductor layer 200, and a plurality of second conductor layers 500 are formed, the second conductor layers 500 and the insulating layer 400 are alternately stacked, and the second conductor layer 500 and the first conductor layer 200 are stacked. Electrically isolated. Next, a hard mask layer 970 is formed on the second conductor layer 500.

11B-11B-1, wherein FIG. 11B-1 shows a cross-sectional view along section line 11B-11B' of FIG. 11B, forming a groove 900A, the groove 900A passing through the insulating layer 400, and the second The conductor layer 500, the first conductor layer 200, and the bottom oxide layer 100 are located on the substrate 100A.

11C-11C-1, wherein FIG. 11C-1 is a schematic cross-sectional view along section line 11C-11C' of FIG. 11C, forming a channel layer 700 on at least one sidewall of the recess 900A, and forming The memory layer 800 is between the channel layer 700 and the second conductor layer 500. In an embodiment, the channel layer 700 is, for example, a polysilicon layer, and the memory layer 800 may have, for example, Oxide-Nitride-Oxide (ONO), yttrium oxide-tantalum nitride-yttria-yttrium nitride. -Oxide-Nitride-Oxide-Nitride-Oxide (ONONO) or yttrium oxide-tantalum nitride-yttria-tantalum nitride-yttria-yttrium-yttrium-yttrium-Oxide -Nitride-Oxide, ONONONO) Composite layer of structure (but not limited to this). Next, a hard mask layer 910 is formed on the channel layer 700.

As shown in FIG. 11D, an organic dielectric layer 930 is formed on the hard mask layer 910 and fills the recess 900A, and another hard mask layer 940 is formed on the organic dielectric layer 930.

As shown in FIG. 11E, a patterned mask layer 960 is disposed over the hard mask layer 940 for subsequent patterning processes. The patterned mask layer 960 has at least one opening 960a corresponding to the predetermined groove 900A.

As shown in FIG. 11F to FIG. 11F-1, FIG. 11F-1 is a schematic cross-sectional view along section line 11F-11F′ of FIG. 11F, and a portion of the organic dielectric layer is removed according to the patterned mask layer 960. 930 and hard mask layer 940 expose a hard mask layer 910 within predetermined recess 900A and a channel layer 700 thereunder. Since the material of the organic dielectric layer 930 has a high selectivity with respect to the hard mask layer 910 and the channel layer 700 therebelow, the hard mask layer 910 left by the organic dielectric layer 930 and the channel layer under it are removed. The 700 has a complete structure and is not damaged by the etching process.

As shown in FIG. 11G, a low temperature oxide layer 920 is formed over the organic dielectric layer 930 and the hard mask layer 940 and filled in the recess 900A.

As shown in FIG. 11H, a portion of the low temperature oxide layer 920 and the hard mask layer 940 are etched away to expose the organic dielectric layer 930.

As shown in FIG. 11I to FIG. 11I, FIG. 11I-1 is a schematic cross-sectional view along section line 11I-11I' of FIG. 11I, etching removes the organic dielectric layer 930, and retains the low temperature oxide layer 920. , a hard mask layer 910 and a channel layer 700. For example, as shown in FIG. 11I-1, in the embodiment, the organic dielectric layer 930 located in the other recess 900A is etched away in this step.

As shown in FIG. 11J, a portion of the hard mask layer 910 and a portion of the channel layer 700 are removed by an iso-tropical etching process to form a protruding outer edge of the upper portion of the low temperature oxide layer 920. Side 920s extends beyond side 910s of extension 910a of hard mask layer 910, and side 910s of extension 910a exceeds side 700s of horizontal extension 700h of channel layer 700.

Next, as shown in FIG. 11K to FIG. 11K-1, FIG. 11K-1 is a schematic cross-sectional view taken along section line 11K-11K' of FIG. 11K, and a top oxide layer 900 is formed on the insulating layer 400 and the second conductor layer. 500, memory layer 800 and low temperature oxide layer 920. Thus far, the memory structure 1100 as shown in Figs. 11K to 11K-1 is formed.

12A to 12B-1 are schematic views showing a manufacturing method of a memory structure according to still another embodiment of the present invention. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

After performing the steps as shown in FIGS. 11A to 11F-1, the steps as shown in FIGS. 9A to 9B are performed to form a structure as shown in FIG. 12A, in which the side 910s of the extended portion 910a of the hard mask layer 910 is formed. The side 700s of the horizontal extension 700h of the channel layer 700 is exceeded.

Next, as shown in FIG. 12B to FIG. 12B-1, FIG. 12B-1 is a schematic cross-sectional view along section line 12B-12B′ of FIG. 12B, and a top oxide layer 900 is formed on the insulating layer 400 and the second conductor layer. 500 and memory layer 800. Thus far, the memory structure 1200 as shown in Figs. 12B to 12B-1 is formed.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10, 20, 30, 40, 50, 50A, 60, 1100, 120‧‧‧ memory structures
100‧‧‧ bottom oxide layer
100A‧‧‧Substrate
200‧‧‧First conductor layer
200A, 400‧‧‧ insulation
210, 220‧‧‧ conductor parts
300‧‧‧First insulation groove
300A, 900A‧‧‧ grooves
500‧‧‧Second conductor layer
500A‧‧‧ sacrificial layer
600‧‧‧Second insulation groove
700‧‧‧channel layer
700a‧‧‧U-zone
700h‧‧‧ horizontal extension
700v‧‧‧ vertical extension
700s, 910s, 920s‧‧‧ side
800‧‧‧ memory layer
900‧‧‧Top oxide layer
910, 940, 970‧‧‧ hard mask layer
910a‧‧‧Extension
920‧‧‧Low temperature oxide layer
930‧‧‧Organic Dielectric Layer
950‧‧‧through opening
960‧‧‧ patterned mask layer
960a‧‧‧ openings
L1, L2‧‧‧ extended length
T1‧‧‧ thickness
W1‧‧‧ first width
W2‧‧‧ second width
W3‧‧‧Width
11B-11B', 11C-11C', 11F-11F', 11I-11I', 11K-11K'‧‧‧ hatching

FIG. 1 is a schematic diagram showing a memory structure of an embodiment of the present disclosure. FIG. 2 is a schematic diagram showing the structure of a memory of another embodiment of the present disclosure. FIG. 3 is a schematic diagram showing the memory structure of still another embodiment of the present disclosure. FIG. 4 is a schematic diagram showing the memory structure of still another embodiment of the present disclosure. FIG. 5 is a schematic diagram showing the memory structure of a further embodiment of the present disclosure. FIG. 6 is a schematic diagram showing the memory structure of still another embodiment of the present disclosure. 7A-7F are schematic views showing a method of fabricating a memory structure in accordance with an embodiment of the present invention. 8A-8H are schematic views showing a method of fabricating a memory structure in accordance with another embodiment of the present invention. 9A to 9B are schematic views showing a method of manufacturing a memory structure according to still another embodiment of the present invention. 10A to 10K are schematic views showing a method of fabricating a memory structure in accordance with still another embodiment of the present invention. 11A to 11K-1 are schematic views showing a method of manufacturing a memory structure in accordance with still another embodiment of the present invention. 12A to 12B-1 are schematic views showing a manufacturing method of a memory structure according to still another embodiment of the present invention.

10‧‧‧ memory structure

100‧‧‧ bottom oxide layer

200‧‧‧First conductor layer

300‧‧‧First insulation groove

400‧‧‧Insulation

500‧‧‧Second conductor layer

600‧‧‧Second insulation groove

700‧‧‧channel layer

700a‧‧‧U-zone

800‧‧‧ memory layer

900‧‧‧Top oxide layer

T1‧‧‧ thickness

W1‧‧‧ first width

W2‧‧‧ second width

Claims (10)

A memory structure comprising: a bottom oxide layer; a first conductor layer on the bottom oxide layer; a first insulating recess through the first conductor layer and on the bottom oxide layer, the first The insulating recess has a first width; a plurality of insulating layers are disposed on the first conductor layer; a plurality of second conductor layers are alternately stacked with the insulating layers and electrically isolated from the first conductor layer; a second insulating groove extending through the insulating layer and the second conductive layer and located on the first insulating groove, the second insulating groove having a second width, the second width being greater than the first width; a channel layer on at least one sidewall of the second insulating recess; and a memory layer between the channel layer and the second conductor layers. The memory structure of claim 1, wherein the channel layer is further located on a bottom surface of the second insulating recess, and the first conductor layer and the second conductor layers respectively comprise polysilicon or tungsten. The memory structure of claim 1, wherein the first conductor layer has a thickness of 1500 to 4000 angstroms, and the first width of the first insulating groove is 15 to 30 nm. The second width of the second insulating groove is 70 to 120 nm. The memory structure of claim 1, wherein the channel layer has a vertical extension and a horizontal extension, and the horizontal extension is located on the second conductor layer, the memory structure further comprising: a hard mask layer on the channel layer, wherein the hard mask layer has an extension segment on the horizontal extension of the channel layer, and an extension of the extension portion of the hard mask layer An extension of the horizontal extension greater than the channel layer; and a low-temperature oxide layer on the hard mask layer and completely covering the extension of the hard mask layer. The memory structure of claim 1, further comprising: a through opening through the insulating layer, the second conductive layer and the first conductive layer, and located on the bottom oxide layer; A top oxide layer is disposed on the insulating layers and the second conductor layers. A method of fabricating a memory structure, comprising: forming a bottom oxide layer; forming a first conductor layer on the bottom oxide layer; forming a first insulating recess, the first insulating recess passing through the first conductive layer And on the bottom oxide layer, the first insulating recess has a first width; forming a plurality of insulating layers on the first conductor layer; forming a plurality of second conductor layers, the second conductor layers and the The insulating layers are alternately stacked and electrically isolated from the first conductive layer; forming a second insulating recess, the second insulating recess passing through the insulating layers and the second conductive layers and located in the first insulating recess a second insulating recess having a second width, the second width being greater than the first width; forming a channel layer on at least one sidewall of the second insulating recess; and forming a memory layer in the channel Between the layer and the second conductor layers. The method of fabricating a memory structure according to claim 6, wherein the channel layer is further located on a bottom surface of the second insulating recess, and the first conductor layer and the second conductor layers respectively comprise polysilicon or Tungsten. The method for manufacturing a memory structure according to claim 6, wherein the first conductor layer has a thickness of 1500 to 4000 angstroms, and the first width of the first insulating groove is 15 to 30 angstroms. The second width of the second insulating groove is 70-120 nm. The method of fabricating a memory structure according to claim 6, wherein the channel layer has a vertical extension and a horizontal extension, and the horizontal extension is located on the second conductor layer, the memory structure The manufacturing method further includes: forming a hard mask layer on the channel layer, wherein the hard mask layer has an extension portion, the extension portion is located on the horizontal extension portion of the channel layer, and the hard mask layer is The extension has an extension length greater than an extension of the horizontal extension of the channel layer; and forming a low-temperature oxide on the hard mask layer and completely covering the hard mask layer Extension. The method of fabricating the memory structure of claim 6, further comprising: forming a through opening, the through opening passing through the insulating layer, the second conductor layer and the first conductor layer, and located at And forming a top oxide layer on the insulating layer and the second conductive layers.