CN107302006B

CN107302006B - Memory structure and manufacturing method thereof

Info

Publication number: CN107302006B
Application number: CN201610227245.7A
Authority: CN
Inventors: 赖二琨; 蒋光浩
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2016-04-13
Filing date: 2016-04-13
Publication date: 2020-01-07
Anticipated expiration: 2036-04-13
Also published as: CN107302006A

Abstract

The invention discloses a memory structure and a manufacturing method thereof. The memory structure comprises a bottom oxide layer, a first conductor layer, a first insulation groove, a plurality of insulation layers, a plurality of second conductor layers, a second insulation groove, a channel layer and a memory layer. The first conductor layer is located on the bottom oxide layer. The first insulation groove penetrates through the first conductor layer and is located on the bottom oxide layer, and the first insulation groove has a first width. The insulating layer is located on the first conductor layer. The second conductor layer and the insulating layer are stacked in a staggered mode, and the second conductor layer is electrically isolated from the first conductor layer. The second insulation groove penetrates through the insulation layer and the second conductor layer and is located on the first insulation groove, the second insulation groove has a second width, and the second width is larger than the first width. The channel layer is positioned on at least one side wall of the second insulation groove. The memory layer is located between the channel layer and the second conductor layer.

Description

Memory structure and manufacturing method thereof

Technical Field

The present invention relates to a memory structure and a method for fabricating the same, and more particularly, to a three-dimensional memory structure and a method for fabricating the same.

Background

Nonvolatile memory devices have the property that data stored in the device is not lost due to interruption of power supply, and thus are one of the memory devices commonly used to store data. Flash memory is a typical non-volatile memory technology.

The method for fabricating a non-volatile memory device with a vertical channel, such as a vertical channel NAND flash memory, generally comprises forming a multi-layer stacked structure on a semiconductor substrate by alternately stacking a plurality of insulating layers and polysilicon layers, forming a through opening in the multi-layer stacked structure, and exposing the substrate; and sequentially blanket forming a memory layer, such as a silicon-silicon oxide-silicon nitride-silicon oxide-silicon (SONOS) memory layer and a polysilicon channel layer, on the sidewalls of the through opening to define a plurality of memory cells on the memory layer, the channel layer and the polysilicon layer.

However, as the applications of memory devices increase, the demand for memory devices also tends to be smaller in size and larger in storage capacity. In response to such a demand, a memory device having a high device density and a small size needs to be manufactured, and thus, the difficulty of the process is increased.

Therefore, there is a need to provide a vertical channel flash memory device and a method for manufacturing the same to solve the problems of the prior art.

Disclosure of Invention

The invention relates to a memory structure and a manufacturing method thereof. In the embodiment, in the memory structure, two grooves are respectively manufactured by two etching processes, so that the depth of the whole groove can be easily controlled, and the width of the second insulating groove is greater than that of the first insulating groove, so that the etching process of the second insulating groove can be easily aligned to the position of the first insulating groove.

According to an embodiment of the present invention, a memory structure is provided. The memory structure comprises a bottom oxide layer, a first conductor layer, a first insulation groove, a plurality of insulation layers, a plurality of second conductor layers, a second insulation groove, a channel layer and a memory layer. The first conductor layer is located on the bottom oxide layer. The first insulation groove penetrates through the first conductor layer and is located on the bottom oxide layer, and the first insulation groove has a first width. The insulating layer is located on the first conductor layer. The second conductor layer and the insulating layer are stacked in a staggered mode, and the second conductor layer is electrically isolated from the first conductor layer. The second insulation groove penetrates through the insulation layer and the second conductor layer and is located on the first insulation groove, the second insulation groove has a second width, and the second width is larger than the first width. The channel layer is positioned on at least one side wall of the second insulation groove. The memory layer is located between the channel layer and the second conductor layer.

According to another embodiment of the present invention, a method for fabricating a memory structure is provided. The manufacturing method of the memory structure comprises the following steps: forming a bottom oxide layer; forming a first conductor layer on the bottom oxide layer; forming a first insulation groove, wherein the first insulation groove penetrates through the first conductor layer and is positioned on the bottom oxide layer, and the first insulation groove has a first width; forming a plurality of insulating layers on the first conductor layer; forming a plurality of second conductor layers, wherein the second conductor layers are stacked with the insulating layers in a staggered manner and are electrically isolated from the first conductor layers; forming a second insulation groove, wherein the second insulation groove penetrates through the insulation layer and the second conductor layer and is positioned on the first insulation groove, the second insulation groove has a second width, and the second width is larger than the first width; forming a channel layer on at least one side wall of the second insulation groove; and forming a memory layer between the channel layer and the second conductor layer.

In order to better understand the above and other aspects of the present invention, the following detailed description of the preferred embodiments is made with reference to the accompanying drawings, in which:

drawings

FIG. 1 is a schematic diagram of a memory structure according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a memory structure according to another embodiment of the invention.

FIG. 3 is a schematic diagram of a memory structure according to another embodiment of the invention.

FIG. 4 is a schematic diagram of a memory structure according to yet another embodiment of the invention.

FIG. 5 is a schematic diagram of a memory structure according to a further embodiment of the invention.

FIG. 6 is a schematic diagram of a memory structure according to yet another embodiment of the invention.

FIGS. 7A-7F are schematic diagrams illustrating a method of fabricating a memory structure according to an embodiment of the invention.

FIGS. 8A-8H are schematic diagrams illustrating a method of fabricating a memory structure according to another embodiment of the invention.

FIGS. 9A-9B are schematic diagrams illustrating a method of fabricating a memory structure according to yet another embodiment of the invention.

FIGS. 10A-10K are schematic diagrams illustrating a method of fabricating a memory structure according to still another embodiment of the invention.

FIGS. 11A-11K-1 are schematic diagrams illustrating a method of fabricating a memory structure according to a further embodiment of the invention.

FIGS. 12A-12B-1 are schematic diagrams illustrating a method of fabricating a memory structure according to yet another embodiment of the invention.

[ notation ] to show

10. 20, 30, 40, 50A, 60, 1100, 120: memory structure

100: bottom oxide layer

100A: substrate

200: first conductor layer

200A, 400: insulating layer

210. 220, and (2) a step of: conductor part

300: first insulating groove

300A, 900A: groove

500: second conductor layer

500A: sacrificial layer

600: second insulating groove

700: channel layer

700 a: u-shaped area

700 h: horizontal extension section

700 v: vertical extension section

700s, 910s, 920 s: side surface

800: storage layer

900: top oxide layer

910. 940, 970: hard mask layer

910 a: extension section

920: low temperature oxide layer

930: organic dielectric layer

950: through opening

960: patterned mask layer

960 a: opening of the container

L1, L2: extended length

T1: thickness of

W1: first width

W2: second width

W3: width of

11B-11B ', 11C-11C ', 11F-11F ', 11I-11I ', 11K-11K ': section line

Detailed Description

In an embodiment of the invention, a memory structure and a method for fabricating the same are provided. In the embodiment, in the memory structure, two grooves are respectively manufactured by two etching processes, so that the depth of the whole groove can be easily controlled, and the width of the second insulating groove is greater than that of the first insulating groove, so that the etching process of the second insulating groove can be easily aligned to the position of the first insulating groove. However, the embodiments are only used as examples and do not limit the scope of the present invention. In addition, the drawings in the embodiments omit some essential elements to clearly show the technical features of the invention.

It should be noted, however, that the specific embodiments and methods are not to be considered as limiting the invention. The invention may be embodied with other features, elements, methods, and parameters. The preferred embodiments are provided only to illustrate the technical features of the present invention, and not to limit the scope of the claims of the present invention. Those skilled in the art will recognize that equivalent modifications and variations can be made in light of the following description without departing from the spirit of the invention. Like elements in different embodiments and drawings will be denoted by like reference numerals.

Referring to fig. 1, a schematic diagram of a memory structure according to an embodiment of the invention is shown. As shown in fig. 1, the memory structure 10 includes a bottom oxide layer 100, a first conductive layer 200, a first insulating groove 300, a plurality of insulating layers 400, a plurality of second conductive layers 500, a second insulating groove 600, a channel layer 700, and a memory layer 800.

As shown in fig. 1, a first conductive layer 200 is located on the bottom oxide layer 100. The first insulation groove 300 penetrates through the first conductive layer 200 and is located on the bottom oxide layer 100, and the first insulation groove 300 has a first width W1. The insulating layer 400 is located on the first conductive layer 200. The second conductive layers 500 and the insulating layers 400 are stacked alternately, and the second conductive layers 500 are electrically isolated from the first conductive layers 200. The second insulation groove 600 penetrates the insulation layer 400 and the second conductor layer 500 and is located on the first insulation groove 300, the second insulation groove 600 has a second width W2, and the second width W2 is greater than the first width W1. The channel layer 700 is disposed on at least one sidewall of the second insulation groove 600. The memory layer 800 is located between the channel layer 700 and the second conductor layer 500.

According to an embodiment of the present invention, the memory structure 10 can be used as a main structure of a three-dimensional vertical channel NAND flash memory device, wherein the first conductive layer 200 is, for example, an inversion gate (inversion gate), and the second conductive layer 500 is, for example, a word line.

According to the embodiment of the invention, the two grooves 300/600 are respectively manufactured by two etching processes, so that the depth of the whole groove can be easily controlled; and the second width W2 of the second insulation groove 600 is greater than the first width W1 of the first insulation groove 300, so the etching process of the second insulation groove 600 can be easily aligned with the position of the first insulation groove 300.

Furthermore, as shown in fig. 1, according to the embodiment of the invention, the channel layer 700 is located on the sidewall and the bottom surface of the second insulation groove 600 to form the U-shaped region 700a in the first conductive layer 200, so that even the U-shaped region 700a of the channel layer 700 can be close to the first conductive layer 200, a relatively large area of the channel layer 700 can be controlled by the gate (via the first conductive layer 200), and the area of the channel layer not controlled by the gate can be effectively reduced, thereby reducing adverse effects of a larger resistance and a smaller current in the area of the channel layer not controlled by the gate on the operation performance of the memory device.

Furthermore, as shown in fig. 1, according to the embodiment of the invention, the channel layer 700 is located on the memory layer 800, in other words, the channel layer 700 is not embedded in the memory layer 800, covered by other layers, or embedded in some pipelines, so that various processes can be easily performed on the channel layer 700, such as heat treatment of the channel layer 700 to increase the grain size, reduce the grain boundary, and increase the current.

In the embodiment shown in fig. 1, the memory structure 10 may further include a top oxide layer 900, wherein the top oxide layer 900 is disposed on the insulating layer 400 and the second conductive layer 500.

In the embodiment shown in fig. 1, the first insulation groove 300 and the second insulation groove 600 are filled with oxide, and the top oxide layer 900 covers the channel layer 700 and the second insulation groove 600.

In an embodiment, as shown in FIG. 1, the first conductive layer 200 has a thickness T1, and the thickness T1 is, for example, 1500-4000 angstroms. In detail, according to the embodiment of the invention, the first conductive layer 200 has a relatively large thickness T1, so that the two grooves 300/600 are respectively formed by two etching processes, so that the connection point of the two grooves 300/600 is located in the first conductive layer 200, the depth of the whole groove can be easily controlled, and the patterning of the second conductive layer 500 (word line) in the process is also facilitated.

In an embodiment, as shown in FIG. 1, the first width W1 of the first insulation groove 300 is, for example, 10 to 30 nm, and the second width W2 of the second insulation groove 600 is, for example, 50 to 150 nm.

In an embodiment, the first conductor layer 200 and the second conductor layer 500 may each comprise polysilicon, tungsten, or a combination of both.

Referring to fig. 2, a schematic diagram of a memory structure according to another embodiment of the invention is shown. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

As shown in fig. 2, in the memory structure 20, the channel layer 700 has a vertically extending section 700v and a horizontally extending section 700h, the vertically extending section 700v and the horizontally extending section 700h are connected, and the horizontally extending section 700h is located on the second conductive layer 500.

In the embodiment shown in fig. 2, the memory structure 20 may further include a hard mask layer 910, and the hard mask layer 910 is disposed on the channel layer 700. The hard mask layer 910 has an extension 910a, the extension 910a is located on the horizontal extension 700h of the channel layer 700, and the extension length L1 of the extension 910a of the hard mask layer 910 is greater than the extension length L2 of the horizontal extension 700h of the channel layer 700. In one embodiment, the horizontally extending segments 700h of the channel layer 700 are used to electrically connect to bit lines of a memory device.

Referring to fig. 3, a schematic diagram of a memory structure according to another embodiment of the invention is shown. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

In the embodiment shown in FIG. 3, the memory structure 30 may further include a low-temperature oxide (low-temperature oxide) 920. The low-temperature oxide layer 920 is located on the hard mask layer 910, and the low-temperature oxide layer 920 completely covers the extension 910a of the hard mask layer 910.

In the embodiment shown in fig. 3, the upper portion of the low temperature oxide layer 920 has a protruding outer edge, the side 920s of the protruding outer edge exceeds the side 910s of the extension 910a, and the side 910s of the extension 910a exceeds the side 700s of the horizontal extension 700 h.

Referring to fig. 4, a schematic diagram of a memory structure according to still another embodiment of the invention is shown. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

In the embodiment shown in FIG. 4, the memory structure 40 further includes a through opening 950. The through opening 950 passes through the insulating layer 400, the second conductor layer 500 and the first conductor layer 200, and the through opening 950 is located on the bottom oxide layer 100.

Referring to fig. 5, a schematic diagram of a memory structure according to a further embodiment of the invention is shown. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

As shown in fig. 5, in an embodiment, the first conductor layer 200 of the memory structure 50 may include two

conductor portions

210 and 220, and the conductor portion 210 and the conductor portion 220 may be made of different materials, for example. For example, the conductor portion 210 adjacent to the first insulation recess 300 is made of polysilicon, and the conductor portion 220 adjacent to the through opening 950 is made of tungsten.

As shown in fig. 5, the conductor portion 210 is located substantially between the second insulation groove 600 and the bottom oxide layer 100, and the conductor portion 220 is located substantially between the insulation layer 400 and the bottom oxide layer 100.

Referring to fig. 6, a schematic diagram of a memory structure according to still another embodiment of the invention is shown. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

In one embodiment, as shown in fig. 6, the first conductive layer 200 of the memory structure 60 may include two

conductive portions

210 and 220, the conductive portion 210 adjacent to the first insulation recess 300 is made of polysilicon, and the conductive portion 220 adjacent to the through opening 950 is made of tungsten.

As shown in fig. 6, the conductor portion 210 made of polysilicon occupies a larger volume than the conductor portion 220 made of tungsten.

FIGS. 7A-7F are schematic diagrams illustrating a method of fabricating a memory structure according to an embodiment of the invention. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

As shown in fig. 7A, a bottom oxide layer 100 is formed, and a first conductive layer 200 is formed on the bottom oxide layer 100. In the embodiment, the first conductive layer 200 is, for example, a polysilicon layer, and the thickness T1 is, for example, 1500 to 4000 angstroms. The first conductive layer 200 may serve as a gate in a memory device.

As shown in fig. 7B, a first insulation groove 300 is formed. The first insulation groove 300 penetrates through the first conductive layer 200 and is located on the bottom oxide layer 100, the first insulation groove 300 has a first width W1, and the first width W1 is, for example, 10 to 30 nanometers. In an embodiment, for example, the first conductive layer 200 is etched and stopped on the bottom oxide layer 100 to form the first insulation recess 300, and the etching process has a high selectivity for the bottom oxide layer 100 and the first conductive layer 200.

As shown in fig. 7C, an insulating material is filled in the first insulating groove 300. In an embodiment, for example, an oxide is deposited in the first insulation groove 300, and then the surface of the oxide is planarized to the upper surface of the first conductive layer 200 by, for example, chemical mechanical polishing.

As shown in fig. 7D, a plurality of insulating layers 400 are formed on the first conductive layer 200, and a plurality of second conductive layers 500 are formed, wherein the second conductive layers 500 are stacked alternately with the insulating layers 400, and the second conductive layers 500 are electrically isolated from the first conductive layers 200. In one embodiment, the insulating layer 400 is an oxide layer, for example, and the second conductive layer 500 is a polysilicon layer, for example, or a doped polysilicon layer, for example, and can be used as a word line in a memory device.

As shown in fig. 7E, a second insulation groove 600 is formed, the second insulation groove 600 passing through the insulation layer 400 and the second conductor layer 500 and being positioned on the first insulation groove 300. The second width W2 of the second insulation groove 600 is greater than the first width W1 of the first insulation groove 300. In the embodiment, the second width W2 of the second insulation groove 600 is, for example, 50-150 nm.

In the embodiment, for example, the insulating material of the insulating layer 400, the second conductive layer 500, a portion of the first conductive layer 200 and a portion of the first insulating groove 300 are etched to stop in the first conductive layer 200, so as to form the second insulating groove 600 on the first insulating groove 300. The relatively large thickness T1 of the first conductor layer 200 facilitates control of the etch depth of this etch process.

According to the embodiment of the invention, the two grooves 300/600 are made by two etching processes, and the joint of the two grooves 300/600 is positioned in the first conductor layer 200, so that the depth of the whole groove is easy to control; and the second width W2 of the second insulation groove 600 is greater than the first width W1 of the first insulation groove 300, so the etching process of the second insulation groove 600 can be easily aligned with the position of the first insulation groove 300.

As shown in fig. 7F, a channel layer 700 is formed on at least one sidewall of the second insulation groove 600, and a memory layer 800 is formed between the channel layer 700 and the second conductive layer 500. In an embodiment, the channel layer 700 is, for example, a polysilicon layer or a germanium (Ge)/germanium silicide (SiGe)/germanium indium tin Oxide (GIZO) layer, and the memory layer 800 may, for example, have a composite layer of a silicon Oxide-silicon Nitride-silicon Oxide (ONO), a silicon Oxide-silicon Nitride-silicon Oxide (ONO), or a silicon Oxide-silicon Nitride-silicon Oxide (Oxide-Nitride-Oxide-silicon Nitride-Oxide-ONO) structure (but not limited thereto).

As shown in fig. 7F, the channel layer 700 may be further formed on the bottom surface of the second insulation groove 600. In this way, most of the channel layer 700 is close to the first conductive layer 200 or the second conductive layer 500, so as to avoid the adverse effect of the larger resistance and the smaller current of the area of the channel layer 700 not controlled by the gate and/or the word line on the operation performance of the memory device.

Next, referring to fig. 1, a top oxide layer 900 is formed on the insulating layer 400 and the second conductive layer 500. To this end, a memory structure 10 as shown in FIG. 1 is formed.

Referring to fig. 7A to 7F and fig. 8A to 8H, a method for manufacturing a memory structure according to another embodiment of the invention is shown. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

After the steps shown in fig. 7A to 7F are performed, a hard mask layer 910 is formed on the channel layer 700 as shown in fig. 8A. In an embodiment, the hard mask layer 910 is, for example, a silicon nitride layer or a silicon oxide layer. The hard mask layer 910 at this stage may be used to protect the channel layer 700.

As shown in fig. 8B, an organic dielectric layer 930 is formed on the hard mask layer 910 and fills the second insulation groove 600, and another hard mask layer 940 is formed on the organic dielectric layer 930. In one embodiment, as shown in FIG. 8B, the organic dielectric layer 930 has a flat top surface, and the hard mask layer 940 is formed on the flat top surface of the organic dielectric layer 930.

In one embodiment, the organic dielectric layer 930 may comprise, for example, an organic dielectric material or a Topaz material (developed by Applied Materials), and the hard mask layer 940 may comprise, for example, a silicon-containing hard-mask bottom-antireflective-coating (SHB), a low-temperature oxide (LTO), or a DARC layer (developed by Applied Materials).

As shown in fig. 8C, a patterned mask layer 960 is disposed on the hard mask layer 940 for performing a subsequent patterning process. The patterned mask layer 960 has at least one opening 960a, and the opening 960a corresponds to the predetermined second insulation groove 600. In the embodiment, as shown in fig. 8C, the structure may also have another second insulation groove 600, and the opening 960a corresponds to only the predetermined second insulation groove 600, and the other second insulation groove 600 is completely covered by the patterned mask layer 960.

As shown in fig. 8D, portions of the organic dielectric layer 930 and the hard mask layer 940 are etched and removed according to the patterned mask layer 960, exposing the hard mask layer 910 in the second insulating groove 600 and the channel layer 700 thereunder, and simultaneously etching and removing the patterned mask layer 960. Since the material of the organic dielectric layer 930 has a high etching selectivity with respect to the hard mask layer 910, the channel layer 700, the insulating layer 400 and the second conductor layer 500, the hard mask layer 910 and the channel layer 700 left by the organic dielectric layer 930 after etching and removing remain intact and are not damaged by the etching process.

As shown in fig. 8E, a low temperature oxide layer 920 is formed on the organic dielectric layer 930 and the hard mask layer 940, and filled in the second insulation groove 600. In an embodiment, the low temperature oxide layer 920 is formed, for example, by Atomic Layer Deposition (ALD). The low temperature oxide layer 920 may protect the hard mask layer 910 and the channel layer 700 from a subsequent iso-isotropic etching (iso-isotropic) process.

As shown in fig. 8F, a portion of the low temperature oxide layer 920 and the hard mask layer 940 is removed by etching to expose the organic dielectric layer 930.

As shown in fig. 8G, the organic dielectric layer 930 is removed by etching, and the low temperature oxide layer 920, the hard mask layer 910 and the channel layer 700 remain. For example, as shown in fig. 8G, in the embodiment, the organic dielectric layer 930 in the second insulation groove 600 is etched and removed in this step.

Next, as shown in fig. 8H, a portion of the hard mask layer 910 and a portion of the channel layer 700 are etched and removed by an isotropic etching (iso-isotropic etching) process, such that a side 920s of the upper portion of the low temperature oxide layer 920 protruding the outer edge exceeds a side 910s of the extension 910a of the hard mask layer 910, and a side 910s of the extension 910a exceeds a side 700s of the horizontal extension 700H of the channel layer 700.

In one embodiment, the isotropic etch process includes, for example, using hot phosphoric acid (H)₃PO₄) Etching the hard mask layer 910 with an etching solution or a Chemical Dry Etch (CDE) process, and using ammonia (NH)₄OH) or tetramethylammonium hydroxide (TMAH) etching solution, or by a Chemical Dry Etching (CDE) process to etch the channel layer 700.

Next, referring to fig. 3, a top oxide layer 900 is formed on the insulating layer 400, the second conductive layer 500 and the low temperature oxide layer 920. To this end, a memory structure 30 as shown in fig. 3 is formed.

According to the manufacturing method of the embodiment of the invention, the horizontal extension 700h can be formed to electrically connect to the bit line of the memory device without etching the memory layer 800. In this way, the integrity of the memory layer 800 can be maintained, the uniformity of the electric field distribution of the memory layer 800 can be maintained, edge effects (edge effects) which may be generated due to the non-uniform electric field distribution can be reduced, and the operation performance and operation speed of programming/erasing of the memory device can be effectively maintained and improved.

Referring to fig. 7A to 7F and fig. 9A to 9B, a method for manufacturing a memory structure according to another embodiment of the invention is shown.

After the steps shown in fig. 7A to 7F are performed, a hard mask layer 910 is formed on the channel layer 700 as shown in fig. 9A. In one embodiment, the hard mask layer 910 is, for example, a silicon nitride layer. The hard mask layer 910 at this stage may be used to protect the channel layer 700.

Next, as shown in fig. 9B, a portion of the hard mask layer 910 and a portion of the channel layer 700 are etched and removed by an isotropic etching process, such that a side 910s of the extension 910a of the hard mask layer 910 exceeds a side 700s of the horizontal extension 700h of the channel layer 700. In an embodiment, for example, the structure including the low temperature oxide layer 920 shown in fig. 8H may be formed, and then the low temperature oxide layer 920 may be removed by diluted hydrofluoric acid (DHF).

In one embodiment, the isotropic etch process includes, for example, using hot phosphoric acid (H)₃PO₄) Etching the hard mask layer 910 with an etching solution or a chemical dry etch (chemical dry etch) process, and using ammonia (NH)₄OH) or tetramethylammonium hydroxide (TMAH) etching solution, or by a chemical dry etch (chemical dry etch) process, the channel layer 700 is etched.

Next, referring to fig. 2, a top oxide layer 900 is formed on the insulating layer 400 and the second conductive layer 500. To this end, a memory structure 20 as shown in fig. 2 is formed.

FIGS. 10A-10K are schematic diagrams illustrating a method of fabricating a memory structure according to still another embodiment of the invention. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

As shown in fig. 10A, a bottom oxide layer 100 is formed, and an insulating layer 200A is formed on the bottom oxide layer 100. In the embodiment, the insulating layer 200A is, for example, a silicon nitride layer, and the thickness T1 is, for example, 1500 to 4000 angstroms.

As shown in fig. 10B, a groove 300A is formed. The groove 300A penetrates through the insulating layer 200A and is located on the bottom oxide layer 100, and the groove 300A has a width W3 of, for example, 70-150 nm. In one embodiment, for example, the insulating layer 200A is etched and stopped on the bottom oxide layer 100 to form the recess 300A.

As shown in fig. 10C, the conductor portion 210 is formed on the sidewall of the recess 300A and defines a first insulation recess 300. In one embodiment, for example, the recess 300A is filled with a conductive material, and then the conductive material in the recess 300A is etched to form the first insulation recess 300 and the conductive portion 210, wherein the first insulation recess 300 has a first width W1 of 10-30 nm. In an embodiment, the conductor material is, for example, polysilicon.

As shown in fig. 10D, an insulating material is filled in the first insulating groove 300.

As shown in fig. 10E, a plurality of insulating layers 400 are formed on the first insulating recesses 300, the conductor portions 210 and the insulating layer 200A, and a plurality of sacrificial layers 500A are formed, wherein the sacrificial layers 500A and the insulating layers 400 are alternately stacked. In the embodiment, the insulating layer 400 is, for example, a silicon oxide layer, and the sacrificial layer 500A is, for example, a silicon nitride layer.

As shown in fig. 10F, a second insulation groove 600 is formed, the second insulation groove 600 passing through the insulation layer 400 and the sacrificial layer 500A and being located on the first insulation groove 300. The second width W2 of the second insulation groove 600 is greater than the first width W1 of the first insulation groove 300. In the embodiment, the second width W2 of the second insulation groove 600 is, for example, 50-150 nm.

As shown in fig. 10G, a channel layer 700 is formed on at least one sidewall of the second insulation groove 600, and a memory layer 800 is formed between the channel layer 700 and the sacrificial layer 500A.

As shown in fig. 10H, a top oxide layer 900 is formed on the insulating layer 400 and the sacrificial layer 500A.

As shown in fig. 10I, a through opening 950 is formed. The through opening 950 passes through the top oxide layer 900, the channel layer 700, the memory layer 800, the insulating layer 400, the sacrificial layer 500A, and the insulating layer 200A, and is located on the bottom oxide layer 100.

As shown in fig. 10J, the sacrificial layer 500A and the insulating layer 200A are removed. In an embodiment, an etching solution is introduced through the through opening 950 to etch and remove the sacrificial layer 500A and the insulating layer 200A.

As shown in fig. 10K, the conductor portion 220 and the second conductor layer 500 are formed. In one embodiment, for example, the conductive material is introduced through the through opening 950 to fill the space left by etching the sacrificial layer 500A and the insulating layer 200A, and then the etching liquid is introduced through the through opening 950 to etch and separate the conductive material of the through opening 950. To this end, a memory structure 50A as shown in fig. 10K is formed.

In another embodiment, referring to fig. 5, fig. 8A to fig. 8H and fig. 10A to fig. 10K together, after the step shown in fig. 10G is performed, the steps shown in fig. 8A to fig. 8H are performed to form the structures of the low temperature oxide layer 920, the extension section 910A of the hard mask layer 910 and the horizontal extension section 700H of the channel layer 700 shown in fig. 5, and then the steps shown in fig. 10H to fig. 10K are performed, and finally, an oxide material is coated on the top oxide layer 900 and in the through opening 950, so as to form the memory structure 50 shown in fig. 5.

The manufacturing method of the memory structure 40 shown in fig. 4 is different from the manufacturing method of the memory structure 50 shown in fig. 5 in the steps shown in fig. 10B to 10C, in which the groove 300A and the conductor portion 210 are not formed, but the first insulating groove 300 having the first width W1 of 10 to 30 nm is directly formed in the insulating layer 200A, and the subsequent manufacturing steps are similar to the steps shown in fig. 10D to 10K.

The difference between the manufacturing method of the memory structure 60 shown in fig. 6 and the manufacturing method of the memory structure 50 shown in fig. 5 lies in the steps shown in fig. 10B to 10C, in which the width W3 of the groove 300A is adjusted to make the width W3 greater than the predetermined second width W2 of the second insulation groove 600, and the subsequent manufacturing steps are similar to the steps shown in fig. 10D to 10K.

FIGS. 11A-11K-1 are schematic diagrams illustrating a method of fabricating a memory structure according to a further embodiment of the invention. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

As shown in fig. 11A, a bottom oxide layer 100 is formed on a substrate 100A, and a first conductive layer 200 is formed on the bottom oxide layer 100. Then, a plurality of insulating layers 400 are formed on the first conductive layer 200, and a plurality of second conductive layers 500 are formed, wherein the second conductive layers 500 are stacked alternately with the insulating layers 400, and the second conductive layers 500 are electrically isolated from the first conductive layers 200. Next, a hard mask layer 970 is formed on the second conductive layer 500.

Referring to fig. 11B-1, wherein fig. 11B-1 shows a cross-sectional view along the section line 11B-11B' of fig. 11B, a groove 900A is formed, the groove 900A penetrates through the insulating layer 400, the second conductive layer 500, the first conductive layer 200 and the bottom oxide layer 100 and is located on the substrate 100A.

Referring to fig. 11C-1, wherein fig. 11C-1 is a cross-sectional view taken along a section line 11C-11C' of fig. 11C, forming a channel layer 700 on at least one sidewall of the trench 900A, and forming a memory layer 800 between the channel layer 700 and the second conductive layer 500. In an embodiment, the channel layer 700 is, for example, a polysilicon layer, and the storage layer 800 may, for example, have a composite layer of a silicon Oxide-silicon Nitride-silicon Oxide (ONO), a silicon Oxide-silicon Nitride-silicon Oxide (ONO), or a silicon Oxide-silicon Nitride-silicon Oxide (Oxide-Nitride-Oxide-Nitride-silicon Oxide-ONO) structure (but not limited thereto). Next, a hard mask layer 910 is formed on the channel layer 700.

As shown in fig. 11D, an organic dielectric layer 930 is formed on the hard mask layer 910 and fills the recess 900A, and another hard mask layer 940 is formed on the organic dielectric layer 930.

As shown in fig. 11E, a patterned mask layer 960 is disposed on the hard mask layer 940 for performing a subsequent patterning process. The patterned mask layer 960 has at least one opening 960A, and the opening 960A corresponds to the predetermined groove 900A.

Referring to FIGS. 11F-1, wherein FIG. 11F-1 shows a schematic cross-sectional view along the section line 11F-11F' of FIG. 11F, a portion of the organic dielectric layer 930 and the hard mask layer 940 are removed by etching according to the patterned mask layer 960, so as to expose the hard mask layer 910 in the predetermined recess 900A and the channel layer 700 therebelow. Since the material of the organic dielectric layer 930 has a high selectivity with respect to the hard mask layer 910 and the channel layer 700 thereunder, the hard mask layer 910 and the channel layer 700 thereunder left after removing the organic dielectric layer 930 have a complete structure and are not damaged by the etching process.

As shown in fig. 11G, a low temperature oxide layer 920 is formed on the organic dielectric layer 930 and the hard mask layer 940, and fills the recess 900A.

As shown in fig. 11H, a portion of the low temperature oxide layer 920 and the hard mask layer 940 is removed by etching to expose the organic dielectric layer 930.

11I-1, wherein FIG. 11I-1 shows a schematic cross-sectional view along the line 11I-11I' of FIG. 11I, the organic dielectric layer 930 is removed by etching, and the low temperature oxide layer 920, the hard mask layer 910 and the channel layer 700 remain. For example, as shown in FIG. 11I-1, in one embodiment, the organic dielectric layer 930 in the other recess 900A is etched away in this step.

As shown in fig. 11J, a portion of the hard mask layer 910 and a portion of the channel layer 700 are etched and removed by an isotropic etching (iso-isotropic etching) process, such that a side 920s of the upper portion of the low temperature oxide layer 920 protruding beyond a side 910s of the extension 910a of the hard mask layer 910 and a side 910s of the extension 910a exceeds a side 700s of the horizontal extension 700h of the channel layer 700.

Next, as shown in FIGS. 11K-1, wherein FIG. 11K-1 is a cross-sectional view taken along the line 11K-11K' of FIG. 11K, a top oxide layer 900 is formed on the insulating layer 400, the second conductive layer 500, the memory layer 800 and the low temperature oxide layer 920. Thus, a memory structure 1100 is formed as shown in FIGS. 11K-1.

FIGS. 12A-12B-1 are schematic diagrams illustrating a method of fabricating a memory structure according to yet another embodiment of the invention. In this embodiment, the same or similar elements as those in the previous embodiment are denoted by the same or similar element numbers, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

After the steps shown in fig. 11A to 11F-1 are performed, the steps shown in fig. 9A to 9B are performed to form the structure shown in fig. 12A in which the side 910s of the extension section 910a of the hard mask layer 910 exceeds the side 700s of the horizontal extension section 700h of the channel layer 700.

Next, as shown in fig. 12B-1, wherein fig. 12B-1 is a schematic cross-sectional view taken along the section line 12B-12B' of fig. 12B, a top oxide layer 900 is formed on the insulating layer 400, the second conductive layer 500 and the memory layer 800. Thus, a memory structure 1200 as shown in FIGS. 12B-1 is formed.

While the invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.

Claims

1. A memory structure, comprising:

a bottom oxide layer;

a first conductor layer on the bottom oxide layer;

a first insulating groove passing through the first conductor layer and located on the bottom oxide layer, the first insulating groove having a first width;

a plurality of insulating layers on the first conductor layer;

a plurality of second conductive layers which are stacked with the insulating layers in a staggered way and are electrically isolated from the first conductive layers;

a second insulation groove passing through the insulation layers and the second conductor layers and located on the first insulation groove, wherein the second insulation groove has a second width which is larger than the first width;

a channel layer located on at least one side wall of the second insulation groove; and

a memory layer located between the channel layer and the second conductive layers;

wherein the channel layer has a vertical extension section and a horizontal extension section, the horizontal extension section is located on the second conductive layers, the memory structure further includes: and the hard mask layer is positioned on the channel layer and provided with an extension section, the extension section is positioned on the horizontal extension section of the channel layer, and the extension length of the extension section of the hard mask layer is greater than that of the horizontal extension section of the channel layer.

2. The memory structure of claim 1, wherein the channel layer is further located on a bottom surface of the second insulation groove, and the first conductive layer and the second conductive layers respectively comprise polysilicon or tungsten.

3. The memory structure of claim 1, wherein the first conductive layer has a thickness of 1500-4000 angstroms, the first width of the first insulation groove is 15-30 nm, and the second width of the second insulation groove is 70-120 nm.

4. The memory structure of claim 1, further comprising:

a low temperature oxide layer on the hard mask layer and completely covering the extension section of the hard mask layer.

5. The memory structure of claim 1, further comprising:

a through opening passing through the insulating layers, the second conductor layers and the first conductor layer and located on the bottom oxide layer; and

and a top oxide layer on the insulating layers and the second conductor layers.

6. A method of fabricating a memory structure, comprising:

forming a bottom oxide layer;

forming a first conductive layer on the bottom oxide layer;

forming a first insulation groove, wherein the first insulation groove penetrates through the first conductor layer and is positioned on the bottom oxide layer, and the first insulation groove has a first width;

forming a plurality of insulating layers on the first conductor layer;

forming a plurality of second conductor layers which are stacked with the insulating layers in a staggered manner and are electrically isolated from the first conductor layers;

forming a second insulation groove, wherein the second insulation groove penetrates through the insulation layers and the second conductor layers and is positioned on the first insulation groove, the second insulation groove has a second width, and the second width is larger than the first width;

forming a channel layer on at least one sidewall of the second insulation groove; and

forming a memory layer between the channel layer and the second conductive layers;

the channel layer has a vertical extension section and a horizontal extension section, the horizontal extension section is located on the second conductor layers, the manufacturing method of the memory structure further comprises: forming a hard mask layer on the channel layer, wherein the hard mask layer has an extension section, the extension section is located on the horizontal extension section of the channel layer, and the extension length of the extension section of the hard mask layer is greater than that of the horizontal extension section of the channel layer.

7. The method according to claim 6, wherein the channel layer is further located on a bottom surface of the second insulation groove, and the first conductive layer and the second conductive layers respectively comprise polysilicon or tungsten.

8. The method of claim 6, wherein the first conductive layer has a thickness of 1500-4000 angstroms, the first width of the first insulation groove is 15-30 nm, and the second width of the second insulation groove is 70-120 nm.

9. The method of claim 6, further comprising:

a low temperature oxide layer is formed on the hard mask layer and completely covers the extension section of the hard mask layer.

10. The method of claim 6, further comprising:

forming a through opening, wherein the through opening penetrates through the insulating layers, the second conductor layers and the first conductor layer and is positioned on the bottom oxide layer; and

a top oxide layer is formed on the insulating layers and the second conductive layers.