TWI685091B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first memory structure and the second memory structure has a radius of curvature. The first memory structure and the second memory structure penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first memory structure and the second memory structure includes at least two protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

Description

Semiconductor structure and its manufacturing method

This case is about a semiconductor structure and a method of manufacturing a semiconductor structure.

In recent years, the structure of semiconductor devices has continuously changed, and the storage capacity of semiconductor devices has continuously increased. Memory devices are used in the storage components of many products, such as MP3 players, digital cameras, and computer files. As these applications increase, the demand for memory devices is concentrated on small size and large storage capacity. In order to satisfy this condition, a memory device having a high device density and a small size and a method of manufacturing the same are required.

Therefore, it is desirable to develop a three-dimensional (3D) memory device with a greater number of stacked planes to achieve greater storage capacity, improve quality, and at the same time maintain a small size of the memory device.

The technical aspect of the present disclosure is a semiconductor structure and a manufacturing method thereof. In the semiconductor structure of the present disclosure, a pair of vertical memory structures each have a horizontal C-shaped cross section, and are separated from each other by an insulating trench. Such a As a result, the memory density in the unit area of the semiconductor structure increases, and thus a larger memory storage capacity is achieved.

According to an embodiment of the present disclosure, a semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of dielectric layers, an insulating structure, a first memory structure, and a second memory structure. The conductive layer and the dielectric layer are alternately stacked on the substrate. The insulating structure is disposed above the substrate and passes through the conductive layer and the dielectric layer. The first memory structure and the second memory structure respectively have a radius of curvature, pass through the conductive layer and the dielectric layer, and are located on opposite sidewalls of the insulating structure. The first memory structure and the second memory structure each include a memory structure layer, a channel layer, and at least two protection structures. The memory structure layer includes a memory storage layer. The channel layer is disposed between the memory structure layer and the insulating structure. The protection structure is disposed at both ends of the memory storage layer, wherein the etching selectivity of the protection structure is different from that of the memory storage layer.

In an embodiment of the present disclosure, the memory structure layer further includes a barrier layer and a tunneling layer, and the barrier layer is disposed on a plurality of sidewalls of the conductive layer and the dielectric layer, and the memory storage layer is disposed between the barrier layer and the tunneling layer And the protection structure is disposed between the barrier layer and the tunneling layer, and is adjacent to the memory storage layer.

In an embodiment of the present disclosure, the first memory structure and the second memory structure each further include a dielectric structure and a conductive plug layer, and the dielectric structure is disposed between the channel layer and the insulating structure, and the conductive plug layer is disposed at Above the dielectric structure.

In an embodiment of the present disclosure, the memory structure layer and the channel layer of the first memory structure are respectively connected to the memory structure layer and the channel layer corresponding to the second memory structure on the bottom surface of the insulating structure.

In an embodiment of the present disclosure, the memory structure layer and the channel layer of the first memory structure are separated from the memory structure layer and the channel layer corresponding to the second memory structure through an insulating structure.

In an embodiment of the present disclosure, the semiconductor structure further includes two contact structures, which are electrically connected to the first memory structure and the second memory structure, respectively.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor structure includes: forming a plurality of insulating layers and a plurality of dielectric layers alternately stacked on a substrate; forming a memory structure group on the substrate and passing through the insulating layer and the dielectric layer , Wherein the memory structure group includes a channel layer, a conductive pin layer, and a memory structure layer including a memory storage layer; a trench is formed through the insulating layer, the dielectric layer, and the memory structure group, so that the memory structure group is divided into the first memory The body structure and the second memory structure, and the plurality of portions of the insulating layer and the plurality of portions of the memory storage layer are exposed by the trench; the exposed portions of the insulating layer and the exposed portions of the memory storage layer are removed to form the first group respectively Space and the second group of spaces; fill a plurality of protection structures in the first group of spaces and the second group of spaces; remove the plurality of parts of the protection structure to expose the insulating layer from the first group of spaces; replace the insulation with a plurality of conductive layers Floor.

In an embodiment of the present disclosure, replacing the insulating layer with a conductive layer includes: after the insulating layer is exposed, removing the insulating layer to form a third set of spaces between the dielectric layers; filling the conductive layer between the first set of spaces and the third Group space.

In an embodiment of the present disclosure, the method for manufacturing a semiconductor structure further includes: In an embodiment of the present disclosure, after filling the conductive layer in the first group of spaces and the third group of spaces, forming an insulating structure in the trench, memory Above the top layer of the bulk structure group and the dielectric layer.

In an embodiment of the present disclosure, the memory structure group further includes a dielectric structure, and the channel layer is located between the dielectric structure and the memory structure layer, and the memory structure group is formed above the substrate and passes through the insulating layer and the dielectric The layer further includes: forming a groove with an elliptical profile, wherein the groove passes through the insulating layer and the dielectric layer; forming a memory structure layer in the groove and above the topmost layer in the dielectric layer; forming a channel layer in the memory structure layer Above; forming a dielectric structure above the channel layer to fill the groove; replacing the top of the dielectric structure with a conductive plug layer; removing a part of the memory structure layer, a part of the conductive plug layer and a part of the channel layer beyond the groove .

According to the above-mentioned embodiment of the present disclosure, the first memory structure and the second memory structure are separated from each other by the insulating structure, so that the memory density in the unit area is increased, thus achieving a larger memory storage capacity. In addition, since the conductive layers stacked between the dielectric layers have lower resistance, they can help increase the programming speed and erasing speed of the semiconductor structure. In addition, the above-mentioned embodiments of the present disclosure also provide a method of replacing the insulating layer with a conductive layer while retaining the memory storage layer having the same material as the insulating layer, thereby simplifying the manufacturing process of the semiconductor structure.

100、100a‧‧‧Semiconductor structure

110‧‧‧ substrate

120‧‧‧Insulation

121‧‧‧Top

123‧‧‧Bottom

130‧‧‧dielectric layer

131‧‧‧Top

133‧‧‧Sidewall

140‧‧‧ memory structure layer

142‧‧‧ barrier

144‧‧‧ memory storage

146‧‧‧Tunnel layer

150‧‧‧channel layer

152‧‧‧conductive latch layer

160‧‧‧dielectric structure

170‧‧‧groove

180‧‧‧The first group of spaces

190‧‧‧The second group of spaces

200‧‧‧ third group space

210‧‧‧Protection structure

220‧‧‧conductive layer

222‧‧‧ masking layer

224‧‧‧Metal layer

225‧‧‧recess

223‧‧‧Side wall

230‧‧‧High dielectric constant dielectric layer

233‧‧‧Side wall

240‧‧‧Insulation structure

241‧‧‧Bottom

242‧‧‧Side wall

244‧‧‧Side wall

246, 248‧‧‧ contact hole

250‧‧‧Isolation layer

300‧‧‧Memory structure group

301‧‧‧Top

310‧‧‧ First memory structure

320‧‧‧Second memory structure

400‧‧‧groove

410‧‧‧Etching space

420、430‧‧‧First contact structure

440、450‧‧‧Second contact structure

460、470‧‧‧third contact structure

500, 500a‧‧‧semiconductor device

X, Y‧‧‧ axis

S10, S20, S30, S40, S50, S60, S70, S80, S90, S100, S110, S120, S130, S140, S150, S160, S170, S180, S190, S200, S210

1B-1B, 2B-2B, 3B-3B~3C-3C, 4B-4B~4C-4C, 5B-5B~5C-5C, 6B-6B~6C-6C, 7B-7B~7D-7D, 8B- 8B~8F-8F, 9B-9B~9F-9F, 10B-10B~10F-10F, 11B-11B~11F-11F, 12B-12B, 12D-12D~12F-12F, 13B-13B~13E-13E, 14B-14B~14E-14E, 15B-15B~15D-15D, 16B-16B~16D-16D, 17B-17B, 18B-18B, 19B-19B~19D-19D, 20B-20B, 21B-21B~21C- 21C‧‧‧Line

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the detailed descriptions of the attached drawings are as follows:

Figure 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A FIG. 14A is a top view of the manufacturing method of the semiconductor structure according to an embodiment of the present disclosure at various steps.

Figures 1B, 2B, 3B to 3C, 4B to 4C, 5B to 5C, 6B to 6C, 7B to 7D, 8B to 8F, 9B to 9F, FIGS. 10B to 10F, 11B to 11F, 12B, 12D to 12F, 13B to 13E, and 14B to 14E illustrate the manufacturing method of the semiconductor structure according to an embodiment of the present disclosure at each step Section view.

FIG. 12C is a partially enlarged view of FIG. 12B.

FIGS. 15A, 16A, 17A, 18A, and 19A illustrate top views at various steps of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

FIGS. 15B to 15D, 16B to 16D, 17B, 18B, and 19B to 19D illustrate cross-sectional views at various steps of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

FIG. 20A illustrates a top view of each step of the method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

FIG. 20B is a cross-sectional view at various steps of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

FIG. 21A illustrates a top view of each step of a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

21B to 21C are cross-sectional views at various steps of a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

In the following, a plurality of embodiments of the disclosure will be disclosed in a diagram. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

In the embodiments of the present disclosure, a semiconductor structure and a manufacturing method thereof are provided. For simplicity and clarity, the method of manufacturing semiconductor structures will first be discussed in this article. In addition, for ease of description, the term “top view” may refer to a cross-sectional view of the topmost layer of the semiconductor structure herein to highlight the technical features of the present disclosure. In addition, in the drawings attached to the following embodiments, some secondary elements may be omitted.

Figures 1A to 1B, 2A to 2B, 3A to 3C, 4A to 4C, 5A to 5C, 6A to 6C, 7A to 7D, 8A to 8F, 9A FIGS. 9 to 9F, FIGS. 10A to 10F, FIGS. 11A to 11F, FIGS. 12A to 12F, FIGS. 13A to 13E, and 14A to 14E illustrate the manufacturing method of the semiconductor structure 100 according to an embodiment of the present disclosure. View of steps. For simplicity and clarity, the elements covered under the semiconductor structure 100 are drawn with solid lines in the drawings.

Referring to FIGS. 1A and 1B, FIG. 1A illustrates a top view of forming the semiconductor structure 100 at step S10, and FIG. 1B illustrates a cross-sectional view taken along line 1B-1B in FIG. 1A. In step S10, a substrate 110 is provided, and a plurality of insulating layers 120 and a plurality of dielectric layers 130 are alternately stacked on the substrate 110. After the stacked layers are provided above the substrate 110, the groove 400 is then formed. The groove 400 passes through the insulating layer 120 and the dielectric layer 130 and stops under the lowest layer in the insulating layer 120. As shown in FIG. 1A, the groove 400 has an oval shape in a plan view Profile, and the long axis (longer diameter) of the elliptical cross-section can be up to about 150 nm. In some embodiments of the present disclosure, the thickness T of the bottommost layer in the insulating layer 120 may be greater than the thickness of other layers in the insulating layer 120.

Referring to FIGS. 2A and 2B, FIG. 2A illustrates a top view of forming the semiconductor structure 100 at step S20, and FIG. 2B illustrates a cross-sectional view taken along line 2B-2B in FIG. 2A. In step S20, the memory structure layer 140 is conformally formed in the groove 400 and above the topmost layer in the dielectric layer 130, and then the channel layer 150 is conformally formed above the memory structure layer 140. The memory structure layer 140 includes a barrier layer 142, a memory storage layer 144, and a tunneling layer 146. The barrier layer 142 is disposed on the sidewalls of the insulating layer 120 and the dielectric layer 130 and above the topmost layer in the dielectric layer 130, the memory storage layer 144 is disposed above the barrier layer 142, and the tunneling layer 146 is disposed above the memory storage layer 144 . In some embodiments of the present disclosure, the barrier layer 142 and the tunneling layer 146 may be made of materials including silicon oxide or other dielectric materials, and the memory storage layer 144 may be made of silicon nitride or other materials capable of trapping electrons. The material of the channel layer 150 may include undoped polysilicon (undoped polysilicon), but it is not used to limit the present disclosure.

Referring to FIGS. 3A to 3C, FIG. 3A shows a top view of forming the semiconductor structure 100 at step S30, FIG. 3B shows a cross-sectional view taken along line 3B-3B in FIG. 3A, and FIG. 3C shows Sectional view taken along line 3C-3C in Figure 3A. In step S30, the dielectric structure 160 is disposed above the channel layer 150 to fill the groove 400, and is formed above the topmost layer in the dielectric layer 130. The portion of the dielectric structure 160 formed above the topmost layer in the dielectric layer 130 is higher than the top surface of the channel layer 150 by a height HD. In some embodiments of the present disclosure, the dielectric structure 160 may be made of materials including silicon oxide or other dielectric materials.

Referring to FIGS. 4A to 4C, FIG. 4A shows a top view of forming the semiconductor structure 100 at step S40, FIG. 4B shows a cross-sectional view taken along line 4B-4B in FIG. 4A, and FIG. 4C shows Sectional view taken along line 4C-4C in Figure 4A. In step S40, the top of the dielectric structure 160 is removed through a selective etching process, thereby forming an etching space 410 as shown in FIGS. 4A to 4C. The selective etching process may be a wet etching process or a dry etching process performed based on the difference in etching selectivity between the oxide material and the polysilicon material, so that the dielectric layer 160 is removed while retaining the channel layer 150. As for the etching depth of the dielectric structure 160 in the groove 400, the selective etching process can be stopped at a desired depth position through time control.

Referring to FIGS. 5A to 5C, FIG. 5A illustrates a top view of forming the semiconductor structure 100 at step S50, FIG. 5B illustrates a cross-sectional view taken along line 5B-5B in FIG. 5A, and FIG. 5C illustrates Sectional view taken along line 5C-5C in Figure 5A. In step S50, a material containing the same material as the channel layer 150, such as doped polysilicon (doped polysilicon), is refilled into the etching space 410 as the conductive pin layer 152, that is, the conductive pin layer 152 is used to replace the dielectric The top of the electrical structure 160 is such that the conductive pin layer 152 is above the dielectric structure 160. In some embodiments of the present disclosure, the height HC (as shown in FIG. 5B) of the conductive pin layer 152 above the top surface of the memory structure layer 140 may be greater than the height above the top surface of the channel layer 150 before performing the selective etching process The height HD of the electrical structure 160 (as shown in FIG. 3B) is not intended to limit the disclosure.

Referring to FIGS. 6A to 6C, FIG. 6A shows a top view of forming the semiconductor structure 100 at step S60, FIG. 6B shows a cross-sectional view taken along line 6B-6B in FIG. 6A, and FIG. 6C shows 6C-6C along the line in Figure 6A Sectional view taken. In step S60, through a planarization process such as a chemical-mechanical polishing (CMP) process, a portion of the memory structure layer 140, a portion of the conductive plug layer 152, and a portion of the channel layer 150 beyond the groove 400 are removed, The top surface 131 of the topmost layer in the dielectric layer 130 is exposed. After the planarization process is performed, the memory structure group 300 including the memory structure layer 140, the channel layer 150, the conductive plug layer 152, and the dielectric structure 160 is formed above the substrate 110, and passes through the insulating layer 120 and the dielectric layer 130 ( (As shown in Figures 6A to 6B). In some embodiments of the present disclosure, the top surface 301 of the memory structure group 300 is substantially flush with the top surface 131 of the topmost layer of the dielectric layer 130.

Referring to FIGS. 7A to 7D, FIG. 7A shows a top view of forming the semiconductor structure 100 at step S70, FIG. 7B shows a cross-sectional view taken along line 7B-7B in FIG. 7A, and FIG. 7C shows The cross-sectional view taken along line 7C-7C in FIG. 7A, and FIG. 7D shows the cross-sectional view taken along line 7D-7D in FIG. 7A. In step S70, part of the dielectric layer 130, part of the insulating layer 120, part of the channel layer 150, part of the conductive plug layer 152, and part of the dielectric structure 160 are removed through the etching process to form the trench 170. As shown in FIG. 7A, after the trench 170 is formed, the memory structure group 300 is divided into a first memory structure 310 and a second memory structure 320, such that part of the insulating layer 120, part of the dielectric layer 130, Part of the memory structure layer 140 (including the barrier layer 142, the memory storage layer 144, and the tunneling layer 146), part of the channel layer 150, part of the conductive plug layer 152, and part of the dielectric structure 160 are exposed from the trench 170. As a result, the memory structure layer 140, the channel layer 150, and the dielectric structure 160 corresponding to the first memory structure 310 and the memory structure layer 140, the channel layer 150, and the dielectric structure 160 corresponding to the second memory structure 320, respectively Connected to the bottom of the trench 170. In this embodiment In this case, the first memory structure 310 and the second memory structure 320 have the same radius of curvature, but it is not used to limit the present disclosure. In other embodiments, the first memory structure 310 and the second memory structure 320 may have different radii of curvature.

As shown in FIGS. 7A to 7C, the etching process is stopped at the position indicated by the etch stop line L between the top surface 121 and the bottom surface 123 of the lowest layer in the insulating layer 120, so that the dielectric structure 160 is exposed from the bottom of the trench 170 Come out, and the memory structure layer 140, the channel layer 150, and the dielectric structure 160 corresponding to the first memory structure 310 are respectively connected to the memory structure layer 140, the channel layer 150, and the dielectric structure 160 corresponding to the second memory structure 320 . In some embodiments, as mentioned above in FIG. 1B, the bottom layer of the insulating layer 120 has a larger thickness, which provides additional etching flexibility, so that the etching process can be stopped in time by etching control The place marked by line L. In some embodiments of the present disclosure, the etching process may be a plasma etching process (Plasma Etching Process). In addition, the first memory structure 310 and the second memory structure 320 have complementary C-shaped cross sections, and the first memory structure 310 and the second memory structure 320 are bidirectionally symmetrical with respect to the groove 170.

Refer to FIGS. 8A to 8F, in which FIG. 8A shows a top view of forming the semiconductor structure 100 at step S80, FIG. 8B shows a cross-sectional view taken along line 8B-8B in FIG. 8A, and FIG. 8C shows Figure 8A is a cross-sectional view taken along line 8C-8C, Figure 8D is a cross-sectional view taken along line 8D-8D in Figure 8A, Figure 8E is a cross-sectional view taken along line 8E-8E in Figure 8A Fig. 8F shows a cross-sectional view taken along line 8F-8F in Fig. 8E. In step S80, the insulating layer 120 exposed from the trench 170 and the memory storage layer 144 exposed from the trench 170 are removed by a selective etching process to form the first A group of spaces 180 and a second group of spaces 190 (as shown in FIGS. 8E to 8F), which in turn leads to the memory structure group 300 (including the first memory structure 310 and the second memory structure) near the trench 170 There is a structural difference between the portion 320) (as shown in FIG. 8E) and the portion (as shown in FIG. 8D) of the memory structure group 300 slightly away from the trench 170. For example, as shown in FIG. 8D, the insulating layer 120 remains between the dielectric layer 130, and the memory storage layer 144 also remains between the barrier layer 142 and the tunneling layer 146; relatively, as shown in FIG. 8E As shown, the insulating layer 120 and the memory storage layer 144 are removed to form a first set of spaces 180 between the dielectric layer 130 and a second set of spaces 190 between the barrier layer 142 and the tunneling layer 146, respectively.

As shown in FIGS. 8A and 8F, the first group of spaces 180 is also formed between the insulating layer 120 and the trench 170. In addition, a second set of spaces 190 are formed on the edges of the first memory structure 310 and the second memory structure 320, respectively, and formed between the trench 170 and the memory storage layer 144. For example, the selective etching process is performed based on the difference in etching selectivity between the nitride material, the oxide material, and the polysilicon material, so that the exposed portion of the insulating layer 120 and the exposed portion of the memory storage layer 144 are removed At the same time, the barrier layer 142, the tunneling layer 146, the channel layer 150, and the dielectric structure 160 remain. In some embodiments of the present disclosure, the etching depth DF of the first group of spaces 180 is approximately the same as the etching depth DS of the second group of spaces 190, and the etching depths DF and DS can be up to about 100 Angstroms (Å), but they are not used To limit this disclosure.

Refer to FIGS. 9A to 9F, where FIG. 9A shows a top view of forming the semiconductor structure 100 at step S90, FIG. 9B shows a cross-sectional view taken along line 9B-9B in FIG. 9A, and FIG. 9C shows Figure 9A is a cross-sectional view taken along line 9C-9C, and Figure 9D is a cross-sectional view taken along line 9D-9D in Figure 9A In the top view, FIG. 9E shows a cross-sectional view taken along line 9E-9E in FIG. 9A, and FIG. 9F shows a cross-sectional view taken along line 9F-9F in FIG. 9E. In step S90, after removing the exposed portion of the insulating layer 120 and the exposed portion of the memory storage layer 144 through a selective etching process, a protective structure 210 is deposited on the first memory structure 310, the second memory structure 320 and the dielectric Above the topmost layer in layer 130 and in trench 170. The protection structure 210 is also filled in the first group of spaces 180 and the second group of spaces 190, as shown in FIGS. 9E and 9F. Since the width WF of the first group of spaces 180 is greater than the width WS of the second group of spaces 190, the first group of spaces 180 may not be completely filled by the protection structure 210, and the second group of spaces 190 is completely filled by the protection structure 210. In other words, as shown in FIG. 9F, the protective structure 210 in the first group of spaces 180 can be regarded as a thin layer disposed on the sidewalls of the barrier layer 142 and the insulating layer 120. In some embodiments of the present disclosure, the protective structure 210 may be made of materials including silicon oxide or other dielectric materials, but it is not intended to limit the present disclosure.

Similar to step S80 discussed above, the portion (as shown in FIG. 9E) of the memory structure group 300 (including the first memory structure 310 and the second memory structure 320) near the groove 170 is slightly away from the groove There are structural differences between the portions of the memory structure group 300 of the slot 170 (as shown in FIG. 9D). That is, as shown in FIG. 9D, the insulating layer 120 remains between the dielectric layer 130, and the memory storage layer 144 also remains between the barrier layer 142 and the tunneling layer 146; relatively, as shown in FIG. 9E As shown, the protective structure 210 is formed in a first group of spaces 180 (as shown in FIG. 8E) between the dielectric layers 130 and a second group of spaces between the barrier layer 142 and the tunneling layer 146 190 (as shown in Figure 8E).

Referring to FIGS. 10A to 10F, FIG. 10A shows a top view of forming the semiconductor structure 100 at step S100, FIG. 10B shows a cross-sectional view taken along line 10B-10B in FIG. 10A, and FIG. 10C shows Figure 10A is a cross-sectional view taken along line 10C-10C, Figure 10D is a cross-sectional view taken along line 10D-10D in Figure 10A, and Figure 10E is a cross-sectional view taken along line 10E-10E in Figure 10A Fig. 10F shows a cross-sectional view taken along line 10F-10F in Fig. 10E. In step S100, the protective structure 210 above the topmost layer in the first memory structure 310, the second memory structure 320, and the dielectric layer 130 and in the trench 170 is removed through a selective etching process. In addition, by performing the selective etching process, the protective structure 210 in the first group of spaces 180 is also completely removed, and the protective structure 210 in the second group of spaces 190 is partially removed, as shown in FIGS. 10E to 10F The picture shows. In some embodiments, when the insulating layer 120 is exposed from the first set of spaces 180, the etching process is stopped. Since the depth of the protective structure 210 in the first group of spaces 180 is smaller than the depth of the protective structure 210 in the second group of spaces 190, when the etching process is stopped, the protective structure 210 remains partially in the second group of spaces 190. In addition, since the dielectric structure 160, the barrier layer 142 and the tunneling layer 146 can also be made of materials containing silicon oxide or other dielectric materials, the etching process in this step can also be performed on the dielectric structure 160 and the barrier layer 142 And the tunneling layer 146, so that part of the dielectric structure 160, part of the barrier layer 142, and part of the tunneling layer 146 are removed, as shown in FIG. 10F.

In this way, as shown in FIGS. 10A and 10F, the protection structure 210 is located on the edges of the first memory structure 310 and the second memory structure 320, respectively, and between the barrier layer 142 and the tunneling layer 146. In other words, guarantee The protective structure 210 is located between the memory storage layer 144 and the trench 170, at opposite ends of the memory storage layer 144, and is adjacent to the memory storage layer 144. In more detail, since the second set of spaces 190 is formed between the barrier layer 142 and the tunneling layer 146, the second set of spaces 190 can be regarded as a recess, the recesses are located at opposite ends of the memory structure layer 140, and the protection structure 210 are respectively disposed in the concave portions.

Referring to FIGS. 11A to 11F, FIG. 11A shows a top view of forming the semiconductor structure 100 at step S110, FIG. 11B shows a cross-sectional view taken along line 11B-11B in FIG. 11A, and FIG. 11C shows Fig. 11A is a cross-sectional view taken along line 11C-11C, Fig. 11D is a cross-sectional view taken along line 11D-11D in Fig. 11A, and Fig. 11E is a cross section taken along line 11E-11E in Fig. 11A FIG. 11F is a cross-sectional view taken along line 11F-11F in FIG. 11E. In step S110, the insulating layer 120 between the dielectric layers 130 is removed by a selective etching process to form a third group of spaces 200 as shown in FIGS. 11D to 11F. Among them, the first group of spaces 180 and the third group of spaces 200 are located between the dielectric layers 130. In some embodiments of the present disclosure, the selective etching process may be a chemical etching process that removes the insulating layer 120 of a material containing silicon nitride in hot phosphoric acid. Since the memory storage layer 144 containing a material of silicon nitride is protected by the protection structure 210 (as shown in FIG. 11F), the memory storage layer 144 is not removed during the etching process. In this way, the memory storage layer 144 and the protection structure 210 may remain between the barrier layer 142 and the tunneling layer 146, as shown in FIGS. 11A and 11F.

Referring to FIGS. 12A to 12F, FIG. 12A shows a top view of forming the semiconductor structure 100 at step S120, FIG. 12B shows a cross-sectional view taken along line 12B-12B in FIG. 12A, and FIG. 12C shows Figure 12B Partially enlarged view, Figure 12D shows a cross-sectional view taken along line 12D-12D in Figure 12A, Figure 12E shows a cross-sectional view taken along line 12E-12E in Figure 12A, Figure 12F shows Figure 12A Sectional view taken along line 12F-12F. In step S120, after the insulating layer 120 is removed through the selective etching process, a conductive layer 220 is provided above the top surface of the semiconductor structure 100 and between the dielectric layer 130. For example, the conductive layer 220 is disposed above the topmost layer of the first memory structure 310, the second memory structure 320, and the dielectric layer 130 and in the trench 170. As shown in FIGS. 12B to 12F, the conductive layer 220 is also disposed between the first group of spaces 180 (as shown in FIG. 11E) and the third group of spaces 200 (as shown in FIG. 11D) between the dielectric layers 130. In this case, the insulating layer 120 is replaced with the conductive layer 220 in this way. As shown in FIG. 12C, each conductive layer 220 includes a shielding layer 222 disposed on each dielectric layer 130 and a metal layer 224 disposed on the shielding layer 222. The conductive layer 220 can be provided through a chemical vapor deposition (CVD) process. In some embodiments of the present disclosure, the shielding layer 222 may be made of a material containing titanium nitride, and the metal layer 224 may be made of a material containing tungsten or other metals, but it is not intended to limit the present disclosure.

In the above embodiment of the present disclosure, the manufacturing method of the semiconductor structure 100 provides a method of replacing the insulating layer 120 with the conductive layer 220 while retaining the memory storage layer 144 containing the same material as the insulating layer 120, thereby simplifying the manufacturing process.

In some embodiments of the present disclosure, a high dielectric constant (high-k) dielectric layer 230 is disposed above the topmost layer of the first memory structure 310, the second memory structure 320, and the dielectric layer 130, and the trench 170 Between the middle and dielectric layers 130 and the shielding layer 222, as shown in FIG. 12C. For example, the conductive layer 220 may be provided The high dielectric constant dielectric layer 230 was previously provided. In addition, the high dielectric constant dielectric layer 230 may be made of a material containing aluminum oxide or other dielectric materials.

Referring to FIGS. 13A to 13E, FIG. 13A shows a top view of forming the semiconductor structure 100 at step S130, FIG. 13B shows a cross-sectional view taken along line 13B-13B in FIG. 13A, and FIG. 13C shows Figure 13A is a cross-sectional view taken along line 13C-13C, Figure 13D is a cross-sectional view taken along line 13D-13D in Figure 13A, and Figure 13E is a cross-sectional view taken along line 13E-13E in Figure 13A Figure. In step S130, the high dielectric constant dielectric layer 230 located above the topmost layer in the first memory structure 310, the second memory structure 320, the dielectric layer 130 and the trench 170 is removed by a selective etching process And the conductive layer 220, so that the first memory structure 310 and the second memory structure 320 are exposed from the trench 170. In some embodiments of the present disclosure, as shown in FIG. 13C, the conductive layer 220 and the side wall 223 of the high dielectric constant dielectric layer 230 may not be aligned with the side wall 133 of the dielectric layer 130; on the contrary, the conductive layer 220 and the high layer The sidewall 233 of the dielectric constant dielectric layer 230 is etched to a deeper depth to form a recess 225 between the dielectric layers 130. This ensures that the conductive layer 220 and the high dielectric constant dielectric layer 230 disposed in the trench 170 are completely removed through the selective etching process.

Referring to FIGS. 14A to 14E, FIG. 14A shows a top view of forming the semiconductor structure 100 at step S140, FIG. 14B shows a cross-sectional view taken along line 14B-14B in FIG. 14A, and FIG. 14C shows Figure 14A is a cross-sectional view taken along line 14C-14C, Figure 14D is a cross-sectional view taken along line 14D-14D in Figure 14A, and Figure 14E is a cross-section taken along line 14E-14E in Figure 14A Figure. In step S140, the insulating structure 240 is then filled in the trench 170 and provided in the first memory structure 310 and the second memory Above the topmost layer in the structure 320 and the dielectric layer 130. The insulating structure 240 has a T-shaped vertical cross section, as shown in FIGS. 14B to 14C. That is, the insulating structure 240 has a first portion interposed between the first memory structure 310 and the second memory structure 320 and a second portion above the semiconductor structure 100. After the insulating structure 240 is provided, a semiconductor structure 100 having a U-shaped vertical cross-sectional memory structure group 300 (including the first memory structure 310 and the second memory structure 320) is generated. As shown in Figure 14A to Figure 14B. In some embodiments of the present disclosure, the memory structure layer 140, the channel layer 150, and the dielectric structure 160 corresponding to the first memory structure 310 and the memory structure layer 140, the channel layer 150 corresponding to the second memory structure 320, respectively The dielectric structure 160 is connected to the bottom surface 241 of the insulating structure 240. In some other embodiments of the present disclosure, an interlayer dielectric (ILD) layer (not shown in the figure) may be further disposed above the top surface of the insulating structure 240 so that the top surface of the semiconductor structure 100 is flat The conversion was completed. The interlayer dielectric layer may be made of materials including silicon oxide or other dielectric materials, but it is not intended to limit the present disclosure.

In the above embodiment of the present disclosure, the manufactured semiconductor structure 100 includes the substrate 110, the conductive layer 220, the dielectric layer 130, the insulating structure 240, the first memory structure 310 and the second memory structure 320. The conductive layer 220 and the dielectric layer 130 are alternately stacked on the substrate 110. The insulating structure 240 is disposed above the substrate 110 and passes through the conductive layer 220 and the dielectric layer 130. The first memory structure 310 and the second memory structure 320 are disposed above the substrate 110, pass through the conductive layer 220 and the dielectric layer 130, and are located on opposite sidewalls 242, 244 of the insulating structure 240. In addition, the first memory structure 310 and the second memory structure 320 have respective radii of curvature. The first memory structure 310 and the second memory structure Each 320 includes a memory structure layer 140, a channel layer 150, a dielectric structure 160, and a protection structure 210. The memory structure layer 140 includes a memory storage layer 144. The channel layer 150 is disposed between the memory structure layer 140 and the insulating structure 240. The dielectric structure 160 is disposed between the channel layer 150 and the insulating structure 240, and a portion of the channel layer 150 is disposed above the top surface of the dielectric structure 160. The protection structure 210 is disposed between the opposite sidewalls 242 and 244 of the memory storage layer 144 and the insulating structure 240, and is located at both ends of the memory storage layer 144, wherein the etching selectivity of the protection structure 210 and the memory storage layer 144 are different .

Since the first memory structure 310 and the second memory structure 320 of the semiconductor structure 100 are separated from each other by the insulating structure 240, the memory density in the unit area is increased, and thus a larger memory storage capacity is achieved. In addition, since the conductive layer 220 stacked between the dielectric layers 130 has a lower resistance, it can help increase the programming speed and the erasing speed of the semiconductor structure 100.

The connection relationship, materials and functions of the components that have been described will not be repeated, and will be described first. In the following description, the details of providing the semiconductor device 500 by processing the manufactured semiconductor structure 100 will be further explained.

Referring to FIGS. 15A to 15D, FIG. 15A shows a top view of forming semiconductor device 500 at step S150, FIG. 15B shows a cross-sectional view taken along line 15B-15B in FIG. 15A, and FIG. 15C shows The cross-sectional view taken along line 15C-15C in FIG. 15A, and FIG. 15D shows the cross-sectional view taken along line 15D-15D in FIG. 15A. In step S150, after the semiconductor structure 100 is provided, two contact holes 246, 248 are then formed in the insulating structure 240 above the memory structure group 300 so that the channel layer 150 corresponding to a portion of the first memory structure 310 And part of the conductive plug layer 152 corresponds to the second Part of the channel layer 150 and part of the conductive plug layer 152 of the memory structure 320 are exposed from the contact hole 246 and the contact hole 248, respectively. Next, two first contact structures 420 and 430 are formed in the two contact holes 246 and 248 respectively, and are electrically connected to the channel layer 150 and the conductive plug layer 152 of the first memory structure 310 and the second memory structure respectively The channel layer 150 and the conductive plug layer 152 of 320.

Referring to FIGS. 16A to 16D, FIG. 16A shows a top view of forming semiconductor device 500 at step S160, FIG. 16B shows a cross-sectional view taken along line 16B-16B in FIG. 16A, and FIG. 16C shows The cross-sectional view taken along line 16C-16C in FIG. 16A, and the cross-sectional view taken along line 16D-16D in FIG. 16A are shown in FIG. 16D. In step S160, an isolation layer 250 is further formed over the insulating structure 240, and then two second contact structures 440, 450 are formed in the isolation layer 250, and are electrically connected to the two first contact structures 420, 430, respectively.

Referring to FIGS. 17A and 17B, FIG. 17A illustrates a top view of forming the semiconductor device 500 at step S170, and FIG. 17B illustrates a cross-sectional view taken along line 17B-17B in FIG. 17A. In step S170, the plurality of semiconductor structures 100 are arranged parallel to each other along the Y axis. In other words, the insulating structure 240 in the semiconductor structure 100 may be continuously formed along the Y axis. In addition, the semiconductor structures 100 may be staggered with each other along the X axis.

Referring to FIGS. 18A and 18B, FIG. 18A illustrates a top view of forming semiconductor device 500 at step S180, and FIG. 18B illustrates a cross-sectional view taken along line 18B-18B in FIG. 18A. In step S180, a signal line such as a common source line (Common Source Line, CSL) may be formed to be electrically connected to the second contact structure formed above the adjacent semiconductor structure 100 440, and the common source line is parallel to the continuously formed insulating structure 240.

Referring to FIGS. 19A to 19D, FIG. 19A shows a top view of forming semiconductor device 500 at step S190, FIG. 19B shows a cross-sectional view taken along line 19B-19B in FIG. 19A, and FIG. 19C shows FIG. 19A is a cross-sectional view taken along line 19C-19C, and FIG. 19D is a cross-sectional view taken along line 19D-19D in FIG. 19A. In step S190, the third contact structure 460 is then electrically connected to the second contact structure 440/450, and the second contact structure 440/450 electrically connected to the third contact structure 460 is not electrically connected to the common source line. Then, a bit line (Bit Line, BL, that is, a signal line) may be formed above the common source line, and the bit line is electrically connected to the third contact structure 460. The bit line is generally orthogonal to the common source line and the continuous insulating structure 240. After forming the bit lines, the semiconductor device 500 is obtained.

In the above embodiment of the present disclosure, as shown in FIG. 19D, when the semiconductor device 500 is used in a three-dimensional (3D) memory device, the most of the conductive layers 220 on the opposite side walls 242, 244 of the insulating structure 240 The top layer may serve as a ground select line (GSL) and a string select line (SSL), respectively, and the semiconductor device 500 is, for example, a vertical channel memory device.

In the following description, a semiconductor structure 100a of another embodiment of the present disclosure is provided. 20A to 20B illustrate a semiconductor structure 100a according to another embodiment of the present disclosure.

Referring to FIGS. 20A and 20B, FIG. 20A illustrates a top view of forming the semiconductor structure 100a at step S200, and FIG. 20B illustrates a cross-sectional view taken along line 20B-20B in FIG. 20A. Compared to Figures 14A to In the semiconductor structure 100 shown in FIG. 14E, the semiconductor structure 100a includes a memory structure group 300 that does not have a U-shaped vertical cross section. In this embodiment, the memory structure layer 140, the channel layer 150, and the dielectric structure 160 corresponding to the first memory structure 310 and the memory structure layer 140, the channel layer 150, and the dielectric structure corresponding to the second memory structure 320, respectively The structures 160 are separated by the insulating structure 240, and the channel layers 150 each contact the substrate 110. For example, the channel layers 150 are each electrically connected to the circuit disposed above the substrate 110.

In order to obtain the semiconductor structure 100a shown in FIGS. 20A to 20B, a manufacturing method is further provided. The manufacturing method here is substantially the same as the manufacturing method described above, but there are some differences in forming the groove 400 shown in FIGS. 1A and 1B and the trench 170 shown in FIGS. 7A and 7B. In detail, a different step of the manufacturing method here is that after forming the memory structure layer 140 in the groove 400, the groove 400 is extended through the memory structure layer 140 so that part of the substrate 110 is exposed from the bottom of the groove 400 come out. Next, a channel layer 150 is formed over the exposed portions of the memory structure layer 140 and the substrate 110. For subsequent steps, refer to the manufacturing method mentioned in the above embodiment. Another difference lies in the step of forming the trench 170 through the insulating layer 120, the dielectric layer 130, and the memory structure group 300. Here, the trench 170 is formed by removing part of the insulating layer 120, part of the dielectric layer 130, part of the channel layer 150, part of the conductive plug layer 152, and part of the dielectric structure 160, so as to correspond to the first memory The memory structure layer 140, the channel layer 150, the conductive latch layer 152, and the dielectric structure 160 of the body structure 310 and the memory structure layer 140, the channel layer 150, the conductive latch layer 152, and the dielectric structure corresponding to the second memory structure 320, respectively 160 is separated from each other by the trench 170 and the insulating structure 240 provided later. The channel layers 150 are each connected to the substrate 110 Touch, so that the channel layers 150 are each electrically connected to the circuit disposed above the substrate 110.

The connection relationship, materials and functions of the components that have been described will not be repeated, and will be described first. In the following description, the details of providing the semiconductor device 500a by processing the manufactured semiconductor structure 100a will be further explained.

Referring to FIGS. 21A to 21C, FIG. 21A shows a top view of forming semiconductor device 500a at step S210, FIG. 21B shows a cross-sectional view taken along line 21B-21B in FIG. 21A, and FIG. 21C shows Sectional view taken along line 21C-21C in Figure 21A. Compared to the semiconductor device 500 shown in FIGS. 19A to 19D, a common source line is not formed above the two second contact structures 440, 450 of the semiconductor structure 100a; conversely, on the second contact structures 440, 450 Two third contact structures 460, 470 are formed above. In addition, the first contact structure 420, the second contact structure 440 and the third contact structure 460 corresponding to the first memory structure 310 are in contact with the first contact structure 430 and the second contact structure 450 corresponding to the second memory structure 320, respectively The third contact structures 470 are staggered. Bit lines are formed above the semiconductor device 500a to form a first group of bit lines (BL1) and a second group of bit lines (BL2). The first set of bit lines is electrically connected to the third contact structure 460 disposed above the first memory structure 310, and the second set of bit lines is electrically connected to the third contact disposed above the second memory structure 320 Structure 470.

In the above-mentioned embodiments of the present disclosure, when the semiconductor device 500a is used in a three-dimensional (3D) memory device, the substrate 110 may serve as a bottom source, and the lowest layer in the conductive layer 220 is, for example, a ground selection line (GSL), and Conductive layer 220 The topmost layer in is, for example, a string selection line (SSL), and the semiconductor device 500a is, for example, a vertical channel type memory device. In addition, since the bidirectionally symmetrically arranged first memory structure 310 and second memory structure 320 are respectively connected to different bit lines (BL1 and BL2, that is, signal lines), the memory density increases, and due to different vertical The memory structure can select different bit lines to handle different programming/erase operations at the same time, so the processing speed can be further improved.

Although this disclosure has been disclosed as above by way of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this skill should be able to make various changes and retouching within the spirit and scope of this disclosure, so the protection of this disclosure The scope shall be determined by the scope of the attached patent application.

100‧‧‧Semiconductor structure

152‧‧‧conductive latch layer

210‧‧‧Protection structure

310‧‧‧ First memory structure

320‧‧‧Second memory structure

S140‧‧‧Step

14B-14B~14E-14E‧‧‧line segment

Claims (10)

A semiconductor structure includes: a substrate; a plurality of conductive layers and a plurality of dielectric layers stacked alternately on the substrate; an insulating structure disposed on the substrate and passing through the conductive layers and the dielectric layers ; And a first memory structure and a second memory structure, each having a radius of curvature, and through the conductive layers and the dielectric layers, and located on the opposite side walls of the insulating structure, wherein the first memory The body structure and the second memory structure each include: a memory structure layer including a memory storage layer; a channel layer disposed between the memory structure layer and the insulating structure; and at least two protective structures disposed on the memory At both ends of the storage layer, the etching selectivity of the at least two protective structures is different from that of the memory storage layer. The semiconductor structure according to claim 1, wherein the memory structure layer further includes a barrier layer and a tunneling layer, and the barrier layer is disposed on the plurality of side walls of the conductive layers and the dielectric layers, and the memory The storage layer is disposed between the barrier layer and the tunneling layer, and the at least two protective structures are disposed between the barrier layer and the tunneling layer and are adjacent to the memory storage layer. The semiconductor structure of claim 1, wherein the first memory structure and the second memory structure each further include a dielectric structure and a A conductive plug layer, and the dielectric structure is disposed between the channel layer and the insulating structure, and the conductive plug layer is disposed above the dielectric structure. The semiconductor structure of claim 1, wherein the memory structure layer and the channel layer of the first memory structure are respectively in contact with the memory structure layer and the channel layer corresponding to the second memory structure of the insulating structure Connected to the bottom. The semiconductor structure of claim 1, wherein the memory structure layer and the channel layer of the first memory structure are separated from the memory structure layer and the channel layer corresponding to the second memory structure through the insulating structure, respectively . The semiconductor structure according to claim 1, further comprising: two contact structures electrically connected to the first memory structure and the second memory structure, respectively. A method for manufacturing a semiconductor structure includes: forming a plurality of insulating layers and a plurality of dielectric layers alternately stacked on a substrate; forming a memory structure group on the substrate and passing through the insulating layers and the dielectrics Layer, wherein the memory structure group includes a channel layer, a conductive pin layer, and a memory structure layer including a memory storage layer; forming a trench through the insulating layers, the dielectric layers, and the memory structure Group, so that the memory structure group is divided into a first memory structure and a second A memory structure, and the plurality of portions of the insulating layers and the plurality of portions of the memory storage layer are exposed by the trench; removing the exposed portions of the insulating layers and the exposed portions of the memory storage layer To form a first group of spaces and a second group of spaces; fill a plurality of protection structures in the first group of spaces and the second group of spaces; remove a plurality of parts of the protection structures to make the insulation The layers are exposed from the first set of spaces; and the insulating layers are replaced with a plurality of conductive layers. The method for manufacturing a semiconductor structure according to claim 7, wherein replacing the insulating layers with the conductive layers comprises: after the insulating layers are exposed, removing the insulating layers to form a third group of spaces in Between the dielectric layers; and filling the conductive layers in the first set of spaces and the third set of spaces. The method for manufacturing a semiconductor structure according to claim 8, further comprising: after filling the conductive layers in the first set of spaces and the third set of spaces, forming an insulating structure in the trench, the memory The top of the structure group and one of the dielectric layers. The method for manufacturing a semiconductor structure according to claim 7, wherein the memory structure group further includes a dielectric structure, and the channel layer is located between the dielectric structure and the memory structure layer and forms the memory structure group To the Above the substrate and passing through the insulating layers and the dielectric layers further includes: forming a groove with an elliptical profile, wherein the groove passes through the insulating layers and the dielectric layers; forming the memory structure A layer in the groove and a top layer of the dielectric layers; forming the channel layer over the memory structure layer; forming the dielectric structure over the channel layer to fill the groove; using the conductive plug A layer replaces a top of the dielectric structure; and removes a portion of the memory structure layer that exceeds the groove, a portion of the conductive pin layer, and a portion of the channel layer.

Images