CN114334834A

CN114334834A - Manufacturing method of semiconductor device and semiconductor device

Info

Publication number: CN114334834A
Application number: CN202011081305.1A
Authority: CN
Inventors: 徐康元; 高建峰; 白国斌; 刘卫兵; 李俊杰
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2022-04-12

Abstract

The invention provides a manufacturing method of a semiconductor device and the semiconductor device, the manufacturing method comprises the following steps: providing a substrate; forming a doped layer covering the substrate above the substrate; the doping concentration of impurities in the doping layers is changed from bottom to top alternately, and the doping concentration of the impurities at the bottom of the doping layers is larger than that of the impurities at the top of the doping layers; etching the doped layer to form a capacitor hole pattern, wherein the capacitor hole pattern comprises at least one capacitor hole, and the hole wall of each capacitor hole is in convex-concave alternating change from bottom to top; a capacitor is formed within each capacitive aperture. By forming the doping layer on the substrate, the doping concentration of impurities in the doping layer is changed alternately, so that the capacitor hole with the pore diameter changed alternately can be etched, and the pore wall of the capacitor hole is changed in a convex-concave shape alternately. Based on the fact that the capacitor hole is provided with the hole wall which is in convex-concave alternating change, the side wall of the lower electrode of the capacitor formed in the capacitor hole can also be in convex-concave alternating change, and the side wall of the lower electrode has larger surface area.

Description

Manufacturing method of semiconductor device and semiconductor device

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.

Background

A Capacitor (Capacitor) is a component that can store electricity and electrical energy. Different amounts of charge can be stored in the capacitor by applying different voltages across the two electrodes of the capacitor. On this basis, the storage of different data can be realized by a capacitor. It follows that the quality of the capacitor directly affects the data storage performance of the semiconductor device.

However, as the integration density of DRAM (dynamic random access memory) semiconductor devices increases, the Aspect Ratio (Aspect Ratio) of capacitors also gradually increases. The capacitor manufactured by the existing semiconductor device process has a smaller bottom surface area of the lower electrode, so that the storage capacity of the capacitor is smaller, and the data storage performance of the semiconductor device is poorer.

Disclosure of Invention

The invention provides a manufacturing method of a semiconductor device and the semiconductor device, which are used for increasing the bottom surface area of a lower electrode and increasing the surface area of the side wall of the lower electrode of a capacitor, thereby increasing the storage capacity of the capacitor and improving the data storage performance of the semiconductor device.

In a first aspect, the present invention provides a method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

forming a doped layer covering the substrate above the substrate; the doping concentration of impurities in the doping layers is changed from bottom to top alternately, and the doping concentration of the impurities at the bottom of the doping layers is greater than that of the impurities at the top of the doping layers;

etching the doped layer to form a capacitor hole pattern, wherein the capacitor hole pattern comprises at least one capacitor hole, and the hole wall of each capacitor hole from bottom to top is in convex-concave alternating change;

a capacitor is formed within each capacitive aperture.

In the above scheme, the doping layer is formed on the substrate, and the doping concentration of the impurities in the doping layer is changed alternately, so that the capacitor hole with the hole diameter changed alternately can be etched, and the hole wall of the capacitor hole is changed in a convex-concave manner alternately. Based on the fact that the capacitor hole is provided with the hole wall which is in convex-concave alternating change, the side wall of the lower electrode of the capacitor formed in the capacitor hole can also be in convex-concave alternating change, and the side wall of the lower electrode has larger surface area. In addition, because the doping concentration of the impurities at the bottom of the doping layer is greater than that of the impurities at the top of the doping layer, the capacitor hole in the shape of the upper and lower equal width can be formed by etching the doping layer, namely, the aperture of the convex structure on the side wall of the capacitor hole is more consistent from top to bottom, and the aperture of the concave structure on the side wall of the capacitor hole is more consistent. The capacitor is formed in the capacitor hole with the side walls in convex-concave alternative change, the convex structures are equal in width from top to bottom, and the concave structures are equal in width from top to bottom, so that the lower electrode of the capacitor is large in side wall surface area and bottom surface area, the storage capacity of the capacitor can be increased, and the data storage performance of the semiconductor device is improved. And the bottom surface area of the lower electrode is larger, so that the contact area between the lower electrode and a structure in contact with the lower electrode can be increased, the contact resistance is reduced, and the working performance of the semiconductor device is improved.

In a specific embodiment, the doped layer comprises at least two pairs of doped stacks stacked over the substrate, each pair of doped stacks comprising a first sublayer and a second sublayer formed on the first sublayer; between any two adjacent pairs of doped stacks, a first sublayer of an upper pair of doped stacks is stacked on a second sublayer of a lower pair of doped stacks. In each pair of doped stacks, the doping concentration of the impurities in the first sub-layer is higher than the doping concentration of the impurities in the second sub-layer. In any two adjacent pairs of doped stacks, the doping concentration of impurities in the second sub-layer in the lower pair of doped stacks is lower than that of impurities in the first sub-layer in the upper pair of doped stacks. And the hole wall surrounded by the first sub-layer on each capacitor hole is a concave structure with a larger hole diameter, and the hole wall surrounded by the second sub-layer on each capacitor hole is a convex structure with a smaller hole diameter.

In a specific embodiment, in each pair of doped stacks, the doping concentration of the impurities in the first sublayer is at least 2.0 wt% higher than that of the impurities in the second sublayer, so that the hole wall of the capacitor hole has a more obvious convex and concave structure, the surface area of the side wall of the lower electrode of the capacitor is increased, the storage capacity of the capacitor is increased, and the data storage performance of the semiconductor device is improved.

In a specific embodiment, in any two adjacent pairs of doping stacks, the doping concentration of impurities in the first sub-layer of the lower pair of doping stacks is higher than that of impurities in the first sub-layer of the upper pair of doping stacks; the doping concentration of the impurities in the second sublayers of the lower pair of doping stacks is higher than that of the impurities in the second sublayers of the upper pair of doping stacks. Therefore, from top to bottom, the aperture of the convex structure on the side wall of the capacitor hole is consistent, and the aperture of the concave structure on the side wall of the capacitor hole is consistent.

In a specific embodiment, in any two adjacent pairs of doped stacks, the doping concentration of impurities in the first sub-layer of the lower pair of doped stacks is 0.1-1.0 wt% higher than that of impurities in the first sub-layer of the upper pair of doped stacks. The doping concentration of impurities in the second sublayers of the lower pair of doping laminated layers is 0.1-1.0 wt% higher than that of impurities in the second sublayers of the upper pair of doping laminated layers.

In one embodiment, the first and second sublayers of each pair of doped stacks have a thickness of

In a specific embodiment, at least one supporting layer is formed inside and/or above the doped layer; etching the doped layer to form a capacitor hole pattern includes: and etching the doped layer and the at least one supporting layer to form the capacitor hole pattern. By providing the support layer, the capacitor formed in the capacitance hole is prevented from collapsing.

In one embodiment, a landing plug is formed on the substrate. Forming a capacitor within each capacitive aperture includes: forming a lower electrode at the bottom and wall of the capacitor hole, wherein the lower electrode is in contact with the landing plug; forming a dielectric layer covering the lower electrode on the lower electrode; and forming an upper electrode covering the dielectric layer on the dielectric layer.

In one embodiment, after forming the lower electrode in each capacitor hole and before forming the dielectric layer on the lower electrode, the method further comprises: removing the doped layer between any two adjacent lower electrodes; and removing part of the supporting layer between any two adjacent lower electrodes, and reserving part of the supporting layer to form a supporting structure for supporting the lower electrodes.

In one embodiment, forming a dielectric layer on the lower electrode to cover the lower electrode comprises: forming a dielectric layer covering the lower electrode on the inner side wall and the outer side wall of the lower electrode and on the supporting structure; forming an upper electrode overlying the dielectric layer includes: and forming upper electrodes covering the dielectric layer and the support structure on the dielectric layer on the inner side and the outer side of the lower electrode. The dielectric layer and the upper electrode are arranged on the inner layer and the outer layer of the lower electrode, so that the utilization rate of the capacitor is increased.

In a second aspect, the present invention also provides a semiconductor device comprising:

a substrate, on which a landing plug is formed;

the doping layer is positioned on the substrate, and a capacitance hole is formed in the doping layer;

a capacitor located in the capacitor hole, the capacitor hole including a lower electrode in contact with the landing plug, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer;

the doping concentration of impurities in the doping layer is changed from bottom to top, and the doping concentration of the impurities at the bottom of the doping layer is greater than that of the impurities at the top of the doping layer;

the hole wall of the capacitor hole is convex-concave alternately from bottom to top, and the side wall of the lower electrode is convex-concave alternately from bottom to top.

Compared with the prior art, the beneficial effects of the semiconductor device provided by the invention are the same as the beneficial effect substrate of the manufacturing method of the semiconductor device provided by the technical scheme, and the details are not repeated here.

In a third aspect, the present invention also provides another semiconductor device, including:

a substrate, on which a landing plug is formed;

the capacitor is arranged on the substrate and comprises a cylindrical lower electrode in contact with the landing plug, dielectric layers covering the inner side wall and the outer side wall of the lower electrode and upper electrodes covering the dielectric layers positioned on the inner side and the outer side of the lower electrode;

wherein, the side walls of the lower electrode, the dielectric layer and the upper electrode are convex-concave alternately.

Compared with the prior art, the semiconductor device provided by the invention has the beneficial effects that in addition to the beneficial effects of the manufacturing method of the semiconductor device provided by the technical scheme, the dielectric layers and the upper electrodes are arranged on the inner side and the outer side of the lower electrode, so that the utilization rate of the capacitor is increased.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a substrate according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a doped layer overlying a substrate according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a capacitor hole etched in a doped layer according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a lower electrode formed in a capacitor hole according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a dielectric layer formed on a lower electrode according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of an upper electrode formed on a dielectric layer according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram illustrating a doped layer and a supporting layer formed on a substrate according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of etching a capacitor hole in a doped layer and a supporting layer according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a structure of forming a lower electrode in the capacitor hole of FIG. 9;

fig. 11 is a schematic structural diagram of fig. 10 after the doped layer between two adjacent lower electrodes is removed;

FIG. 12 is a schematic diagram illustrating a structure of forming a dielectric layer and an upper electrode on the lower electrode in FIG. 11 according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a process for fabricating another capacitor according to an embodiment of the present invention;

FIG. 14 is a schematic structural diagram of another process step in the fabrication of another capacitor according to an embodiment of the present invention;

FIG. 15 is a schematic structural diagram of another process in the manufacture of another capacitor according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of another process step in the fabrication of another capacitor according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of another process in the process of manufacturing another capacitor according to the embodiment of the present invention.

Reference numerals:

10-substrate 11-landing plug 12-isolation

20-doped layer 21-doped stack 211-first sublayer

212-second sublayer 30-capacitive aperture 31-bump structure

32-recessed structure 41-lower electrode 42-dielectric layer

43-upper electrode 50-support layer 51-support structure

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

To facilitate understanding of the method for manufacturing a semiconductor device according to the embodiment of the present invention, an application scenario of the method for manufacturing a semiconductor device according to the embodiment of the present invention is first described below, where the method for manufacturing a capacitor in a semiconductor device is used, and the semiconductor device may specifically be an electronic device such as a DRAM (dynamic random access memory) or a FLASH memory. The method for manufacturing the semiconductor device will be described in detail below with reference to the accompanying drawings.

Referring to fig. 1, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:

s10: providing a substrate;

s20: forming a doped layer covering the substrate above the substrate; the doping concentration of impurities in the doping layers is changed from bottom to top alternately, and the doping concentration of the impurities at the bottom of the doping layers is greater than that of the impurities at the top of the doping layers;

s30: etching the doped layer to form a capacitor hole pattern, wherein the capacitor hole pattern comprises at least one capacitor hole, and the hole wall of each capacitor hole from bottom to top is in convex-concave alternating change;

s40: a capacitor is formed within each capacitive aperture.

In the above scheme, the doping layer is formed on the substrate, and the doping concentration of the impurities in the doping layer is changed alternately, so that the capacitor hole with the hole diameter changed alternately can be etched, and the hole wall of the capacitor hole is changed in a convex-concave manner alternately. Based on the fact that the capacitor hole is provided with the hole wall which is in convex-concave alternating change, the side wall of the lower electrode of the capacitor formed in the capacitor hole can also be in convex-concave alternating change, and the side wall of the lower electrode has larger surface area. In addition, because the doping concentration of the impurities at the bottom of the doping layer is greater than that of the impurities at the top of the doping layer, the capacitor hole in the shape of the upper and lower equal width can be formed by etching the doping layer, namely, the aperture of the convex structure on the side wall of the capacitor hole is more consistent from top to bottom, and the aperture of the concave structure on the side wall of the capacitor hole is more consistent. The capacitor is formed in the capacitor hole with the side walls in convex-concave alternative change, the convex structures are equal in width from top to bottom, and the concave structures are equal in width from top to bottom, so that the lower electrode of the capacitor is large in side wall surface area and bottom surface area, the storage capacity of the capacitor can be increased, and the data storage performance of the semiconductor device is improved. And the bottom surface area of the lower electrode is larger, so that the contact area between the lower electrode and a structure in contact with the lower electrode can be increased, the contact resistance is reduced, and the working performance of the semiconductor device is improved. Each of the above steps will be described in detail with reference to the accompanying drawings.

First, referring to fig. 2, a substrate 10 is provided. The substrate 10 may be a structure including a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, and the like. The substrate 10 may also be a stacked structure in which a portion of the semiconductor structure has been formed. For example, when a DRAM is manufactured by using the manufacturing method provided by the embodiment of the present invention, the substrate 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a memory contact, an insulating portion, a landing plug 11, and an isolation portion 12. The transistor may be formed on a substrate of a semiconductor device. A bitline structure may be formed over the transistor. A storage contact and an insulating portion are formed between adjacent bit line structures. The storage contact portion is in contact with a source region or a drain region of the transistor. The insulating part is used for isolating two adjacent storage contact parts. Meanwhile, each landing plug 11 is formed on the storage contact portion corresponding thereto. The landing plug 11 is electrically connected to a source region or a drain region of the transistor through a storage contact. An isolation portion 12 is formed on the bit line structure and the insulating portion, and the isolation portion 12 is used to isolate the adjacent two landing plugs 11.

Next, referring to fig. 3, over the substrate 10, a doped layer 20 is formed covering the substrate 10. Doped layer 20 may comprise a material that facilitates removal. The amount, type and concentration range of the impurities doped in the doped layer 20 may be set according to practical application scenarios, and are not limited herein. The doping concentration profile of the impurities in the doping layer 20 is: the doping concentrations of the impurities in the bottom-up doping layers 20 are alternately changed, that is, the doping concentrations of the impurities in different depth layers in the bottom-up doping layers 20 are alternately changed in the sequence of 'decreasing, increasing, decreasing and increasing … …'. And the doping concentration of the impurity at the bottom of the doping layer 20 is greater than that at the top of the doping layer 20, i.e. the doping concentration of the deepest depth layer in the doping layer 20 is greater than that of the shallowest depth layer in the doping layer 20.

For example, the doped layer 20 may include at least two pairs of doped stacks 21 stacked over the substrate 10, each pair of doped stacks 21 including a first sublayer 211, and a second sublayer 212 formed on the first sublayer 211; between any adjacent two pairs of doped stacks 21, the first sublayer 211 of the upper pair of doped stacks 21 is stacked on the second sublayer 212 of the lower pair of doped stacks 21. As shown in fig. 3, the number of pairs of doped stacks 21 may be 8, each pair including a first sublayer 211 and a second sublayer 212. From bottom to top, they are denoted by D1_1, D1_2, D2_1, D2_2, … …, D8_1, and D8_2, wherein the "front" D1, etc. denotes the number of pairs of different doped stacks 21, and the "rear" 1 and 2 denote the first and

second sublayers

211 and 212, respectively, in each pair of doped stacks 21. It should be understood that the number of pairs of doping stacks 21 is not limited to 8 pairs in fig. 3, but the number of pairs of doping stacks 21 may be any value more than 2 pairs of 5 pairs, 7 pairs, 9 pairs, 11 pairs, etc. It should be noted that the number of sublayers in each pair of doped stacks 21 is not limited to the two shown above, and besides, there may be 3 sublayers, 4 sublayers, etc. in the doped stacks 21.

May be provided in each of the at least two pairs of doping stacks 21, the doping concentration of the impurities in the first sub-layer 211 being higher than the doping concentration of the impurities in the second sub-layer 212. In any two adjacent pairs of doped stacks 21, the doping concentration of the impurity in the second sub-layer 212 of the lower pair of doped stacks 21 is lower than the doping concentration of the impurity in the first sub-layer 211 of the upper pair of doped stacks 21. And the doping concentration of the impurity in the first sub-layer 211 in the lowermost pair of doping stacks 21 is greater than the doping concentration of the impurity in the second sub-layer 212 in the uppermost pair of doping stacks 21. So that the doping concentration of the impurity in the doping layer 20 is alternately changed from bottom to top, and the doping concentration of the impurity at the bottom of the doping layer 20 is greater than that at the top of the doping layer 20.

In particular determining the type of impurities in doped layer 20 and doped layer 20, doped layer 20 may be a borosilicate glass layer (BSG), i.e., by doping a silicon glass layer with boron to obtain doped layer 20. At this time, the doping concentration of the impurity means: the doping concentration of impurity boron in different depth layers in the silicon glass layer.

It should be understood that the type of impurities in doped layer 20 is not limited to that shown above, and other types of impurities may be used.

For example, doped layer 20 may also be a phosphosilicate glass layer (PSG), i.e., by doping a silicon glass layer with phosphorous to obtain doped layer 20. At this time, the doping concentration of the impurity means: the doping concentration of impurity phosphorus in different depth layers in the silicon glass layer.

The doped layer 20 may also be a borophosphosilicate glass layer (BPSG). I.e. by doping the silicon glass layer with boron and phosphorus to obtain the doped layer 20. At this time, the doping concentration of the impurity means: the doping concentration of impurity phosphorus in different depth layers in the silicon glass layer and the doping concentration of impurity boron in different depth layers in the silicon glass layer. It should be noted that, at this time, the change in the doping concentration of the impurity of different depth layers within the doping layer 20 refers to the change in the doping concentration of the same type of impurity, that is, the doping concentrations of the impurities boron and phosphorus respectively satisfy the above-described doping concentration profile.

When determining the thicknesses of the sub-layers, the thicknesses of the first sub-layer 211 and the second sub-layer 212 in each pair of doped stacks 21 may be

Specifically, the thickness of the first sub-layer 211 and the second sub-layer 212 may be set to be

Is between

Any value in between. In the pair of doped stacks 21, the thicknesses of the first sublayer 211 and the second sublayer 212 may be equal or different. The thickness of the different pairs of doped stacks 21 may or may not be equal.

Next, referring to fig. 4, the doped layer 20 is etched to form a capacitor hole 30 pattern, wherein the capacitor hole 30 pattern includes at least one capacitor hole 30, and the hole wall of each capacitor hole 30 is convex-concave alternately from bottom to top. During specific etching, a mask pattern can be formed on the doping layer 20, and the region covered by the mask pattern is a region where the capacitor hole 30 is not required to be formed subsequently; then, under the action of the mask pattern, the doped layer 20 is etched from above by using an etchant having an etching rate consistent with the variation trend of the doping concentration of the impurities in the doped layer 20 in a dry etching manner to form a pattern of the capacitor hole 30. The capacitor hole 30 pattern includes the bottom of the capacitor hole 30 contacting the corresponding landing plug 11 on the substrate 10. The parameters (position, specification, number, etc.) of each capacitor hole 30 included in the pattern of the capacitor holes 30 can be set with reference to the parameters of the landing plugs 11 on the substrate 10.

Since the etchant having the etching rate in accordance with the variation tendency of the impurity doping concentration is used, the etching rate of the etchant increases as the impurity doping concentration increases. When the doped layer 20 is etched from top to bottom by using the etching agent to form the pattern of the capacitor hole 30, the distance between two adjacent depth layers in the doped layer 20 is short, the etching time of the etching agent is relatively close, and the doping concentration of impurities between two adjacent depth layers is changed alternately, so that the capacitor hole 30 with the hole diameter changed alternately can be etched, and the hole wall of the capacitor hole 30 is changed in a convex-concave manner alternately. In addition, when the doping layer 20 is etched with the above etchant from top to bottom to form the pattern of the capacitor hole 30, since the doping concentration of the impurity at the bottom of the doping layer 20 is greater than the doping concentration of the impurity at the top of the doping layer 20, the etching rate of the etchant to the bottom of the doping layer 20 is greater than the etching rate of the etchant to the top of the doping layer 20. At this time, although the etchant has a longer etching time for the top of the doped layer 20 and a shorter etching time for the bottom of the doped layer 20. However, because the etchant has a lower etch rate for the top of the doped layer 20 and a higher etch rate for the bottom of the doped layer 20. Therefore, the amount of material etched away from the bottom of doped layer 20 is not reduced by the shortened etching time. Based on this, the capacitor hole 30 in the shape of "equal width from top to bottom" can be formed by etching the doped layer 20, that is, from top to bottom, the aperture of the protruding structure 31 on the sidewall of the capacitor hole 30 is more uniform, and the aperture of the recessed structure 32 on the sidewall of the capacitor hole 30 is more uniform.

For example, when each pair of doped stacks 21 includes the first sublayer 211 and the second sublayer 212 as shown in fig. 3, when the etching is performed by using the above etchant, since the doping concentration of the impurity in the first sublayer 211 is greater than the doping concentration of the impurity in the second sublayer 212, the etching rate on the first sublayer 211 is greater than the etching rate on the second sublayer 212. And because the distance between the first sublayer 211 and the second sublayer 212 is relatively short, the etching duration of the etchant is relatively short, so that the material etched by the etchant on the first sublayer 211 is relatively large, the aperture of the capacitor hole 30 etched at the position of the first sublayer 211 is relatively large, and the hole wall surrounded by the first sublayer 211 on the capacitor hole 30 is the concave structure 32 with relatively large aperture. The material etched by the etchant on the second sublayer 212 is less, and the aperture of the capacitor hole 30 etched at the position of the second sublayer 212 is smaller, so that the hole wall surrounded by the second sublayer 212 on the capacitor hole 30 is the protrusion structure 31 with smaller aperture.

May be provided in each pair of doped stacks 21, the doping concentration of the impurities in the first sub-layer 211 is at least 2.0 wt% greater than the doping concentration of the impurities in the second sub-layer 212. Specifically, in each pair of doped stacks 21, the doping concentration of the impurity in the first sub-layer 211 may be greater than the doping concentration of the impurity in the second sub-layer 212 by any value not less than 2.0 wt%, 2.1 wt%, 2.2 wt%, 2.3 wt%, 2.5 wt%, 2.8 wt%, 3.0 wt%, 3.2 wt%, 3.5 wt%, etc. The wall of the capacitor hole 30 has a relatively obvious convex and concave structure 32, so that the surface area of the sidewall of the capacitor lower electrode 41 is increased, the storage capacity of the capacitor is increased, and the data storage performance of the semiconductor device is improved.

In addition, in two adjacent pairs of doping stacks 21, the doping concentration of the impurity in the first sub-layer 211 of the lower pair of doping stacks 21 may be higher than the doping concentration of the impurity in the first sub-layer 211 of the upper pair of doping stacks 21. When the etching is performed by using the etchant, since the two first sublayers 211 in the two adjacent pairs of doping stacks 21 are separated by the second sublayer 212 in the lower pair of doping stacks 21, so that the distance between the two first sublayers 211 is relatively long, the time duration for etching the two first sublayers 211 by using the etchant also has a large difference, and the time duration for etching the first sublayer 211 in the upper pair of doping stacks 21 is longer than the time duration for etching the first sublayer 211 in the lower pair of doping stacks 21. By setting the doping concentration of the impurities in the first sublayers 211 of the lower pair of doping stacks 21 to be higher than the doping concentration of the impurities in the first sublayers 211 of the upper pair of doping stacks 21, the etching rate of the etchant for etching the first sublayers 211 of the upper pair of doping stacks 21 is lower than the etching rate of the first sublayers 211 of the lower pair of doping stacks 21, so that the apertures of the capacitor holes 30 surrounded by the two etching first sublayers 211 can be relatively consistent, and the apertures of the recess structures 32 on the sidewalls of the capacitor holes 30 can be relatively consistent. In any two adjacent pairs of doped stacks 21, the doping concentration of the impurities in the first sub-layer 211 of the lower pair of doped stacks 21 may be 0.1-1.0 wt% greater than the doping concentration of the impurities in the first sub-layer 211 of the upper pair of doped stacks 21. Specifically, the doping concentration of the impurity in the first sub-layer 211 of the lower pair of doping stacks 21 may be 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, 0.7 wt%, 0.8 wt%, 0.9 wt%, 1.0 wt%, or the like, which is greater than the doping concentration of the impurity in the first sub-layer 211 of the upper pair of doping stacks 21 by any value between 0.1 wt% and 1.0 wt%.

Likewise, in two adjacent pairs of doping stacks 21, it is also possible to set the doping concentration of the impurities in the second sub-layer 212 of the lower pair of doping stacks 21 to be higher than the doping concentration of the impurities in the second sub-layer 212 of the upper pair of doping stacks 21. When the etching is performed by using the etchant, since the two second sublayers 212 in the two adjacent pairs of doping stacks 21 are separated by the first sublayer 211 in the upper pair of doping stacks 21, so that the distance between the two second sublayers 212 is relatively long, the etchant also has a large difference in the time length for etching the two second sublayers 212, and the time length for etching the second sublayer 212 of the upper pair of doping stacks 21 is longer than the time length for etching the second sublayer 212 of the lower pair of doping stacks 21. By setting the doping concentration of the impurities in the second sublayers 212 of the lower pair of doping stacks 21 to be higher than the doping concentration of the impurities in the second sublayers 212 of the upper pair of doping stacks 21, the etching rate of the etchant for etching the second sublayers 212 of the upper pair of doping stacks 21 is lower than the etching rate of the second sublayers 212 of the lower pair of doping stacks 21, so that the apertures of the capacitor holes 30 surrounded by the two etching second sublayers 212 are more consistent, and the apertures of the protruding structures 31 on the sidewalls of the capacitor holes 30 are more consistent. In any two adjacent pairs of doped stacks 21, the doping concentration of the impurity in the second sub-layer 212 of the lower pair of doped stacks 21 may be 0.1-1.0 wt% higher than the doping concentration of the impurity in the second sub-layer 212 of the upper pair of doped stacks 21. Specifically, the doping concentration of the impurity in the second sub-layer 212 of the lower pair of doping stacks 21 may be greater than the doping concentration of the impurity in the second sub-layer 212 of the upper pair of doping stacks 21 by any value between 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, 0.7 wt%, 0.8 wt%, 0.9 wt%, 1.0 wt%, and the like.

For example, the doping concentration of the impurity in the N1_1 layer may be set to 6.0 wt%, and the doping concentration of the impurity in the N1_2 layer may be set to 4.0 wt%; the doping concentration of the impurity in the N2_1 layer was 5.9 wt%, and the doping concentration of the impurity in the N2_2 layer was 3.9 wt%; the doping concentration of the impurity in the N3_1 layer was 5.8 wt%, and the doping concentration of the impurity in the N3_2 layer was 3.8 wt%; the doping concentration of the impurity in the N4_1 layer was 5.7 wt%, and the doping concentration of the impurity in the N4_2 layer was 3.7 wt%; the doping concentration of the impurity in the N5_1 layer was 5.6 wt%, and the doping concentration of the impurity in the N5_2 layer was 3.6 wt%; the doping concentration of the impurity in the N6_1 layer is 5.5 wt%, and the doping concentration of the impurity in the N6_2 layer is 3.5 wt%; the doping concentration of the impurity in the N7_1 layer is 5.4 wt%, and the doping concentration of the impurity in the N7_2 layer is 3.4 wt%; the doping concentration of the impurity in the N8_1 layer was 5.3 wt%, and the doping concentration of the impurity in the N8_2 layer was 3.3 wt%.

Next, referring to FIGS. 5-7, a capacitor is formed within each capacitor hole 30. Specifically, referring to fig. 5, first, the lower electrode 41 is formed in the capacitor hole 30, and the electrode material covering the pattern of the capacitor hole 30 and the doped layer 20 may be formed by direct deposition or the like. Thereafter, the electrode material on the doped layer 20 may be removed, leaving only the electrode material within the capacitor holes 30. The electrode material located in the capacitor hole 30 forms the lower electrode 41. As for the material contained in the lower electrode 41, a doped polysilicon, a metal nitride or other conductive material may be used. The thickness of the lower electrode 41 may be set according to practical circumstances and is not particularly limited herein. Since the capacitor hole 30 has the hole wall alternately changing in the convex-concave shape, the sidewall of the lower electrode 41 of the capacitor formed in the capacitor hole 30 can also alternately change in the convex-concave shape, so that the sidewall of the lower electrode 41 has a larger surface area, the storage capacity of the capacitor can be increased, and the data storage performance of the semiconductor device can be improved.

As shown in fig. 5, the bottom of the lower electrode 41 is in contact with the landing plug 11. Since the aperture of the protruding structure 31 on the sidewall of the capacitor hole 30 is uniform, and the aperture of the recessed structure 32 on the sidewall of the capacitor hole 30 is uniform, the bottom surface area of the lower electrode 41 is large, and thus the contact area between the lower electrode 41 and the landing plug 11 in contact with the lower electrode 41 can be increased. Since the contact area is inversely proportional to the contact resistance, the contact resistance can be reduced, thereby improving the operating performance of the semiconductor device.

Referring to fig. 6, a forming dielectric layer 42 covering the lower electrode 41 is formed on the lower electrode 41, and chemical vapor deposition or the like may be specifically adopted. The material contained in the dielectric layer 42 may be an insulating material such as silicon oxide or a high K (dielectric constant) material. Referring to fig. 7, an upper electrode 43 is formed on the dielectric layer 42 to cover the dielectric layer 42. The material contained in the upper electrode 43 may be a conductive material such as doped polysilicon, metal, or metal nitride. Compared with the technical scheme that the doping layer 20 with the same doping concentration is adopted in the prior art, the formed capacitor hole 30 is in a shape of being wide at the top and narrow at the bottom, and the manufacturing method provided by the invention is characterized in that a capacitor is formed in the capacitor hole 30 with the side walls in a convex-concave shape, the convex structures 31 are equal in width at the top and the bottom, and the concave structures 32 are equal in width at the top and the bottom, so that the lower electrode 41 of the capacitor has the advantages of large side wall surface area and large bottom surface area, the storage capacity of the capacitor can be increased, and the data storage performance of a semiconductor device is improved. And the bottom surface area of the lower electrode 41 is large, so that the contact area between the lower electrode 41 and a structure in contact with the lower electrode 41 is increased, the contact resistance is reduced, and the working performance of the semiconductor device is improved.

In addition, referring to fig. 8, after the doped layer 20 covering the substrate 10 is formed, at least one support layer 50 covering the doped layer 20 may be further formed over the doped layer 20 before forming a capacitor in each of the capacitor holes 30. In other embodiments of the present invention, other support layers 50 may also be formed inside the doped layer 20. The material and the composition of the supporting layer 50 are conventional materials and compositions capable of supporting the sidewall of a capacitor with a large aspect ratio in the semiconductor manufacturing process in the prior art. The number of layers of the support layer 50 may be one layer, two layers, three layers, etc.

Referring to fig. 9, the doping layer 20 and the support layer 50 are etched to form the capacitor hole 30 pattern.

Referring to fig. 10, a lower electrode 41 is formed in each of the capacitor holes 30 in such a manner that the lower electrode 41 is formed on the inner wall of the capacitor hole 30, specifically, the inner wall of the capacitor hole 30 partially surrounded by the doped layer 20 and the inner wall of the capacitor hole 30 partially surrounded by the support layer 50.

Referring to fig. 11, after forming the lower electrode 41 in each of the capacitor holes 30, the doped layer 20 between any two adjacent lower electrodes 41 may be removed before forming the dielectric layer 42 on the lower electrode 41. The method for removing the doped layer 20 between any two adjacent lower electrodes 41 may be to open an opening on the support layer 50 between the adjacent lower electrodes 41, and then remove the doped layer 20 located below the support layer 50. The portion of the support layer 50 connected to the outer wall of the lower electrode 41 may be left unremoved, that is, the portion of the support layer 50 is left as the support structure 51 to support the lower electrode 41, so as to prevent the lower electrode 41 and the dielectric layer 42 and the upper electrode 43 formed subsequently from collapsing. The resulting support structure 51 forms at least one ring-like structure around the outer wall of the lower electrode 41.

Thereafter, referring to fig. 12, a dielectric layer 42 covering the lower electrode 41, and an upper electrode 43 covering the dielectric layer 42 are formed on the lower electrode 41 to complete the manufacture of the capacitor. Referring to fig. 12, the dielectric layer 42 may be formed on the lower electrode 41 by forming the dielectric layer 42 on both the inner wall and the outer wall of the lower electrode 41 and forming the dielectric layer 42 on both the inner wall, the outer wall and the upper surface of the supporting structure 51, i.e., the dielectric layer 42 covers both the inner wall and the outer wall of the lower electrode 41 and the surface of the supporting structure 51. The upper electrode 43 may be formed on the dielectric layer 42 by forming the upper electrode 43 on the inner wall, the outer wall, and the upper end surface connecting the inner wall and the outer wall of the dielectric layer 42, thereby completing the manufacture of the capacitor. The support layer 50 can support the sidewall of the capacitor, so that the subsequent hole pattern can be ensured to have good vertical profile. And prevents collapse of the capacitance hole 30 having a large aspect ratio while preventing collapse of the capacitor formed in the capacitance hole 30.

It should be noted that the arrangement of the support layer 50 and the support structure 51 is not limited to the arrangement above the doped layer 20, and other arrangements may be adopted.

For example, it is also possible to arrange at least one support layer 50 inside the doped layer 20, in which case the support structure 51 is not located above the capacitor, but rather in a position close to the middle of the capacitor. For example, referring to fig. 13, at least one support layer 50 may be disposed between the fourth pair of doped stacks 21 and the fifth pair of doped stacks 21, and the number of layers of the support layer 50 may be one, two, three, and so on. Then, referring to fig. 14, the doped layer 20 and the support layer 50 are etched to form a capacitor hole pattern, and each capacitor hole 30 penetrates through the doped layer 20 and the support layer 50 and then communicates with the lower landing plug 11. As shown in fig. 15, a lower electrode 41 is then deposited on the sidewalls and bottom wall of the capacitor hole 30. Thereafter, referring to fig. 16, the doped layer 20 and a portion of the supporting layer 50 between two adjacent lower electrodes are removed, and a portion of the supporting layer 50 remains to form a supporting structure 51 supporting the lower electrode 41. Thereafter, referring to fig. 17, a dielectric layer covering the lower electrode and the support structure is formed on the inner and outer sidewalls and the bottom wall of the lower electrode and the support structure. And forming upper electrodes covering the dielectric layer on the dielectric layers on the inner side and the outer side of the lower electrode to complete the manufacture of the capacitor.

In addition, at least one support layer 50 may be formed above the doped layer 20, and at least one support layer 50 may be formed inside the doped layer 20, in which case, not only the support structure 51 may be formed above the capacitor, but also the support structure 51 may be formed at a position intermediate to the capacitor. The specific manner of forming the capacitor is substantially the same as the above-mentioned manner, and is not described herein again.

By forming the doping layers 20 on the substrate 10 and the doping concentration of the impurities in the doping layers 20 is alternately changed, an etchant having an etching rate in accordance with the changing tendency of the doping concentration of the impurities may be used when the doping layers 20 are etched to form the pattern of the capacitor holes 30. I.e., the etch rate of the etchant increases with the doping concentration of the impurity. When the doped layer 20 is etched from top to bottom by using the etching agent to form the pattern of the capacitor hole 30, the distance between two adjacent depth layers in the doped layer 20 is short, the etching time of the etching agent is relatively close, and the doping concentration of impurities between two adjacent depth layers is changed alternately, so that the capacitor hole 30 with the hole diameter changed alternately can be etched, and the hole wall of the capacitor hole 30 is changed in a convex-concave manner alternately. Since the capacitor hole 30 has the hole wall alternately changing in the convex-concave shape, the side wall of the lower electrode 41 of the capacitor formed in the capacitor hole 30 can also alternately change in the convex-concave shape, and the side wall of the lower electrode 41 can have a larger surface area. In addition, when the doping layer 20 is etched with the above etchant from top to bottom to form the pattern of the capacitor hole 30, since the doping concentration of the impurity at the bottom of the doping layer 20 is greater than the doping concentration of the impurity at the top of the doping layer 20, the etching rate of the etchant to the bottom of the doping layer 20 is greater than the etching rate of the etchant to the top of the doping layer 20. At this time, although the etchant has a longer etching time for the top of the doped layer 20 and a shorter etching time for the bottom of the doped layer 20. However, because the etchant has a lower etch rate for the top of the doped layer 20 and a higher etch rate for the bottom of the doped layer 20. Therefore, the amount of material etched away from the bottom of doped layer 20 is not reduced by the shortened etching time. Based on this, the capacitor hole 30 in the shape of "equal width from top to bottom" can be formed by etching the doped layer 20, that is, from top to bottom, the aperture of the protruding structure 31 on the sidewall of the capacitor hole 30 is more uniform, and the aperture of the recessed structure 32 on the sidewall of the capacitor hole 30 is more uniform. Compared with the technical scheme that the doping layer 20 with the same doping concentration is adopted in the prior art, the formed capacitor hole 30 is in a shape of being wide at the top and narrow at the bottom, and the manufacturing method provided by the invention is characterized in that a capacitor is formed in the capacitor hole 30 with the side walls in a convex-concave shape, the convex structures 31 are equal in width at the top and the bottom, and the concave structures 32 are equal in width at the top and the bottom, so that the lower electrode 41 of the capacitor has the advantages of large side wall surface area and large bottom surface area, the storage capacity of the capacitor can be increased, and the data storage performance of a semiconductor device is improved. The bottom surface area of the lower electrode 41 is large, and the contact area between the lower electrode 41 and the structure in contact with the lower electrode 41 can be increased. Since the contact area is inversely proportional to the contact resistance, the contact resistance can be reduced, thereby improving the operating performance of the semiconductor device.

In addition, referring to fig. 7, an embodiment of the present invention also provides a semiconductor device including: a substrate 10, a landing plug 11 is formed on the substrate 10. A doped layer 20 is formed on the substrate 10, and a capacitor hole 30 is formed in the doped layer 20. A capacitor is formed in the capacitor hole 30, and the capacitor hole 30 includes a lower electrode 41 contacting the landing plug 11, a dielectric layer 42 formed on the lower electrode 41, and an upper electrode 43 formed on the dielectric layer 42. The doping concentration of the impurities in the doping layers 20 changes from bottom to top alternately, and the doping concentration of the impurities at the bottom of the doping layers 20 is greater than that at the top of the doping layers 20. The wall of the capacitor hole 30 varies in a convex-concave manner from bottom to top, and the sidewall of the lower electrode 41 varies in a convex-concave manner from bottom to top. Compared with the prior art, the beneficial effects of the semiconductor device provided by the embodiment of the invention are the same as the beneficial effects of the manufacturing method of the semiconductor device provided by the technical scheme, and the details are not repeated here.

Further, referring to fig. 12 and 17, an embodiment of the present invention also provides another semiconductor device including: a substrate 10, a landing plug 11 is formed on the substrate 10. A capacitor including a cylindrical lower electrode 41 in contact with the landing plug 11, a dielectric layer 42 covering inner and outer sidewalls of the lower electrode 41, and an upper electrode 43 covering the dielectric layer 42 inside and outside the lower electrode 41 is disposed above the substrate 10. The sidewalls of the lower electrode 41, the dielectric layer 42 and the upper electrode 43 are all convex-concave and alternate, so as to increase the areas of the lower electrode 41 and the upper electrode 43 and improve the performance of the capacitor. When the capacitor is installed, the bottom wall of the cylindrical lower electrode 41 is in contact with the landing plug 11, and a dielectric layer 42 and an upper electrode 43 are formed on the bottom wall and the inner and outer side walls of the lower electrode 41, so as to further improve the performance of the capacitor. Compared with the prior art, the semiconductor device provided by the invention has the beneficial effects that in addition to the beneficial effects of the manufacturing method of the semiconductor device provided by the technical scheme, the dielectric layer 42 and the upper electrode 43 are arranged on the inner side and the outer side of the cylindrical lower electrode 41, so that the utilization rate of the capacitor is increased.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a doped layer covering the substrate above the substrate; the doping concentration of impurities in the doping layer is changed from bottom to top alternately, and the doping concentration of the impurities at the bottom of the doping layer is greater than that of the impurities at the top of the doping layer;

a capacitor is formed within each capacitive aperture.

2. The method of manufacturing according to claim 1, wherein the doped layer comprises at least two pairs of doped stacks stacked over the substrate, each pair of doped stacks comprising a first sub-layer and a second sub-layer formed on the first sub-layer; between any two adjacent pairs of doped stacks, a first sublayer of the upper pair of doped stacks is stacked on a second sublayer of the lower pair of doped stacks;

in each pair of doped stacks, the doping concentration of the impurities in the first sublayer is higher than the doping concentration of the impurities in the second sublayer;

in any two adjacent pairs of doped lamination layers, the doping concentration of impurities in a second sublayer in the lower pair of doped lamination layers is lower than that of impurities in a first sublayer in the upper pair of doped lamination layers;

and the hole wall surrounded by the first sub-layer on each capacitor hole is a concave structure with a larger hole diameter, and the hole wall surrounded by the second sub-layer on each capacitor hole is a convex structure with a smaller hole diameter.

3. The method of manufacturing of claim 2, wherein in each pair of doped stacks, the doping concentration of the impurity in the first sublayer is at least 2.0 wt% greater than the doping concentration of the impurity in the second sublayer.

4. The manufacturing method according to claim 2, wherein, in any two adjacent pairs of doped stacks, the doping concentration of the impurity in the first sublayer of the lower pair of doped stacks is higher than the doping concentration of the impurity in the first sublayer of the upper pair of doped stacks; the doping concentration of the impurities in the second sublayers of the lower pair of doping stacks is higher than that of the impurities in the second sublayers of the upper pair of doping stacks.

5. The manufacturing method according to claim 4, wherein in any two adjacent pairs of doped stacks, the doping concentration of the impurity in the first sublayer of the lower pair of doped stacks is 0.1 to 1.0 wt% greater than the doping concentration of the impurity in the first sublayer of the upper pair of doped stacks; the doping concentration of impurities in the second sublayers of the lower pair of doping laminated layers is 0.1-1.0 wt% higher than that of impurities in the second sublayers of the upper pair of doping laminated layers.

6. The method of claim 2, wherein the first and second sublayers in each pair of doped stacks have a thickness of

7. The method according to claim 1, wherein at least one support layer is formed inside the doped layer and/or above the doped layer;

the etching the doped layer to form a capacitor hole pattern comprises:

and etching the doped layer and the at least one supporting layer to form the capacitor hole pattern.

8. The method of claim 7, wherein landing plugs are formed on the substrate;

the forming a capacitor within each capacitive aperture includes:

forming a lower electrode at the bottom and the wall of each capacitor hole, wherein the lower electrode is in contact with the landing plug;

forming a dielectric layer covering the lower electrode on the lower electrode;

and forming an upper electrode covering the dielectric layer on the dielectric layer.

9. The method of manufacturing of claim 8, wherein after forming the lower electrode in each of the capacitor holes and before forming the dielectric layer on the lower electrode, the method further comprises:

removing the doped layer between any two adjacent lower electrodes;

and removing part of the supporting layer between any two adjacent lower electrodes, and reserving part of the supporting layer to form a supporting structure for supporting the lower electrodes.

10. The method of manufacturing of claim 9, wherein forming a dielectric layer on the lower electrode overlying the lower electrode comprises: forming a dielectric layer covering the lower electrode and the support structure on the inner side wall and the outer side wall of the lower electrode and the support structure;

the forming of the upper electrode on the dielectric layer to cover the dielectric layer includes: and forming upper electrodes covering the dielectric layer on the inner side and the outer side of the lower electrode.

11. A semiconductor device, comprising:

a substrate, wherein a landing plug is formed on the substrate;

the doped layer is positioned on the substrate, and a capacitance hole is formed in the doped layer;

a capacitor positioned within the capacitive via, the capacitor including a lower electrode in contact with the landing plug, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer;

the doping concentration of impurities in the doping layer is changed from bottom to top alternately, and the doping concentration of the impurities at the bottom of the doping layer is larger than that of the impurities at the top of the doping layer;

the hole wall of the capacitor hole is convex-concave alternating from bottom to top, and the side wall of the lower electrode is convex-concave alternating from bottom to top.

12. A semiconductor device, comprising:

a substrate, wherein a landing plug is formed on the substrate;

a capacitor disposed on the substrate, the capacitor including a cylindrical lower electrode in contact with the landing plug, dielectric layers covering inner and outer sidewalls of the lower electrode, and an upper electrode covering the dielectric layers on inner and outer sides of the lower electrode;

the side walls of the lower electrode, the dielectric layer and the upper electrode are convex-concave-shaped and alternate.