KR20040001960A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of improving the stability of cylindrical capacitor. CONSTITUTION: The first capacitor insulating layer is formed on a semiconductor substrate(20). The second capacitor insulating layer having different etching selectivity is formed on the first capacitor insulating layer. A capacitor hole is formed by selectively etching the second and first capacitor insulating layer. By removing the second capacitor insulating layer using a desired etching solution, the lower width of the capacitor hole is wide. Then, a lower electrode is formed in the capacitor hole. After removing the second and first capacitor insulating layer, a dielectric film and an upper electrode are sequentially formed on the lower electrode.

Description

Method for fabricating capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = ε · As / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, and multilayer fin structures, are all proposed to increase the effective surface area of electrodes in a limited layout area and are widely used in concave or cylindrical shapes. It is used.

On the other hand, silicon is mainly used as a lower electrode of the capacitor because a stack of silicon nitride and oxide or tantalum oxide is applied as a capacitor dielectric material.

Since maintaining a constant capacitance in a limited area of an increasingly integrated semiconductor device is technically difficult in the manufacturing method of a three-dimensional capacitor, the lower electrode is formed in a concave shape, and then a silicon seed forming process is performed. The surface area has been increased.

However, as more and more fine design rules are applied, there is a disadvantage in that space for applying an additional silicon seed forming process is not secured. To overcome this, cylindrical capacitors are now mainly applied instead of concave. Cylindrical capacitors have the effect of increasing the area by applying an additional seed process by removing the oxide film that forms the die and using the area of the capacitor to the outer surface of the lower electrode.

1A to 1D are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to the prior art.

First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. The contact hole is filled with a conductive material to form the contact plugr 13. Subsequently, the capacitor insulating film 14 is formed as large as the capacitor is formed.

Subsequently, as shown in FIG. 1B, the capacitor insulating film 15 in the region where the capacitor is to be formed is selectively removed to form the capacitor hole 15. The capacitor insulating film 15 serves as a form for forming the lower electrode.

Subsequently, as shown in FIG. 1C, the lower electrode 16 is formed on the sidewall and the bottom of the capacitor hole 15 using silicon.

Subsequently, as shown in FIG. 1D, the capacitor insulating film 14 is removed using a wet etching process. Thus, by forming the lower electrode in a cylindrical shape, there is an effect of using the area of the capacitor to the outer surface of the lower electrode as described above.

However, as capacitors are manufactured in increasingly fine patterns, there is a structural weakness in which the thin lower electrode silicon must stand alone in a cylindrical shape. Therefore, when the capacitor insulating film 14 is removed by an aqueous solution, the lower electrodes formed of silicon stick together. This is shown in "A" of Figure 1d. When the lower electrodes are attached to each other, data is shared with each other, thereby causing dual bit-fail, resulting in deterioration of operational reliability of the semiconductor memory device.

In order to prevent such dual bit failing, precise control of the exposure process and proper mechanical stability of the silicon used as the lower electrode are required, but in the fine design rule, the height of the lower electrode must be increased to secure an area, and thus the mechanical stability is further deteriorated. It must be.

It is an object of the present invention to provide a method for producing a cylindrical capacitor which is more stable and more advantageous for integration.

1A to 1D are cross-sectional views showing a method of manufacturing a cylindrical capacitor according to the prior art.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor capacitor according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

20: substrate

21: active area

22: interlayer insulating film

23: Contact Plug

24: etching stop film

25: first capacitor insulating film

26: second capacitor insulating film

29,30: conductive film for first and second lower electrodes

31,32: lower electrode

The present invention for achieving the above object comprises the steps of forming a first capacitor insulating film on the substrate; Forming a second capacitor insulating film on the first capacitor insulating film, the second capacitor insulating film having a different etching selectivity from the first capacitor insulating film in a predetermined solution; Selectively removing the first and second capacitor insulating films in the region where the capacitor is to be formed to form a capacitor hole; Removing the second capacitor insulating layer with the predetermined solution to widen the lower area of the capacitor hole; Forming a lower electrode in the capacitor hole; Removing the first and second capacitor insulating films; And forming a dielectric thin film and an upper electrode on the lower electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2F are views illustrating a method of manufacturing a cylindrical capacitor according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. A contact plug 23 is formed by filling a contact hole with a conductive snow material. Subsequently, an etch stop film 24 is formed in the range of 300 to 1000 Å by chemical vapor deposition using SiON, Si ₃ N _4, or the like as an insulating nitride film, and the first and second capacitor insulating films are formed to have a height on which the capacitor is formed. 25,26). In a subsequent process, the first capacitor insulating films 25 and 26 are used as formwork for the capacitor lower electrode.

The first capacitor insulating layer 25 is formed of a material having a higher etching rate in a predetermined solution than the second capacitor insulating layer 26. Preferably, the first capacitor insulating layer 25 is made of USG (Undoped-Silicate Glass), PSG. (Phospho-Silicate Glass) and BPSG (Boro-Phospho-Silicate Glass), etc., if the oxide film is applied by chemical vapor deposition method, the second capacitor insulating film 26 is applied TEOS (Tetraethylorthosilicate) and plasma enhanced chemical vapor deposition It is formed by the (Plasma Enhanced CVD) method. Here, the total thickness of the first capacitor insulating film 25 and the second capacitor insulating film 26 is formed in the range of 5000 ~ 25000Å, the ratio of the thickness is 1: 4 ~ 1: 1.

Subsequently, as illustrated in FIG. 2B, the capacitor holes 27 are formed by removing the first and second capacitor insulating layers 25 and 26 and the etch stop layer so that the contact plugs 23 are exposed.

Subsequently, as shown in FIG. 2C, the second capacitor insulating layer 25 is etched using a wet etching process to widen the lower end of the capacitor hole 27. In this case, an aqueous solution containing NH ₄ OH and H ₂ O ₂ in a predetermined ratio is used as the solution, and the process temperature is in the range of 90 ° C. from normal temperature, and the time proceeds in the range of 1 to 25 minutes.

Subsequently, as shown in FIG. 2D, silicon doped with P as the first lower electrode conductive film 29 is formed on the sidewall and the bottom of the capacitor hole 27 by chemical vapor deposition, followed by pure silicon having excellent step coverage. The film is formed by chemical vapor deposition into the second lower electrode conductive film 30. At this time, the P doping is plasma doped using a PH ₃ or doped in a high temperature furnace, and is carried out separately from the heat treatment process.

In this case, when silicon is formed on the inner surface of the capacitor hole 27 by chemical vapor deposition, when the P is formed while doping, the step coverage is reduced, so the process is divided into the first and lower electrodes 29 and 30. . In this case, the first and second lower electrode conductive films 29 and 30 are applied to each of 250 to 1000 mm, and the thickness ratio is formed such that each conductive film is 5: 1 to 1: 1.

Subsequently, as shown in FIG. 2E, the first and second capacitor insulating layers 29 and 30 formed on the second capacitor insulating layer 26 are removed by chemical mechanical polishing (CMP) or dry etching to lower the electrode 31. , 32).

Subsequently, as shown in FIG. 2F, the first and second capacitor insulating layers 25 and 26 are removed using a wet etching process. The wet etching process performed here is carried out for 5 to 60 minutes in an aqueous solution containing NH ₄ F and HF.

Subsequently, the dielectric thin film and the upper electrode of the capacitor are formed in a subsequent process to complete the capacitor.

Accordingly, as described above, when the lower electrode of the silicon semiconductor is formed, the silicon lower electrode having higher structural stability can be formed in the microdesign rule than using a conventional single layer of crystalline silicon.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention can be expected to improve the productivity by increasing the stability of the cylinder-type capacitor in the semiconductor manufacturing process fine design rule.

Claims (9)

Forming a first capacitor insulating film on the substrate; Forming a second capacitor insulating film on the first capacitor insulating film, the second capacitor insulating film having a different etching selectivity from the first capacitor insulating film in a predetermined solution; Selectively removing the first and second capacitor insulating films in the region where the capacitor is to be formed to form a capacitor hole; Removing the second capacitor insulating layer with the predetermined solution to widen the lower area of the capacitor hole; Forming a lower electrode in the capacitor hole; Removing the first and second capacitor insulating films; And Forming a dielectric thin film and an upper electrode on the lower electrode Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, Forming a lower electrode in the capacitor hole Forming a silicon film doped with P in the capacitor hole; And And forming a pure silicon film on said P-doped silicon film. The method of claim 1, And the first capacitor insulating film is formed by chemical vapor deposition using one selected from USG, PSG, and BPSG. The method of claim 3, wherein The second capacitor insulating film is a capacitor manufacturing method of a semiconductor device, characterized in that the TEOS film is applied and formed by a plasma enhanced chemical vapor deposition method. The method of claim 4, wherein The total thickness of the first capacitor insulating film and the second capacitor insulating film 26 is formed in the range of 5000 ~ 25000Å, the ratio of the thickness is 1: 4 ~ 1: 1 manufacturing method of the capacitor of the semiconductor device. . The method of claim 4, wherein In the step of removing the second capacitor insulating film with the predetermined solution to widen the lower area of the capacitor hole, an aqueous solution containing NH ₄ OH and H ₂ O ₂ in a predetermined ratio is used as the solution to be used, and the process temperature. The capacitor manufacturing method of the semiconductor device characterized by the above-mentioned progressing in the range of 1 to 25 minutes in normal temperature from 90 degreeC. The method of claim 2, And the thickness of the lower electrode is in the range of 250 kV to 1000 kV and the thickness ratio of the P-doped silicon film and the pure silicon film is in the range of 5: 1 to 1: 1. The method of claim 7, wherein The doping of the P is a plasma manufacturing method using a PH ₃ or a capacitor manufacturing method of a semiconductor device, characterized in that the doping in a high temperature furnace. The method of claim 1, Removing the first and second capacitor insulating film is A method for manufacturing a capacitor of a semiconductor device, characterized in that for 5 to 60 minutes in a solution containing NH ₄ F and HF using a wet etching process.