TW201639126A - Semiconductor structure and manufacturing method of the same - Google Patents

Semiconductor structure and manufacturing method of the same Download PDF

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Publication number
TW201639126A
TW201639126A TW104112476A TW104112476A TW201639126A TW 201639126 A TW201639126 A TW 201639126A TW 104112476 A TW104112476 A TW 104112476A TW 104112476 A TW104112476 A TW 104112476A TW 201639126 A TW201639126 A TW 201639126A
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Taiwan
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vertical memory
layer
memory structure
substrate
insulating
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TW104112476A
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Chinese (zh)
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TWI541984B (en
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江昱維
葉騰豪
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旺宏電子股份有限公司
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Abstract

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a first vertical memory structure, a second vertical memory structure, and an isolation trench. The conductive layers and the insulating layers are interlaced and stacked on the substrate. The first vertical memory structure and the second memory structure penetrate the conductive layers and the insulating layers are formed on the substrate. The first vertical memory structure has a first horizontal C shaped cross-section, and the second vertical memory structure has a second horizontal C shaped cross-section. The isolation trench is formed between the first vertical memory structure and the second vertical memory structure.

Description

半導體結構及其製造方法Semiconductor structure and method of manufacturing same 【0001】【0001】

本揭露內容是有關於一種半導體結構及其製造方法,且特別是有關於一種具有高記憶密度之半導體結構及其製造方法。The present disclosure relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a high memory density and a method of fabricating the same.

【0002】【0002】

近年來半導體元件的結構不斷地改變,且元件的記憶體儲存容量也不斷增加。記憶裝置係使用於許多產品之中,例如MP3播放器、數位相機、電腦檔案等等之儲存元件中。隨著應用的增加,對於記憶裝置的需求也趨向較小的尺寸、較大的記憶容量。因應這種需求,係需要製造高元件密度及具有小尺寸的記憶裝置。In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density and a small size.

【0003】[0003]

因此,設計者們無不致力於開發一種三維記憶裝置,不但具有許多堆疊平面而達到更高的記憶儲存容量,具有更微小的尺寸,同時具備良好之穩定性。Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has good stability.

【0004】[0004]

本揭露內容係有關於一種半導體結構及其製造方法。實施例中,半導體結構中,由於一對垂直記憶結構皆具有水平C形剖面且以絕緣溝槽相隔,因此增大單位面積內的記憶密度,進而達到更高的記憶儲存容量。The disclosure relates to a semiconductor structure and a method of fabricating the same. In the embodiment, in the semiconductor structure, since a pair of vertical memory structures have horizontal C-shaped cross sections and are separated by insulating trenches, the memory density per unit area is increased, thereby achieving higher memory storage capacity.

【0005】[0005]

根據本揭露內容之一實施例,係提出一種半導體結構。半導體結構包括一基板、複數個導電層和複數個絕緣層、一第一垂直記憶結構和一第二垂直記憶結構以及一絕緣溝槽(isolation trench)。導電層和絕緣層形成於基板上,其中導電層與絕緣層係交錯設置(interlaced)堆疊於基板上。第一垂直記憶結構和第二垂直記憶結構穿過導電層與絕緣層並形成於基板上,其中第一垂直記憶結構具有一第一水平C形剖面,第二垂直記憶結構具有一第二水平C形剖面。絕緣溝槽形成於基板上並位於第一垂直記憶結構和第二垂直結構之間。In accordance with an embodiment of the present disclosure, a semiconductor structure is proposed. The semiconductor structure includes a substrate, a plurality of conductive layers and a plurality of insulating layers, a first vertical memory structure and a second vertical memory structure, and an isolation trench. The conductive layer and the insulating layer are formed on the substrate, wherein the conductive layer and the insulating layer are interlaced and stacked on the substrate. The first vertical memory structure and the second vertical memory structure are formed on the substrate through the conductive layer and the insulating layer, wherein the first vertical memory structure has a first horizontal C-shaped cross section and the second vertical memory structure has a second horizontal C Profile. An insulating trench is formed on the substrate and between the first vertical memory structure and the second vertical structure.

【0006】[0006]

根據本揭露內容之另一實施例,係提出一種半導體結構的製造方法。半導體結構的製造方法包括以下步驟。提供一基板;形成複數個導電層和複數個絕緣層於基板上,其中此些導電層與此些絕緣層係交錯設置堆疊於基板上;形成一第一垂直記憶結構和一第二垂直記憶結構於基板上,其中第一垂直記憶結構和第二垂直記憶結構穿過此些導電層與此些絕緣層,第一垂直記憶結構具有一第一水平C形剖面,第二垂直記憶結構具有一第二水平C形剖面;以及形成一絕緣溝槽於基板上並位於第一垂直記憶結構和第二垂直結構之間。In accordance with another embodiment of the present disclosure, a method of fabricating a semiconductor structure is presented. The method of fabricating a semiconductor structure includes the following steps. Providing a substrate; forming a plurality of conductive layers and a plurality of insulating layers on the substrate, wherein the conductive layers and the insulating layers are alternately stacked on the substrate; forming a first vertical memory structure and a second vertical memory structure On the substrate, wherein the first vertical memory structure and the second vertical memory structure pass through the conductive layers and the insulating layers, the first vertical memory structure has a first horizontal C-shaped cross section, and the second vertical memory structure has a first a two-level C-shaped profile; and forming an insulating trench on the substrate and between the first vertical memory structure and the second vertical structure.

【0007】【0007】

為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

【0047】[0047]

100‧‧‧半導體結構
110‧‧‧基板
120‧‧‧導電層
130‧‧‧絕緣層
130b‧‧‧最底層
140‧‧‧第一垂直記憶結構
150‧‧‧第二垂直記憶結構
160‧‧‧絕緣溝槽
170‧‧‧磊晶結構
180‧‧‧記憶結構層
181‧‧‧阻隔層
183‧‧‧記憶儲存層
185‧‧‧穿隧層
190‧‧‧通道層
191、193‧‧‧絕緣層
240‧‧‧第一接觸結構
250‧‧‧第二接觸結構
310‧‧‧凹槽
480‧‧‧記憶結構材料層
481‧‧‧阻隔材料層
483‧‧‧記憶儲存材料層
485‧‧‧穿隧材料層
490‧‧‧通道材料層
510‧‧‧氧化物材料層
51a‧‧‧空氣間隙
810‧‧‧絕緣材料
991‧‧‧絕緣材料層
BL1‧‧‧第一位元線
BL2‧‧‧第二位元線
D1、D2‧‧‧距離
R1‧‧‧短軸方向
T‧‧‧溝槽
W1、W2、X1‧‧‧寬度
W4‧‧‧長軸
Y1‧‧‧長度
1B-1B’、1C-1C’、1D-1D’、1E-1E’、3B-3B’、4B-4B’、5B-5B’、5C-5C’、6B-6B’、6C-6C’、6D-6D’、7B-7B’、7C-7C’、7D-7D’、8B-8B’、8C-8C’、8D-8D’、9B-9B’、9C-9C’、9D-9D’、10B-10B’、11B-11B’‧‧‧剖面線
100‧‧‧Semiconductor structure
110‧‧‧Substrate
120‧‧‧ Conductive layer
130‧‧‧Insulation
130b‧‧‧ bottom level
140‧‧‧First vertical memory structure
150‧‧‧Second vertical memory structure
160‧‧‧Insulation trench
170‧‧‧ epitaxial structure
180‧‧‧ memory structure layer
181‧‧‧Barrier
183‧‧‧ memory storage layer
185‧‧‧ Tunneling
190‧‧‧channel layer
191, 193‧‧‧Insulation
240‧‧‧First contact structure
250‧‧‧Second contact structure
310‧‧‧ Groove
480‧‧‧Memory structural material layer
481‧‧‧layer of barrier material
483‧‧‧Memory storage material layer
485‧‧‧Through tunneling material layer
490‧‧‧channel material layer
510‧‧‧Oxide material layer
51a‧‧‧Air gap
810‧‧‧Insulation
991‧‧‧Insulation layer
BL1‧‧‧ first bit line
BL2‧‧‧ second bit line
D1, D2‧‧‧ distance
R1‧‧‧ short axis direction
T‧‧‧ trench
W1, W2, X1‧‧‧ width
W4‧‧‧ long axis
Y1‧‧‧ length
1B-1B', 1C-1C', 1D-1D', 1E-1E', 3B-3B', 4B-4B', 5B-5B', 5C-5C', 6B-6B', 6C-6C', 6D-6D', 7B-7B', 7C-7C', 7D-7D', 8B-8B', 8C-8C', 8D-8D', 9B-9B', 9C-9C', 9D-9D', 10B-10B', 11B-11B'‧‧‧ hatching

【0008】[0008]


第1A圖繪示本揭露內容之一實施例之半導體結構之上視圖。
第1B圖繪示沿第1A圖之剖面線1B-1B’之剖面示意圖。
第1C圖繪示沿第1A圖之剖面線1C-1C’之剖面示意圖。
第1D圖繪示沿第1A圖之剖面線1D-1D’之剖面示意圖。
第1E圖繪示沿第1A圖之剖面線1E-1E’之剖面示意圖。
第2圖繪示本揭露內容之一實施例之半導體結構之多個第一垂直記憶結構和多個第二垂直記憶結構之配置上視圖。
第3A圖~第11B圖繪示依照本發明之一實施例之一種半導體結構之製造方法示意圖。

FIG. 1A is a top view of a semiconductor structure of an embodiment of the present disclosure.
FIG. 1B is a schematic cross-sectional view taken along line 1B-1B' of FIG. 1A.
FIG. 1C is a schematic cross-sectional view taken along line 1C-1C' of FIG. 1A.
FIG. 1D is a schematic cross-sectional view taken along line 1D-1D' of FIG. 1A.
FIG. 1E is a schematic cross-sectional view taken along line 1E-1E' of FIG. 1A.
2 is a top plan view showing a configuration of a plurality of first vertical memory structures and a plurality of second vertical memory structures of a semiconductor structure according to an embodiment of the present disclosure.
3A-11B illustrate schematic views of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

【0009】【0009】

在此揭露內容之實施例中,係提出一種半導體結構及其製造方法。實施例中,半導體結構中,由於一對垂直記憶結構皆具有水平C形剖面且以絕緣溝槽相隔,因此增大單位面積內的記憶密度,進而達到更高的記憶儲存容量。然而,實施例僅用以作為範例說明,並不會限縮本發明欲保護之範圍。此外,實施例中之圖式係省略部份要之元件,以清楚顯示本發明之技術特點。In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. In the embodiment, in the semiconductor structure, since a pair of vertical memory structures have horizontal C-shaped cross sections and are separated by insulating trenches, the memory density per unit area is increased, thereby achieving higher memory storage capacity. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

【0010】[0010]

請參照第1A~1E圖,第1A圖繪示本揭露內容之一實施例之半導體結構100之上視圖,第1B圖繪示沿第1A圖之剖面線1B-1B’之剖面示意圖,第1C圖繪示沿第1A圖之剖面線1C-1C’之剖面示意圖,第1D圖繪示沿第1A圖之剖面線1D-1D’之剖面示意圖,第1E圖繪示沿第1A圖之剖面線1E-1E’之剖面示意圖。實施例中,半導體結構100例如是三維記憶裝置的主要結構。1A to 1E, FIG. 1A is a top view of a semiconductor structure 100 according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view taken along line 1B-1B of FIG. 1A, 1C. The figure shows a schematic cross-sectional view along the section line 1C-1C' of FIG. 1A, FIG. 1D shows a schematic cross-sectional view along the section line 1D-1D' of FIG. 1A, and FIG. 1E shows a section line along the 1st AA. Schematic diagram of 1E-1E'. In an embodiment, the semiconductor structure 100 is, for example, the primary structure of a three-dimensional memory device.

【0011】[0011]

如第1A~1E圖所示,半導體結構100包括基板110、複數個導電層120、複數個絕緣層130、第一垂直記憶結構140、第二垂直記憶結構150以及絕緣溝槽(isolation trench)160。導電層120和絕緣層130形成於基板110上,且此些導電層120與此些絕緣層130係交錯設置(interlaced)堆疊於基板110上。第一垂直記憶結構140和第二垂直記憶結構150穿過導電層120與絕緣層130並形成於基板110上。如第1A圖所示,第一垂直記憶結構140具有一第一水平C形剖面,第二垂直記憶結構150具有一第二水平C形剖面。如第1B和1E圖所示,絕緣溝槽160形成於基板110上並位於第一垂直記憶結構140和第二垂直結構150之間。As shown in FIGS. 1A-1E, the semiconductor structure 100 includes a substrate 110, a plurality of conductive layers 120, a plurality of insulating layers 130, a first vertical memory structure 140, a second vertical memory structure 150, and an isolation trench 160. . The conductive layer 120 and the insulating layer 130 are formed on the substrate 110, and the conductive layers 120 and the insulating layers 130 are interlaced on the substrate 110. The first vertical memory structure 140 and the second vertical memory structure 150 pass through the conductive layer 120 and the insulating layer 130 and are formed on the substrate 110. As shown in FIG. 1A, the first vertical memory structure 140 has a first horizontal C-shaped cross section and the second vertical memory structure 150 has a second horizontal C-shaped cross section. As shown in FIGS. 1B and 1E, an insulating trench 160 is formed on the substrate 110 between the first vertical memory structure 140 and the second vertical structure 150.

【0012】[0012]

實施例中,半導體結構100用於三維記憶裝置時,基板110例如是底源極(bottom source),導電層120例如是字元線,導電層120中的最底層例如是接地選擇線(ground select line,GSL),導電層120中的最頂層例如是串選擇線(string select line,SSL),第一垂直記憶結構140和第二垂直結構150例如是記憶串(memory string),則此三維記憶裝置例如是垂直通道型(vertical channel)記憶裝置。In the embodiment, when the semiconductor structure 100 is used in a three-dimensional memory device, the substrate 110 is, for example, a bottom source, the conductive layer 120 is, for example, a word line, and the bottom layer of the conductive layer 120 is, for example, a ground selection line. Line, GSL), the topmost layer of the conductive layer 120 is, for example, a string select line (SSL), and the first vertical memory structure 140 and the second vertical structure 150 are, for example, a memory string, and the three-dimensional memory The device is for example a vertical channel memory device.

【0013】[0013]

實施例中,半導體結構100中,由於一對垂直記憶結構皆具有水平C形剖面且以絕緣溝槽160相隔,因此增大單位面積內的記憶密度,進而達到更高的記憶儲存容量。實施例中,兩個對稱設置的第一垂直記憶結構140和第二垂直記憶結構150可分別連接至不同的位元線,不僅增大記憶密度,同時經由不同的位元線可以同時選取多個不同的垂直記憶結構(記憶串),因而可以同時處理不同的編程/抹除(program/erase)操作,因此可以進一步提升處理速度。In the embodiment, in the semiconductor structure 100, since a pair of vertical memory structures have a horizontal C-shaped cross section and are separated by the insulating trenches 160, the memory density per unit area is increased, thereby achieving a higher memory storage capacity. In an embodiment, the two symmetrically disposed first vertical memory structures 140 and the second vertical memory structure 150 can be respectively connected to different bit lines, which not only increases the memory density, but also can select multiple simultaneously through different bit lines. Different vertical memory structures (memory strings) can handle different program/erase operations at the same time, thus further increasing the processing speed.

【0014】[0014]

如第1B和1E圖所示,半導體結構100更包括磊晶結構170。磊晶結構170形成於絕緣溝槽160和基板110之間,第一垂直記憶結構140和第二垂直記憶結構150經由磊晶結構170電性連接至基板110。As shown in FIGS. 1B and 1E, the semiconductor structure 100 further includes an epitaxial structure 170. The epitaxial structure 170 is formed between the insulating trench 160 and the substrate 110 , and the first vertical memory structure 140 and the second vertical memory structure 150 are electrically connected to the substrate 110 via the epitaxial structure 170 .

【0015】[0015]

如第1B和1D~1E圖所示,第一垂直記憶結構140和第二垂直記憶結構150分別包括一記憶結構層180和一通道層190,通道層190形成於記憶結構層180上。As shown in FIGS. 1B and 1D-1E, the first vertical memory structure 140 and the second vertical memory structure 150 respectively include a memory structure layer 180 and a channel layer 190, and the channel layer 190 is formed on the memory structure layer 180.

【0016】[0016]

實施例中,記憶結構層180包括阻隔層(blocking layer)181、記憶儲存層183和穿隧層185,阻隔層181形成於導電層120上,記憶儲存層183形成於阻隔層181上,穿隧層185形成於記憶儲存層183上。實施例中,阻隔層181和穿隧層185例如是氧化矽層,記憶儲存層183例如是氮化矽層,通道層190例如是多晶矽層。In an embodiment, the memory structure layer 180 includes a blocking layer 181, a memory storage layer 183, and a tunneling layer 185. The barrier layer 181 is formed on the conductive layer 120, and the memory storage layer 183 is formed on the barrier layer 181. Layer 185 is formed on memory storage layer 183. In the embodiment, the barrier layer 181 and the tunneling layer 185 are, for example, a ruthenium oxide layer, the memory storage layer 183 is, for example, a tantalum nitride layer, and the channel layer 190 is, for example, a polysilicon layer.

【0017】[0017]

如第1A圖所示,第一垂直記憶結構140的第一水平C形剖面的圖案和第二垂直記憶結構150的第二水平C形剖面的圖案係相對於絕緣溝槽160而左右對稱。舉例而言,第一垂直記憶結構140的第一水平C形剖面的C形圖案的缺口和第二垂直記憶結構150的第二水平C形剖面的C形圖案的缺口均朝向絕緣溝槽160。As shown in FIG. 1A, the pattern of the first horizontal C-shaped cross-section of the first vertical memory structure 140 and the pattern of the second horizontal C-shaped cross-section of the second vertical memory structure 150 are bilaterally symmetric with respect to the insulating trench 160. For example, the notch of the C-shaped pattern of the first horizontal C-shaped cross section of the first vertical memory structure 140 and the notch of the C-shaped pattern of the second horizontal C-shaped cross section of the second vertical memory structure 150 are both directed toward the insulating trench 160.

【0018】[0018]

如第1B和1E圖所示,第一垂直記憶結構140和第二垂直記憶結構150直接接觸絕緣溝槽160。As shown in FIGS. 1B and 1E, the first vertical memory structure 140 and the second vertical memory structure 150 directly contact the insulating trenches 160.

【0019】[0019]

如第1A和1D~1E圖所示,半導體結構100更包括第一接觸結構240和第二接觸結構250。第一接觸結構240電性連接至第一垂直記憶結構140,第二接觸結構250電性連接至第二垂直記憶結構150。實施例中,半導體結構100更包括絕緣層191,絕緣層191形成於第一垂直記憶結構140和第二垂直記憶結構150上,而第一接觸結構240和第二接觸結構250形成於絕緣層191之中。絕緣層191例如是層間介電層(ILD),例如是由氧化物所製成。As shown in FIGS. 1A and 1D to 1E, the semiconductor structure 100 further includes a first contact structure 240 and a second contact structure 250. The first contact structure 240 is electrically connected to the first vertical memory structure 140 , and the second contact structure 250 is electrically connected to the second vertical memory structure 150 . In an embodiment, the semiconductor structure 100 further includes an insulating layer 191 formed on the first vertical memory structure 140 and the second vertical memory structure 150, and the first contact structure 240 and the second contact structure 250 are formed on the insulating layer 191. Among them. The insulating layer 191 is, for example, an interlayer dielectric layer (ILD), for example, made of an oxide.

【0020】[0020]

如第1A和1D~1E圖所示,半導體結構100更包括第一位元線BL1和第二位元線BL2。第一位元線BL1電性連接至第一接觸結構240,第二位元線BL2電性連接至第二接觸結構250。實施例中,半導體結構100更包括絕緣層193,絕緣層193形成於絕緣層191上,而第一位元線BL1和第二位元線BL2形成於絕緣層193之中。絕緣層193例如是氧化物層。As shown in FIGS. 1A and 1D to 1E, the semiconductor structure 100 further includes a first bit line BL1 and a second bit line BL2. The first bit line BL1 is electrically connected to the first contact structure 240, and the second bit line BL2 is electrically connected to the second contact structure 250. In an embodiment, the semiconductor structure 100 further includes an insulating layer 193 formed on the insulating layer 191, and the first bit line BL1 and the second bit line BL2 are formed in the insulating layer 193. The insulating layer 193 is, for example, an oxide layer.

【0021】[0021]

第2圖繪示本揭露內容之一實施例之半導體結構100之多個第一垂直記憶結構140和多個第二垂直記憶結構150之配置上視圖。圖式中,係省略部份非必要之元件,並且部分元件以透視方式繪示,以清楚顯示本發明之技術特點。2 is a top plan view showing a plurality of first vertical memory structures 140 and a plurality of second vertical memory structures 150 of the semiconductor structure 100 of one embodiment of the present disclosure. In the drawings, some non-essential elements are omitted, and some of the elements are shown in perspective to clearly show the technical features of the present invention.

【0022】[0022]

如第2圖所示,多組第一垂直記憶結構140和第二垂直記憶結構150以絕緣溝槽160分隔開來。實施例中,絕緣溝槽160的寬度W1例如是40~50奈米(nm),第一垂直記憶結構140和第二垂直記憶結構150係經由絕緣溝槽160的寬度W1相隔開來。實施例中,絕緣溝槽160之間的距離D1例如是大約90奈米。As shown in FIG. 2, the plurality of sets of first vertical memory structures 140 and second vertical memory structures 150 are separated by insulating trenches 160. In the embodiment, the width W1 of the insulating trench 160 is, for example, 40 to 50 nanometers (nm), and the first vertical memory structure 140 and the second vertical memory structure 150 are separated by the width W1 of the insulating trench 160. In the embodiment, the distance D1 between the insulating trenches 160 is, for example, about 90 nm.

【0023】[0023]

實施例中,第一垂直記憶結構140的第一水平C形剖面的尺寸和第二垂直記憶結構150的第二水平C形剖面的尺寸例如是約50~80奈米。實施例中,第一水平C形剖面的尺寸和第二水平C形剖面的尺寸實質上相同。舉例而言,如第2圖所示,多個第一水平C形剖面和多個第二水平C形剖面的尺寸與形狀實質上相同,各個C形剖面的最大寬度W2例如是大約80奈米,各個C形剖面的最小寬度W3例如是大約50奈米。再者,第一垂直記憶結構140和相鄰的第二垂直記憶結構150之間的距離D2例如是大約30~40奈米。In an embodiment, the size of the first horizontal C-shaped cross-section of the first vertical memory structure 140 and the second horizontal C-shaped cross-section of the second vertical memory structure 150 are, for example, about 50-80 nm. In an embodiment, the dimension of the first horizontal C-shaped section and the dimension of the second horizontal C-shaped section are substantially the same. For example, as shown in FIG. 2, the plurality of first horizontal C-shaped sections and the plurality of second horizontal C-shaped sections are substantially the same in size and shape, and the maximum width W2 of each C-shaped section is, for example, about 80 nm. The minimum width W3 of each C-shaped cross section is, for example, about 50 nm. Moreover, the distance D2 between the first vertical memory structure 140 and the adjacent second vertical memory structure 150 is, for example, about 30 to 40 nm.

【0024】[0024]

實施例中,以相隔的區域源極線(local source line)SL之間的Y方向的長度Y1大約為560奈米、而X方向的寬度X1大約為156奈米作為一個記憶陣列單元為例,根據本揭露內容之實施例,此種尺寸的記憶陣列單元中可包括16個垂直記憶結構(記憶串),則大約每平方微米內可容納92個記憶串。然而,當記憶串結構的剖面為具有約110奈米之尺寸的同心圓時,在Y方向的長度大約為480奈米、而X方向的寬度大約為160奈米的記憶陣列單元中僅可包括8個記憶串,則大約每平方微米內僅可容納52個記憶串。如此一來,根據本揭露內容之實施例,記憶密度可提高大約1.8倍。In the embodiment, the length Y1 in the Y direction between the separated local source lines SL is about 560 nm, and the width X1 in the X direction is about 156 nm as an example of a memory array unit. In accordance with an embodiment of the present disclosure, a memory array unit of this size can include 16 vertical memory structures (memory strings) that can accommodate approximately 92 memory strings per square micrometer. However, when the cross section of the memory string structure is a concentric circle having a size of about 110 nm, the memory array unit having a length of about 480 nm in the Y direction and a width of about 160 nm in the X direction may only be included. With 8 memory strings, only about 52 memory strings can be accommodated per square micron. As such, according to an embodiment of the present disclosure, the memory density can be increased by about 1.8 times.

【0025】[0025]

再者,相較於剖面為具有約110奈米之尺寸的同心的記憶串結構,根據本揭露內容之實施例,垂直記憶結構具有尺寸為大約是50~80奈米的C形剖面,因此具有較小的曲度(curvature),而具有較佳的電場增強(field enhancement)效果,進而可以提高整體裝置的效能。Furthermore, in accordance with an embodiment of the present disclosure, the vertical memory structure has a C-shaped profile having a size of about 50 to 80 nanometers, as compared to a concentric memory string structure having a size of about 110 nanometers. The smaller curvature, with better field enhancement effect, can improve the performance of the overall device.

【0026】[0026]

更進一步,如第1A圖所示,第一接觸結構240和第二接觸結構250沿位元線BL1/BL2方向並未對齊而彼此錯開,且多組第一垂直記憶結構140和第二垂直記憶結構150排列成蜂巢狀(honeycomb-like)配置,因而可以於單位面積內連接至較多的位元線並且有效增大記憶密度。Further, as shown in FIG. 1A, the first contact structure 240 and the second contact structure 250 are not aligned with each other along the bit line BL1/BL2 direction, and are offset from each other, and the plurality of sets of the first vertical memory structure 140 and the second vertical memory The structures 150 are arranged in a honeycomb-like configuration so that more bit lines can be connected per unit area and the memory density is effectively increased.

【0027】[0027]

請同時參照第1A~1E圖和第3A圖~第11B圖,其繪示依照本發明之一實施例之一種半導體結構100之製造方法示意圖。Referring to FIGS. 1A-1E and 3A-11B, a schematic diagram of a method of fabricating a semiconductor structure 100 in accordance with an embodiment of the present invention is shown.

【0028】[0028]

第3B圖繪示沿第3A圖之剖面線3B-3B’之剖面示意圖。如第3A~3B圖所示,提供基板110,以及形成複數個導電層120和複數個絕緣層130於基板110上,此些導電層120與此些絕緣層130係交錯設置堆疊於基板110上。Fig. 3B is a schematic cross-sectional view taken along line 3B-3B' of Fig. 3A. As shown in FIG. 3A to FIG. 3B, a substrate 110 is provided, and a plurality of conductive layers 120 and a plurality of insulating layers 130 are formed on the substrate 110. The conductive layers 120 and the insulating layers 130 are stacked on the substrate 110. .

【0029】[0029]

接著,形成第一垂直記憶結構140和第二垂直記憶結構150於基板110上。第一垂直記憶結構140和第二垂直記憶結構150的製造方法例如包括以下步驟。Next, a first vertical memory structure 140 and a second vertical memory structure 150 are formed on the substrate 110. The manufacturing method of the first vertical memory structure 140 and the second vertical memory structure 150 includes, for example, the following steps.

【0030】[0030]

如第3A~3B圖所示,形成一凹槽310,凹槽310穿過導電層120與絕緣層130並停止於基板110上。如第3A圖所示,凹槽310具有一橢圓形剖面,且此橢圓形的長軸W4(最大直徑)例如大約為150奈米。As shown in FIGS. 3A-3B, a recess 310 is formed, and the recess 310 passes through the conductive layer 120 and the insulating layer 130 and stops on the substrate 110. As shown in Fig. 3A, the groove 310 has an elliptical cross section, and the major axis W4 (maximum diameter) of the ellipse is, for example, about 150 nm.

【0031】[0031]

第4B圖繪示沿第4A圖之剖面線4B-4B’之剖面示意圖。如第4A~4B圖所示,形成記憶結構材料層480於凹槽310內,形成通道材料層490於記憶結構材料層480上。記憶結構材料層480包括阻隔材料層(blocking layer)481、記憶儲存材料層483和穿隧材料層485,阻隔材料層481形成於導電層120上,記憶儲存材料層483形成於阻隔材料層481上,穿隧材料層485形成於記憶儲存材料層483上。實施例中,阻隔材料層481和穿隧材料層485例如是氧化矽層,記憶儲存材料層483例如是氮化矽層,通道材料層490例如是多晶矽層。Fig. 4B is a schematic cross-sectional view taken along line 4B-4B' of Fig. 4A. As shown in FIGS. 4A-4B, a memory structure material layer 480 is formed in the recess 310 to form a channel material layer 490 on the memory structure material layer 480. The memory structure material layer 480 includes a blocking material layer 481, a memory storage material layer 483, and a tunneling material layer 485. The barrier material layer 481 is formed on the conductive layer 120, and the memory storage material layer 483 is formed on the barrier material layer 481. A tunneling material layer 485 is formed on the memory storage material layer 483. In the embodiment, the barrier material layer 481 and the tunneling material layer 485 are, for example, a ruthenium oxide layer, the memory storage material layer 483 is, for example, a tantalum nitride layer, and the channel material layer 490 is, for example, a polysilicon layer.

【0032】[0032]

第5B圖繪示沿第5A圖之剖面線5B-5B’之剖面示意圖,第5C圖繪示沿第5A圖之剖面線5C-5C’之剖面示意圖。如第5A~5C圖所示,形成氧化物材料層510於通道材料層490上並填入凹槽310中,形成的氧化物材料層510中具有一空氣間隙(air gap)510a。Fig. 5B is a cross-sectional view taken along line 5B-5B' of Fig. 5A, and Fig. 5C is a cross-sectional view taken along line 5C-5C' of Fig. 5A. As shown in FIGS. 5A-5C, an oxide material layer 510 is formed on the channel material layer 490 and filled in the recess 310, and the formed oxide material layer 510 has an air gap 510a therein.

【0033】[0033]

第6B圖繪示沿第6A圖之剖面線6B-6B’之剖面示意圖,第6C圖繪示沿第6A圖之剖面線6C-6C’之剖面示意圖,第6D圖繪示沿第6A圖之剖面線6D-6D’之剖面示意圖。如第6A~6D圖所示,沿著橢圓形剖面的短軸方向R1移除部分導電層120、部分絕緣層130、部分記憶結構材料層480、部分通道材料層490和部分氧化物材料層510以形成一溝槽T。6B is a cross-sectional view taken along line 6B-6B' of FIG. 6A, FIG. 6C is a cross-sectional view taken along line 6C-6C' of FIG. 6A, and FIG. 6D is a view along line 6A. A schematic cross-sectional view of the section line 6D-6D'. As shown in FIGS. 6A to 6D, a portion of the conductive layer 120, a portion of the insulating layer 130, a portion of the memory structure material layer 480, a portion of the channel material layer 490, and a portion of the oxide material layer 510 are removed along the short-axis direction R1 of the elliptical cross-section. To form a trench T.

【0034】[0034]

如第6A~6C圖所示,例如是以一蝕刻製程移除部分導電層120、部分絕緣層130、部分記憶結構材料層480、部分通道材料層490和部分氧化物材料層510。蝕刻之後,如第6B圖所示,凹槽310內的部分記憶結構材料層480、部分通道材料層490和部分氧化物材料層510被蝕刻移除以暴露出基板110。蝕刻之後,如第6C圖所示,凹槽310之外的部分導電層120和部分絕緣層130被蝕刻移除以暴露出此些絕緣層130之一最底層130b。換言之,由於空氣間隙510a的存在,凹槽310內的材料以較快的速度被蝕刻,因而蝕刻的深度較深,形成的溝槽T的此區域連接至基板110。而凹槽310之外的材料不具有空氣間隙510a,以較慢的速度被蝕刻,因而蝕刻的深度較淺,形成的溝槽T的此區域僅到達絕緣層130的最底層130b,並未接觸到基板110。至此,形成多個記憶結構層180。As shown in FIGS. 6A-6C, a portion of the conductive layer 120, a portion of the insulating layer 130, a portion of the memory structure material layer 480, a portion of the channel material layer 490, and a portion of the oxide material layer 510 are removed, for example, by an etching process. After etching, as shown in FIG. 6B, a portion of the memory structural material layer 480, a portion of the channel material layer 490, and a portion of the oxide material layer 510 within the recess 310 are etched away to expose the substrate 110. After etching, as shown in FIG. 6C, a portion of the conductive layer 120 and a portion of the insulating layer 130 outside the recess 310 are etched away to expose one of the bottom layers 130b of the insulating layers 130. In other words, due to the presence of the air gap 510a, the material within the recess 310 is etched at a faster rate, and thus the depth of the etch is deeper, and this region of the formed trench T is connected to the substrate 110. The material outside the groove 310 does not have the air gap 510a, is etched at a slower speed, and thus the etching depth is shallow, and the region of the formed trench T reaches only the bottommost layer 130b of the insulating layer 130, and is not in contact. To the substrate 110. So far, a plurality of memory structure layers 180 are formed.

【0035】[0035]

由於溝槽T的形成,而能夠形成後續的第一垂直記憶結構140和第二垂直結構150的水平C形剖面,因而可以使最後製作完成的半導體結構具有如前所述的功效與優點。Due to the formation of the trench T, a horizontal C-shaped cross-section of the subsequent first vertical memory structure 140 and the second vertical structure 150 can be formed, thereby enabling the final fabricated semiconductor structure to have the aforementioned advantages and advantages.

【0036】[0036]

第7B圖繪示沿第7A圖之剖面線7B-7B’之剖面示意圖,第7C圖繪示沿第7A圖之剖面線7C-7C’之剖面示意圖,第7D圖繪示沿第7A圖之剖面線7D-7D’之剖面示意圖。如第7A~7D圖所示,形成溝槽T之後,形成磊晶結構170於凹槽310內的基板110上。也就是說,磊晶結構170形成於後續會形成的絕緣溝槽160和基板110之間。7B is a cross-sectional view taken along line 7B-7B' of FIG. 7A, FIG. 7C is a cross-sectional view taken along line 7C-7C' of FIG. 7A, and FIG. 7D is a view along line 7A. A schematic cross-sectional view of the section line 7D-7D'. As shown in FIGS. 7A-7D, after the trench T is formed, the epitaxial structure 170 is formed on the substrate 110 in the recess 310. That is, the epitaxial structure 170 is formed between the insulating trench 160 and the substrate 110 which will be formed later.

【0037】[0037]

實施例中,磊晶結構170以選擇性磊晶(Selective epitaxial growth,SEG)製程製作,因此磊晶結構170成長的區域具有高選擇性,會形成於具有晶種的表面,例如是具有單晶矽結構的基板110表面上,而不會形成於其他材料(例如是氧化物層或多晶矽層)上。In the embodiment, the epitaxial structure 170 is fabricated by a selective epitaxial growth (SEG) process, so that the region in which the epitaxial structure 170 grows has high selectivity and is formed on a surface having a seed crystal, for example, having a single crystal. The surface of the substrate 110 of the germanium structure is not formed on other materials such as an oxide layer or a polysilicon layer.

【0038】[0038]

第8B圖繪示沿第8A圖之剖面線8B-8B’之剖面示意圖,第8C圖繪示沿第8A圖之剖面線8C-8C’之剖面示意圖,第8D圖繪示沿第8A圖之剖面線8D-8D’之剖面示意圖。如第8A~8D圖所示,填入一絕緣材料810於溝槽T中,此時,絕緣溝槽160係形成。8B is a cross-sectional view taken along line 8B-8B' of FIG. 8A, FIG. 8C is a cross-sectional view taken along line 8C-8C' of FIG. 8A, and FIG. 8D is a view along line 8A. A schematic cross-sectional view of the section line 8D-8D'. As shown in FIGS. 8A to 8D, an insulating material 810 is filled in the trench T, and at this time, the insulating trench 160 is formed.

【0039】[0039]

第9B圖繪示沿第9A圖之剖面線9B-9B’之剖面示意圖,第9C圖繪示沿第9A圖之剖面線9C-9C’之剖面示意圖,第9D圖繪示沿第9A圖之剖面線9D-9D’之剖面示意圖。如第9A~9D圖所示,以化學機械研磨製程移除暴露於溝槽T之外的通道材料層490,以形成多個通道層190。9B is a cross-sectional view taken along line 9B-9B' of FIG. 9A, FIG. 9C is a cross-sectional view taken along line 9C-9C' of FIG. 9A, and FIG. 9D is a view along line 9A. A schematic cross-sectional view of the section line 9D-9D'. As shown in FIGS. 9A-9D, the channel material layer 490 exposed outside the trench T is removed by a chemical mechanical polishing process to form a plurality of channel layers 190.

【0040】[0040]

至此,如第9A~9D圖所示,形成多個第一垂直記憶結構140和多個第二垂直記憶結構150,第一垂直記憶結構140和第二垂直記憶結構150穿過導電層120與絕緣層130,第一垂直記憶結構140具有第一水平C形剖面,第二垂直記憶結構150具有第二水平C形剖面。So far, as shown in FIGS. 9A-9D, a plurality of first vertical memory structures 140 and a plurality of second vertical memory structures 150 are formed, and the first vertical memory structures 140 and the second vertical memory structures 150 pass through the conductive layer 120 and are insulated. Layer 130, first vertical memory structure 140 has a first horizontal C-shaped cross-section, and second vertical memory structure 150 has a second horizontal C-shaped cross-section.

【0041】[0041]

再者,化學機械研磨製程之後,留在溝槽T中的氧化物材料層510和絕緣材料810形成絕緣溝槽160,絕緣溝槽160形成於基板110上並位於第一垂直記憶結構140和第二垂直結構150之間。Furthermore, after the chemical mechanical polishing process, the oxide material layer 510 and the insulating material 810 remaining in the trench T form an insulating trench 160 formed on the substrate 110 and located in the first vertical memory structure 140 and Between two vertical structures 150.

【0042】[0042]

並且,各個垂直記憶結構的通道層190沿著Y方向係彼此分隔開來,則形成的磊晶結構170位於絕緣溝槽160和基板110之間,第一垂直記憶結構140和第二垂直記憶結構150經由磊晶結構170電性連接至基板110。詳細來說,第一垂直記憶結構140的通道層190和第二垂直記憶結構150的通道層190經由磊晶結構170電性連接至基板110。Moreover, the channel layers 190 of the respective vertical memory structures are spaced apart from each other along the Y direction, and the formed epitaxial structure 170 is located between the insulating trenches 160 and the substrate 110, the first vertical memory structure 140 and the second vertical memory. The structure 150 is electrically connected to the substrate 110 via the epitaxial structure 170. In detail, the channel layer 190 of the first vertical memory structure 140 and the channel layer 190 of the second vertical memory structure 150 are electrically connected to the substrate 110 via the epitaxial structure 170.

【0043】[0043]

第10B圖繪示沿第10A圖之剖面線10B-10B’之剖面示意圖,如第10A~10B圖所示,形成絕緣材料層991於第一垂直記憶結構140和第二垂直記憶結構150上。10B is a schematic cross-sectional view taken along line 10B-10B' of FIG. 10A. As shown in FIGS. 10A-10B, an insulating material layer 991 is formed on the first vertical memory structure 140 and the second vertical memory structure 150.

【0044】[0044]

第11B圖繪示沿第11A圖之剖面線11B-11B’之剖面示意圖,如第11A~11B圖所示,形成第一接觸結構240電性連接至第一垂直記憶結構140,以及形成第二接觸結構250電性連接至第二垂直記憶結構250。實施例中,例如是在絕緣材料層991中形成接觸孔,接著將導電材料填入接觸孔中以形成第一接觸結構240和第二接觸結構250於絕緣層191之中。11B is a schematic cross-sectional view along section line 11B-11B' of FIG. 11A. As shown in FIGS. 11A-11B, the first contact structure 240 is electrically connected to the first vertical memory structure 140, and the second is formed. The contact structure 250 is electrically connected to the second vertical memory structure 250. In the embodiment, for example, a contact hole is formed in the insulating material layer 991, and then a conductive material is filled in the contact hole to form the first contact structure 240 and the second contact structure 250 in the insulating layer 191.

【0045】[0045]

接著,請參照第1A~1E圖,形成絕緣層193於絕緣層191上,形成第一位元線BL1和第二位元線BL2於絕緣層193之中。第一位元線BL1電性連接至第一接觸結構240,第二位元線BL2電性連接至第二接觸結構250。至此,形成於第1A~1E圖所示的半導體結構100。Next, referring to FIGS. 1A to 1E, an insulating layer 193 is formed on the insulating layer 191, and the first bit line BL1 and the second bit line BL2 are formed in the insulating layer 193. The first bit line BL1 is electrically connected to the first contact structure 240, and the second bit line BL2 is electrically connected to the second contact structure 250. Thus far, the semiconductor structure 100 shown in FIGS. 1A to 1E is formed.

【0046】[0046]

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

140‧‧‧第一垂直記憶結構 140‧‧‧First vertical memory structure

150‧‧‧第二垂直記憶結構 150‧‧‧Second vertical memory structure

240‧‧‧第一接觸結構 240‧‧‧First contact structure

250‧‧‧第二接觸結構 250‧‧‧Second contact structure

BL1‧‧‧第一位元線 BL1‧‧‧ first bit line

BL2‧‧‧第二位元線 BL2‧‧‧ second bit line

1B-1B’、1C-1C’、1D-1D’、1E-1E’‧‧‧剖面線 1B-1B', 1C-1C', 1D-1D', 1E-1E'‧‧‧ hatching

Claims (10)

【第1項】[Item 1] 一種半導體結構,包括:
一基板;
複數個導電層和複數個絕緣層,形成於該基板上,其中該些導電層與該些絕緣層係交錯設置(interlaced)堆疊於該基板上;
一第一垂直記憶結構和一第二垂直記憶結構,穿過該些導電層與該些絕緣層並形成於該基板上,其中該第一垂直記憶結構具有一第一水平C形剖面,該第二垂直記憶結構具有一第二水平C形剖面;以及
一絕緣溝槽(isolation trench),形成於該基板上並位於該第一垂直記憶結構和該第二垂直結構之間。
A semiconductor structure comprising:
a substrate;
a plurality of conductive layers and a plurality of insulating layers are formed on the substrate, wherein the conductive layers and the insulating layers are interlaced on the substrate;
a first vertical memory structure and a second vertical memory structure are formed on the substrate through the conductive layer and the insulating layer, wherein the first vertical memory structure has a first horizontal C-shaped profile, the first The two vertical memory structures have a second horizontal C-shaped cross-section; and an isolation trench formed on the substrate between the first vertical memory structure and the second vertical structure.
【第2項】[Item 2] 如申請專利範圍第1項所述之半導體結構,更包括:
一磊晶結構,形成於該絕緣溝槽和該基板之間,其中該第一垂直記憶結構和該第二垂直記憶結構經由該磊晶結構電性連接至該基板。
For example, the semiconductor structure described in claim 1 of the patent scope further includes:
An epitaxial structure is formed between the insulating trench and the substrate, wherein the first vertical memory structure and the second vertical memory structure are electrically connected to the substrate via the epitaxial structure.
【第3項】[Item 3] 如申請專利範圍第1項所述之半導體結構,其中該第一垂直記憶結構和該第二垂直記憶結構分別包括:
一記憶結構層,包括:
一阻隔層(blocking layer),形成於該些導電層上;
一記憶儲存層,形成於該阻隔層上;及
一穿隧層,形成於該記憶儲存層上;以及
一通道層,形成於該記憶結構層上,其中該通道層係為多晶矽層。
The semiconductor structure of claim 1, wherein the first vertical memory structure and the second vertical memory structure respectively comprise:
A memory structure layer, including:
a blocking layer formed on the conductive layers;
a memory storage layer formed on the barrier layer; and a tunneling layer formed on the memory storage layer; and a channel layer formed on the memory structure layer, wherein the channel layer is a polysilicon layer.
【第4項】[Item 4] 如申請專利範圍第1項所述之半導體結構,更包括:
一第一接觸結構,電性連接至該第一垂直記憶結構;
一第二接觸結構,電性連接至該第二垂直記憶結構;
一第一位元線,電性連接至該第一接觸結構;以及
一第二位元線,電性連接至該第二接觸結構;
其中該第一垂直記憶結構的該第一水平C形剖面的圖案和該第二垂直記憶結構的該第二水平C形剖面的圖案係相對於該絕緣溝槽而左右對稱。
For example, the semiconductor structure described in claim 1 of the patent scope further includes:
a first contact structure electrically connected to the first vertical memory structure;
a second contact structure electrically connected to the second vertical memory structure;
a first bit line electrically connected to the first contact structure; and a second bit line electrically connected to the second contact structure;
The pattern of the first horizontal C-shaped cross section of the first vertical memory structure and the pattern of the second horizontal C-shaped cross section of the second vertical memory structure are bilaterally symmetrical with respect to the insulating trench.
【第5項】[Item 5] 如申請專利範圍第1項所述之半導體結構,其中該第一垂直記憶結構和該第二垂直記憶結構直接接觸該絕緣溝槽,該絕緣溝槽的寬度係為40~50奈米(nm),該第一垂直記憶結構和該第二垂直記憶結構係經由該絕緣溝槽的該寬度相隔開來,該第一水平C形剖面和該第二水平C形剖面的尺寸係為約50~80奈米。
The semiconductor structure of claim 1, wherein the first vertical memory structure and the second vertical memory structure directly contact the insulating trench, and the insulating trench has a width of 40 to 50 nanometers (nm). The first vertical memory structure and the second vertical memory structure are separated by the width of the insulating trench, and the first horizontal C-shaped cross section and the second horizontal C-shaped cross-section have a size of about 50-80 Nano.
【第6項】[Item 6] 一種半導體結構之製造方法,包括:
提供一基板;
形成複數個導電層和複數個絕緣層於該基板上,其中該些導電層與該些絕緣層係交錯設置堆疊於該基板上;
形成一第一垂直記憶結構和一第二垂直記憶結構於該基板上,其中該第一垂直記憶結構和該第二垂直記憶結構穿過該些導電層與該些絕緣層,該第一垂直記憶結構具有一第一水平C形剖面,該第二垂直記憶結構具有一第二水平C形剖面;以及
形成一絕緣溝槽於該基板上並位於該第一垂直記憶結構和該第二垂直結構之間。
A method of fabricating a semiconductor structure, comprising:
Providing a substrate;
Forming a plurality of conductive layers and a plurality of insulating layers on the substrate, wherein the conductive layers and the insulating layers are alternately stacked on the substrate;
Forming a first vertical memory structure and a second vertical memory structure on the substrate, wherein the first vertical memory structure and the second vertical memory structure pass through the conductive layers and the insulating layers, the first vertical memory The structure has a first horizontal C-shaped cross section, the second vertical memory structure has a second horizontal C-shaped cross section; and an insulating trench is formed on the substrate and located in the first vertical memory structure and the second vertical structure between.
【第7項】[Item 7] 如申請專利範圍第6項所述之半導體結構之製造方法,更包括:
形成一磊晶結構於該絕緣溝槽和該基板之間,其中該第一垂直記憶結構和該第二垂直記憶結構經由該磊晶結構電性連接至該基板。
The method for manufacturing a semiconductor structure as described in claim 6 further includes:
An epitaxial structure is formed between the insulating trench and the substrate, wherein the first vertical memory structure and the second vertical memory structure are electrically connected to the substrate via the epitaxial structure.
【第8項】[Item 8] 如申請專利範圍第6項所述之半導體結構之製造方法,其中形成第一垂直記憶結構、該第二垂直記憶結構和該絕緣溝槽包括:
形成一凹槽穿過該些導電層與該些絕緣層並停止於該基板上,其中該凹槽具有一橢圓形剖面;
形成一記憶結構材料層於該凹槽內;
形成一通道材料層於該記憶結構材料層上;
形成一氧化物材料層於該通道材料層上並填入該凹槽中,其中該氧化物材料層中具有一空氣間隙(air gap);
沿著該橢圓形剖面的一短軸方向移除部分該些導電層、部分該些絕緣層、部分該記憶結構材料層、部分該通道材料層和部分該氧化物材料層以形成一溝槽;以及
填入一絕緣材料於該溝槽中以形成該絕緣溝槽。
The method of fabricating a semiconductor structure according to claim 6, wherein the forming the first vertical memory structure, the second vertical memory structure, and the insulating trench comprises:
Forming a groove through the conductive layer and the insulating layer and stopping on the substrate, wherein the groove has an elliptical cross section;
Forming a memory structural material layer in the recess;
Forming a channel material layer on the memory structure material layer;
Forming an oxide material layer on the channel material layer and filling the groove, wherein the oxide material layer has an air gap therein;
Removing a portion of the conductive layer, a portion of the insulating layer, a portion of the memory structural material layer, a portion of the channel material layer and a portion of the oxide material layer to form a trench along a minor axis direction of the elliptical cross section; And filling an insulating material into the trench to form the insulating trench.
【第9項】[Item 9] 如申請專利範圍第8項所述之半導體結構之製造方法,更包括:
形成該溝槽之後,形成一磊晶結構於該絕緣溝槽和該基板之間;以及
以一化學機械研磨製程移除暴露於該溝槽之外的該通道材料層;
其中係以一蝕刻製程移除部分該些導電層、部分該些絕緣層、部分該記憶結構材料層、部分該通道材料層和部分該氧化物材料層,該凹槽內的部分該記憶結構材料層、部分該通道材料層和部分該氧化物材料層係被蝕刻移除以暴露出該基板,部分該些導電層和部分該些絕緣層係被蝕刻移除以暴露出該些絕緣層之一最底層。
The method for manufacturing a semiconductor structure according to claim 8 of the patent application, further comprising:
After forming the trench, forming an epitaxial structure between the insulating trench and the substrate; and removing the channel material layer exposed outside the trench by a chemical mechanical polishing process;
Wherein the conductive layer, a portion of the insulating layer, a portion of the memory structure material layer, a portion of the channel material layer and a portion of the oxide material layer are removed by an etching process, and a portion of the memory structure material in the recess a layer, a portion of the channel material layer and a portion of the oxide material layer are etched away to expose the substrate, and a portion of the conductive layers and portions of the insulating layers are etched away to expose one of the insulating layers Lowest level.
【第10項】[Item 10] 如申請專利範圍第6項所述之半導體結構之製造方法,更包括:
形成一第一接觸結構電性連接至該第一垂直記憶結構;
形成一第二接觸結構電性連接至該第二垂直記憶結構;
形成一第一位元線電性連接至該第一接觸結構;以及
形成一第二位元線電性連接至該第二接觸結構。
The method for manufacturing a semiconductor structure as described in claim 6 further includes:
Forming a first contact structure electrically connected to the first vertical memory structure;
Forming a second contact structure electrically connected to the second vertical memory structure;
Forming a first bit line electrically connected to the first contact structure; and forming a second bit line electrically connected to the second contact structure.
TW104112476A 2015-04-17 2015-04-17 Semiconductor structure and manufacturing method of the same TWI541984B (en)

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