TW201639126A - Semiconductor structure and manufacturing method of the same - Google Patents

Abstract

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a first vertical memory structure, a second vertical memory structure, and an isolation trench. The conductive layers and the insulating layers are interlaced and stacked on the substrate. The first vertical memory structure and the second memory structure penetrate the conductive layers and the insulating layers are formed on the substrate. The first vertical memory structure has a first horizontal C shaped cross-section, and the second vertical memory structure has a second horizontal C shaped cross-section. The isolation trench is formed between the first vertical memory structure and the second vertical memory structure.

Description

Semiconductor structure and method of manufacturing same 【0001】

The present disclosure relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a high memory density and a method of fabricating the same.

【0002】

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density and a small size.

[0003]

Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has good stability.

[0004]

The disclosure relates to a semiconductor structure and a method of fabricating the same. In the embodiment, in the semiconductor structure, since a pair of vertical memory structures have horizontal C-shaped cross sections and are separated by insulating trenches, the memory density per unit area is increased, thereby achieving higher memory storage capacity.

[0005]

In accordance with an embodiment of the present disclosure, a semiconductor structure is proposed. The semiconductor structure includes a substrate, a plurality of conductive layers and a plurality of insulating layers, a first vertical memory structure and a second vertical memory structure, and an isolation trench. The conductive layer and the insulating layer are formed on the substrate, wherein the conductive layer and the insulating layer are interlaced and stacked on the substrate. The first vertical memory structure and the second vertical memory structure are formed on the substrate through the conductive layer and the insulating layer, wherein the first vertical memory structure has a first horizontal C-shaped cross section and the second vertical memory structure has a second horizontal C Profile. An insulating trench is formed on the substrate and between the first vertical memory structure and the second vertical structure.

[0006]

In accordance with another embodiment of the present disclosure, a method of fabricating a semiconductor structure is presented. The method of fabricating a semiconductor structure includes the following steps. Providing a substrate; forming a plurality of conductive layers and a plurality of insulating layers on the substrate, wherein the conductive layers and the insulating layers are alternately stacked on the substrate; forming a first vertical memory structure and a second vertical memory structure On the substrate, wherein the first vertical memory structure and the second vertical memory structure pass through the conductive layers and the insulating layers, the first vertical memory structure has a first horizontal C-shaped cross section, and the second vertical memory structure has a first a two-level C-shaped profile; and forming an insulating trench on the substrate and between the first vertical memory structure and the second vertical structure.

【0007】

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0047]

100‧‧‧Semiconductor structure
110‧‧‧Substrate
120‧‧‧ Conductive layer
130‧‧‧Insulation
130b‧‧‧ bottom level
140‧‧‧First vertical memory structure
150‧‧‧Second vertical memory structure
160‧‧‧Insulation trench
170‧‧‧ epitaxial structure
180‧‧‧ memory structure layer
181‧‧‧Barrier
183‧‧‧ memory storage layer
185‧‧‧ Tunneling
190‧‧‧channel layer
191, 193‧‧‧Insulation
240‧‧‧First contact structure
250‧‧‧Second contact structure
310‧‧‧ Groove
480‧‧‧Memory structural material layer
481‧‧‧layer of barrier material
483‧‧‧Memory storage material layer
485‧‧‧Through tunneling material layer
490‧‧‧channel material layer
510‧‧‧Oxide material layer
51a‧‧‧Air gap
810‧‧‧Insulation
991‧‧‧Insulation layer
BL1‧‧‧ first bit line
BL2‧‧‧ second bit line
D1, D2‧‧‧ distance
R1‧‧‧ short axis direction
T‧‧‧ trench
W1, W2, X1‧‧‧ width
W4‧‧‧ long axis
Y1‧‧‧ length
1B-1B', 1C-1C', 1D-1D', 1E-1E', 3B-3B', 4B-4B', 5B-5B', 5C-5C', 6B-6B', 6C-6C', 6D-6D', 7B-7B', 7C-7C', 7D-7D', 8B-8B', 8C-8C', 8D-8D', 9B-9B', 9C-9C', 9D-9D', 10B-10B', 11B-11B'‧‧‧ hatching

[0008]

FIG. 1A is a top view of a semiconductor structure of an embodiment of the present disclosure.
FIG. 1B is a schematic cross-sectional view taken along line 1B-1B' of FIG. 1A.
FIG. 1C is a schematic cross-sectional view taken along line 1C-1C' of FIG. 1A.
FIG. 1D is a schematic cross-sectional view taken along line 1D-1D' of FIG. 1A.
FIG. 1E is a schematic cross-sectional view taken along line 1E-1E' of FIG. 1A.
2 is a top plan view showing a configuration of a plurality of first vertical memory structures and a plurality of second vertical memory structures of a semiconductor structure according to an embodiment of the present disclosure.
3A-11B illustrate schematic views of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

【0009】

In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. In the embodiment, in the semiconductor structure, since a pair of vertical memory structures have horizontal C-shaped cross sections and are separated by insulating trenches, the memory density per unit area is increased, thereby achieving higher memory storage capacity. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

[0010]

1A to 1E, FIG. 1A is a top view of a semiconductor structure 100 according to an embodiment of the present disclosure, and FIG. 1B is a cross-sectional view taken along line 1B-1B of FIG. 1A, 1C. The figure shows a schematic cross-sectional view along the section line 1C-1C' of FIG. 1A, FIG. 1D shows a schematic cross-sectional view along the section line 1D-1D' of FIG. 1A, and FIG. 1E shows a section line along the 1st AA. Schematic diagram of 1E-1E'. In an embodiment, the semiconductor structure 100 is, for example, the primary structure of a three-dimensional memory device.

[0011]

As shown in FIGS. 1A-1E, the semiconductor structure 100 includes a substrate 110, a plurality of conductive layers 120, a plurality of insulating layers 130, a first vertical memory structure 140, a second vertical memory structure 150, and an isolation trench 160. . The conductive layer 120 and the insulating layer 130 are formed on the substrate 110, and the conductive layers 120 and the insulating layers 130 are interlaced on the substrate 110. The first vertical memory structure 140 and the second vertical memory structure 150 pass through the conductive layer 120 and the insulating layer 130 and are formed on the substrate 110. As shown in FIG. 1A, the first vertical memory structure 140 has a first horizontal C-shaped cross section and the second vertical memory structure 150 has a second horizontal C-shaped cross section. As shown in FIGS. 1B and 1E, an insulating trench 160 is formed on the substrate 110 between the first vertical memory structure 140 and the second vertical structure 150.

[0012]

In the embodiment, when the semiconductor structure 100 is used in a three-dimensional memory device, the substrate 110 is, for example, a bottom source, the conductive layer 120 is, for example, a word line, and the bottom layer of the conductive layer 120 is, for example, a ground selection line. Line, GSL), the topmost layer of the conductive layer 120 is, for example, a string select line (SSL), and the first vertical memory structure 140 and the second vertical structure 150 are, for example, a memory string, and the three-dimensional memory The device is for example a vertical channel memory device.

[0013]

In the embodiment, in the semiconductor structure 100, since a pair of vertical memory structures have a horizontal C-shaped cross section and are separated by the insulating trenches 160, the memory density per unit area is increased, thereby achieving a higher memory storage capacity. In an embodiment, the two symmetrically disposed first vertical memory structures 140 and the second vertical memory structure 150 can be respectively connected to different bit lines, which not only increases the memory density, but also can select multiple simultaneously through different bit lines. Different vertical memory structures (memory strings) can handle different program/erase operations at the same time, thus further increasing the processing speed.

[0014]

As shown in FIGS. 1B and 1E, the semiconductor structure 100 further includes an epitaxial structure 170. The epitaxial structure 170 is formed between the insulating trench 160 and the substrate 110 , and the first vertical memory structure 140 and the second vertical memory structure 150 are electrically connected to the substrate 110 via the epitaxial structure 170 .

[0015]

As shown in FIGS. 1B and 1D-1E, the first vertical memory structure 140 and the second vertical memory structure 150 respectively include a memory structure layer 180 and a channel layer 190, and the channel layer 190 is formed on the memory structure layer 180.

[0016]

In an embodiment, the memory structure layer 180 includes a blocking layer 181, a memory storage layer 183, and a tunneling layer 185. The barrier layer 181 is formed on the conductive layer 120, and the memory storage layer 183 is formed on the barrier layer 181. Layer 185 is formed on memory storage layer 183. In the embodiment, the barrier layer 181 and the tunneling layer 185 are, for example, a ruthenium oxide layer, the memory storage layer 183 is, for example, a tantalum nitride layer, and the channel layer 190 is, for example, a polysilicon layer.

[0017]

As shown in FIG. 1A, the pattern of the first horizontal C-shaped cross-section of the first vertical memory structure 140 and the pattern of the second horizontal C-shaped cross-section of the second vertical memory structure 150 are bilaterally symmetric with respect to the insulating trench 160. For example, the notch of the C-shaped pattern of the first horizontal C-shaped cross section of the first vertical memory structure 140 and the notch of the C-shaped pattern of the second horizontal C-shaped cross section of the second vertical memory structure 150 are both directed toward the insulating trench 160.

[0018]

As shown in FIGS. 1B and 1E, the first vertical memory structure 140 and the second vertical memory structure 150 directly contact the insulating trenches 160.

[0019]

As shown in FIGS. 1A and 1D to 1E, the semiconductor structure 100 further includes a first contact structure 240 and a second contact structure 250. The first contact structure 240 is electrically connected to the first vertical memory structure 140 , and the second contact structure 250 is electrically connected to the second vertical memory structure 150 . In an embodiment, the semiconductor structure 100 further includes an insulating layer 191 formed on the first vertical memory structure 140 and the second vertical memory structure 150, and the first contact structure 240 and the second contact structure 250 are formed on the insulating layer 191. Among them. The insulating layer 191 is, for example, an interlayer dielectric layer (ILD), for example, made of an oxide.

[0020]

As shown in FIGS. 1A and 1D to 1E, the semiconductor structure 100 further includes a first bit line BL1 and a second bit line BL2. The first bit line BL1 is electrically connected to the first contact structure 240, and the second bit line BL2 is electrically connected to the second contact structure 250. In an embodiment, the semiconductor structure 100 further includes an insulating layer 193 formed on the insulating layer 191, and the first bit line BL1 and the second bit line BL2 are formed in the insulating layer 193. The insulating layer 193 is, for example, an oxide layer.

[0021]

2 is a top plan view showing a plurality of first vertical memory structures 140 and a plurality of second vertical memory structures 150 of the semiconductor structure 100 of one embodiment of the present disclosure. In the drawings, some non-essential elements are omitted, and some of the elements are shown in perspective to clearly show the technical features of the present invention.

[0022]

As shown in FIG. 2, the plurality of sets of first vertical memory structures 140 and second vertical memory structures 150 are separated by insulating trenches 160. In the embodiment, the width W1 of the insulating trench 160 is, for example, 40 to 50 nanometers (nm), and the first vertical memory structure 140 and the second vertical memory structure 150 are separated by the width W1 of the insulating trench 160. In the embodiment, the distance D1 between the insulating trenches 160 is, for example, about 90 nm.

[0023]

In an embodiment, the size of the first horizontal C-shaped cross-section of the first vertical memory structure 140 and the second horizontal C-shaped cross-section of the second vertical memory structure 150 are, for example, about 50-80 nm. In an embodiment, the dimension of the first horizontal C-shaped section and the dimension of the second horizontal C-shaped section are substantially the same. For example, as shown in FIG. 2, the plurality of first horizontal C-shaped sections and the plurality of second horizontal C-shaped sections are substantially the same in size and shape, and the maximum width W2 of each C-shaped section is, for example, about 80 nm. The minimum width W3 of each C-shaped cross section is, for example, about 50 nm. Moreover, the distance D2 between the first vertical memory structure 140 and the adjacent second vertical memory structure 150 is, for example, about 30 to 40 nm.

[0024]

In the embodiment, the length Y1 in the Y direction between the separated local source lines SL is about 560 nm, and the width X1 in the X direction is about 156 nm as an example of a memory array unit. In accordance with an embodiment of the present disclosure, a memory array unit of this size can include 16 vertical memory structures (memory strings) that can accommodate approximately 92 memory strings per square micrometer. However, when the cross section of the memory string structure is a concentric circle having a size of about 110 nm, the memory array unit having a length of about 480 nm in the Y direction and a width of about 160 nm in the X direction may only be included. With 8 memory strings, only about 52 memory strings can be accommodated per square micron. As such, according to an embodiment of the present disclosure, the memory density can be increased by about 1.8 times.

[0025]

Furthermore, in accordance with an embodiment of the present disclosure, the vertical memory structure has a C-shaped profile having a size of about 50 to 80 nanometers, as compared to a concentric memory string structure having a size of about 110 nanometers. The smaller curvature, with better field enhancement effect, can improve the performance of the overall device.

[0026]

Further, as shown in FIG. 1A, the first contact structure 240 and the second contact structure 250 are not aligned with each other along the bit line BL1/BL2 direction, and are offset from each other, and the plurality of sets of the first vertical memory structure 140 and the second vertical memory The structures 150 are arranged in a honeycomb-like configuration so that more bit lines can be connected per unit area and the memory density is effectively increased.

[0027]

Referring to FIGS. 1A-1E and 3A-11B, a schematic diagram of a method of fabricating a semiconductor structure 100 in accordance with an embodiment of the present invention is shown.

[0028]

Fig. 3B is a schematic cross-sectional view taken along line 3B-3B' of Fig. 3A. As shown in FIG. 3A to FIG. 3B, a substrate 110 is provided, and a plurality of conductive layers 120 and a plurality of insulating layers 130 are formed on the substrate 110. The conductive layers 120 and the insulating layers 130 are stacked on the substrate 110. .

[0029]

Next, a first vertical memory structure 140 and a second vertical memory structure 150 are formed on the substrate 110. The manufacturing method of the first vertical memory structure 140 and the second vertical memory structure 150 includes, for example, the following steps.

[0030]

As shown in FIGS. 3A-3B, a recess 310 is formed, and the recess 310 passes through the conductive layer 120 and the insulating layer 130 and stops on the substrate 110. As shown in Fig. 3A, the groove 310 has an elliptical cross section, and the major axis W4 (maximum diameter) of the ellipse is, for example, about 150 nm.

[0031]

Fig. 4B is a schematic cross-sectional view taken along line 4B-4B' of Fig. 4A. As shown in FIGS. 4A-4B, a memory structure material layer 480 is formed in the recess 310 to form a channel material layer 490 on the memory structure material layer 480. The memory structure material layer 480 includes a blocking material layer 481, a memory storage material layer 483, and a tunneling material layer 485. The barrier material layer 481 is formed on the conductive layer 120, and the memory storage material layer 483 is formed on the barrier material layer 481. A tunneling material layer 485 is formed on the memory storage material layer 483. In the embodiment, the barrier material layer 481 and the tunneling material layer 485 are, for example, a ruthenium oxide layer, the memory storage material layer 483 is, for example, a tantalum nitride layer, and the channel material layer 490 is, for example, a polysilicon layer.

[0032]

Fig. 5B is a cross-sectional view taken along line 5B-5B' of Fig. 5A, and Fig. 5C is a cross-sectional view taken along line 5C-5C' of Fig. 5A. As shown in FIGS. 5A-5C, an oxide material layer 510 is formed on the channel material layer 490 and filled in the recess 310, and the formed oxide material layer 510 has an air gap 510a therein.

[0033]

6B is a cross-sectional view taken along line 6B-6B' of FIG. 6A, FIG. 6C is a cross-sectional view taken along line 6C-6C' of FIG. 6A, and FIG. 6D is a view along line 6A. A schematic cross-sectional view of the section line 6D-6D'. As shown in FIGS. 6A to 6D, a portion of the conductive layer 120, a portion of the insulating layer 130, a portion of the memory structure material layer 480, a portion of the channel material layer 490, and a portion of the oxide material layer 510 are removed along the short-axis direction R1 of the elliptical cross-section. To form a trench T.

[0034]

As shown in FIGS. 6A-6C, a portion of the conductive layer 120, a portion of the insulating layer 130, a portion of the memory structure material layer 480, a portion of the channel material layer 490, and a portion of the oxide material layer 510 are removed, for example, by an etching process. After etching, as shown in FIG. 6B, a portion of the memory structural material layer 480, a portion of the channel material layer 490, and a portion of the oxide material layer 510 within the recess 310 are etched away to expose the substrate 110. After etching, as shown in FIG. 6C, a portion of the conductive layer 120 and a portion of the insulating layer 130 outside the recess 310 are etched away to expose one of the bottom layers 130b of the insulating layers 130. In other words, due to the presence of the air gap 510a, the material within the recess 310 is etched at a faster rate, and thus the depth of the etch is deeper, and this region of the formed trench T is connected to the substrate 110. The material outside the groove 310 does not have the air gap 510a, is etched at a slower speed, and thus the etching depth is shallow, and the region of the formed trench T reaches only the bottommost layer 130b of the insulating layer 130, and is not in contact. To the substrate 110. So far, a plurality of memory structure layers 180 are formed.

[0035]

Due to the formation of the trench T, a horizontal C-shaped cross-section of the subsequent first vertical memory structure 140 and the second vertical structure 150 can be formed, thereby enabling the final fabricated semiconductor structure to have the aforementioned advantages and advantages.

[0036]

7B is a cross-sectional view taken along line 7B-7B' of FIG. 7A, FIG. 7C is a cross-sectional view taken along line 7C-7C' of FIG. 7A, and FIG. 7D is a view along line 7A. A schematic cross-sectional view of the section line 7D-7D'. As shown in FIGS. 7A-7D, after the trench T is formed, the epitaxial structure 170 is formed on the substrate 110 in the recess 310. That is, the epitaxial structure 170 is formed between the insulating trench 160 and the substrate 110 which will be formed later.

[0037]

In the embodiment, the epitaxial structure 170 is fabricated by a selective epitaxial growth (SEG) process, so that the region in which the epitaxial structure 170 grows has high selectivity and is formed on a surface having a seed crystal, for example, having a single crystal. The surface of the substrate 110 of the germanium structure is not formed on other materials such as an oxide layer or a polysilicon layer.

[0038]

8B is a cross-sectional view taken along line 8B-8B' of FIG. 8A, FIG. 8C is a cross-sectional view taken along line 8C-8C' of FIG. 8A, and FIG. 8D is a view along line 8A. A schematic cross-sectional view of the section line 8D-8D'. As shown in FIGS. 8A to 8D, an insulating material 810 is filled in the trench T, and at this time, the insulating trench 160 is formed.

[0039]

9B is a cross-sectional view taken along line 9B-9B' of FIG. 9A, FIG. 9C is a cross-sectional view taken along line 9C-9C' of FIG. 9A, and FIG. 9D is a view along line 9A. A schematic cross-sectional view of the section line 9D-9D'. As shown in FIGS. 9A-9D, the channel material layer 490 exposed outside the trench T is removed by a chemical mechanical polishing process to form a plurality of channel layers 190.

[0040]

So far, as shown in FIGS. 9A-9D, a plurality of first vertical memory structures 140 and a plurality of second vertical memory structures 150 are formed, and the first vertical memory structures 140 and the second vertical memory structures 150 pass through the conductive layer 120 and are insulated. Layer 130, first vertical memory structure 140 has a first horizontal C-shaped cross-section, and second vertical memory structure 150 has a second horizontal C-shaped cross-section.

[0041]

Furthermore, after the chemical mechanical polishing process, the oxide material layer 510 and the insulating material 810 remaining in the trench T form an insulating trench 160 formed on the substrate 110 and located in the first vertical memory structure 140 and Between two vertical structures 150.

[0042]

Moreover, the channel layers 190 of the respective vertical memory structures are spaced apart from each other along the Y direction, and the formed epitaxial structure 170 is located between the insulating trenches 160 and the substrate 110, the first vertical memory structure 140 and the second vertical memory. The structure 150 is electrically connected to the substrate 110 via the epitaxial structure 170. In detail, the channel layer 190 of the first vertical memory structure 140 and the channel layer 190 of the second vertical memory structure 150 are electrically connected to the substrate 110 via the epitaxial structure 170.

[0043]

10B is a schematic cross-sectional view taken along line 10B-10B' of FIG. 10A. As shown in FIGS. 10A-10B, an insulating material layer 991 is formed on the first vertical memory structure 140 and the second vertical memory structure 150.

[0044]

11B is a schematic cross-sectional view along section line 11B-11B' of FIG. 11A. As shown in FIGS. 11A-11B, the first contact structure 240 is electrically connected to the first vertical memory structure 140, and the second is formed. The contact structure 250 is electrically connected to the second vertical memory structure 250. In the embodiment, for example, a contact hole is formed in the insulating material layer 991, and then a conductive material is filled in the contact hole to form the first contact structure 240 and the second contact structure 250 in the insulating layer 191.

[0045]

Next, referring to FIGS. 1A to 1E, an insulating layer 193 is formed on the insulating layer 191, and the first bit line BL1 and the second bit line BL2 are formed in the insulating layer 193. The first bit line BL1 is electrically connected to the first contact structure 240, and the second bit line BL2 is electrically connected to the second contact structure 250. Thus far, the semiconductor structure 100 shown in FIGS. 1A to 1E is formed.

[0046]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor structure

140‧‧‧First vertical memory structure

150‧‧‧Second vertical memory structure

240‧‧‧First contact structure

250‧‧‧Second contact structure

BL1‧‧‧ first bit line

BL2‧‧‧ second bit line

1B-1B', 1C-1C', 1D-1D', 1E-1E'‧‧‧ hatching

Claims (10)

[Item 1] A semiconductor structure comprising:
a substrate;
a plurality of conductive layers and a plurality of insulating layers are formed on the substrate, wherein the conductive layers and the insulating layers are interlaced on the substrate;
a first vertical memory structure and a second vertical memory structure are formed on the substrate through the conductive layer and the insulating layer, wherein the first vertical memory structure has a first horizontal C-shaped profile, the first The two vertical memory structures have a second horizontal C-shaped cross-section; and an isolation trench formed on the substrate between the first vertical memory structure and the second vertical structure.
[Item 2] For example, the semiconductor structure described in claim 1 of the patent scope further includes:
An epitaxial structure is formed between the insulating trench and the substrate, wherein the first vertical memory structure and the second vertical memory structure are electrically connected to the substrate via the epitaxial structure.
[Item 3] The semiconductor structure of claim 1, wherein the first vertical memory structure and the second vertical memory structure respectively comprise:
A memory structure layer, including:
a blocking layer formed on the conductive layers;
a memory storage layer formed on the barrier layer; and a tunneling layer formed on the memory storage layer; and a channel layer formed on the memory structure layer, wherein the channel layer is a polysilicon layer.
[Item 4] For example, the semiconductor structure described in claim 1 of the patent scope further includes:
a first contact structure electrically connected to the first vertical memory structure;
a second contact structure electrically connected to the second vertical memory structure;
a first bit line electrically connected to the first contact structure; and a second bit line electrically connected to the second contact structure;
The pattern of the first horizontal C-shaped cross section of the first vertical memory structure and the pattern of the second horizontal C-shaped cross section of the second vertical memory structure are bilaterally symmetrical with respect to the insulating trench.
[Item 5] The semiconductor structure of claim 1, wherein the first vertical memory structure and the second vertical memory structure directly contact the insulating trench, and the insulating trench has a width of 40 to 50 nanometers (nm). The first vertical memory structure and the second vertical memory structure are separated by the width of the insulating trench, and the first horizontal C-shaped cross section and the second horizontal C-shaped cross-section have a size of about 50-80 Nano.
[Item 6] A method of fabricating a semiconductor structure, comprising:
Providing a substrate;
Forming a plurality of conductive layers and a plurality of insulating layers on the substrate, wherein the conductive layers and the insulating layers are alternately stacked on the substrate;
Forming a first vertical memory structure and a second vertical memory structure on the substrate, wherein the first vertical memory structure and the second vertical memory structure pass through the conductive layers and the insulating layers, the first vertical memory The structure has a first horizontal C-shaped cross section, the second vertical memory structure has a second horizontal C-shaped cross section; and an insulating trench is formed on the substrate and located in the first vertical memory structure and the second vertical structure between.
[Item 7] The method for manufacturing a semiconductor structure as described in claim 6 further includes:
An epitaxial structure is formed between the insulating trench and the substrate, wherein the first vertical memory structure and the second vertical memory structure are electrically connected to the substrate via the epitaxial structure.
[Item 8] The method of fabricating a semiconductor structure according to claim 6, wherein the forming the first vertical memory structure, the second vertical memory structure, and the insulating trench comprises:
Forming a groove through the conductive layer and the insulating layer and stopping on the substrate, wherein the groove has an elliptical cross section;
Forming a memory structural material layer in the recess;
Forming a channel material layer on the memory structure material layer;
Forming an oxide material layer on the channel material layer and filling the groove, wherein the oxide material layer has an air gap therein;
Removing a portion of the conductive layer, a portion of the insulating layer, a portion of the memory structural material layer, a portion of the channel material layer and a portion of the oxide material layer to form a trench along a minor axis direction of the elliptical cross section; And filling an insulating material into the trench to form the insulating trench.
[Item 9] The method for manufacturing a semiconductor structure according to claim 8 of the patent application, further comprising:
After forming the trench, forming an epitaxial structure between the insulating trench and the substrate; and removing the channel material layer exposed outside the trench by a chemical mechanical polishing process;
Wherein the conductive layer, a portion of the insulating layer, a portion of the memory structure material layer, a portion of the channel material layer and a portion of the oxide material layer are removed by an etching process, and a portion of the memory structure material in the recess a layer, a portion of the channel material layer and a portion of the oxide material layer are etched away to expose the substrate, and a portion of the conductive layers and portions of the insulating layers are etched away to expose one of the insulating layers Lowest level.
[Item 10] The method for manufacturing a semiconductor structure as described in claim 6 further includes:
Forming a first contact structure electrically connected to the first vertical memory structure;
Forming a second contact structure electrically connected to the second vertical memory structure;
Forming a first bit line electrically connected to the first contact structure; and forming a second bit line electrically connected to the second contact structure.