CN211789012U

CN211789012U - Semiconductor memory device with a plurality of memory cells

Info

Publication number: CN211789012U
Application number: CN202020708455.XU
Authority: CN
Inventors: 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-04-30
Filing date: 2020-04-30
Publication date: 2020-10-27
Anticipated expiration: 2030-04-30

Abstract

The utility model discloses a semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate; a word line structure located in the semiconductor substrate and extending in a first direction; a bit line structure located above the word line structure and extending across the word line structure in a second direction; a spacer structure located directly above the word line structure and between the bit line structures, wherein the spacer structure has an upper half portion and a lower half portion, the upper half portion has a width greater than the lower half portion, and a gap is formed inside the spacer structure; and the contact structure is positioned in a space defined by the bit line structure and the spacer structure and is connected with the semiconductor substrate.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

Embodiments of the present disclosure relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a spacer structure between memory cells.

Background

Semiconductor devices have been widely used in the electronics industry due to their small size, versatility, and/or low manufacturing cost characteristics. The semiconductor device may be classified into a semiconductor memory device storing logic data, a semiconductor logic device processing an operation of the logic data, and a hybrid device having functions of both the memory device and the logic device.

The semiconductor devices may include vertically stacked layer structure patterns and contact plugs or interconnection structures electrically connecting the stacked patterns to each other. As semiconductor devices continue to shrink and increase integration, the spacing between such patterns and/or the spacing between patterns and contact plugs also continues to decrease. As such, parasitic capacitance between patterns and/or between a pattern and a contact plug increases, and contact resistance between a pattern and an interconnect structure also increases, resulting in deterioration of performance of a semiconductor device, such as a reduction in operating speed.

SUMMERY OF THE UTILITY MODEL

In view of the conventional problems encountered in the semiconductor device, the present invention provides a novel semiconductor memory device, which is characterized in that the spacer structure between the memory cells has a special shape, the contact area between the memory cells and the active region can be increased to reduce the contact resistance, and the spacer structure has a void therein to reduce the parasitic capacitance.

One of the objectives of the present invention is to provide a semiconductor memory device, including a semiconductor substrate, a word line structure, a bit is in the semiconductor substrate and toward the first direction extension, a bit line structure, a bit is in on the word line structure and toward the second direction extension stride over the word line structure, a spacer structure, a bit is directly over the word line structure and between the bit line structure, wherein the spacer structure has an upper half portion and a lower half portion, the width of the upper half portion is greater than the lower half portion, and the inside of the spacer structure has a space and a contact structure, located the bit line structure with in the space defined by the spacer structure and with the semiconductor substrate is connected.

Another aspect of the present invention is to provide a method for fabricating a semiconductor memory device, including providing a semiconductor substrate, forming a word line structure extending in a first direction in the semiconductor substrate, forming a bit line structure extending across the word line structure in a second direction on the word line structure, forming a spacer structure directly above the word line structure and between the bit line structure, wherein the spacer structure has an upper half portion and a lower half portion, the width of the upper half portion is greater than the lower half portion, and the inside of the spacer structure has a cavity and a contact structure formed in a space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate.

These and other objects of the present invention will become more apparent to those skilled in the art after a reading of the following detailed description of the preferred embodiment illustrated in the various figures and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings depict some embodiments of the invention and, together with the description, serve to explain its principles.

In these figures:

fig. 1A, 2A, 3A, 4A, 5A and 6A illustrate plan views of a method of manufacturing a semiconductor memory device according to an example embodiment;

FIG. 1B, FIG. 2B, FIG. 3B, FIG. 4B, FIG. 5B and FIG. 6B are sectional views taken along line I-I' of FIGS. 1A to 6A, respectively;

fig. 1C, 2C, 3C, 4C, 5C, and 6C are sectional views taken along the line ii-ii' of fig. 1A to 6A, respectively;

FIGS. 7-11 are flowcharts illustrating steps for fabricating a spacer structure having a particular cross-sectional profile according to an exemplary embodiment; and

fig. 12-16 are cross-sectional views illustrating spacer structures having special cross-sectional profiles according to other exemplary embodiments.

It should be noted that all the figures in this specification are schematic in nature, and that for the sake of clarity and convenience, various features may be shown exaggerated or reduced in size or in proportion, where generally the same reference signs are used to indicate corresponding or similar features in modified or different embodiments.

Wherein the reference numerals are as follows:

1a, a first doping area; 1b, a second doped region; 100. a semiconductor substrate; 101. a device isolation layer; 103. a gate insulating layer; 105. a gate hard mask pattern; 107. an insulating interlayer; 109. a recessed region; 111. a polysilicon pattern; 113. a silicide pattern; 115. a metal pattern; 117. a hard mask pattern; 119. a bit line contact pattern; 121. a bit line contact spacer; 123. a partition wall; 125. an insulating layer; 127. a pattern of spacers; 127a, the upper half part; 127b, lower half; 127c, a third site; 129. a sacrificial layer; 131. a composite mask; 133. a sacrificial pattern; 133a, upper half sacrificial pattern; 133b, lower half sacrificial pattern; 135. a void; 137. an organic dielectric layer; 139. a sacrificial layer; 141. a contact hole; 143. a storage node contact; 145. an outer layer; 147. an inner layer; ACT, active region; d1, first direction; d2, second direction; d3, third direction; w1, W2, width; WL, word line.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, which will reference features described in order for a reader to understand and achieve a technical effect. It will be understood by the reader that the description herein is by way of illustration only and is not intended to be limiting. The various embodiments of the disclosure and the various features of the embodiments that are not mutually inconsistent can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the disclosure may be apparent to those skilled in the art without departing from the spirit and scope of the disclosure, and are intended to be included within the scope of the disclosure.

It should be readily understood by the reader that the meaning of "on …", "above …" and "above …" in this case should be read in a broad manner such that "on …" not only means "directly on" something "but also includes the meaning of" on "something with intervening features or layers therebetween, and" on … "or" above … "not only means" on "something" or "above" but also includes the meaning of "on" or "above" something with no intervening features or layers therebetween (i.e., directly on something).

Moreover, spatially relative terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures.

As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

In the drawings of this specification, fig. 1A, 2A, 3A, 4A, 5A, and 6A are plan views illustrating a method of manufacturing a semiconductor memory device according to an example embodiment of the present invention. Fig. 1B, 2B, 3B, 4B, 5B, and 6B are cross-sectional views taken along lines i-i' of fig. 1A to 6A, respectively, which cut through the long axis of an entire active region. Fig. 1C, 2C, 3C, 4C, 5C, and 6C are cross-sectional views taken along the line ii-ii' of fig. 1A to 6A, respectively, which cuts through a plurality of word lines and predetermined locations of memory cells. Fig. 7-11 are flow charts illustrating steps for fabricating a spacer structure with a special cross-sectional profile according to an exemplary embodiment. Fig. 12-14 are cross-sectional views illustrating a spacer structure with a special cross-sectional profile according to other exemplary embodiments.

Please refer to fig. 1A, fig. 1B and fig. 1C. First, a semiconductor substrate 100 is provided, and a device isolation layer 101 defining an active region ACT is formed in the semiconductor substrate 100. The semiconductor substrate 100 may include a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. The device isolation layer 101 may be formed by performing a photolithography process on the semiconductor substrate 100 to form respective separated active regions ACT, and filling a recess between the active regions ACT with an isolation material, such as silicon oxide. In an example, the active area ACT has a stripe shape in a plan view and has a long axis extending to the third direction D3. The plurality of active regions ACT are uniformly arranged in a staggered manner on a plane.

Next, a plurality of word lines WL are formed in the semiconductor substrate 100, extending in the first direction D1. The included angle between the first direction D1 and the third direction D3 is preferably between 45 degrees and 90 degrees. In an example, the active region ACT and the device isolation layer 101 may be patterned via a photolithography process to form gate recess regions 102 extending in the first direction D1, and gate insulating layers 103 are respectively formed in the gate recess regions 102. Thereafter, word lines WL positioned on the gate insulating layers 103 may be respectively formed in the corresponding gate recess regions 102. The material of the word line WL may be a metal, such as tungsten, aluminum, titanium, and/or tantalum. The bottom surface of the gate recess region 102 may be set higher than the bottom surface of the device isolation layer 101. The top surface of the word line WL may be set lower than the top surface of the device isolation layer 101. After the word line WL is formed, a gate hard mask pattern 105, such as a silicon nitride layer, is then formed in the gate recess region 102 remaining on the word line WL.

After the gate hard mask pattern 105 is formed, first and second impurity-doped regions 1a and 1b, which may be formed through an ion implantation process and may include dopants of a conductivity type opposite to that of the active region ACT, may be then formed in the active region ACT on both sides of the word line WL, respectively. The bottom surfaces of the first and second doping regions 1a and 1b may be positioned at a predetermined depth downward from the top surface of the active region ACT. The first doped region 1a is located in the middle of the active region ACT, which is then electrically connected to the bit line. The second doping regions 1b are located at both ends of the active region ACT, which are then electrically connected to the storage node contacts. In addition, an insulating interlayer 107 may be formed on the surface of the semiconductor substrate 100 to isolate the active region ACT from the components above. The insulating interlayer 107 may be formed of a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, and/or a silicon oxynitride layer, and the like.

According to an example, the semiconductor substrate 100 and the insulating interlayer 107 may be patterned via a photolithography process to form the recess region 109 exposing the first doping region 1 a. In one example, the recessed region 109 can be elliptical in shape. In addition, the concave regions 109 may be uniformly arranged in a staggered manner on a plane. In some embodiments, the recess region 109 may be formed by an anisotropic etching process. In this case, a portion of the device isolation layer 101 and a portion of the gate hard mask pattern 105 adjacent to the first doping region 1a may be etched together. The bottom surface of the recess region 109 may be higher than the bottom surface of the first doping region 1a (as indicated by a dotted line), and a portion of the device isolation layer 101 and a portion of the gate hard mask pattern 105 may be exposed from the recess region 109.

Please refer to fig. 2A, 2B and 2C. After the active region ACT is defined and the word lines WL, the insulating interlayer 107, and the like are formed, the bit line structure BLS extending in the second direction D2 is formed on the semiconductor substrate 100. The angle between the second direction D2 and the third direction D3 is preferably between 0 degrees and 45 degrees, and the second direction D2 is preferably orthogonal to the first direction D1. The step of forming the bit line structure BLS may include: a polysilicon layer, a silicide layer, a metal layer and a hard mask layer are sequentially formed on the semiconductor substrate 100, wherein the polysilicon layer fills the recess 109, and then the hard mask layer, the metal layer, the silicide layer and the polysilicon layer are sequentially etched using the bit line mask pattern as an etch mask, thereby forming the bit line structure BLS as shown in fig. 2B. The bit line mask pattern may be removed after the etching process. In an example, the polysilicon layer may be a doped polysilicon layer, and the metal layer may be a tungsten layer, an aluminum layer, a titanium layer, a tantalum layer, or the like. As such, each bitline structure BLS may include, in order from bottom to top, a stacked polysilicon pattern 111, a silicide pattern 113, a metal pattern 115, and a hard mask pattern 117. A portion of the polysilicon pattern 111 is formed in the recess 109 as a bit line contact pattern 119 directly contacting the first impurity region 1 a. In addition, the minimum width of the recess region 109 may be greater than the width of each bit line structure BLS. Sidewalls of the polysilicon patterns 111 of the bit line structure BLS may be spaced apart from sidewalls of the corresponding recess regions 109.

Please refer to fig. 3A, 3B and 3C. After the bit line structures BLS are formed, an insulating structure is formed on the sidewalls of each bit line structure BLS to prevent the bit line structures BLS from being electrically connected to surrounding components. The insulating structure may include a lower portion formed in the recess 109 and an upper portion covering a sidewall of the bit line structure BLS. More specifically, in one example, the step of forming the insulating structure may include depositing an insulating stack that fills the recess 109 and conformally covers the bit line structure BLS. The insulating stack may include a first nitride layer, an oxide layer, a second nitride layer, and the like, which are sequentially stacked. When anisotropically etching the insulating stack, the intervening oxide layer may act as an etch stop layer, such that the oxide layer and the second nitride layer may remain locally in the recessed region 109 to form the bitline contact spacer 121. The bit line contact spacer 121 may be formed of an insulating material having an etch selectivity with respect to the insulating interlayer 107. For example, the bit line contact spacer 121 may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer. For the upper half of the insulating structure, it may form spacers 123 on the sidewalls of the bit line structure BLS, and form an insulating layer 125 on the spacers 123 and the insulating interlayer 107 conformally. The spacers 123 may be formed by depositing a spacer and performing an anisotropic etch, and as such, may be formed of a material that is selective to the dielectric structure in the recess 109, such as silicon oxide. The material of the insulating layer 125 has an etch selectivity with respect to both the spacer 123 and the insulating interlayer 107, such as a silicon nitride layer and/or a silicon oxynitride layer.

Please refer to fig. 4A, 4B and 4C. After the formation of the insulating layer 125 and the bitline contact spacer 121, a spacer structure is formed to define a memory cell region between the bitline BLS and the wordline WL. As shown in fig. 4A, a plurality of spacer structures 127 are formed in the space between the bit line BLS and the bit line BLS. In the illustrated example, the spacer structure 127 is located directly above the word line WL and also extends in the first direction D1, and the spacer structure 127 contacts the insulating layer 125 on the sidewalls of the bit line BLS, such that the spacer structure 127 is spaced apart from the bit line BLS and defines a plurality of spaces on the insulating layer 125, each of the spaces corresponding to a memory cell region and being located above the second doped region 1b of the active region ACT, wherein a storage node contact is to be formed. In one example, more particularly, the spacer structures 127 may have a particular cross-sectional profile. As shown, in the present invention, the spacer structure 127 has an upper half portion 127a and a lower half portion 127b, which are distinct, and is characterized in that the width of the upper half portion 127a of the spacer structure 127 is greater than the width of the lower half portion 127b, and the width thereof is tapered from the surface of the sacrificial layer 129 to the insulating layer 125. Moreover, the cross-sectional curves of the upper half portion 127a and the lower half portion 127b of the spacer structure 127 are not smooth curves, and there is a discontinuous state at the junction of the two, so that the upper half portion and the lower half portion can be clearly distinguished.

Such a special cross-sectional profile of the spacer structure 127 may be achieved by adjusting the parameters of the etching process. In one example, as shown in fig. 7-11, steps for fabricating the spacer structure 127 are illustrated: (1) first, as shown in fig. 7, a sacrificial layer 129 is formed on the insulating layer 125, and a composite mask 131 having spacer structure patterns is formed on the sacrificial layer 129, wherein the sacrificial layer 129 may be formed using a spin-on hard mask (S0H) material, such as S0H silicon oxide, and the composite mask 131 may sequentially include an Organic Dielectric Layer (ODL), an anti-reflective coating (ARC), and a photoresist layer (PR) having spacer structure patterns defined therein from bottom to top;

(2) next, as shown in fig. 8, a first etching process is performed by using the composite mask 131 and the bit line structure BLS (fig. 4B) as an etching mask to etch the sacrificial layer 129, so as to form an upper half sacrificial pattern 133a in the sacrificial layer 129, where the upper half sacrificial pattern 133a is a pattern of the upper half portion 127a of the spacer structure;

(3) next, as shown in fig. 9, an etching parameter is adjusted, for example, an etching gas and/or the etching parameter is adjusted to have a stronger anisotropic property, and then a second etching process is performed to form a lower half sacrificial pattern 133b in the sacrificial layer 129, where the lower half sacrificial pattern 133b is a pattern of the lower half 127b of the spacer structure, and the upper half sacrificial pattern 133a and the lower half sacrificial pattern 133b together form a sacrificial pattern 133. Because the lower sacrificial pattern 133b is formed by etching the upper sacrificial pattern 133a and then by using an etching process having strong anisotropy, the width of the formed lower sacrificial pattern 133b is smaller than that of the upper sacrificial pattern 133a, and the joint of the two sacrificial patterns has a discontinuous state;

(4) next, as shown in fig. 10, the composite mask 131 is removed, and the sacrificial pattern 133 is filled with a spacer material, so as to form a spacer structure 127. At this time, a void 135 may be formed inside the spacer structure 127, especially in the lower half portion 127b of the spacer structure 127, and the presence of the void 135 may increase the insulation property of the spacer structure 127, thereby reducing the parasitic capacitance of the entire device. Voids 135 may be achieved by using spacer materials with poor hole-filling properties. For example, spacer structures 127 may be formed of an insulating material having etch selectivity with respect to sacrificial layer 129. For example, the spacer structure 127 may be formed of silicon nitride, and the sacrificial layer 129 may be formed of silicon oxide or silicon oxynitride. Then, another organic dielectric layer 137 is formed on the spacer material to provide a flat surface for the subsequent back etching process;

(5) finally, as shown in fig. 11, an etch-back process is performed to remove the organic dielectric layer 137 and the spacer material on the surface of the sacrificial layer 129, thereby separating the respective spacer structures 127 and completing the fabrication of the spacer structures 127.

The spacer structure with the special cross-sectional shape can also have other variants. As shown in fig. 12, another sacrificial layer 139 may be formed on the surface of the sacrificial layer 129, and an uppermost third portion 127c of the spacer structure 127 may be formed therein, wherein the width of the third portion 127c is smaller than the width of the lower upper half portion 127 a. The lateral etching rate of the material of the sacrificial layer 139 is preferably lower than that of the material of the sacrificial layer 129, so that the width of the sacrificial layer 139 is smaller than that of the upper portion 127a formed therebelow due to the lower lateral etching rate during the process of forming the sacrificial pattern by the etching process.

In addition, as shown in fig. 13, on the basis of not forming an additional sacrificial layer, portions of the spacer structure 127 with different widths may be formed directly in different stages of the same etching process by adjusting etching gas and/or parameters. For example, the third portion 127c is formed by initially using a more anisotropic etching gas and/or parameter setting, then the etching gas and/or parameter is adjusted to have a more isotropic property to form the upper portion 127a, such that the portion has a larger width, and finally the etching gas and/or parameter is adjusted back to the original more anisotropic setting to form the lower portion 127 b.

In other examples, as shown in fig. 14, the spacer structure 127 may also be fabricated with voids 135 in both the top portion 127a and the bottom portion 127b, again by using spacer materials with poor hole-filling efficiency. As such, almost all of the spacer structure 127 has voids therein, which may further reduce parasitic capacitance.

In other examples, as shown in fig. 15, the spacer structure 127 may also be fabricated to have a double-layer structure, such as an outer layer 145 on the sidewall of the spacer structure 127 and an inner layer 147 filling the inside. In one example, the outer layer structure may be formed by forming a conformal layer on the surface of the sacrificial pattern 133 and removing the composite mask 131 in fig. 9 and then etching back. Alternatively, as shown in fig. 16, the outer layer 145 may be formed after the contact hole 141 is formed and before the storage node contact 143 is formed at the stage of fig. 5B, by forming the conformal outer layer 145 on the surface of the contact hole 141, and then etching back the bottom surface of the outer layer 145 to expose the active region (the second doped region 1B), such that the outer layer 145 is formed only on the sidewall of the spacer structure 127. The material of the outer and

inner layers

145, 147 of the spacer structure 127 may be formed of an insulating material having etch selectivity with respect to the sacrificial layer 129. For example, the material of the outer layer of the spacer structure 127 may be formed of silicon oxynitride, the material of the inner layer 147 may be formed of silicon nitride, and the sacrificial layer 129 may be formed of silicon oxide.

Please refer to fig. 5A, 5B and 5C. After the formation of the spacer structure 127, the sacrificial layer 129 may be removed by an etch recipe having an etch selectivity with respect to the spacer structure 127 and the insulating layer 125, thereby defining a contact region between the bitline structure BLS and the spacer structure 127 for landing a storage node, however, since the active region (the second doped region 1b) under the contact region is covered by the insulating interlayer 107 and the insulating layer 125, the insulating interlayer 107 and the insulating layer 125 must be removed to expose the active region. Accordingly, the exposed insulating interlayer 107 and the insulating layer 125 may be removed by performing an anisotropic etching using the spacer structures 127 and the bit line structures BLS as an etching mask, thereby forming the contact holes 141. This anisotropic etching also removes portions of the second impurity region 1b, the gate hard mask pattern 105, and the device isolation layer 101, so that the bottom surface of the contact hole 141 may be lower than the top surface of the semiconductor substrate 100.

As can be seen from fig. 5B and 5C, since the spacer structure 127 has a cross-sectional shape with a wide top and a narrow bottom in the present invention, the contact hole 141 separated by the spacer structure has a corresponding cross-sectional shape with a narrow top and a wide bottom, as shown in the figure, W1 is larger than W2. This feature has the advantage that the contact width subsequently formed in the contact hole 141 is larger than that of a contact formed by a conventional technique, which can effectively reduce the contact resistance between the memory node and the connected active region, and improve the performance of the device. Similarly, in the variant embodiments of fig. 12 and 13, the feature of the spacer structure 127 having the narrower third portion 127c also increases the contact area with the overlying component, such as a capacitor, thereby reducing the contact resistance and improving the performance of the device.

Please refer to fig. 6A, 6B and 6C. After the contact holes 141 are formed, storage node contacts 143 are next formed in the contact holes 141, respectively. In an example, a top surface of the storage node contact 143 may be lower than a top surface of the hard mask pattern 117 of the bit line structure BLS. The storage node contact 143 may be formed through the following process: a conductive layer is deposited to fill the contact hole 141, a planarization process is performed to remove the conductive layer over the top surfaces of the bit line structure BLS and the spacer structure 127, and an etch-back process is performed to recess the top surface of the conductive layer, thereby forming the storage node contact 143. The storage node contacts 143 may include, for example, a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, and/or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), and/or a metal-semiconductor alloy (e.g., a metal silicide).

In some other embodiments, the storage node contact 143 may include, in order from bottom to top, a polysilicon layer, a metal silicide layer, and a landing pad, on which respective corresponding capacitors are connected as a storage node. Since the above portions are not the focus of the present invention, the detailed description of these portions will be omitted herein in order to avoid obscuring the focus of the present invention.

In accordance with the foregoing illustrative embodiments, the present invention provides a novel semiconductor memory device including a semiconductor substrate, wordline structures located in the semiconductor substrate and extending in a first direction, bitline structures located above the wordline structures and extending in a second direction across the wordline structures, spacer structures located directly above the wordline structures and between the bitline structures. The semiconductor memory device is characterized in that the spacer structure is provided with an upper half part and a lower half part, the width of the upper half part is larger than that of the lower half part, a gap and a contact structure are arranged in the spacer structure, and the contact structure is positioned in a space defined by the bit line structure and the spacer structure and is connected with the semiconductor substrate.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, comprising:

a semiconductor substrate;

a word line structure located in the semiconductor substrate and extending in a first direction;

a bit line structure located above the word line structure and extending across the word line structure in a second direction;

the spacer structure is positioned right above the word line structure and between the bit line structures, wherein the spacer structure is provided with an upper half part and a lower half part, the width of the upper half part is greater than that of the lower half part, and a cavity is arranged inside the spacer structure; and

and the storage node contact is positioned in a space defined by the bit line structure and the spacer structure and is connected with the semiconductor substrate.

2. The semiconductor memory device of claim 1, wherein the width of the spacer structure tapers from top to bottom.

3. The semiconductor memory device of claim 1, wherein the upper portion and the lower portion of the spacer structure are discontinuous in cross-section.

4. The semiconductor memory device of claim 1, wherein the void is in both the upper and lower portions of the spacer structure.

5. The semiconductor memory device of claim 1, wherein the spacer structure further comprises a third portion located on the upper half, the third portion having a width less than a width of the upper half.

6. The semiconductor memory device of claim 1, wherein an insulating layer is further provided between the spacer structure and the bit line structure.

7. The semiconductor memory device according to claim 6, wherein a gate hard mask layer and the insulating layer are further provided between the spacer structure and the word line.

8. The semiconductor memory device of claim 1, wherein the spacer structure has an outer layer and an inner layer, the outer layer is made of silicon nitride oxide, and the inner layer is made of silicon nitride.