CN114678362A

CN114678362A - Dynamic random access memory

Info

Publication number: CN114678362A
Application number: CN202210286521.2A
Authority: CN
Inventors: 冯立伟; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2022-03-22
Filing date: 2022-03-22
Publication date: 2022-06-28

Abstract

The invention discloses a dynamic random access memory, which comprises a substrate, wherein the substrate comprises a first active region, a first isolation region, a second active region and a second isolation region which are continuously arranged along a first direction. The first bit line is located over the first active region. The second bit line is located on the second isolation region. The storage node contact structure is located between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region. The storage node contact structure of the present invention has a larger contact area with the top surface of the second active region, thereby reducing the contact resistance.

Description

Dynamic random access memory

Technical Field

The present invention relates to a dynamic random access memory, and more particularly, to a dynamic random access memory including a storage node contact structure.

Background

A Dynamic Random Access Memory (DRAM), which belongs to a volatile memory, includes an array area (array area) composed of a plurality of memory cells (memory cells) and a peripheral area (peripheral area) composed of a control circuit. Each memory cell is composed of a transistor (transistor) and a capacitor (capacitor) electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. The control circuit is addressable to each memory cell by Word Lines (WL) and Bit Lines (BL) extending across the array region and electrically connected to each memory cell to control access to data from each memory cell.

In order to reduce the size of the memory cell and manufacture the chip with higher integration density, the structure of the memory cell has been developed towards three-dimensional (three-dimensional), for example, embedded word line connection (buried word line) and stacked capacitor (stacked capacitor) are adopted. The stacked capacitor has the capacitor of the memory unit vertically over the substrate, and this can save the substrate area occupied by the capacitor and increase the height of the electrode plate of the capacitor to obtain even greater capacitance. At present, the stacked capacitor is electrically connected to a transistor formed in a substrate through a storage node contact structure (storage node contact structure). There is still a need in the art for a storage node contact structure that provides good electrical connection quality to ensure the performance of a dram.

Disclosure of Invention

It is therefore an objective of the claimed invention to provide a dynamic random access memory device, in which the contact area between the storage node contact structure and the substrate is large, so as to reduce the contact resistance and improve the performance of the dynamic random access memory device.

The dynamic random access memory provided by an embodiment of the invention includes a substrate, which includes a first active region, a first isolation region, a second active region and a second isolation region arranged continuously along a first direction. A first bit line on the first active region. A second bit line on the second isolation region. A storage node contact structure between the first bit line and the second bit line and in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

In another embodiment, a dynamic random access memory device includes a substrate including an active region between two isolation structures. Two buried word lines are located in the active region, dividing the active region into a middle portion and two end portions. A bit line on the intermediate portion. A storage node contact structure on the end portion, wherein the storage node contact structure includes a contact portion and a plug portion. The contact portion is in direct contact with a top surface of the end portion, a sidewall of the embedded word line, and a sidewall of the isolation structure. The plug portion is located on the contact portion, and has a width greater than a width of the contact portion.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 9 are schematic diagrams illustrating a dram at different stages during manufacturing according to an embodiment of the present invention, wherein fig. 1 and 4 are plan views. The left side drawings of fig. 2, 3, 5 to 9 are cross-sectional views along line AA 'of fig. 1 or 4, respectively, and the right side drawings of fig. 2, 3, 5 to 9 are cross-sectional views along line BB' of fig. 1 or 4, respectively.

FIG. 10 is a cross-sectional view of a DRAM according to another embodiment of the present invention.

Wherein the reference numerals are as follows:

10 substrate

12 active region

14 isolation structure

16 insulating layer

16a bottom surface

21 first insulating layer

22 second insulating layer

32 dielectric layer

42 storage node contact structure

43 base angle

44 base angle

45 bottom corner

102 conductive layer

104 insulating cap layer

106 gate insulation layer

202 semiconductor layer

204 metal layer

206 hard mask layer

12a first active region

12a1 middle part

12a2 end

12b second active region

12b' residue

14a first isolation region

14b second isolation region

16a bottom surface

42a contact part

42b plug part

42c contact pad portion

Area A1

Area A2

Cutting line AA

BB' tangent line

BC groove

BL bit line

BL1 first bit line

BL2 second bit line

Direction D1

Direction D2

Direction D3

E1 etching process

E2 etching process

L1 barrier layer

M1 Metal layer

R1 deep groove

S1 semiconductor layer

Lower part of S1D

S1T Upper part

SC storage node contact hole

SP spacer

SP1 first spacer

SP2 second spacer

Width of W1

Width of W2

WL buried word line

Detailed Description

In order that those skilled in the art will be able to more fully understand the present invention, the following description of the preferred embodiments of the present invention, taken together with the accompanying drawings, will provide a further understanding of the invention. It is to be understood that the embodiments described below may be implemented in various other forms of implementation, which may be substituted, recombined, or mixed with other features of various embodiments without departing from the spirit of the present invention.

Fig. 1 to 9 are schematic diagrams illustrating a dram according to an embodiment of the present invention during manufacturing, wherein fig. 1 and 4 are plan views, the left side illustration of fig. 2, 3, 5 to 9 is a cross-sectional view substantially along the line AA 'of fig. 1 or 4, and the right side illustration of fig. 2, 3, 5 to 9 is a cross-sectional view substantially along the line BB' of fig. 1 or 4. In order to simplify the illustration, the plan views of fig. 1 and 4 omit a part of the structure.

Referring to fig. 1 and 2, a substrate 10, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, is provided, but not limited thereto. Next, an isolation structure 14 is formed in the substrate 10, and a plurality of mutually parallel active regions 12 are defined in the substrate 10 by the isolation structure 14. The isolation structure 14 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen doped silicon carbon (NDC), a low-k dielectric material, such as Fluorinated Silica Glass (FSG), silicon carbon oxide (SiCOH), spin-on glass (spin-on glass), a porous low-k dielectric material (porous low-k dielectric material), an organic polymer dielectric material, or a combination thereof, but is not limited thereto. Active regions 12 each have a length extending along direction D1 and are arranged in an array along direction D2 and direction D3, where direction D2 and direction D3 are perpendicular to each other and direction D1 is different from direction D2 and direction D3. According to some embodiments of the invention, the angle between the direction D1 and the direction D3 may be between 30 degrees and 75 degrees. According to some embodiments of the present invention, a heavily doped region (not shown) may be formed in an upper half of each active region 12 for forming ohmic contacts with bit line contacts and storage node contact structures to be fabricated later. In other embodiments, a heavily doped region may be formed in the exposed active region 12 after forming the recess of the bit line contact (e.g., the recess BC shown in fig. 3) and the storage node contact hole (e.g., the storage node contact hole SC and the deep recess R1 in fig. 8), respectively.

After the isolation structures 14 and the active regions 12 are formed, an insulating layer 16 may be selectively formed on the substrate 10, a plurality of word line trenches (not shown) are formed through the insulating layer 16 and extending into the substrate 10, and the word line trenches are cut through the isolation structures 14 and the active regions 12, and the embedded word lines WL are formed in the word line trenches. The buried word lines WL extend along the direction D2, respectively, and are arranged in parallel along the direction D3. The buried word line WL may include a conductive layer 102 located at a lower portion of the word line trench, an insulating cap layer 104 located at an upper portion of the word line trench, and a gate insulating layer 106 located between the substrate 10 and the conductive layer 102 and the insulating cap layer 104. The conductive layer 102 may include a metal material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), a work function metal, or a compound, an alloy and/or a composite layer of the foregoing metal materials, but is not limited thereto. The insulating layer 16, insulating cap layer 104, and gate insulating layer 106 may each comprise a dielectric material, such as silicon oxide (SiO)₂) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high dielectric (high-k) constant dielectric materials, or combinations thereof, but is not limited thereto. According to some embodiments of the invention, the insulating layer 16 and the insulating cap layer104 may comprise the same material, such as silicon nitride (SiN). As shown in fig. 1 and 2, each active region 12 is divided into a middle portion 12a1 and two end portions 12a2 by two buried word lines WL. In order to more clearly describe the features of the present invention, the portions of the active region 12 and the isolation structure 14 that are cut through by the AA' cut are specifically defined herein as a first active region 12a, a first isolation region 14a, a second active region 12b, and a second isolation region 14b, and are indicated in the left side legend of fig. 1 and 2. In view of fig. 1, it should be clearly understood that the first active region 12a and the second active region 12b, which are indicated by the legend on the left side of fig. 2, are the middle portion and the end portion of two adjacent active regions 12, respectively.

Please refer to fig. 3. A mask layer (not shown) may be formed on the substrate 10, which may include a plurality of openings respectively exposing the middle portions 12a1 of the active regions 12, and then the substrate 10 is subjected to an etching process through the openings, so that the middle portion 12a1 of each active region 12 is etched to be recessed below the end portions 12a2 at both sides, and a groove BC is formed at the position of the middle portion 12a1 of each active region 12. As shown in the left-hand illustration of fig. 3, the groove BC is located substantially above the first active region 12a (which is the middle portion), and the top surface of the first active region 12a is recessed below the top surface of the second active region 12 b. A portion of the first isolation region 14a is also removed in the etching process to form a portion of the recess BC, so that a portion of the top surface of the first isolation region 14a is lower than the top surface of the second isolation region 14 b.

Please refer to fig. 4 and 5. After the mask layer is removed, a plurality of deposition processes may be performed to sequentially form the semiconductor layer 202, the metal layer 204 and the hard mask layer 206 on the substrate 10, and then a patterning process (e.g., photolithography and etching) is performed to remove the excess portions of the semiconductor layer 202, the metal layer 204 and the hard mask layer 206, thereby forming a plurality of bit lines BL on the substrate 10. The bit lines BL extend along the direction D3, respectively, and are arranged in parallel along the direction D2. The portion of the bit line BL passing through the recess BC (or called bit line contact) is in direct contact with and electrically connected to the middle portion 12a1 of the active region 12. The other portion of the bit line BL is separated and electrically isolated from the active region 12 by an insulating layer 16. The material of the semiconductor layer 202 of the bit line BL may include polysilicon, amorphous silicon, or other materialsSuitable semiconductor materials. The material of the metal layer 204 may include aluminum (Al), tungsten (W), copper (Cu), titanium aluminum (TiAl) alloy, or other suitable low resistance metal material. The hard mask layer 206 may comprise a dielectric material, which may comprise, for example, silicon oxide (SiO)₂) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but is not limited thereto. In some embodiments, an interface layer (not shown) may be included between the semiconductor layer 202 and the metal layer 204, such as a single-layer or multi-layer structure layer composed of titanium (Ti), tungsten silicide (WSi), tungsten nitride (WN), and/or other metal silicide or metal nitride, but not limited thereto. In order to more clearly describe the features of the present invention, the bit line BL on the first active region 12a in the left side illustration of fig. 5 is specifically defined as a first bit line BL1, and the bit line BL on the second isolation region 14b is defined as a second bit line BL 2.

Please refer to fig. 6. Then, deposition and etching processes are performed to form spacers SP on the sidewalls of the bit lines BL and fill the trenches BC with the spacers SP. According to some embodiments of the present invention, the spacer SP may include a multi-layer structure, for example, a first insulating layer 21 and a second insulating layer 22, wherein the first insulating layer 21 covers along the sidewall of the bit line BL and the surface of the groove BC, and the second insulating layer 22 is located on the first insulating layer 21 and fills the remaining space of the groove BC. The first insulating layer 21 and the second insulating layer 22 may each comprise a dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination thereof. According to an embodiment of the present invention, the first insulating layer 21 may include silicon nitride, and the second insulating layer 22 may include silicon oxide. In order to more clearly describe the features of the present invention, the spacer SP located on the sidewall of the first bit line BL1 in the left side illustration of fig. 6 is specifically defined as the first spacer SP1, and the spacer SP located on the sidewall of the second bit line BL2 is defined as the second spacer SP 2.

Please refer to fig. 7. A deposition process may then be performed to form a dielectric layer 32 on the substrate 10 to fill the gaps between the bit lines BL, and an etching process E1 (e.g., a dry etching process) may be performed to remove a portion of the dielectric layer 32 and a portion of the insulating layer 16 to form a trenchThe lines BL are between and through the dielectric layer 32 and the insulating layer 16 to expose the storage node contact holes SC at the surface of the active region 12. According to some embodiments of the invention, the etching process may use a fluorine (F) -containing gas as an etchant, such as tetrafluoromethane (CF)₄) Trifluoromethane (CHF)₃) Difluoromethane (C)₂F₂) Or a combination of the foregoing, but is not limited thereto. As shown in the left-side illustration of fig. 7, portions of the top surfaces of the first isolation region 14a and the second active region 12b are exposed from the bottom of the storage node contact hole SC. According to some embodiments of the present invention, the top surface of the second active region 12b exposed from the storage node contact hole SC may have an area a 1. As shown in the right-side diagram of fig. 7, two end portions 12a2 of the active region 12 are respectively exposed from different storage node contact holes SC.

Please refer to fig. 8. Next, another etching process E2 (e.g., a wet etching process) may be performed to etch the exposed portions of the active region 12 through the storage node contact holes SC, thereby forming a deep trench R1 below each storage node contact hole SC. The etching process E2 requires the use of an etchant having an etching selectivity with respect to the material of the substrate 10, for example, when the substrate 10 is a silicon substrate, the etchant of the etching process E2 may include ammonium hydroxide (NH)₄OH), potassium Hydroxide (KOH), hydrofluoric acid (HF), Tetramethylammonium Hydroxide (TMAH), nitric acid (HNO)₃) Or a combination of the foregoing, but is not limited thereto. As shown in the left side illustration of FIG. 8, the deep groove R1 and the storage node contact hole SC may include a vertical offset along the line cut AA', which may not be aligned. The deep recess R1 between the first bit line BL1 and the second bit line BL2 may extend to the front direction of the second spacer SP2 while exposing the top surface of the second active region 12b, the sidewalls of the first isolation region 14a, and the sidewalls of the second isolation region 14 b. In some embodiments, the exposed top surface of the second active region 12b may have an area a2, and the area a2 may be greater than or equal to the area a 1. In some embodiments, the deep recess R1 and the bottom surface 16a of the insulating layer 16 may include a residue 12b' of the active region 12 therebetween. As shown in the right side of the figure 8, the deep groove R1 is located with the storage node contact hole SC along the line BBMay be substantially vertically aligned. Sidewalls of the buried word lines WL (e.g., portions of the gate insulating layer 106 or the insulating cap layer 104) at both sides of the middle portion 12a1 may be exposed from the deep groove R1, respectively.

It is noted that, since the deep groove R1 is formed by selectively removing the exposed portion of the active region 12, the width of the deep groove R1 is mainly determined by the width of the end portion 12a2 of the active region 12. In some embodiments, the storage node contact hole SC and the deep groove R1 may have different widths, for example, referring to the right side illustration of fig. 8, the storage node contact hole SC may have a width W1, and the deep groove R1 may have a width W2, wherein the width W2 may be smaller than the width W1.

It is also noted that the top surface of the second active region 12b (or the end portion 12a2) exposed from the deep groove R1 shown in fig. 8 is a plane, which is only an example, and in other embodiments, the type of the etchant used in the etching process E2 may be selected such that the top surface of the second active region 12b (or the end portion 12a2) is a concave surface, a convex surface, a slant surface, or an included angle surface, but is not limited thereto. In some embodiments, a suitable etchant may be selected and the depth of the deep groove R1 adjusted such that area a2 is greater than area a 1.

Please refer to fig. 9. An epitaxial growth process and/or a deposition process may be performed to form a semiconductor layer S1 to fill the deep trench R1 and the lower portion of the storage node contact hole SC, then form a barrier layer L1 to cover the top surface of the semiconductor layer S1 and the top surfaces of the spacer SP and the bit line BL, and then form a metal layer M1 to cover the bit line BL and fill the remaining space of the storage node contact hole SC. Then, a recess process is performed to remove a portion of the metal layer M1 and the barrier layer L1 outside the storage node contact hole SC, so as to obtain a storage node contact structure 42 filled in the storage node contact hole SC and the deep trench R1, and directly contacting and electrically connecting to the end 12a2 of the active region 12. In detail, the storage node contact structure 42 may include three portions, i.e., a contact portion 42a located in the deep groove R1 and directly contacting the end 12a2 of the active region 12, a plug portion 42b located in the storage node contact hole SC, and a contact pad portion 42c located outside the storage node contact hole SC. The contact portion 42a is mainly formed of the semiconductor layer S1, the plug portion 42b is formed of both the semiconductor layer S1 and the metal layer M1, and the contact pad portion 42c is mainly formed of the metal layer M1. The material of semiconductor layer S1 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of the metal layer M1 may include, but is not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and/or a composite layer thereof. The shape, size and position of the contact portion 42a and the plug portion 42b are determined by the deep recess R1 and the storage node contact hole SC, respectively. The contact portion 42a and the plug portion 42b may have a width W2 and a width W1, respectively. In some embodiments, width W2 may be less than width W1. As shown in the left-hand illustration of fig. 9, the contact portion 42a and the plug portion 42b may include a misalignment in the vertical direction, and the two may not be aligned. The contact 42a may be offset in the direction of one of the bit lines BL, with a misalignment with the plug 42 b. As previously described, the shape of the contact surface between the contact portion 42a and the end portion 12a2 may be concave, convex, sloped, or angled, but is not limited thereto.

At this point, the DRAM of the present invention is completed. As shown in the left side of the figure 9, the dynamic random access memory of the present invention may include a substrate 10, which includes a first active region 12a, a first isolation region 14a, a second active region 12b, and a second isolation region 14b, which are arranged consecutively along a first direction (i.e., a direction of an AA' tangent). A first bit line BL1 is located on the first active region 12a, in direct contact with and electrically connected to the first active region 12 a. Second bit line BL2 is situated over second isolation region 14b and is separated from second isolation region 14b by insulating layer 16, not in direct contact. The storage node contact structure 42 is located between the first bit line BL1 and the second bit line BL2, and is in direct contact with the top surface of the second active region 12b, the sidewall of the first isolation region 14a, and the sidewall of the second isolation region 14 b.

In some embodiments, the top surface of the first active region 12a may be recessed below the top surface of the second active region 12 b. The bottom surface of the storage node contact structure 42 is higher than the bottom surface of the first bit line BL1 and lower than the bottom surface of the second bit line BL 2. A portion of the first isolation region 14a is removed when forming the recess BC so that the top surface is lower than the top surface of the second isolation region 14 b.

In some embodiments, the storage node contact structure 42 may include a stepped profile at the bottom due to the misalignment between the storage node contact hole SC and the deep recess R1.

In some embodiments, first and second spacers SP1 and SP2 may be disposed on sidewalls of the first and second bit lines BL1 and BL2, respectively, to electrically isolate the storage node contact structure 42 from the first and second bit lines BL1 and BL 2. The stepped profile of the storage node contact structure 42 may include a bottom corner 43 on the first spacer SP1 and a lateral extension directly below the second spacer SP2 (or the insulating layer 16).

In some embodiments, the storage node contact structure 42, the insulating layer 16, and the second isolation region 14b may include a residue 12b' of the active region 12 left after the etching process E2.

In some embodiments, the storage node contact structure 42 may include a semiconductor layer S1 located at the lower half and in direct contact with the top surface of the second active region 12b, the sidewall of the first isolation region 14a, and the sidewall of the second isolation region 14b, and a metal layer M1 located at the upper half (located on the semiconductor layer S1).

Viewed from another side, as shown in the right side illustration of fig. 9, the dynamic random access memory of the present invention may include a substrate 10 including isolation structures 14 and an active region 12 located between the isolation structures 14. The two buried word lines WL are located in the active region 12, dividing the active region 12 into one middle portion 12a1 and two end portions 12a 2. A bit line BL is located on the middle portion 12a1 of the active region 12 in direct contact with and electrically connected to the middle portion 12a1 of the active region 12. The storage node contact structures 42 are respectively located on the end portions 12a2 of the active region 12, and include a contact portion 42a and a plug portion 42b located on the contact portion 42a, wherein the contact portion 42a is in direct contact with the top surface of the end portion 12a2, the sidewalls of the buried word line WL, and the sidewalls of the isolation structure 14, and the width W2 of the plug portion 42b is greater than the width W1 of the contact portion 42 a.

In some embodiments, the contact portion 42a and the plug portion 42b may include a stepped profile therebetween. One bottom corner 44 of the plug portion 42b may be located on the buried word line WL, and the other bottom corner 45 may be located on the isolation structure 14.

In some embodiments, the dram further includes a spacer SP on the sidewall of the bit line BL and electrically isolating the storage node contact structure 42 from the bit line BL.

In some embodiments, the top surface of the middle portion 12a1 can be recessed below the top surface of the end portions 12a 2. The bottom surface of the storage node contact structure 42 may be higher than the bottom surface of the bit line BL and lower than the top surface of the buried word line WL.

In some embodiments, the contact portion 42a of the storage node contact structure 42 and the lower half of the plug portion 42b are formed by a semiconductor layer S1, and the upper half of the plug portion 42b is formed by a metal layer M1.

Referring to fig. 10, a cross-sectional structure of a dram according to another embodiment of the present invention is shown, which is substantially the same as the structure of the dram shown in fig. 9, and includes a substrate 10, an active region 12, an isolation structure 14, a buried word line WL, a bit line BL, a storage node contact structure 42, and the like. The main difference between the drams of fig. 10 and 9 is that the dram of fig. 10 can adjust the etching process E2, such as the lateral etching rate or the etching time of the etching process E2, to completely remove the residue 12b' between the deep trench R1 and the bottom surface 16a of the insulating layer 16 when the deep trench R1 is formed. Therefore, the storage node contact structure 42 of the dram of fig. 10 may directly contact the bottom surface 16a of the insulating layer 16. In some embodiments, the semiconductor layer S1 can be divided into a lower portion S1D filling the deep groove R1 and an upper portion S1T located between the lower portion S1D and the metal layer M1, wherein the lower portion S1D can be an epitaxial semiconductor layer formed by an epitaxial growth process, and the upper portion S1T can be a deposited semiconductor layer formed by a deposition process. In some embodiments, the lower portion S1D and the upper portion S1T can comprise different materials. For example, the lower portion S1D can include single crystal silicon and the upper portion S1T can include polysilicon. Preferably, the upper portion S1T is formed by performing a deposition process after the top surface of the lower portion S1D is higher than the bottom surface 16a of the insulating layer 16.

In the conventional method for fabricating the storage node contact structure, the material of the storage node contact structure is usually filled after the formation of the storage node contact hole. However, if the etching depth of the storage node contact hole is insufficient, the position of the storage node contact hole is shifted, or the bottom of the storage node contact hole has an abnormal shape, the exposed area of the active region is often insufficient, and the contact resistance of the storage node contact structure is abnormally increased. In the dynamic random access memory provided by the present invention, particularly after the formation of the storage node contact hole, a selective etching process (i.e., etching process E2 in the step of fig. 8) is performed to further recess the active region and to enlarge the exposed area of the active region (e.g., from area a1 to area a 2). Therefore, the storage node contact structure manufactured subsequently and the active region can have larger contact area and lower contact resistance, and the purpose of improving the performance of the dynamic random access memory is achieved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic random access memory, comprising:

a substrate including a first active region, a first isolation region, a second active region and a second isolation region arranged continuously along a first direction;

a first bit line over and in direct contact with the first active region;

a second bit line on the second isolation region;

an insulating layer between the second bit line and the second isolation region to isolate the second bit line from the second isolation region; and

a storage node contact structure between the first bit line and the second bit line and in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

2. The dynamic random access memory of claim 1, wherein a bottom of the storage node contact structure comprises a stair-stepped profile.

3. The dynamic random access memory of claim 1, further comprising:

a first spacer on a sidewall of the first bit line and electrically isolating the storage node contact structure from the first bit line; and

a second spacer on a sidewall of the second bit line and electrically isolating the storage node contact structure from the second bit line.

4. The dynamic random access memory of claim 3 wherein a bottom corner of the storage node contact structure is located on the first spacer.

5. The dynamic random access memory of claim 3, wherein a portion of the storage node contact structure is directly below the second spacer.

6. The dynamic random access memory of claim 1, wherein the storage node contact structure is in direct contact with a bottom surface of the insulating layer.

7. The dynamic random access memory of claim 1, wherein a remaining portion of the second active region is included between the storage node contact structure and the insulating layer and the second isolation region.

8. The dynamic random access memory of claim 1, wherein a top surface of the first active region is lower than the top surface of the second active region.

9. The dynamic random access memory of claim 1 wherein a top surface of the first isolation region is lower than a top surface of the second isolation region.

10. The dynamic random access memory of claim 1, wherein the storage node contact structure comprises:

a semiconductor layer in direct contact with said top surface of said second active region, said sidewall of said first isolation region, and said sidewall of said second isolation region; and

and the metal layer is positioned on the semiconductor layer.

11. The dynamic random access memory according to claim 10, wherein the semiconductor layer comprises:

a lower portion comprising an epitaxial semiconductor layer, wherein a top surface of the lower portion is higher than a bottom surface of the insulating layer; and

an upper portion between the lower portion and the metal layer and including a deposited semiconductor layer.

12. A dynamic random access memory, comprising:

a substrate including an active region located between two isolation structures;

two buried word lines are located in the active region, dividing the active region into a middle portion and two end portions;

a bit line on the middle portion;

a storage node contact structure on the end portion, wherein the storage node contact structure comprises:

a contact portion directly contacting a top surface of the end portion, a sidewall of the buried word line, and a sidewall of the isolation structure; and

a plug portion on the contact portion, wherein the width of the plug portion is greater than the width of the contact portion.

13. The dram of claim 12 wherein a bottom corner of the plug portion is located on the buried word line.

14. The dynamic random access memory of claim 13 wherein another bottom corner of the plug portion is located on the isolation structure.

15. The dynamic random access memory of claim 12 including a stepped profile between the contact portion and the plug portion.

16. The dynamic random access memory of claim 12 further comprising a spacer on a sidewall of the bit line and electrically isolating the storage node contact structure from the bit line.

17. The dynamic random access memory of claim 12, wherein a top surface of the middle portion is lower than the top surfaces of the end portions.

18. The dynamic random access memory of claim 12 wherein the contact portion and the lower half of the plug portion are formed of a semiconductor layer and the upper half of the plug portion is formed of a metal layer.

19. The dynamic random access memory of claim 18, wherein the semiconductor layer comprises:

a lower portion including an epitaxial semiconductor layer; and

an upper portion, located between the lower portion and the metal layer, includes a deposited semiconductor layer.