TW201735333A - 具有像素級偏壓控制之單光子崩潰二極體陣列 - Google Patents
具有像素級偏壓控制之單光子崩潰二極體陣列 Download PDFInfo
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Abstract
一種感測裝置包括一感測元件陣列。各感測元件包括一光二極體,其包括一p-n接面;及一局部偏壓電路,其係經耦合以用一偏壓電壓反向偏壓該p-n接面,該偏壓電壓比該p-n接面之一崩潰電壓(breakdown voltage)大一足量差額,使得入射在該p-n接面上之一單光子觸發來自該感測元件之一崩潰脈衝輸出(avalanche pulse output)。一偏壓控制電路係經耦合以設定在該等感測元件的不同者中之該偏壓電壓為大於該崩潰電壓之不同的各別值。
Description
本發明大致上係關於光電裝置,且具體係關於高靈敏度偵測器陣列。
單光子崩潰二極體(SPAD)(亦已知為蓋格模式(Geiger-mode)崩潰二極體(GAPD))係能夠以非常高的抵達時間解析度(約數十微微秒)擷取個別光子的偵測器。其等可以專用的半導體程序或以標準CMOS技術製造。製造於一單一晶片上的SPAD感測器陣列已實驗性地用在3D成像攝影機中。Charbon等人在公開於TOF
範圍成像相機(TOF Range-Imaging Cameras
)(Springer-Verlag, 2013)中之「SPAD基感測器(SPAD-Based Sensors)」中提供SPAD技術的有用評論,其係以引用方式併入本文中。
在一SPAD中,一p-n接面係以一遠高於接面之崩潰電壓(breakdown voltage)的位準經反向偏壓。在此偏壓下,電場係如此高以致由於一入射光子而注入空乏層之一單電荷載體可觸發一自持崩潰(avalanche)。崩潰電流脈衝的前緣(leading edge)標記所偵測之光子的抵達時間。電流持續直到藉由將偏壓電壓往下降低至崩潰電壓或低於崩潰電壓來淬熄崩潰。此後者的功能係藉由一淬熄電路(quenching circuit)來執行,該淬熄電路可僅包含一與SPAD串聯之高電阻壓載負載,或者可替代地包含主動式電路元件。
下文所述之本發明的實施例提供改善的單光子感測陣列及用於陣列操作的方法。
因而根據本發明之一實施例提供一感測裝置,其包括一感測元件陣列。各感測元件包括一光二極體,其包括一p-n接面;及一局部偏壓電路,其係經耦合以用一偏壓電壓反向偏壓該p-n接面,該偏壓電壓比該p-n接面之一崩潰電壓大一足量差額,使得入射在該p-n接面上之一單光子觸發來自該感測元件之一崩潰脈衝輸出。一偏壓控制電路係經耦合以設定在該等感測元件的不同者中之該偏壓電壓為大於該崩潰電壓之不同的各別值。
在一些實施例中,該裝置包括一全域偏壓產生器(global bias generator),其係經耦合以施加一全域偏壓電壓至該陣列中之該等感測元件的全部,其中各感測元件中的該局部偏壓電路係經組態以施加一過量偏壓,使得跨各p-n接面之該偏壓電壓係該全域偏壓電壓與該過量偏壓之一總和。一般而言,各感測元件包括一淬熄電路,且各感測元件中之該光二極體、該局部偏壓電路、及該淬熄電路係串聯地耦合在一起。
在所揭示之一實施例中,該局部偏壓電路包括一電壓加法器,其係經耦合至提供各別輸入電壓之複數個電壓線,且係經組態以選擇及加總該等輸入電壓,以便提供該偏壓電壓給該p-n接面。
在一些實施例中,該偏壓控制電路係經組態以設定在該等感測元件之不同者中的該偏壓電壓,以便均化該等感測元件對入射光子之一靈敏度。額外地或替代地,該偏壓控制電路係經組態以識別具有高於一指定限值之雜訊位準之該等感測元件的一或多者,並設定該等經識別之感測元件的該偏壓電壓,以便降低該等雜訊位準。
另外,額外地或替代地,該偏壓控制電路係經組態以增加在該陣列之一選定區域中之該等感測元件的該偏壓電壓,使得該選定區域中之該等感測元件對入射光子具有一靈敏度,其係大於該指定區域以外之該等感測元件的靈敏度。在一實施例中,該偏壓控制電路係經組態以修改該等感測元件之該偏壓電壓,以便跨該陣列掃掠該選定區域。
在所揭示之一實施例中,該感測元件陣列包括該等感測元件之一第一二維矩陣,其係形成在一第一半導體晶片上,且該偏壓控制電路包括偏壓控制元件的一第二二維矩陣,其係形成在一第二半導體晶片上,且係以在該等感測元件與該等偏壓控制元件間以一對一的對應耦合至該第一矩陣。一般而言,該第二半導體晶片包括處理電路,該等處理電路係經耦合以接收來自該等感測元件之各別的輸出脈衝,其中該等處理電路包括一各別的時間數位轉換器(TDC),其係耦合至各感測元件。
根據本發明之一實施例,亦提供一用於感測的方法,該方法包括提供一感測元件陣列,各感測元件包括一光二極體,該光二極體包括一p-n接面;及一偏壓電路,其係經耦合以用一偏壓電壓反向偏壓該p-n接面,該偏壓電壓比該p-n接面之一崩潰電壓大一足量差額,使得入射在該p-n接面上之一單光子觸發來自該感測元件之一崩潰脈衝輸出。在該等感測元件的不同者中的該偏壓電壓係設定為大於該崩潰電壓之不同的各別值。
由本發明實施例之下列詳細說明、連同圖式將更完整地了解本發明,其中:
一SPAD感測元件上的偏壓電壓超過崩潰電壓的差額判定感測元件的量子效率及暗雜訊兩者。(量子效率及暗雜訊兩者隨著過量的偏壓電壓增加。)同時,由於諸如幾何及摻質濃度中的局部差異,一SPAD陣列中之感測元件的崩潰電壓在元件間一般會有所變動。因此,當施加全域偏壓時,以跨各光二極體之相同的總偏壓電壓,偏壓電壓超過崩潰電壓的差額在元件間將有所變動,也造成在靈敏度及雜訊位準中感測元件之間的差異。
本文所述之本發明的實施例藉由使一陣列中之不同感測元件的偏壓電壓能夠被設定為不同值來解決此問題。此特徵不僅可用於均化整個陣列的靈敏度及安定雜訊像素,且亦用於為了更有選擇性且有效率地利用陣列之偵測能力的目的而引入有意的靈敏度差異。例如,本發明的原理可應用在例如SPAD成像陣列(諸如,基於飛行時間(TOF)測量的3D攝影機中所用者)以及在矽光電倍增器(SiPM)裝置與其他種類的崩潰二極體陣列中。
在所揭示的實施例中,一感測裝置包含一感測元件陣列,感測元件之各者包含一光二極體及一偏壓電路。各感測元件中的偏壓電路能夠以一偏壓電壓施加一反向偏壓至光二極體的p-n接面,該偏壓電壓比p-n接面的接面崩潰電壓大一足量差額,使得入射在p-n接面上之一單光子觸發來自該感測元件之一崩潰脈衝輸出。一偏壓控制電路設定在不同的感測元件中的偏壓電壓為大於崩潰電壓之不同的各別值。
在一些實施例中,一全域偏壓產生器施加一全域偏壓電壓至陣列中全部的感測元件,而各感測元件中的局部偏壓電路除了全域偏壓以外施加一過量偏壓。因此,跨各p-n接面的偏壓電壓係全域偏壓電壓與過量偏壓之一總和(其中過量偏壓相對於全域偏壓可為正或負,取決於電路組態)。一般而言,各感測元件亦包含一淬熄電路,而各感測元件中的光二極體、偏壓電路、及淬熄電路係串聯地耦合在一起。
偏壓控制電路可設定在不同的感測元件中的偏壓電壓的不同值以達成各種目的。例如,在一實施例中,偏壓電壓係經設定以便補償崩潰電壓差,且因此均化感測元件對入射光子的靈敏度。替代地或額外地,偏壓控制電路可識別具有高於一指定限值之雜訊位準之感測元件的一或多者,並可設定經識別之此等感測元件的偏壓電壓,以便降低雜訊位準,可能到完全切斷帶雜訊的感測元件的程度。
在其他實施例中,偏壓控制電路增加在陣列之某一選定區域中之感測元件的偏壓電壓,使得此區域中的感測元件對入射光子具有一大於該區域以外之感測元件的靈敏度。如早前所提及者,此特徵在更有效率地利用陣列的偵測能力上可為有用的,例如,藉由將陣列的靈敏區域裁製為一照明光束的形狀或一成像場景中之一受關注區域的形狀。在一些實施例中,偏壓控制電路可動態地修改感測元件之偏壓電壓,以便跨陣列掃掠選定區域。
圖1係根據本發明之一實施例示意地繪示一感測裝置20的方塊圖。裝置20包含感測元件24(亦稱為像素)之一陣列22,各感測元件24包含一SPAD及相關聯的偏壓電路與處理電路,如進一步於下文所述者。一全域高壓偏壓產生器26施加一全域偏壓電壓至陣列22中全部的感測元件24。此外,各感測元件24中之一局部偏壓電路28施加一過量偏壓,其在感測元件中與全域偏壓加總。一像素偏壓控制電路30設定在不同的感測元件中的過量偏壓電壓為不同的各別值,該等過量偏壓電壓由局部偏壓電路28所施加。
圖2係根據本發明之一實施例顯示陣列22中之感測元件24之一者的組件的方塊圖。此實施例中的陣列22包含形成在一第一半導體晶片32上的感測元件之一二維矩陣,以及形成在一第二半導體晶片34上的偏壓控制電路及處理電路之一第二二維矩陣。(僅顯示兩矩陣各者之一單一元件。)晶片32及晶片34係耦合在一起,使得兩個矩陣呈一對一的對應,藉此晶片32上的各感測元件與晶片34上之對應的偏壓控制元件及處理元件接觸。
晶片32及晶片34兩者可連同如本文所述之伴隨的偏壓控制電路及處理電路,基於所屬領域中已知的SPAD感測器設計,使用眾所周知的CMOS製造程序由矽晶圓製成。替代地,本文所述之偵測的設計與原理可使用其他材料與程序加上必要的修改來實施。例如,圖2所示的全部組件可形成在一單一晶片上,或者晶片之間的組件分布可有所不同。所有此類替代實施方案均視為屬於本發明的範圍。
感測元件24包含一SPAD 36,其包含一光敏p-n接面,如所屬領域中已知者。包括一淬熄電路38及局部偏壓電路28的周邊電路一般係與SPAD一起位於晶片32上。如上文所解釋的,施加至SPAD 36的實際偏壓係偏壓產生器26(圖1)所提供的全域Vbias
與偏壓電路28所施加之一過量偏壓的總和。像素偏壓控制電路30藉由設定在晶片34上之一偏壓記憶體40中的一對應的數位值而設定在各像素中之欲施加的過量偏壓。
回應各經擷取的光子,SPAD 36輸出一崩潰脈衝,其係由晶片34上的處理電路接收,處理電路包括數位邏輯42及一經組態作為一輸出緩衝器44的記憶體。例如,此等處理元件可經組態以作用如一時間數位轉換器(TDC),其測量SPAD 36之各脈衝輸出相對於一參考時間的延遲,並輸出一對應該延遲的數位資料值。替代地或額外地,邏輯42及緩衝器44可測量及輸出其他種類的值,包括(但不限於)脈衝延遲時間的直方圖。
圖3係根據本發明之一實施例示意地繪示隨局部偏壓電路28所施加的偏壓而變動之SPAD 36對一入射光子之回應的圖。此圖顯示三個曲線50、52、54,其等代表SPAD 36在偏壓電路28之三個不同的過量偏壓設定下的脈衝輸出。
曲線50對應設定過量偏壓以得到跨p-n接面之一實質上大於崩潰電壓之總偏壓電壓的情況。以此設定,感測元件24具有一高靈敏度,且SPAD 36回應入射光子之崩潰脈衝輸出結果具有一高振幅。
曲線52代表一中間偏壓設定,以此該輸出脈衝具有一較低振幅,意味著較低的靈敏度。同時,此偏壓設定下的暗雜訊一般將低於針對曲線50之設定。
曲線54代表設定過量偏壓使得總偏壓電壓小於跨p-n接面之崩潰電壓的情況。以此偏壓位準,感測元件24基本上被切斷,且亦貢獻極少的暗雜訊或無貢獻暗雜訊給裝置20。此低總體偏壓設定可用於安定雜訊像素,且藉由切斷一受關注之電流區域以外的像素而降低裝置20的總功率消耗。
在一實施例中,在將裝置20置於操作狀態前,偏壓控制電路30參與一校準程序。在此一類程序中,以某一預先界定的測試圖案(其可僅包含均勻的低位準照度)照明陣列,並評估感測元件24的輸出。當校準結果顯示感測元件之間的靈敏度差異時,偏壓控制電路30可設定個別的像素偏壓電壓以便均化靈敏度,例如,藉由增加用於展現低靈敏度之感測元件的總電壓及/或反之亦然。額外地或替代地,當偏壓控制電路識別顯著帶雜訊(例如,具有一高於一指定限值的暗雜訊位準)的一感測元件時,其可設定此感測元件24中由局部偏壓電路28所施加的過量偏壓電壓以便降低雜訊位準,包括完全切斷感測元件,如曲線54所繪示者。
圖4A至圖4C係根據本發明之三個不同的實施例示意地繪示陣列22中在晶片32內之一感測元件之組件的電路圖。在全部的實施例中,光二極體36、局部偏壓電路28、及淬熄電路38係串聯地耦合在一起。藉由全域偏壓產生器26將全域偏壓電壓Vbias
(或等效地,圖4B中的負偏壓Vbd
)施加至全部的感測元件24。局部偏壓電路28施加一過量偏壓Vq
,其係與跨SPAD 36的全域偏壓加總。如早前所提及者,如在本說明書以及在申請專利範圍中於此上下文中所用的用語「總和(sum)」包括正極性與負極性兩種求和。因此,圖4A及圖4C中跨SPAD 36的實際偏壓係Vbias
–Vq
;且在此等實施例中由電路28增加Vq
得出SPAD上之較低的淨偏壓。淬熄電路38可同樣地耦合至SPAD 36之陽極或陰極的任一者,且來自SPAD的脈衝輸出可經AC耦合(如圖4A及圖4C)或經DC耦合(如圖4B)。
圖5係根據本發明之一實施例示意地顯示局部偏壓電路28之細節的電路圖。在此實例實施方案中,局部偏壓電路28包含一電壓加法器,其係經耦合至多個電壓線,該多個電壓線經由各別的輸入電阻器50提供各別的輸入電壓:Voff
(亦即,一基線電壓)、V1
、V2
、…、Vn
。將開關52設定至斷開或閉合位置,以便選擇欲加總的輸入電壓以給出所欲的過量偏壓,而一具有反饋電阻(feedback resistance)56的運算放大器54加總輸入電壓,以便提供偏壓電壓Vq
給SPAD 36。
此實施方案的有利之處在於其使像素偏壓控制電路30能夠從一相對較大範圍的值選擇欲由各感測元件24施加的偏壓,同時最小化實際上必須供給陣列22之電壓線的數目。開關52的設定一般係儲存在偏壓記憶體40中,且為了設定在各架構中的開關而被讀出。開關的設定可如上文所解釋般地經預先校準,或者該等開關的設定可如下文所述般地在裝置20的操作期間替代地或額外地經動態修改。替代地,局部偏壓電路28可包含其他種類的電壓控制機構,如所屬領域中已知者。
圖6係根據本發明之一實施例示意地繪示裝置20之一組態的方塊圖,該裝置所具有的靈敏度在陣列22中的感測元件之間有所變動。在此實施例中,偏壓控制電路30設定由局部偏壓電路28所施加的過量偏壓電壓,使得感測元件的淨偏壓電壓(以及因此靈敏度)在陣列的某一區域中高於該區域以外的區域。具體地,偏壓電壓及靈敏度在像素60中最大,在周圍像素62中較低,且在周邊像素64中還要更低。所選定區域以外的像素66中的偏壓係經設定使得切斷彼等像素。雖然在此情況下,所選定的區域係陣列22的中心內之一概略為圓形的區域,可以此方式選擇具有任何合適形狀的任何區域。
如早前所提及者,此實施例係有用的,尤其是在將陣列22的靈敏區域裁製為一照明光束的形狀或一欲成像場景中之一受關注區域的形狀。例如,在將感測元件24的輸出連接在一起的矽光電倍增器(SiPM)應用中,圖6的組態特別有助於最大化裝置20相對於功率消耗的靈敏度,同時降低來自像素對信號無貢獻的背景雜訊。
圖7係根據本發明之一實施例示意地繪示具有一靈敏度掃描區域70之SPAD陣列22的方塊圖。在此情況下,偏壓控制電路30將區域70內之像素60與像素62的偏壓電壓設定為高於陣列22中之剩餘像素的值。然而,偏壓控制電路30動態地修改感測元件24的偏壓電壓,以便跨陣列掃掠區域70,如圖中之箭頭所繪示者。例如,電路30可以一光柵掃描(raster scan)掃掠區域70,與一雷射光束跨一成像至陣列22上之場景的掃描同步。
在一替代實施例(圖中未圖示)中,偏壓控制電路30設定局部偏壓電壓,使得區域70具有一線性形狀,其沿著陣列22之一或多個行延伸,並匹配一照明光束的線性形狀。電路30接著可與照明光束同步跨陣列22掃掠此線性區域70。替代地,可實施其他掃描圖案,包括矩形及適應性掃描圖案兩者。
當理解上述實施例係經由實例方式引用,且本發明並未受限於上文已具體顯示及敘述者。毋寧說,本發明的範圍包括上述各種特徵的組合及子組合兩者以及所屬技術領域中具有通常知識者一經閱讀前文敘述所發想且未經先前技術揭示的變化與修改。
20‧‧‧感測裝置;裝置
22‧‧‧陣列
24‧‧‧感測元件
26‧‧‧全域高壓偏壓產生器;偏壓產生器
28‧‧‧局部偏壓電路;偏壓電路
30‧‧‧像素偏壓控制電路
32‧‧‧第一半導體晶片;晶片
34‧‧‧第二半導體晶片;晶片
36‧‧‧SPAD
38‧‧‧淬熄電路
40‧‧‧偏壓記憶體
42‧‧‧數位邏輯;邏輯
44‧‧‧輸出緩衝器;緩衝器
50‧‧‧曲線;電阻器
52‧‧‧曲線;開關
54‧‧‧曲線;運算放大器
56‧‧‧反饋電阻
60‧‧‧像素
62‧‧‧像素
64‧‧‧像素
66‧‧‧像素
70‧‧‧靈敏度掃描區域;區域
22‧‧‧陣列
24‧‧‧感測元件
26‧‧‧全域高壓偏壓產生器;偏壓產生器
28‧‧‧局部偏壓電路;偏壓電路
30‧‧‧像素偏壓控制電路
32‧‧‧第一半導體晶片;晶片
34‧‧‧第二半導體晶片;晶片
36‧‧‧SPAD
38‧‧‧淬熄電路
40‧‧‧偏壓記憶體
42‧‧‧數位邏輯;邏輯
44‧‧‧輸出緩衝器;緩衝器
50‧‧‧曲線;電阻器
52‧‧‧曲線;開關
54‧‧‧曲線;運算放大器
56‧‧‧反饋電阻
60‧‧‧像素
62‧‧‧像素
64‧‧‧像素
66‧‧‧像素
70‧‧‧靈敏度掃描區域;區域
[圖1]係根據本發明之一實施例示意地繪示一SPAD基感測裝置的方塊圖; [圖2]係根據本發明之一實施例顯示一SPAD陣列中之一感測元件之組件的方塊圖; [圖3]係根據本發明之一實施例示意地繪示隨偏壓變動之一SPAD陣列中的偵側器對一入射光子之回應的圖; [圖4A至圖4C]係根據本發明之三個不同的實施例示意地繪示一SPAD矩陣中之一像素之組件的電路圖; [圖5]係根據本發明之一實施例示意地繪示一局部偏壓控制器的電路圖; [圖6]係根據本發明之一實施例示意地繪示一具有可變靈敏度之SPAD陣列的方塊圖;以及 [圖7]係根據本發明之一實施例示意地繪示一具有一靈敏度掃描區域之SPAD陣列的方塊圖。
20‧‧‧感測裝置;裝置
22‧‧‧陣列
24‧‧‧感測元件
26‧‧‧全域高壓偏壓產生器;偏壓產生器
28‧‧‧局部偏壓電路;偏壓電路
30‧‧‧像素偏壓控制電路
Claims (20)
- 一種感測裝置,其包含: 一感測元件陣列,各感測元件包含: 一光二極體,其包含一p-n接面;以及 一局部偏壓電路,其係經耦合以用一偏壓電壓反向偏壓該p-n接面,該偏壓電壓比該p-n接面之一崩潰電壓(breakdown voltage)大一足量差額,使得入射在該p-n接面上之一單光子觸發來自該感測元件之一崩潰脈衝輸出(avalanche pulse output);以及 一偏壓控制電路,其係經耦合以設定在該等感測元件的不同者中之該偏壓電壓為大於該崩潰電壓之不同的各別值。
- 如請求項1之裝置,並包含一全域偏壓產生器,該全域偏壓產生器係經耦合以施加一全域偏壓電壓至該陣列中之該等感測元件的全部,其中各感測元件中的該局部偏壓電路係經組態以施加一過量偏壓,使得跨各p-n接面之該偏壓電壓係該全域偏壓電壓與該過量偏壓之一總和。
- 如請求項2之裝置,其中各感測元件包含一淬熄電路,且其中各感測元件中之該光二極體、該局部偏壓電路、及該淬熄電路係串聯地耦合在一起。
- 如請求項1之裝置,其中該局部偏壓電路包含一電壓加法器,該電壓加法器係經耦合至提供各別輸入電壓之複數個電壓線,且係經組態以選擇及加總該等輸入電壓,以便提供該偏壓電壓給該p-n接面。
- 如請求項1之裝置,其中該偏壓控制電路係經組態以設定在該等感測元件之不同者中之該偏壓電壓,以便均化該等感測元件對入射光子之一靈敏度。
- 如請求項1之裝置,其中該偏壓控制電路係經組態以識別具有高於一指定限值之雜訊位準之該等感測元件的一或多者,以及設定經識別之該等感測元件的該偏壓電壓,以便降低該等雜訊位準。
- 如請求項1之裝置,其中該偏壓控制電路係經組態以增加在該陣列之一選定區域中之該等感測元件的該偏壓電壓,使得該選定區域中之該等感測元件對入射光子具有一靈敏度,其係大於該指定區域以外之該等感測元件的靈敏度。
- 如請求項7之裝置,其中該偏壓控制電路係經組態以修改該等感測元件之該偏壓電壓,以便跨該陣列掃掠該選定區域。
- 如請求項1至8中任一項之裝置,其中該感測元件陣列包含該等感測元件之一第一二維矩陣,其係形成在一第一半導體晶片上,且其中該偏壓控制電路包含偏壓控制元件的一第二二維矩陣,其係形成在一第二半導體晶片上,且係以在該等感測元件與該等偏壓控制元件間以一對一的對應耦合至該第一矩陣。
- 如請求項9之裝置,其中該第二半導體晶片包含處理電路,該等處理電路經耦合以接收來自該等感測元件之各別的輸出脈衝,其中該等處理電路包含一各別的時間數位轉換器(TDC),其係耦合至各感測元件。
- 一種用於感測的方法,其包含: 提供一感測元件陣列,各感測元件包含一光二極體,其包含一p-n接面;及一偏壓電路,其係經耦合以用一偏壓電壓反向偏壓該p-n接面,該偏壓電壓比該p-n接面之一崩潰電壓大一足量差額,使得入射在該p-n接面上之一單光子觸發來自該感測元件之一崩潰脈衝輸出;以及 設定在該等感測元件的不同者中之該偏壓電壓為大於該崩潰電壓之不同的各別值。
- 如請求項11之方法,其中設定該偏壓電壓包含施加一全域偏壓電壓至該陣列中之該等感測元件的全部;以及在各感測元件中設定一局部偏壓電路以施加一過量偏壓,使得跨各p-n接面之該偏壓電壓係該全域偏壓電壓與該過量偏壓之一總和。
- 如請求項12之方法,其中各感測元件包含一淬熄電路,且其中提供該陣列包含耦合各感測元件中之該光二極體、該局部偏壓電路、及該淬熄電路串聯地耦合在一起。
- 如請求項11之方法,其中該局部偏壓電路包含一電壓加法器,其係經耦合至提供各別輸入電壓之複數個電壓線,且其中設定該偏壓電壓包含選擇及加總該等輸入電壓,以便提供該偏壓電壓給該p-n接面。
- 如請求項11之方法,其中該等感測元件之不同一者中的該偏壓電壓係經設定,以便均化該等感測元件對入射光子之一靈敏度。
- 如請求項11之方法,其中設定該偏壓電壓包含識別具有高於一指定限值之雜訊位準之該等感測元件的一或多者;以及設定經識別之該等感測元件的該偏壓電壓,以便降低該等雜訊位準。
- 如請求項11之方法,其中設定該偏壓電壓包含增加在該陣列之一選定區域中之該等感測元件的該偏壓電壓,使得該選定區域中之該等感測元件對入射光子具有一靈敏度,其係大於該指定區域以外之該等感測元件的靈敏度。
- 如請求項17之方法,其中增加該偏壓電壓包含修改該等感測元件之該偏壓電壓,以便跨該陣列掃掠該選定區域。
- 如請求項11至18中任一項之方法,其中提供該感測元件陣列包含提供該等感測元件之一第一二維矩陣,其係形成在一第一半導體晶片上;以及提供偏壓控制元件的一第二二維矩陣,其係形成在一第二半導體晶片上,且係以在該等感測元件與該等偏壓控制元件間以一對一的對應耦合至該第一矩陣。
- 如請求項19之方法,其中該第二半導體晶片包含處理電路,該等處理電路係經耦合以接收來自該等感測元件之各別的輸出脈衝,其中該等處理電路包含一各別的時間數位轉換器(TDC),其係耦合至各感測元件。
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US9331116B2 (en) | 2014-01-15 | 2016-05-03 | Omnivision Technologies, Inc. | Back side illuminated single photon avalanche diode imaging sensor with high short wavelength detection efficiency |
CN103763485A (zh) | 2014-02-17 | 2014-04-30 | 苏州超锐微电子有限公司 | 一种用于智能图像传感器的单光子级分辨率图像采集芯片前端电路模块 |
JP6483725B2 (ja) * | 2014-04-07 | 2019-03-13 | サムスン エレクトロニクス カンパニー リミテッド | 光学的イベントを感知する方法とそのための光学的イベントセンサ、及び距離測定モバイル装置 |
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2015
- 2015-12-20 US US14/975,790 patent/US9997551B2/en active Active
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2016
- 2016-11-28 TW TW105139124A patent/TWI628785B/zh active
- 2016-11-29 EP EP16201123.3A patent/EP3182154A1/en not_active Withdrawn
- 2016-12-16 KR KR1020160172229A patent/KR101901033B1/ko active IP Right Grant
- 2016-12-19 CN CN201611176089.2A patent/CN106898675B/zh active Active
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI703340B (zh) * | 2018-03-27 | 2020-09-01 | 美商豪威科技股份有限公司 | 適用於遠程飛行時間應用的雙模堆疊式光倍增器 |
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CN106898675B (zh) | 2018-10-19 |
EP3182154A1 (en) | 2017-06-21 |
KR20170073515A (ko) | 2017-06-28 |
KR101901033B1 (ko) | 2018-09-20 |
CN106898675A (zh) | 2017-06-27 |
TWI628785B (zh) | 2018-07-01 |
CN206401341U (zh) | 2017-08-11 |
US9997551B2 (en) | 2018-06-12 |
US20170179173A1 (en) | 2017-06-22 |
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