TW201735121A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201735121A
TW201735121A TW105144134A TW105144134A TW201735121A TW 201735121 A TW201735121 A TW 201735121A TW 105144134 A TW105144134 A TW 105144134A TW 105144134 A TW105144134 A TW 105144134A TW 201735121 A TW201735121 A TW 201735121A
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TWI723111B (zh
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世海 楊
王聖禎
陳燕銘
溫宗堯
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台灣積體電路製造股份有限公司
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Abstract

提供半導體裝置及其製造方法。此半導體裝置包含在基底上沿第一方向延伸的鰭，以及在鰭上沿第二方向延伸的閘極結構。此閘極結構包含：在鰭上的閘極介電層；在閘極介電層上的閘極電極；以及位於閘極電極的第一橫向表面上，且沿第二方向延伸的第一絕緣閘極間隙物。此半導體裝置亦包含源極/汲極區，其形成於鰭內鄰近於閘極電極的區域內，且源極/汲極區的一部分沿第一方向，以大抵上固定的距離延伸在絕緣閘極間隙物下方。

Description

半導體裝置
本發明實施例係有關於半導體裝置及其製造方法，特別係有關於半導體裝置的源極和汲極區的製造方法。
為追求更高的裝置密度、更高的效能及低成本，半導體工業已進步至奈米科技製程節點，來自製造和設計議題兩者的挑戰造成了三維設計的發展，例如鰭式場效電晶體(FinFET)。典型的FinFET裝置包含具有高深寬比(aspect ratio)的半導體鰭，並且在其內部形成半導體電晶體裝置的通道和源極/汲極區。閘極沿著(例如，環繞)鰭結構而形成於其上，利用通道和源極/汲極區增加的表面積之優勢製造更快、可信度更高及更好控制的半導體電晶體裝置。在一些裝置，FinFET裡源極/汲極(S/D)部分內的應力材料使用，例如矽化鍺(SiGe)、矽化磷(SiP)或碳化矽(SiC)，可提升載子的移動率。
本發明的一些實施例提供半導體裝置，其包含在基底上沿第一方向延伸的鰭，以及在鰭上沿第二方向延伸的閘極結構。此閘極結構包含：在鰭上的閘極介電層；在閘極介電層上的閘極電極；以及位於閘極電極的第一橫向表面上，且沿第二方向延伸的第一絕緣閘極間隙物。此半導體裝置亦包 含源極/汲極區，其形成於鰭內鄰近於閘極電極的區域內，且源極/汲極區的一部分沿第一方向，以大抵上固定的距離延伸在絕緣閘極間隙物下方。
10‧‧‧半導體基底
12‧‧‧鰭
14‧‧‧淺溝槽隔離區
16‧‧‧閘極結構
18‧‧‧閘極電極
20‧‧‧閘極介電層
22‧‧‧側壁間隙物
24‧‧‧第一區
26‧‧‧凹陷
28‧‧‧摻雜區
30、40、46、62‧‧‧源極和汲極區
32、42、48、64‧‧‧輕摻雜區
34、44、50、66‧‧‧重摻雜區
36‧‧‧第二區
38‧‧‧氮化物層
60、70‧‧‧擴大的凹陷
100‧‧‧HVT裝置
110‧‧‧PMOS區
120‧‧‧NMOS區
200‧‧‧SVT裝置
300‧‧‧LVT裝置
本發明實施例的各種樣態最好的理解方式為閱讀以下說明書的詳說明並配合所附圖式。應該注意的是，本發明實施例的各種不同部件(feature)並未依據工業標準作業的尺寸而繪製。事實上，為使說明書能清楚描繪，各種不同部件的尺寸可以任意放大或縮小。
第1-5圖顯示根據本發明的一實施例，形成半導體裝置之示例製程。
第6-7圖顯示形成半導體裝置之其他製程。
第8-10圖顯示根據本發明的一實施例，形成半導體裝置之示例製程的更多步驟。
第11-16圖顯示根據本發明的另一實施例，形成半導體裝置之示例製程。
第17-18圖顯示根據本發明的另一實施例之半導體裝置。
第19-20圖顯示根據本發明的另一實施例之半導體裝置。
要瞭解的是本說明書以下的發明內容提供許多不同的實施例或範例，以實施本發明的實施例不同部件。而本說明書以下的發明內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的發明內容敘述了將一第 一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。另外，本發明的實施例的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如”在...之下”、”下方”、”下部”、”上方”、”上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或步驟中的裝置的不同方位。例如，若翻轉圖式中的裝置，描述為位於其他元件或部件”下方”或”在...之下”的元件，將定位為位於其他元件或部件”上方”。因此，範例的用語”下方”可涵蓋上方及下方的方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
本發明各種實施例係關於半導體裝置及其形成方法。在各種實施例，半導體裝置包含鰭式場效電晶體(fin field-effect transistor,FinFET)。FinFET是形成在形成於基底上的鰭結構上的場效電晶體。在一些實施例，鰭形成一陣列。
根據本發明的一些實施例，如第1圖所示，形成半導體裝置的方法包含形成鰭結構，其包含一或多個鰭12位於半導體基底10上。在一實施例，半導體基底10為矽基底。或者，半導體基底10可包含鍺、矽鍺、砷化鎵或其他適合的 半導體材料。或者，半導體基底可包含磊晶層。例如，半導體基底可具有位於半導體塊材上的磊晶層。此外，可對半導體基底賦予應力以提高效能。例如，磊晶層可包含與半導體塊材不同的半導體材料，例如位於矽塊材上的矽鍺層或位於矽鍺塊材上的矽層。此具有應力的基底可藉由選擇性磊晶成長(selective epitaxial growth,SEG)形成。此外，半導體基底可包含絕緣上覆半導體(semiconductor-on-insulator,SOI)結構。或者，半導體基底可包含掩埋介電層，例如埋氧(buried oxide,BOX)層，其可例如藉由植氧分離(separation by implantation of oxygen,SIMOX)技術、晶圓接合(bonding)、SEG或其他適合的方法形成。在其他實施例，基底可包含複合半導體，其包含四四族(IV-IV)複合半導體，例如SiC及SiGe；三五族(III-V)複合半導體，例如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。在一些實施例，半導體基底10例如為具有摻雜濃度介於約1×1015cm-3至約2×1015cm-3的p型矽基底。在其他實施例，半導體基底10例如為具有摻雜濃度介於約1×1015cm-3至約2×1015cm-3的n型矽基底。
鰭12設置於半導體基底10上，且鰭12可由與半導體基底10相同的材料製作，並且可由半導體基底10連續地延伸。鰭12可藉由選擇性地蝕刻半導體基底10而形成。或者，鰭12可由磊晶優先方法(EPI first method)形成。在磊晶優先方法中，形成磊晶層於半導體基底10上，之後圖案化磊晶層形成鰭12。
可使用微影製程定義半導體基底10上的鰭12。在一些實施例，形成硬遮罩層於半導體基底10上。硬遮罩層可包含兩層的SiN和SiO2。旋轉塗佈光阻層於半導體基底上。藉由讓光阻選擇性曝光於光化輻射下而將光阻圖案化。一般而言，圖案化可包含光阻塗佈(例如旋轉塗佈)、軟烤、遮罩對位、曝光、曝光後烤、光阻顯影、清洗、乾燥(例如，硬烤)，其他適合的製程或其組合。或者，可實施微影曝光製程或由其他適合的方法取代，例如無遮罩微影、電子束寫入、直寫入(direct-writing)、離子束寫入及/或奈米刻印(nano-imprinting)。
藉由蝕刻硬遮罩層所露出的區域，使光阻層的圖案轉移至硬遮罩層。接著，在蝕刻半導體基底時，硬遮罩層用來作為遮罩。半導體基底可藉由各種方法蝕刻，包含乾蝕刻，濕蝕刻，或乾蝕刻與濕蝕刻的組合。乾蝕刻製程可實施含氟氣體(例如CF4、SF6、CH2F2、CHF3及/或C4F8)、含氯氣體(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如HBr及/或CHBr3)、含氧氣體、含碘氣體、其他適合的氣體及/或電漿，或其組合。蝕刻製程可包含多階段蝕刻，以增加蝕刻選擇性、彈性及得到想要的蝕刻輪廓。
在一些實施例，半導體裝置包含絕緣材料，其沿著鰭12的下部而形成於半導體基底10上。在包含複數個鰭的實施例，絕緣材料在複數個鰭之間形成淺溝槽隔離(shallow trench isolation,STI)區14。淺溝槽隔離區14可包含氧化矽、氮化矽、氮氧化矽、其他適合的材料及其組合。淺溝槽隔離區14可藉由任意適合的製程形成。在一實施例，淺溝槽隔離區 14藉由化學氣相沉積(chemical vapor deposition,CVD)，將一或多層介電材料填入鰭之間的區域而形成。在一些實施例，被填入的區域可具有多層結構，例如填入熱氧化襯層與氮化矽或氧化矽。形成淺溝槽隔離區後，可實施退火製程。退火製程包含快速熱退火(rapid thermal anneal,RTA)、雷射退火製程或其他適合的退火製程。
在一些實施例，淺溝槽隔離區14係利用可流動式化學氣相沉積(flowable CVD)形成。在可流動式化學氣相沉積中，並非沉積氧化矽，而是沉積可流動式介電材料。可流動式介電材料如其名所表明，在沉積的過程中能”流動”以填入具有較高的深寬比(aspect ratio)的缺口或間隙。通常，添加各種化學物質至含矽前驅物，使沉積膜能流動。在一些實施例，添加氮氫鍵。可流動式介電前驅物的示例，特別是可流動式氧化矽前驅物包含矽酸鹽(silicate)、矽氧烷(siloxane)、甲基矽酸鹽(methyl silsesquioxane,MSQ)、氫矽酸鹽(hydrogen silsesquioxane,HSQ)、MSQ/HSQ、全氫矽氮烷(perhydrosilazane,TCPS)、全氫聚矽氮烷(perhydro-polysilazane,PSZ)、四乙氧基矽烷(tetraethyl orthosilicate,TEOS)，或甲矽烷基胺(silyl-amine)，例如三甲矽烷胺(trisilylamine,TSA)。這些可流動式氧化矽材料由多重步驟(multiple-operation)製程形成。沉積可流動式薄膜後，經固化及退火來移除不需要的元素，以形成氧化矽。移除不需要的元素時，可流動式薄膜變得緻密且緊縮。在一些實施例，實施多重退火製程。可流動式薄膜在例如約600.℃至約1200℃的 溫度範圍及例如一小時或總合為更久的延展期間中，經過超過一次的固化及退火。
實施化學機械研磨(chemical mechanical polishing,CMP)步驟，以移除從淺溝槽隔離區多出的材料來提供大抵平坦的表面。接下來，植入摻雜質至鰭，以形成n及p型井區，並且接著使裝置退火。回蝕刻淺溝槽隔離區以移除一部分的淺溝槽隔離區，並且露出鰭的上部，亦即之後用來形成閘極結構及源極/汲極區的地方。形成閘極結構可包含額外的沉積、圖案化及蝕刻製程。藉由適合的蝕刻製程移除淺溝槽隔離區，例如使用HF+NH3之電漿或NF3+NH3之電漿的半等向性蝕刻；或例如使用稀釋的HF之等向性蝕刻。
在一些實施例，如第2圖所示，形成一或多個閘極結構16於鰭結構上。形成閘極結構製程可包含沉積閘極介電層20、沉積閘極電極18及圖案化沉積後的閘極電極成為閘極結構之步驟。接下來，形成側壁間隙物22於閘極結構16上。第3圖係第2圖中沿著線段A-A的剖面圖，其繪示鰭12和閘極結構16的排列。第4圖係第2圖中沿著線段B-B的剖面圖，其繪示位於鰭12的第二區36上的閘極結構16之排列。第4圖及之後的圖式中鰭12上的虛線表示閘極電極包圍鰭之投影。在接下來的圖式，為簡化圖式而未繪示位於閘極電極下方的閘極介電層。
閘極介電層20可包含氧化矽、氮化矽、氮氧化矽、高介電常數介電材料、其他適合的介電材料及/或其組合。在一些實施例，閘極電極18由多晶矽形成，且可包含形成於閘 極電極上的硬遮罩。硬遮罩可由適合的硬遮罩材料，包含SiO2、SiN或SiCN形成。閘極結構可包含額外的層，例如介面層、覆蓋層、擴散/阻擋層、介電層、導電層及其他適合的層，及其組合。閘極電極18可包含任意的其他適合的材料，例如鋁、銅、鈦、鉭、鎢、鉬、氮化鉭、矽化鎳、矽化鈷、錫、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他適合的材料或其組合來取代多晶矽。
在一些實施例，FinFET可由閘極優先(gate first)方法或閘極後製(gate last)方法形成。在使用高介電常數介電層及金屬閘極(HK/MG)的實施例，實施閘極後製方法形成閘極電極。在閘極後製方法中，形成虛置閘極，在之後的高溫退火步驟後，移除虛置(dummy)閘極，並且形成高介電常數介電層及金屬閘極(HK/MG)。
根據本發明的實施例，高介電常數閘極介電層20可包含HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的高介電常數介電材料或其組合。金屬閘極的材料可包含一或多層的Ti、TiN、鈦鋁合金、Al、AlN、Ta、TaN、TaC、TaCN、TaSi、及其類似的材料。
在一些實施例，側壁間隙物22用來補償(offset)後續形成的摻雜區，例如源極/汲極區。側壁間隙物22更可用來設計或修改源極/汲極區(接面)的輪廓。側壁間隙物22可藉由適合的沉積和蝕刻技術形成，並且可包含氮化矽、碳化矽、氮氧化矽、其他適合的材料或其組合。在一些實施例，側壁間 隙物包含複數層。這些層可包含氧化層與位於其上方的氮化物或碳化物層。
來到第5圖，在第一區24非等向性蝕刻鰭12以形成凹陷26。蝕刻步驟藉由適合的慣用的非等向性蝕刻技術實施。
為提升FinFET的效能，需要設置源極/汲極區使其鄰近於閘極電極下方的通道區。形成源極/汲極區，使其接近閘極電極，並再蝕刻凹陷以移除側壁間隙物的下部。在本發明的實施例，蝕刻凹陷持續至移除閘極電極的下部。如第6圖所示，實施等向性蝕刻以移除至少一部分之側壁間隙物22的下部。在一些實施例，持續蝕刻步驟直到蝕刻至位於閘極電極16下方的鰭12的一部分。依據鰭材料和適合的蝕刻技術，選擇利用適合的慣用等向性蝕刻劑以實施等向性蝕刻步驟。然而，如第6圖所示，雖然是等向性蝕刻，卻製造出具有不均勻邊界的擴大的凹陷60。
如第7圖所示，源極或汲極區62包含之後形成於擴大的凹陷60內的輕摻雜區64及重摻雜區66。源極或汲極區62可藉由適當的磊晶技術形成。例如，輕摻雜區64可藉由磊晶沉積半導體材料(例如在PMOS區使用Si或SiGe，在NMOS區使用Si、SiC或SiCP)而形成。重摻雜區66可藉由磊晶沉積半導體材料(例如在PMOS區使用Ge或SiGe，在NMOS區使用SiP或SiCP)而形成，此半導體材料可依據半導體裝置所需的功能，使用適量的已知摻雜質來摻雜。
為了提升半導體製造製程的控制性及半導體操作 參數的控制性，需要形成與閘極電極具有大抵均勻的間隔之源極及汲極區。源極及汲極區之大抵均勻的間隔可藉由在凹陷內形成均勻地摻雜區，之後蝕刻此摻雜區而達成。
如第8圖所示，形成均勻的摻雜區28於凹陷26的表面。摻雜區28可藉由在鰭12內植入摻雜質於大抵上均勻的深度而形成。植入摻雜質於大抵上均勻的深度可藉由共形(conformally)摻雜凹陷26的表面而達成。摻雜區28可以是在鰭12上之在凹陷26的表面具有厚度約從0.5nm至約10nm的一層。在本發明的一些實施例，摻雜區28藉由電漿摻雜而形成。
在一些實施例，在設有感應耦合電漿(inductively coupled plasma,ICP)源的電漿摻雜裝置內實施電漿摻雜。在一些實施例，在摻雜步驟的過程中，半導體晶圓的溫度可維持在40℃以下。摻雜質材料之氣體可以是適合的摻雜質氣體，包含AsH3或B2H6與惰性承載氣體(例如He或Ar)之組合。在一些實施例，摻雜質氣體的質量濃度佔總氣體濃度(摻雜質氣體+承載氣體)約0.01至約5質量%。在一些實施例，在電漿摻雜步驟的過程中，氣體之流速介於約5至約2000cm3/min的範圍。在一些實施例，在摻雜步驟的過程中，電漿摻雜裝置的壓力介於約0.05Pa至約10Pa的範圍。在一些實施例，電漿可在約100W至約2500W的功率下產生。
如第9圖所示，相對於鰭12未被摻雜的部分，可選擇性地蝕刻鰭12表面之均勻的摻雜區28，藉此使凹陷26均勻地延伸至鰭12之位於閘極結構16下方的部分，而形成擴 大的凹陷70。可藉由實施等向性蝕刻技術而選擇性蝕刻摻雜區28。在一些實施例，使用對摻雜區28具有選擇性的液態蝕刻劑。適合的液態蝕刻劑包含硫酸(H2SO4)和過氧化氫(H2O2)之混合物(也被稱為SPM或食人魚(piranha)蝕刻)。
如第10圖所示，源極或汲極區30包含之後形成在擴大的凹陷70內的輕摻雜區32及重摻雜區34，以形成半導體裝置100。源極或汲極區30可藉由一或多道磊晶或外延(epitaxial,epi)製程形成，使得Si部件、SiC部件、SiGe部件、SiP部件、SiCP部件，或其他適合的部件結晶化而形成在鰭上。磊晶製程包含CVD沉積技術(例如，氣相磊晶(vapor-phase epitaxy,VPE)及/或超高真空CVD(ultra-high vacuum CVD,UHV-CVD))、原子層沉積(atomic layer deposition,ALD)、分子束磊晶(molecular beam epitaxy)及/或其他適合的製程。
例如，輕摻雜區32可藉由磊晶沉積半導體材料而形成，例如PMOS區沉積SiGe或Si，NMOS區沉積Si、SiC或SiCP。重摻雜區34可藉由磊晶沉積半導體材料而形成，例如PMOS區沉積Ge或SiGe，NMOS區沉積SiP或SiCP。半導體材料可依據半導體裝置所需的功能，藉由離子佈植摻雜適量的已知摻雜質。
離子佈植可為例如砷或磷，作為NMOS的n型摻雜質，或例如硼作為PMOS的p型摻雜質。在一些實施例，摻雜輕摻雜區32的佈值能量和劑量各別介於約10-60keV及約1×1013-5×1014摻雜質/cm2的範圍間。摻雜重摻雜區34的佈值能量和劑量各別介於約10-80keV及約8×1014-2×1016摻雜質 /cm2的範圍間。源極/汲極區30的摻雜使半導體非晶化，然後再結晶以活化源極/汲極區30。在離子佈植摻雜質後，使半導體裝置退火，例如藉由快速熱退火、毫秒退火或雷射退火，以再結晶源極及汲極區30。
第11圖繪示形成CMOS裝置的其他實施例。CMOS裝置具有複數個區域，包含NMOS區及PMOS區。PMOS和NMOS區一般藉由淺溝槽隔離區來隔開。絕緣層38順應地形成在閘極電極18和鰭12的第一區24上方。在一些實施例，絕緣層38為氮化物層。此步驟僅繪示一個區(NMOS或PMOS)，藉由相同的步驟，在NMOS及PMOS區兩者實施移除摻雜區。
進行至第12圖，非等向性蝕刻絕緣層38，露出鰭12的第一區24，之後非等向性蝕刻鰭12的第一區24而形成凹陷26。利用適合的慣用的非等向性蝕刻技術來實施蝕刻步驟。
如第13圖所示，凹陷26的表面形成均勻的摻雜區28。摻雜區28可藉由電漿摻雜形成，如以下敘述，將摻雜質植入鰭12內至大抵上均勻的深度。可藉由共形摻雜凹陷26的表面使摻雜質植入鰭12內至大抵上均勻的深度。如第14圖所示，如同下述，相對於鰭12未摻雜部分，可選擇性蝕刻凹陷26所畫線之鰭12共形摻雜表面的部分，藉此形成一擴大的凹陷70，其均勻地延伸至鰭12之中，位於閘極結構16下方的部分。
NMOS和PMOS區係各別獨立地形成。例如，如 第15圖所示，當半導體材料磊晶沉積至PMOS區110擴大的凹陷70，以形成包含輕摻雜區42和重摻雜區44的源極或汲極區40時，可遮住NMOS區(未繪示)。可依據半導體裝置所需的功能，藉由適合的磊晶技術形成源極或汲極區40後，使用已知的摻雜質以適當的量離子佈植。在一些實施例，用來形成輕摻雜區42所沉積的半導體材料是Si或SiGe，用來形成重摻雜區44所沉積的半導體材料是SiGe或Ge。
在一些實施例，如第16圖所示，形成PMOS區110後，在磊晶沉積半導體材料至NMOS區120的擴大的凹陷70時，移除位於NMOS區120上的阻擋層，並遮這PMOS區110(未繪示)。NMOS區120包含了包括輕摻雜區48及重摻雜區50的源極或汲極區46。可依據半導體裝置所需的功能，藉由適合的磊晶技術形成源極或汲極區46後，使用已知的摻雜質以適當的量離子佈植後。在一些實施例，用來形成輕摻雜區48所沉積的半導體材料是Si、SiC或SiCP，用來形成重摻雜區50所沉積的半導體材料是SiP或SiCP。形成PMOS和NMOS區步驟是可以互換的。可在遮住PMOS區時，先形成NMOS裡的源極和汲極，並且在之後遮住NMOS區時，形成PMOS裡的源極和汲極。
本發明實施例至今所描述的例示的半導體裝置100是高壓閾(high voltage threshold,HVT)裝置。在本發明實施例的其他實施例形成了標準壓閾(standard voltage threshold,SVT)裝置200及低壓閾(low voltage threshold,LVT)裝置300。
如第17和18圖所示，在本發明一些實施，形成 SVT裝置200。在SVT裝置中，在鰭12內形成的摻雜區28厚度比HVT裝置100的摻雜區28厚。在一些實施例，SVT裝置200的摻雜區28比HVT裝置100的摻雜區28厚約0.5nm至2nm。在SVT裝置200中，在鰭的第二區36內，摻雜區28及隨後形成的源極和汲極區30延伸至閘極電極18下方。
如第19和20圖所示，在本發明一些實施，形成LVT裝置300。在LVT裝置中，在鰭12內形成的摻雜區28厚度比HVT裝置100的摻雜區28厚。在一些實施例，LVT裝置300的摻雜區28比HVT裝置100的摻雜區28厚約0.5nm至2nm。在LVT裝置300中，在鰭的第二區36內，摻雜區28及隨後形成的源極和汲極區30延伸至閘極電極18下方。
在本發明的一些實施例，形成源極/汲極電極接觸至各自的源極/汲極區。電極可由適合的導電材料形成，例如銅、鎢、鎳、鈦或類似材料。在一些實施例，金屬矽化物形成在導電材料和源極/汲極的界面以增加界面的導電性。在一個示例，利用鑲嵌及/或雙鑲嵌製程以形成以銅為基礎的多層內連線結構。在其他實施例，利用鎢形成鎢插塞。
根據本發明的實施例，之後的製程也可形成各種接觸窗/通孔/線及多層內連線部件(例如金屬層和層間介電層)於半導體基底上，配置來連接各種FinFET裝置的部件或結構。例如，多層內連線包含垂直內連線，例如傳統的通孔或接觸窗，以及水平內連線，例如金屬線。
本發明的一實施例提供半導體裝置。半導體裝置包含在基底上沿第一方向延伸的鰭，以及在鰭上沿第二方向延 伸的閘極結構。此閘極結構包含：在鰭上的閘極介電層；在閘極介電層上的閘極電極；以及位於閘極電極的第一橫向表面上，且沿第二方向延伸的第一絕緣閘極間隙物。此半導體裝置亦包含源極/汲極區，其形成於鰭內鄰近於閘極電極的區域內，且源極/汲極區的一部分沿第一方向，以大抵上固定的距離延伸在絕緣閘極間隙物下方。
在一些實施例，其中源極/汲極區延伸於閘極電極下方。
在一些實施例，上述半導體裝置包含複數個沿第二方向延伸的閘極結構於鰭上。
在一些實施例，上述半導體裝置包含複數個沿第一方向延伸的鰭，且前述複數個閘極結構位於這些鰭的每一個鰭之間上方。
在一些實施例，上述半導體裝置更包含沿第二方向延伸的第二絕緣閘極間隙物於閘極電極的相對的第二橫向表面上。
在一些實施例，其中源極/汲極區延伸於相鄰的閘極結構的絕緣閘極間隙物的下方。
本發明的其他實施例提供半導體裝置的製造方法，此方法包含形成沿第一方向延伸的鰭於基底上，及形成沿第二方向延伸的複數個閘極結構於鰭上。閘極結構包含閘極介電層於鰭上、閘極電極於閘極介電層上，及沿第二方向延伸的絕緣閘極間隙物於閘極電極的相對兩側表面上。此製造方法亦包含移除第一區位於相鄰閘極結構間的鰭的一部分，以形成凹 陷於鰭內，形成摻雜區於凹陷的表面上。此製造方法更包含移除摻雜區以形成擴大的凹陷，且形成源極/汲極區於擴大的凹陷的表面上，源極/汲極區沿第二方向延伸於相鄰的閘極電極的絕緣閘極間隙物的下方。
在一些實施例，其中摻雜區係藉由植入摻雜質至凹陷的表面上而形成。
在一些實施例，其中摻雜區係藉由共形的表面摻雜在凹陷的表面內形成具有大抵上均勻厚度的摻雜層而形成。
在一些實施例，其中摻雜區係藉由電漿摻雜而形成。
在一些實施例，其中摻雜層具有約0.5nm至約10nm的厚度。
在一些實施例，其中形成源極/汲極區包含沉積磊晶材料於擴大的凹陷內。
本發明的其他實施例提供半導體裝置的製造方法，此方法包含形成一個或更多個沿第一方向延伸的鰭於基底上，一個或更多個鰭包含至少一個沿第一方向的第二區及在每一個第二區的任一側之沿第一方向的第一區，形成沿第二方向延伸的閘極結構於鰭的第二區上。此閘極結構包含閘極介電層於鰭上、閘極電極於閘極介電層上，及一對沿第二方向延伸的絕緣閘極間隙物形成於閘極電極的相對兩側表面上。此製造方法亦包含移除第一區內的鰭的一部分，以在第一區內形成凹陷，形成摻雜區於凹陷的表面上。此製造方法更包含移除摻雜區以形成擴大的凹陷，及形成源極/汲極區於擴大的凹陷的表 面上，其中源極/汲極區沿第二方向延伸在相鄰的絕緣閘極間隙物下方。
在一些實施例，其中摻雜區係藉由植入摻雜質至凹陷的表面而形成。
在一些實施例，其中摻雜區係藉由共形的表面摻雜在凹陷的表面內形成具有大抵上均勻厚度的摻雜層而形成。
在一些實施例，其中摻雜區係藉由電漿摻雜而形成。
在一些實施例，其中摻雜層具有約0.5nm至約10nm的厚度。
在一些實施例，其中複數個第二區形成在每一個鰭上，且第二區及第一區係沿第一方向交替地形成。
在一些實施例，其中閘極結構係形成在每一個第二區上。
在一些實施例，其中形成源極/汲極區包含沉積磊晶材料在擴大的凹陷內。
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解本發明的概念。所屬技術領域中具有通常知識者能夠理解，其可利用本發明實施例內容作為基礎，以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解，不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作各種之更動、替代與潤飾。
40‧‧‧源極和汲極區
42‧‧‧輕摻雜區
44‧‧‧重摻雜區
100‧‧‧半導體裝置
110‧‧‧PMOS區

Claims (1)

  1. 一種半導體裝置，包括：一鰭，位於一基底上，且沿一第一方向延伸；以及一閘極結構，位於該鰭上，且沿一第二方向延伸；其中該閘極結構包括：一閘極介電層，位於該鰭上；一閘極電極，位於該閘極介電層上；一第一絕緣閘極間隙物，位於該閘極電極的一第一橫向表面上，且沿該第二方向延伸；以及一源極/汲極區，形成於該鰭內鄰近於該閘極結構的一區域內；其中該源極/汲極區的一部分沿該第一方向，以大抵上固定的距離延伸於該絕緣閘極間隙物下方。
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