TW201719874A - Imaging device, module, electronic device, and method of operating the imaging device - Google Patents

Abstract

An imaging device whose dynamic range can be wide with a simple structure is provided. In a circuit configuration and an operation method of the imaging device, whether a charge detection portion provided in a pixel is saturated with electrons is determined and an operation mode is changed depending on the determination result. First imaging data is captured first, and is read out in the case where the charge detection portion is not saturated with electrons. In the case where the charge detection portion is saturated with electrons, the saturation of the charge detection portion is eliminated and second imaging data is captured and read out.

Description

Work of camera, module, electronic device and camera method

One embodiment of the present invention is directed to an image pickup apparatus and a method of operating the same.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the present specification and the like relates to an object, a method or a manufacturing method. Alternatively, one embodiment of the invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in the present specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, and a memory. Devices, imaging devices, methods of operating such devices, or methods of making such devices.

Note that the semiconductor device in the present specification and the like refers to all devices that can operate by utilizing semiconductor characteristics. The transistor and the semiconductor circuit are one embodiment of a semiconductor device. Further, the memory device, the display device, the imaging device, and the electronic device may include a semiconductor device.

As a semiconductor material that can be used for a transistor, an oxide semiconductor is attracting attention. For example, a technique of forming a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor has been disclosed (see Patent Document 1 and Patent Document 2).

In addition, Patent Document 3 discloses an image pickup apparatus in which a transistor including an oxide semiconductor is used for a part of a pixel circuit.

[references]

[Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[Patent Document 2] Japanese Patent Application Publication No. 2007-96055

[Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119711

Now CMOS image sensors are installed in various devices and are expected to improve the camera function. The dynamic range of the conventional CMOS image sensor is from 3 to 4 digits (60 dB to 80 dB), and is required to be increased to 5 to 6 digits (100 dB to 120 dB) equivalent to silver salt film and the naked eye. ).

As a method of increasing the dynamic range, a method of switching the charge storage unit to perform imaging or a method of performing analog data processing in a pixel has been proposed. However, the former requires external control, and thus a device for detecting illuminance or the like is also required. On the other hand, since there are many transistors in the latter pixel, there is a problem of image deterioration due to leakage current or noise of the transistor.

Accordingly, it is an object of one embodiment of the present invention to provide an image pickup apparatus capable of expanding a dynamic range with a simple configuration. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus that changes the sensitivity of a pixel after the first image capture and then performs the second image capture. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus with low power consumption. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus that reads data of a previous frame during an exposure period. Further, an object of one embodiment of the present invention is to provide an image pickup apparatus capable of capturing an image with less noise. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus suitable for high speed operation. Further, it is an object of one embodiment of the present invention to provide a high-resolution imaging apparatus. Further, it is an object of one embodiment of the present invention to provide a highly integrated imaging apparatus. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus capable of performing image pickup in a low illumination environment. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus that can be used over a wide temperature range. Further, it is an object of one embodiment of the present invention to provide an image pickup apparatus having a high aperture ratio. In addition, one embodiment of the present invention One of the purposes of the formula is to provide a highly reliable camera device. Further, it is an object of one embodiment of the present invention to provide a novel image pickup apparatus and the like. Further, it is an object of one embodiment of the present invention to provide a method of operating the above-described image pickup apparatus. Further, it is an object of one embodiment of the present invention to provide a novel semiconductor device or the like.

Note that the records of these topics do not hinder the existence of other topics. Moreover, one embodiment of the present invention does not need to solve all of the above problems. In addition, in the descriptions of the specification, the drawings, and the scope of the patent application, it is apparent that there is a problem other than the above-described problems, and problems other than the above-described problems can be obtained from the descriptions of the specification, the drawings, and the scope of the patent application.

One embodiment of the present invention relates to an image pickup apparatus capable of automatically changing the sensitivity of a pixel to perform imaging.

One embodiment of the present invention is an image pickup apparatus including first to sixth transistors, a photoelectric conversion element, a first capacitor, and a second capacitor, wherein one electrode of the photoelectric conversion element and a source of the first transistor And electrically connected to one of the drain electrodes, one of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, the source and the drain of the first transistor The other one is electrically connected to one of the source and the drain of the third transistor, and the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fourth transistor. The other of the source and the drain of the first transistor is electrically connected to the gate electrode of the fifth transistor, and the other of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor The other of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor, one of the source and the drain of the fifth transistor and the source and the drain of the sixth transistor An electrical connection, a first transistor, a second transistor, Three transistor and a fourth transistor including an oxide semiconductor region formed in the channel.

The oxide semiconductor preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). In addition, the fifth transistor and the sixth transistor may also include an oxide semiconductor in a region where the channel is formed.

In the photoelectric conversion element, selenium or a compound containing selenium may be used for the photoelectric conversion layer. For example, as selenium, amorphous selenium or crystalline selenium can be used.

Another embodiment of the present invention is an image pickup apparatus including a pixel, a first circuit, a second circuit, a third circuit, a fourth circuit, and a fifth circuit, wherein the pixel is electrically connected to the first circuit, the first circuit and the first The second circuit is electrically connected, the second circuit is electrically connected to the third circuit, the second circuit is electrically connected to the fourth circuit, the third circuit is electrically connected to the fifth circuit, the fifth circuit is electrically connected to the pixel, and the pixel has the first camera data. Or a function of the second image data, the pixel having a function of storing the first image data or the second image data in the charge storage portion, the pixel having the first image data or the second image data stored in the charge storage portion is transferred to The function of the charge detecting unit, the first circuit having a signal obtained by adding an absolute value of a difference between a potential corresponding to the second image data and a potential corresponding to the reset potential of the charge detecting portion to the reference potential or The function of the signal obtained by subtracting the absolute value from the potential, the second circuit has a function of determining whether or not the charge detecting unit is saturated by the first imaging data, and the third The circuit has a function of outputting a signal that does not acquire the second imaging material to the pixel by the fifth circuit in the case where it is determined that the charge detecting portion is not saturated, and the third circuit has the function of eliminating the charge detecting portion in the case where it is determined that the charge detecting portion is saturated The function of outputting a signal for acquiring the second image data to the pixel by the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data.

Another embodiment of the present invention is an operation method of an image pickup apparatus that performs the following steps in the nth (n is a natural number of 1 or more) frame period in order to reset the potential of the charge storage portion a second step of storing a charge in the charge storage portion; a third step of resetting the potential of the charge detecting portion; a fourth step of transferring the potential of the charge storage portion to the charge detecting portion; and reading and charging The fifth step of determining the presence or absence of saturation of the charge detecting unit based on the signal corresponding to the potential of the detecting unit. When it is determined in the fifth step that the charge detecting portion is saturated, the following steps are performed in order: a sixth step of resetting the potential of the charge storage portion; a seventh step of storing the charge in the charge storage portion; temporarily increasing the charge detection The capacity of the portion, the eighth step of eliminating saturation of the charge detecting portion; and the ninth step of transferring the potential of the charge storage portion to the charge detecting portion, and the first step and the period during the (n+1)th frame period At the same time as the two steps, a signal corresponding to the potential of the charge detecting portion of the ninth step of the nth period is read. When it is determined in the fifth step that the charge detecting portion is not saturated, the first step and the second step of the (n+1)th frame period are read out simultaneously with the charge detecting portion of the fourth step of the nth billing period. The signal corresponding to the potential.

One embodiment of the present invention is an image pickup apparatus including first to seventh transistors, a photoelectric conversion element, a first capacitor, a second capacitor, and a third capacitor, wherein one electrode of the photoelectric conversion element and the first electricity One of the source and the drain of the crystal is electrically connected, first One of a source and a drain of the transistor is electrically connected to one of a source and a drain of the second transistor, and the other of the source and the drain of the first transistor and the source of the third transistor Electrically connected to one of the drain electrodes, the other of the source and the drain of the first transistor being electrically connected to one of the source and the drain of the fourth transistor, the source and the drain of the first transistor The other of the electrodes is electrically connected to the gate electrode of the fifth transistor, and the other of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, and the source and the drain of the fourth transistor The other of the electrodes is electrically connected to one electrode of the second capacitor, and one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor, and the gate of the fourth transistor The pole is electrically connected to one of the source and the drain of the seventh transistor, and the gate of the fourth transistor is electrically connected to one electrode of the third capacitor, the first transistor, the second transistor, the third transistor, The fourth transistor and the seventh transistor include an oxide semiconductor in a region where the channel is formed.

The oxide semiconductor preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). In addition, the fifth transistor and the sixth transistor may also include an oxide semiconductor in a region where the channel is formed.

In the photoelectric conversion element, selenium or a compound containing selenium may be used for the photoelectric conversion layer. For example, as selenium, amorphous selenium or crystalline selenium can be used.

Another embodiment of the present invention is an image pickup apparatus including a pixel, a first circuit, a second circuit, a third circuit, and a fourth circuit, wherein the pixel includes a charge storage portion and a charge detecting portion, and the charge detecting portion and the first capacitor And the second capacitor is electrically connected, the pixel is electrically connected to the first circuit, the first circuit is electrically connected to the second circuit, the second circuit is electrically connected to the third circuit, the second circuit is electrically connected to the fourth circuit, and the third circuit and the pixel are electrically connected Electrically connected, the pixel has a function of acquiring the first image data or the second image data, and the pixel has a function of storing the first image data or the second image data in the charge storage portion, and the pixel has a portion to be stored in the charge storage portion a function of transmitting the image data or the second image data to the charge detecting portion, the first circuit having an absolute value of a difference between a potential corresponding to the second image data and a potential corresponding to the reset potential of the charge detecting portion a function of a signal obtained by adding a reference potential or a signal obtained by subtracting the absolute value from a reference potential, the second circuit having a determination charge detection The function of saturating the first image data, and the third circuit has a function of outputting a signal that causes the charge detecting portion and one electrode of the second capacitor to be non-conductive to the pixel when the charge detecting portion is not saturated. The third circuit has an electrode that will cause the charge detecting portion and the second capacitor in the case where it is determined that the charge detecting portion is saturated a function of outputting a signal in an on state to a pixel, the pixel having a function of transferring the second image data from the charge storage portion to the charge detecting portion after the determination, the second circuit and the fourth circuit having the output of the first circuit The function of converting signals into digital data.

Another embodiment of the present invention is an operation method of an image pickup apparatus that performs the following steps in the nth (n is a natural number of 1 or more) frame period in order to reset the potential of the charge storage portion a second step of storing a charge in the charge storage portion; a third step of resetting the potential of the charge detecting portion; a fourth step of transferring the potential of the charge storage portion to the charge detecting portion; and reading and charging The fifth step of determining the presence or absence of saturation of the charge detecting unit based on the signal corresponding to the potential of the detecting unit. When it is determined in the fifth step that the charge detecting portion is saturated, the following steps are performed in order: a sixth step of increasing the capacity of the charge detecting portion; and a seventh step of resetting the potential of the charge detecting portion. When it is determined in the fifth step that the charge detecting portion is not saturated, the seventh step is performed, and in the fifth step to the seventh step, the following steps are sequentially performed: an eighth step of resetting the potential of the charge storage portion; and The ninth step of storing the charge in the charge storage portion, and performing the tenth step of transferring the potential of the charge storage portion to the charge detecting portion, in the first step and the second step of the (n+1)th frame period At the same time, a signal corresponding to the potential of the charge detecting portion in the tenth step of the nth period is read.

By using one embodiment of the present invention, it is possible to provide an image pickup apparatus capable of expanding the dynamic range with a simple structure. In addition, it is possible to provide an image pickup apparatus that changes the sensitivity of the pixel after the first image capture and then performs the second image pickup. In addition, a low power consumption camera device can be provided. In addition, it is possible to provide an image pickup apparatus that reads out the material of the previous frame during the exposure period. In addition, it is possible to provide an image pickup apparatus capable of capturing an image with less noise. In addition, an image pickup apparatus suitable for high speed operation can be provided. In addition, a high-resolution imaging device can be provided. In addition, a highly integrated camera device can be provided. In addition, it is possible to provide an image pickup apparatus capable of performing imaging in a low illumination environment. In addition, an image pickup apparatus that can be used over a wide temperature range can be provided. In addition, an image pickup device having a high aperture ratio can be provided. In addition, a highly reliable image pickup device can be provided. In addition, a novel imaging device or the like can be provided. In addition, a method of operating the above-described image pickup apparatus can be provided. In addition, a novel semiconductor device or the like can be provided.

Note that one embodiment of the present invention is not limited to these effects. For example, one embodiment of the present invention may have effects other than those effects depending on the situation or situation. Or, for example, One embodiment of the present invention sometimes does not have the above effects depending on the situation or situation.

10‧‧‧ pixels

11‧‧‧Pixel Array

12‧‧‧ Circuitry

13‧‧‧ Circuitry

14‧‧‧ Circuitry

15‧‧‧ Circuitry

16‧‧‧ Circuitry

17‧‧‧ Comparator circuit

18‧‧‧Determination of output circuit

19‧‧‧Counting circuit

20‧‧ ‧ pixels

21‧‧‧Pixel Array

22‧‧‧ Circuitry

23‧‧‧ Circuitry

24‧‧‧ Circuitry

25‧‧‧ Circuitry

27‧‧‧ Comparator circuit

28‧‧‧Determining the output circuit

29‧‧‧Counting circuit

35‧‧‧Substrate

41‧‧‧Optoelectronics

42‧‧‧Optoelectronics

43‧‧‧Optoelectronics

44‧‧‧Optoelectronics

45‧‧‧Optoelectronics

46‧‧‧Optoelectronics

51‧‧‧Optoelectronics

52‧‧‧Optoelectronics

53‧‧‧Optoelectronics

54‧‧‧Optoelectronics

61‧‧‧Wiring

62‧‧‧Wiring

63‧‧‧Wiring

64‧‧‧Wiring

65‧‧‧Wiring

71‧‧‧Wiring

71a‧‧‧ Conductive layer

71b‧‧‧ Conductive layer

72‧‧‧Wiring

73‧‧‧Wiring

74‧‧‧Wiring

75‧‧‧Wiring

80‧‧‧Insulation

81‧‧‧Electric conductor

82‧‧‧Insulation

82a‧‧‧Insulation

82b‧‧‧Insulation

83‧‧‧Insulation

88‧‧‧Wiring

91‧‧‧Wiring

92‧‧‧Wiring

93‧‧‧Wiring

94‧‧‧Wiring

101‧‧‧Optoelectronics

102‧‧‧Optoelectronics

103‧‧‧Optoelectronics

104‧‧‧Optoelectronics

105‧‧‧Optoelectronics

106‧‧‧Optoelectronics

107‧‧‧Optoelectronics

108‧‧‧Optoelectronics

109‧‧‧Optoelectronics

110‧‧‧Optoelectronics

111‧‧‧Optoelectronics

112‧‧‧Optoelectronics

113‧‧‧Optoelectronics

115‧‧‧Substrate

120‧‧‧Insulation

130‧‧‧Oxide semiconductor layer

130a‧‧‧Oxide semiconductor layer

130b‧‧‧Oxide semiconductor layer

130c‧‧‧Oxide semiconductor layer

140‧‧‧ Conductive layer

141‧‧‧ Conductive layer

142‧‧‧ Conductive layer

150‧‧‧ Conductive layer

151‧‧‧ Conductive layer

152‧‧‧ Conductive layer

160‧‧‧Insulation

170‧‧‧ Conductive layer

171‧‧‧ Conductive layer

172‧‧‧ Conductive layer

173‧‧‧ Conductive layer

175‧‧‧Insulation

180‧‧‧Insulation

190‧‧‧Insulation

231‧‧‧ Area

232‧‧‧Area

233‧‧‧Area

331‧‧‧Area

332‧‧‧Area

333‧‧‧Area

334‧‧‧Area

335‧‧‧Area

During the period of 400‧‧

401‧‧‧

During the period of 402‧‧

403‧‧‧

561‧‧‧Photoelectric conversion layer

562‧‧‧Light conductive layer

563‧‧‧Semiconductor layer

564‧‧‧Semiconductor layer

565‧‧‧Semiconductor layer

566‧‧‧electrode

566a‧‧‧ Conductive layer

566b‧‧‧ Conductive layer

567‧‧‧ partition wall

568‧‧‧ hole injection into the barrier layer

569‧‧‧Electronic injection barrier layer

600‧‧‧矽 substrate

610‧‧‧Optoelectronics

620‧‧‧Optoelectronics

650‧‧‧active layer

660‧‧‧矽 substrate

741‧‧‧Optoelectronics

742‧‧‧Optoelectronics

743‧‧‧Optoelectronics

744‧‧‧Optoelectronics

745‧‧‧Optoelectronics

746‧‧‧Optoelectronics

747‧‧‧Optoelectronics

751‧‧‧Optoelectronics

752‧‧‧Optoelectronics

753‧‧‧Optoelectronics

754‧‧‧Optoelectronics

761‧‧‧ wiring

762‧‧‧Wiring

763‧‧‧Wiring

764‧‧‧Wiring

765‧‧‧Wiring

771‧‧‧Wiring

772‧‧‧Wiring

773‧‧‧Wiring

774‧‧‧Wiring

775‧‧‧Wiring

791‧‧‧Wiring

792‧‧‧Wiring

793‧‧‧Wiring

794‧‧‧Wiring

810‧‧‧Package substrate

811‧‧‧Package substrate

820‧‧‧glass cover

821‧‧‧Lens cover

830‧‧‧Binder

835‧‧‧ lens

840‧‧‧Bumps

841‧‧‧ pads

850‧‧‧Image sensor chip

851‧‧‧Image sensor chip

860‧‧‧disk electrode

861‧‧‧ disc electrode

870‧‧‧ line

871‧‧‧ line

880‧‧‧through hole

885‧‧‧ pads

890‧‧‧ IC chip

901‧‧‧Shell

902‧‧‧ Shell

903‧‧‧ indicates the Ministry

904‧‧‧ indicates the Ministry

905‧‧‧ microphone

906‧‧‧Speaker

907‧‧‧ operation keys

908‧‧‧ stylus

909‧‧‧ camera

911‧‧‧ Shell

912‧‧‧Display Department

919‧‧‧ camera

931‧‧‧ Shell

932‧‧‧Display Department

933‧‧‧ wristband

935‧‧‧ button

936‧‧‧ crown

939‧‧‧ camera

951‧‧‧Shell

952‧‧‧ lens

953‧‧‧Support

961‧‧‧Shell

962‧‧‧Shutter button

963‧‧‧ microphone

965‧‧ lens

967‧‧‧Lighting Department

971‧‧‧Shell

972‧‧‧Shell

973‧‧‧Display Department

974‧‧‧ operation keys

975‧‧‧ lens

976‧‧‧Connecting Department

1100‧‧ layer

1200‧‧ ‧

1400‧‧ layer

1500‧‧‧diffraction grating

1600‧‧ layer

2500‧‧‧Insulation

2510‧‧‧Lighting layer

2520‧‧‧Organic resin layer

2530‧‧‧Color filters

2530a‧‧‧Color filters

2530b‧‧‧Color filters

2530c‧‧‧Color filters

2540‧‧‧Microlens array

2550‧‧‧Optical conversion layer

2560‧‧‧Insulation

1A and 2B are block diagrams illustrating a top view of an image pickup apparatus, a circuit diagram of a CDS circuit, and an A/D conversion circuit; and FIGS. 3A and 3B are determination output circuits and pixels. FIG. 4 is a timing chart illustrating the operation of the imaging device and FIG. 6 is a flowchart illustrating the operation of the imaging device; FIG. 6 is a timing chart illustrating the operation of the imaging device; FIG. 7A and FIG. 7B is a timing chart illustrating the operation of the CDS circuit and the comparator circuit; FIG. 8 is a timing chart illustrating the operation of the image pickup apparatus; FIG. 9 is a diagram illustrating the pixel circuit; FIGS. 10A and 10B are diagrams illustrating the pixel circuit; FIG. 12 is a timing diagram illustrating the operation of the image pickup apparatus; FIG. 13A is a diagram illustrating a pixel circuit; FIG. 14 is a diagram illustrating a pixel circuit; FIG. 15A to FIG. FIG. 16A to FIG. 16C are cross-sectional views illustrating the structure of the image pickup apparatus; FIGS. 17A to 17C are diagrams illustrating the operation of the image pickup apparatus; FIGS. 18A to 18C are diagrams illustrating photoelectric conversion. FIG. 19A to FIG. 19D are cross-sectional views illustrating a connection manner of a photoelectric conversion element; FIGS. 20A and 20B are cross-sectional views illustrating a connection manner of the photoelectric conversion element; and FIG. 21 is a cross-sectional view illustrating the image pickup apparatus. 22A to 22C are cross-sectional views illustrating a connection mode of the photoelectric conversion element; FIG. 23 is a cross-sectional view illustrating the image pickup apparatus; FIGS. 24A and 24B are cross-sectional views illustrating the image pickup apparatus; and FIGS. 25A to 25C are diagrams illustrating the image pickup apparatus FIG. 26 is a cross-sectional view illustrating the image pickup apparatus; FIG. 27 is a cross-sectional view illustrating the image pickup apparatus; 28 is a cross-sectional view illustrating the structure of the image pickup apparatus, FIG. 30 is a cross-sectional view illustrating the structure of the image pickup apparatus, and FIG. 31 is a cross-sectional view illustrating the structure of the image pickup apparatus; FIG. 33A is a circuit diagram illustrating a pixel; FIG. 34A and FIG. FIG. 35 is a circuit diagram illustrating the operation of the determination output circuit; FIG. 37 is a flowchart illustrating the operation of the image pickup apparatus; FIG. 38 is a flowchart illustrating the operation of the image pickup apparatus FIG. 39A and FIG. 39B are timing charts illustrating the operation of the CDS circuit and the comparator circuit; FIG. 40 is a diagram illustrating a pixel circuit; FIGS. 41A and 41B are diagrams illustrating a pixel circuit; FIG. 43A and FIG. 43B are diagrams illustrating a pixel circuit; FIG. 44 is a view illustrating a pixel circuit; FIGS. 45A to 45F are plan views and cross-sectional views illustrating the transistor; FIGS. 46A to 46F are diagrams FIG. 47A to FIG. 47D are diagrams illustrating a cross section of the transistor in the channel width direction; FIGS. 48A to 48F are diagrams illustrating a cross section of the transistor in the channel length direction; FIGS. 49A to 49E are FIGS. 4A to 50F are a plan view and a cross-sectional view of the transistor; FIGS. 51A to 51F are a plan view and a cross-sectional view of the transistor; and FIGS. 52A to 52D are diagrams illustrating the transistor. FIG. 53A to FIG. 53F are diagrams illustrating a cross section of a transistor in a channel length direction; FIGS. 54A and 54B are a plan view and a cross-sectional view illustrating a transistor; and FIGS. 55A to 55C are diagrams illustrating a transistor. FIG. 56A to FIG. 56E are diagrams illustrating structural analysis of CAAC-OS and single crystal oxide semiconductor obtained by XRD and a diagram showing selected area electronic diffraction patterns of CAAC-OS; FIGS. 57A to 57E are diagrams Profile TEM image, planar TEM image and image of CAAC-OS FIG. 58A to FIG. 58D are electron diffraction patterns of nc-OS and cross-sectional TEM images of nc-OS; FIGS. 59A and 59B are cross-sectional TEM images of a-like OS; FIG. 60 is an In view of electron irradiation. FIG. 61A to FIG. 61D are a perspective view and a cross-sectional view of a package accommodating an image pickup device; and FIGS. 62A to 62D are a perspective view and a cross-sectional view of a package accommodating the image pickup device; 63A to 63F are diagrams illustrating an electronic device.

The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the present invention can be modified without departing from the spirit and scope of the present invention. For a variety of forms. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. It is to be noted that, in the structures of the invention described below, the same component symbols are used in the different drawings to denote the same parts or the parts having the same functions, and the repeated description thereof is omitted. Note that the shadows of the same components are sometimes omitted or changed as appropriate in different drawings.

In addition, the first and second ordinal numerals are added for convenience, and they do not indicate a process sequence or a stacking order. Therefore, for example, "first" may be appropriately replaced with "second" or "third" or the like for explanation. Further, the ordinal numbers described in the present specification and the like sometimes do not coincide with the ordinal numbers used to designate one embodiment of the present invention.

For example, in the present specification and the like, when explicitly referred to as "X and Y connection", it means that X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship (for example, a connection relationship such as a drawing or a text), and a connection relationship other than the connection relationship shown in the drawings or the text is also included in the contents described in the drawings or the text.

Here, X and Y are objects (for example, devices, components, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, it can be exemplified that there is no between X and Y. Connecting elements capable of electrically connecting X and Y (such as switches, transistors, capacitors, inductors, resistive elements, diodes, display elements, light-emitting elements, loads, etc.), and X and Y are not electrically connected to X and A case where a component of Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor element, a diode, a display element, a light-emitting element, a load, etc.) is connected.

As an example of the case where X and Y are electrically connected, for example, one or more elements capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistance element, and a diode) may be connected between X and Y. , display components, light-emitting components, loads, etc.). In addition, the switch has the function of controlling the opening and closing. In other words, whether or not current is caused to flow is controlled by turning the switch in an on state (on state) or a non-conduction state (off state). Alternatively, the switch has the function of selecting and switching the current path. In addition, the case where X and Y are electrically connected includes a case where X and Y are directly connected.

As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y may be connected between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR) Circuit, etc.), signal conversion circuit (D/A conversion circuit, A/D conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), change signal potential Level level transfer circuit, etc.), voltage source, current source, switching circuit, amplifier circuit (circuit capable of increasing signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit) Etc.), signal generation circuit, memory circuit, control circuit, etc.). Note that, for example, even if other circuits are sandwiched between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected. In addition, the case where X and Y are functionally connected includes a case where X and Y are directly connected, and a case where X and Y are electrically connected.

Further, when explicitly described as "X and Y electrical connection", in the present specification and the like, it means that X and Y are electrically connected (that is, X and Y are connected in such a manner that other elements or other circuits are interposed therebetween). X; Y is functionally connected (ie, X and Y are functionally connected in such a way as to have other circuits in between); X is directly connected to Y (ie, without other components or other circuits in between) Way to connect X and Y). In other words, in the present specification and the like, the case where it is clearly described as "electrical connection" is the same as the case where it is clearly described as "connected".

Note that, for example, the source (or the first terminal, etc.) of the transistor is electrically connected to X by Z1 (or not by Z1), and the drain (or second terminal, etc.) of the transistor is by Z2 (or not) By Z2) connected to Y and in the source (or first terminal, etc.) of the transistor and part of Z1 Direct connection, another part of Z1 is directly connected to X, the drain of the transistor (or the second terminal, etc.) is directly connected to a part of Z2, and the other part of Z2 is directly connected to Y, which can be expressed as follows.

For example, it can be expressed as "X, Y, the source of the transistor (or the first terminal, etc.) and the gate of the transistor (or the second terminal, etc.) are electrically connected to each other, X, the source of the transistor (or the first The terminal, etc.), the drain of the transistor (or the second terminal, etc.) and the Y are sequentially electrically connected. Alternatively, it can be expressed as "the source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and the source of X, the transistor (or One terminal, etc.), the drain of the transistor (or the second terminal, etc.) is electrically connected to Y in sequence. Alternatively, it can be expressed as "X is electrically connected to Y by the source (or first terminal, etc.) of the transistor and the drain (or the second terminal, etc.), X, the source of the transistor (or the first terminal, etc.) The drain of the transistor (or the second terminal, etc.) and Y are sequentially arranged to be connected to each other. By specifying the connection order in the circuit configuration using the same representation method as the above example, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical range.

In addition, as another display method, for example, “the source (or the first terminal, etc.) of the transistor may be electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path. The second connection path is a path between a source (or a first terminal, etc.) of the transistor and a drain (or a second terminal, etc.) of the transistor, the first connection path being a path through Z1, the transistor The drain (or the second terminal, etc.) is electrically connected to Y through at least a third connection path, the third connection path does not have the second connection path, and the third connection path is a path by Z2. Alternatively, the source (or the first terminal or the like) of the transistor may be electrically connected to the X through at least the first connection path, and the first connection path does not have the second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to the Y through at least the third connection path, and the third connection path does not have the Two connection paths". Alternatively, the source (or the first terminal, etc.) of the transistor may be electrically connected to at least the first electrical path, and the first electrical path does not have the second electrical path. The second electrical path is an electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor passes at least the third The electrical path is electrically connected to Y by Z2, the third electrical path does not have a fourth electrical path, the fourth electrical path is from the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the electrical path of the first terminal, etc.). By using the same representation as this example The method stipulates the connection path in the circuit structure, and can distinguish the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) to determine the technical range.

Note that this representation method is only an example and is not limited to the above representation method. Here, X, Y, Z1, and Z2 are objects (for example, devices, components, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

In addition, even if the drawings show that the individual components on the circuit diagram are electrically connected to each other, there is a case where one component has the function of a plurality of components. For example, when a part of the wiring is used as an electrode, one conductive film functions as both the wiring and the two components of the electrode. Therefore, the term "electrical connection" in the present specification also includes the case where such a conductive film has the function of a plurality of components.

In addition, depending on the situation or state, the words "film" and "layer" can be interchanged. For example, it is sometimes possible to change the "conductive layer" to a "conductive film." In addition, it is sometimes possible to change the "insulation film" to the "insulation layer".

In addition, in general, the potential (voltage) is relative, and its magnitude is determined by the difference from the reference potential. Therefore, when it is described as "ground", "GND", etc., the potential is not necessarily limited to 0V. For example, there is a case where "ground" or "GND" is defined based on the lowest potential in the circuit. Alternatively, "ground" or "GND" may be defined based on the intermediate potential in the circuit. Next, the positive potential and the negative potential are defined based on the potential.

Embodiment 1

In the present embodiment, an image pickup apparatus according to an embodiment of the present invention will be described with reference to the drawings.

One embodiment of the present invention is a circuit configuration and an operation method of an image pickup apparatus capable of determining a saturation state of electrons of a charge detecting portion provided in a pixel and changing an operation mode according to a determination result. First, the first imaging data is acquired, and when the charge detecting unit is not saturated, the first imaging data is directly read. When the charge detecting unit is saturated, the saturation of the charge detecting unit is eliminated, and the second image data is acquired and read. The first imaging material corresponds to image data corresponding to low illumination, and the second imaging data corresponds to image data corresponding to high illumination.

With the above work, it is possible to acquire an image with a wide dynamic range in which the noise is small and the gray scale is maintained even in a low illumination environment. In addition, even if the image is taken in an environment containing high illumination, the gray scale of the bright portion can be maintained, and an image with a wide dynamic range can be obtained.

1 is a circuit diagram of a pixel 10 included in an image pickup apparatus according to an embodiment of the present invention. An example in which an n-ch type transistor is used as a transistor is shown in FIG. 1 and the like, but one embodiment of the present invention is not limited thereto, and a part of the transistor may also use a p-ch type transistor instead of the n-ch type. Transistor.

In the pixel 10, one electrode of the photoelectric conversion element PD is electrically connected to one of the source and the drain of the transistor 41. One of the source and the drain of the transistor 41 is electrically connected to one of the source and the drain of the transistor 42. The other of the source and the drain of the transistor 41 is electrically connected to one of the source and the drain of the transistor 43. The other of the source and the drain of the transistor 41 is electrically connected to one of the source and the drain of the transistor 44. The other of the source and the drain of the transistor 41 is electrically connected to the gate of the transistor 45. The other of the source and the drain of the transistor 41 is electrically connected to one electrode of the capacitor C1. The other of the source and the drain of the transistor 44 is electrically connected to one electrode of the capacitor C2. One of the source and the drain of the transistor 45 is electrically connected to one of the source and the drain of the transistor 46.

Here, a node AN connecting one electrode of the photoelectric conversion element PD, one of the source and the drain of the transistor 41, and one of the source and the drain of the transistor 42 is referred to as a charge storage portion. Further, one of the source and the drain of the transistor 41, one of the source and the drain of the transistor 43, one of the source and the drain of the transistor 44, and the gate of the transistor 45 are A node FD to which one electrode of the capacitor C1 is connected is referred to as a charge detecting portion.

The other electrode of the photoelectric conversion element PD is electrically connected to the wiring 71 (VPD). The other of the source and the drain of the transistor 42 and the other of the source and the drain of the transistor 43 are electrically connected to the wiring 72 (VRS). The other electrode of the capacitor C1 and the other electrode of the capacitor C2 are electrically connected to the wiring 73 (VSS). The other of the source and the drain of the transistor 45 is electrically connected to the wiring 74 (VPI). The other of the source and the drain of the transistor 46 is electrically connected to the wiring 91 (OUT1).

In the connection method of each of the above components, a case where a plurality of transistors or a plurality of capacitors are electrically connected to a common wiring is shown as an example, but a plurality of transistors or a plurality of capacitors may be divided. Do not electrically connect to different wiring.

The wiring 71 (VPD), the wiring 72 (VRS), the wiring 73 (VSS), and the wiring 74 (VPI) may have the function of a power supply line. For example, the wiring 71 (VPD) and the wiring 73 (VSS) can be used as a low potential power supply line. Wiring 72 (VRS) and wiring 74 (VPI) can be used as a high potential power line.

The gate of the transistor 41 is electrically connected to the wiring 61 (TX). The gate of the transistor 42 is electrically connected to the wiring 62 (GWRS). The gate of the transistor 43 is electrically connected to the wiring 63 (RS). The gate of the transistor 44 is electrically connected to the wiring 64 (CN). The gate of the transistor 46 is electrically connected to the wiring 65 (SE).

The wiring 61 (TX), the wiring 62 (GWRS), the wiring 63 (RS), the wiring 64 (CN), and the wiring 65 (SE) can be used as signal lines for controlling conduction of the transistors connected to these wirings. The wiring 63 (RS) and the wiring 65 (SE) can be controlled in rows.

The transistor 41 can be used as a transistor that transmits the potential of the node AN to the node FD. The transistor 42 can be used as a transistor for resetting the potential of the node AN. The transistor 43 can be used as a transistor for resetting the potential of the node FD. The transistor 44 can be used as a transistor that controls the electrical connection between the node FD and the capacitor C2 and divides the electrons stored in the node FD. The transistor 45 can be used as a transistor that outputs according to the potential of the node FD. The transistor 46 can be used as a transistor for selecting the pixel 10.

Note that the configuration of the above-described pixel 10 is an example, and sometimes does not include a part of the circuit, a part of the transistor, a part of the capacitor, or a part of the wiring or the like. Further, a circuit, a transistor, a capacitor, a wiring, and the like which are not included in the above configuration may be included. Further, the connection method of a part of the wiring may be different from the connection method of the above structure.

Fig. 2A is a view for explaining an image pickup apparatus according to an embodiment of the present invention. The image pickup apparatus includes: a pixel array 11 including pixels 10 arranged in a matrix; a circuit 12 (row driver) having a function of driving the pixels 10; and CDS (Correlated Double Sampling) operation on an output signal of the pixel 10. Circuit 13 (CDS circuit); circuit 14 (A/D conversion circuit or the like) having a function of determining the presence or absence of saturation of the node FD and converting the analog data output from the circuit 13 into digital data; having a selection pass circuit 24 The circuit 15 (column driver) of the function read out by the converted data; and the change of the pixel according to the saturation of the node FD A mode circuit 16 (pixel control circuit). Alternatively, a configuration in which the circuit 13 is not provided may be employed.

2B is a circuit diagram of a circuit 13 connected to one column of the pixel array 11 and a block diagram of the circuit 14. The circuit 13 may include a transistor 51, a transistor 52, a transistor 53, a capacitor C3, and a capacitor C4. Additionally, circuit 14 may include comparator circuit 17, decision output circuit 18, and counting circuit 19.

The transistor 54 has the function of a current source circuit. One of the source and the drain of the transistor 54 is electrically connected to the wiring 91 (OUT1), and the other of the source and the drain is connected to the power supply line. The power line can be, for example, a low potential power line. Further, the gate of the transistor 54 is biased uninterruptedly.

In the pixel 13, one of the source and the drain of the transistor 51 is electrically connected to one of the source and the drain of the transistor 52. One of the source and the drain of the transistor 51 is electrically connected to one electrode of the capacitor C3. The other of the source and the drain of the transistor 52 is electrically connected to one of the source and the drain of the transistor 53. The other of the source and the drain of the transistor 52 is electrically connected to one electrode of the capacitor C4. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 92 (OUT2). The other of the source and the drain of the transistor 53 and the other electrode of the capacitor C3 are electrically connected to the wiring 91 (OUT1). The other of the source and the drain of the transistor 51 is electrically connected, for example, to a high potential power supply line (CDSVDD) to which a reference potential is supplied. The other electrode of the capacitor C4 is electrically connected, for example, to a low potential power line (CDSVSS).

An example of the operation of the circuit 13 when connected to the pixel 10 shown in Fig. 1 will be described. First, the transistor 51 and the transistor 52 are turned on. Next, the potential of the image data is output from the pixel 10 to the wiring 91 (OUT1), and the reference potential (CDSVDD) is held in the wiring 92 (OUT2). Then, the transistor 51 is turned off, and the reset potential (here, a potential higher than the potential of the image data, for example, the VDD potential) is output from the pixel 10 to the wiring 91 (OUT1). At this time, the potential of the wiring 92 (OUT2) is a potential obtained by adding the absolute value of the difference between the potential of the imaging material and the reset potential to the reference potential (CDSVDD). Therefore, a potential signal having a small amount of noise obtained by adding a potential of the substantial imaging material to the reference potential (CDSVDD) can be supplied to the circuit 14.

Further, when the reset potential is lower than the potential of the image data (for example, GND potential or the like), the potential of the wiring 92 (OUT2) is the potential and weight of the image data subtracted from the reference potential (CDSVDD). The potential obtained by setting the absolute value of the difference between the potentials.

Further, when the transistor 53 is turned on, a bypass is formed, whereby the signal of the wiring 91 (OUT1) can be directly output to the wiring 92 (OUT2).

In the circuit 14, the signal potential input from the circuit 13 is compared with the reference potential (REF) by the comparator circuit 17. The signal potential corresponding to the first image data or the second image data is input to the comparator circuit 17 by the wiring 92 (OUT2). Here, the first imaging material is the first exposure data, and is used to determine the presence or absence of saturation of the node FD of the pixel 10. The second imaging material is the second exposure data obtained based on the determination.

First, when the first imaging material is input, the comparator circuit 17 outputs the determination result to the determination output circuit 18. The determination output circuit 18 has a function of adjusting the output timing to remove the noise output from the comparator circuit 17.

The comparator circuit 17 determines whether the first image data saturates the node FD of the pixel 10. At this time, the reference potential (REF) input to the comparator circuit 17 is a fixed potential corresponding to the saturation of the node FD. The presence or absence of saturation is determined by comparing the potential with a signal potential corresponding to the first imaging data. In the present embodiment, the circuit circuit 13 inputs a signal potential corresponding to the first image data to the comparator circuit 17, but the signal potential corresponding to the first image data may be input to the comparator circuit 17 in a manner that does not bypass the circuit 13. .

When it is determined that the node FD is not saturated, it is determined that the output circuit 18 outputs a signal that does not acquire the second imaging material to the circuit 16. Therefore, the signal potential corresponding to the first image data is input to the comparator circuit 17 through the circuit 13. The reference potential input to the comparator circuit 17 has a ramp waveform. The result of comparing the reference potential with the signal potential corresponding to the first imaging material is output to the counting circuit 19. The counting circuit 19 outputs digital data corresponding to the first image data to the wiring 94 (OUT4).

When it is determined that the node FD is saturated, the determination output circuit 18 outputs a signal for acquiring the second imaging material to the circuit 16. And, the circuit 16 outputs a signal for acquiring the second imaging material to the pixel 10. The signal potential corresponding to the second imaging material is input to the comparator circuit 17 through the circuit 13. The reference potential input to the comparator circuit 17 has a ramp waveform. The reference potential corresponds to the second camera The result of the comparison of the signal potentials of the data is output to the counter circuit 19. The counting circuit 19 outputs the digital data corresponding to the second imaging material to the wiring 94 (OUT4).

As the determination output circuit 18, for example, the circuit shown in Fig. 3A can be used. The input terminal (IN) of the circuit is electrically connected to the output terminal of the comparator circuit 17. The output terminal (OUT) of this circuit is electrically connected to the wiring 93 (OUT3). The decision output circuit 18 is reset in accordance with the JRES signal in the selected row, and then the decision result of the comparator circuit 17 is output to the circuit 16.

As the circuit 16, for example, the circuit shown in Fig. 3B can be used. The input terminal (IN) of the circuit is electrically connected to the wiring 93 (OUT3). There are two types of output terminals (OUT) of the circuit, one electrically connected to the wiring 61 (TX) and the other electrically connected to the wiring 64 (CN). A signal input to one of the terminal TX1 and the terminal TX2 is output from the circuit to the wiring 61 (TX). Further, a signal input to one of the terminal CN1 and the terminal CN2 is output from the circuit to the wiring 64 (CN). Further, a control signal may be input to the terminal GCN to fix a signal output from the wiring 61 (TX) and the wiring 64 (CN). Since the circuit 16 has a latch function, the signal output from the decision output circuit 18 is held in the circuit 16 when it is determined that the node FD is saturated. Therefore, even if the decision is repeated until the last line, the above signal is held.

The above circuit can operate according to the timing chart shown in FIG. The RCK 1/2 and RCKB 1/2 shown in FIG. 4 are clock signals and inverted clock signals input to the circuit 12 (row driver), JRES is a signal input to the circuit shown in FIG. 3A, and GRES and JENB are inputs. To the signal of the circuit shown in Fig. 3B, EN_CDS is a signal input to the gate of the transistor 53 of the circuit 13, SE[1] is a signal input to the wiring 65 of the pixel 10 of the first row, SE[N] is The signal of the wiring 65 of the pixel 10 input to the last row.

The period indicated by frame[n] corresponds to the period of the nth frame (n is a natural number of 2 or more). In the nth frame, a period 401 is a period in which the material of the (n-1)th frame is read, a period 402 is a period in which the first image data is read and a determination is made, and a period 400 is a period in which the row driver does not operate. . Further, the period 403 in the (n+1)th frame is a period in which the material of the nth frame is read.

Next, the operation of the pixel 10 shown in Fig. 1 will be described with reference to the flowchart shown in Fig. 5 and the timing chart shown in Fig. 6. The image pickup apparatus of one embodiment of the present invention operates in a global shutter mode, and the work in one frame is roughly divided into: acquisition of the first image data; judgment of the first image data The acquisition of the second camera data; and the reading of the camera data of the previous frame. The acquisition of the first image data and the reading of the image data of the previous frame are performed simultaneously.

In FIGS. 5 and 6, an arbitrary nth frame will be described as a reference. The wiring 71 (VPD) and the wiring 73 (VSS) are at a low potential ("L"), and the wiring 72 (VRS) and the wiring 74 (VPI) are at a high potential ("H").

In FIG. 6, GWRS is the potential of the wiring 62 (GWRS), RS[1] is the potential of the wiring 63 (RS) of the specific pixel 10 of the first row, and RS[N] is the wiring 63 of the specific pixel 10 of the last row. (RS) potential, CN is the potential of the wiring 64 (CN), TX is the potential of the wiring 61 (TX), AN[1] is the potential of the node AN of the specific pixel 10 of the first row, and AN[N] is the last The potential of the node AN of the specific pixel 10 of the row, FD[1] is the potential of the node FD of the specific pixel 10 of the first row, and FD[N] is the potential of the node FD of the specific pixel 10 of the last row.

First, the acquisition of the first image data and the reading of the image data acquired in the previous frame will be described.

The exposure time of the imaging mode of the first imaging material is relatively long, so that a wide dynamic range image can be obtained in a low illumination environment. On the other hand, since the exposure time is relatively long, the node FD is saturated in a high illumination environment. The timing chart of Fig. 6 shows the operation in the case where the node FD is saturated at the time of the determination of the first image data.

At time T1, when GWRS is set to "H", AN[1:N] is reset to become "H" (potential of wiring 72 (VRS)) (S1).

At time T2, when GWRS is set to "L", AN[1:N] starts to decrease according to illuminance (No. One exposure, S2)

At time T3, when RS[1:N] is set to "H" and CN is set to "H", FD[1:N] is reset to become "H" (potential of wiring 72 (VRS)) (S3). At this time, the node FD is electrically connected to the capacitor C2 via the transistor 44.

At time T4, when RS[1:N] is set to "L", CN is set to "L" and TX is set When "H" is set, the electrical connection between the node FD and the capacitor C2 is cut off, whereby the potential of the node FD at the time of reset is held in the capacitor C2. Further, the potential of the node AN is transmitted to the node FD, and the potential of the node FD starts to drop (S4).

At time T5, when TX is set to "L", FD[1:N] is held. Here is the acquisition of the first camera data.

Here, between time T1 and T3, SE[1] to SE[N] are sequentially "H" for a certain period, and image data determined in the (n-1)th frame is read (510'). . That is to say, the acquisition of the first image data of the nth frame described above is performed simultaneously with the reading of the image data determined in the (n-1)th frame. By reading the image data in the next frame by the above method, the time for exposure or the like can be extended even if the global shutter mode is employed. Therefore, an image with a wide dynamic range and low noise can be obtained under low illumination.

Fig. 7A is a timing chart for explaining reading of image data in the first line. SH is the potential of the gate supplied to the transistor 52 in the circuit 13, CL is the potential of the gate supplied to the transistor 51 in the circuit 13, and REF (RAMP) is the reference potential supplied to the comparator circuit 17, OUT2 It is the potential of the wiring 92 (OUT2), and COMP_OUT is the potential of the output terminal of the comparator circuit 17.

In FIG. 6, before time T3, RS[1] to RS[N] are sequentially "H" for a certain period of time, and the node FD is reset. This work is performed based on the operation of the circuit 13 shown in Fig. 7A.

Next, the determination of the first imaging material and the operation based on the determination result will be described.

In time T6 to T8, SE[1] to SE[N] are sequentially "H" for a certain period of time, and the first image data is read out in rows, thereby whether or not the saturation of the node FD of all the effective pixels is present. A determination is made (S5).

FIG. 7B is a timing chart for explaining the reading of the first image data at times T6 to T8. In the readout period of the first image data, EN_CDS is set to "H" and CL is set to "H", and the bypass circuit 13 inputs the signal output from the pixel 10 to the comparator circuit 17. REF(CONST) is set to a fixed potential and is slightly higher than the potential output to the wiring 91 (OUT1) when the node FD is saturated. High potential. With the above operation, the presence or absence of saturation of the node FD can be determined based on the output of the comparator circuit 17. FIG. 7B shows a state when the node FD of the selected specific pixel 10 is saturated, whereby the potential output from the output terminal of the comparator circuit 17 is "L". Further, EN_CDS may be set to "L", and the first image data is read out by the circuit 13 without returning. At this time, the potential output from the output terminal of the comparator circuit 17 is "H".

At this time, the first image data is used to determine the presence or absence of saturation of the node FD, and is not output to the outside. Therefore, the operation of the output circuit such as the circuit 15 (column driver) required for external output can be stopped.

The determination result of the first imaging data is output to the circuit 16 by the determination output circuit 18. Here, the output terminals of the determination output circuit 18 in each column are connected to the wiring 93 (OUT3). Thus, when at least one of all the pixels 10 is determined to be saturated with its node FD, the circuit 16 sets CN to "H" and sets TX to "H" at a specified time, and switches to acquire the second image data. Mode. Here, it is the determination of the first imaging material and the operation based on the determination result.

Next, the acquisition of the second imaging material will be described. The exposure time of the imaging mode of the second imaging material is relatively short, whereby a wide dynamic range image can be obtained in a high illumination environment.

The exposure work for acquiring the second image data may be performed regardless of the determination result of the first image data or before all the determination results are obtained. For example, as shown in FIG. 6, at time T7, GWRS is set to "H" and AN[1:N] is reset (S6). Then, at time T8, GWRS is set to "L", and a second exposure is performed before time T10 (S7). In order to prevent saturation of the node FD, the exposure time of the second exposure is set to be shorter than the exposure time of the first exposure.

At time T9 before the end of the second exposure, CN is set to "H" by the operation of the circuit 16, the transistor 44 is turned on, and the node FD is electrically connected to the capacitor C2 again.

Immediately before time T9, the node FD is in an electronic saturation state, that is, a state in which the voltage is zero. At time T9, the capacitor C2 storing the potential at the time of resetting of the node FD is electrically connected to the node FD, and the stored electrons are divided, whereby the potential of the node FD rises (S8).

At time T10, when the operation of the circuit 16 is utilized, the CN is set to "L" and the TX is set to At "H", the potential of the node AN is transmitted to the node FD (S9).

At time T11, when TX is set to "L", FD[1:N] is held. Here is the acquisition of the second camera data. In the (n+1)th frame, the second image data is read as the image data of the nth frame (S10).

FIG. 8 is a timing chart when the determination node FD is not saturated with the first imaging data. In the case where the nodes FD of all the pixels 10 are not saturated, the circuit 16 does not perform the operation of setting CN and TX to "H". That is to say, it does not switch to the mode of acquiring the second imaging material. Therefore, the material acquired as the first image data is directly read. Further, when it is determined that the node FD is not saturated, the operation of setting GWRS to "H" at times T7 to T8 may be invalidated without performing the second exposure.

As described above, the image pickup apparatus of one embodiment of the present invention operates in a global shutter mode. Therefore, in a case where it is determined that the node FD of at least one of all the pixels 10 is saturated, switching to the mode of acquiring the second image data, all the pixels 10 acquire the second image data.

With the above work, the second image data can be automatically acquired as needed, and the gray scale of the bright portion can be maintained even if the image with the light and dark portions is captured. In other words, you can get a wide dynamic range of images. In addition, wide dynamic range images with less noise and grayscale retention can be obtained even in low illumination environments.

The pixel 10 can also have the structure shown in FIG. The pixel 10 shown in FIG. 9 is different from the pixel 10 shown in FIG. 1 in the connection direction of the photoelectric conversion element PD. The pixel 10 shown in FIG. 9 can operate according to the timing chart of FIG. 11 (the acquisition operation of the second imaging material) or the timing chart of FIG. 12 (the acquisition operation without the second imaging material). At this time, the wiring 71 (VPD) and the wiring 74 (VPI) are at a high potential ("H"), and the wiring 72 (VRS) and the wiring 73 (VSS) are at a low potential ("L").

In this case, the node AN and the node FD are in an electronic saturation state at the time of resetting, and are in an electronically insufficient state in a high illuminance environment. Therefore, the potential changes of the node AN and the node FD are opposite to those of the pixel 10 shown in FIG. 1 described above.

Further, the pixel 10 may have the configuration shown in FIGS. 10A and 10B. Figure 10A is no The structure of the transistor 42 is set. In this configuration, by setting the potential of the wiring 71 (VPD) to a high potential, the potential of the node AN can be reset. FIG. 10B shows a structure in which one of the source and the drain of the transistor 45 is connected to the wiring 91 (OUT).

In addition, the transistor for the pixel 10 may have a structure in which a back gate is provided in the transistor 41 to the transistor 46 as shown in FIGS. 13A and 13B. Fig. 13A shows a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. In FIG. 13A, as an example, a case where the back gate is connected to the wiring 71 (VPD), the wiring 73 (VSS), or the wiring 75 (VSS2) that supplies the low potential is mentioned, but the back gate and the above wiring may be employed. The structure of a connection in . In addition, FIG. 13B is a structure in which the same potential as the front gate is applied to the back gate, and by adopting this configuration, the on-state current can be increased and the off-state current can be reduced. Further, the structure and the like shown in FIGS. 13A and 13B may be combined in such a manner that the desired transistor has appropriate electrical characteristics. Alternatively, a transistor having no back gate may be provided. Further, the structures of FIGS. 9, 10A and 10B, and FIGS. 13A and 13B can be combined as needed.

As shown in FIG. 14, the pixel 10 can adopt a manner in which a plurality of pixels collectively use the transistor 43 to the transistor 46. 14 shows a structural example in which a plurality of pixels in the vertical direction use the crystal 43 to the transistor 46 in common, and it is also possible to employ a structure in which the plurality of pixels in the horizontal direction or the horizontal vertical direction use the crystal 43 to the transistor 46 in common. By adopting the above structure, the number of transistors each pixel has can be reduced.

In FIG. 14, a manner in which four pixels collectively use the transistor 43 to the transistor 46 is shown, and a mode in which the transistor 43 to the transistor 46 are commonly used for two pixels, three pixels, or five pixels or more may be used. In addition, the structure and the structures shown in FIGS. 9, 10A and 10B, and 13A and 13B can be arbitrarily combined.

The image pickup apparatus according to an embodiment of the present invention may employ a laminated structure of a pixel array 11 and a substrate 35 including the circuit 12 to the circuit 16. For example, FIG. 15A is a plan view of the pixel array 11, and FIG. 15B is a plan view of the substrate 35. A stacked structure of the pixel array 11 and the substrate 35 as shown in the front view of FIG. 15C can be employed. By adopting this configuration, it is possible to use a suitable transistor for each component, and it is possible to reduce the area of the image pickup device. In addition, the circuit layout shown in FIG. 15B is an example, and other layouts may be employed.

In order to simultaneously realize high-speed operation and a structure using a CMOS circuit, the circuit 12 to the circuit 16 are preferably formed using a transistor using germanium (hereinafter, referred to as a Si transistor). For example, a germanium substrate can be used as the substrate 35, and the above-described circuit can be formed on the germanium substrate. Further, the pixel array 11 is preferably formed by a transistor (hereinafter referred to as an OS transistor) using an oxide semiconductor. Further, a transistor constituting a part of the circuit 12 to the circuit 16 may be disposed on the same surface as the pixel array 11.

A specific configuration example of an image pickup apparatus according to an embodiment of the present invention will be described with reference to the drawings. The cross-sectional view shown in Fig. 16A is an example of a specific connection mode of the photoelectric conversion element PD, the transistor 41, the transistor 43, and the capacitor C1 in the pixel 10 shown in Fig. 1. The transistor 42, the transistor 44, the transistor 45, the transistor 46, and the capacitor C2 are not shown in Fig. 16A. The transistor 41 to the transistor 46 and the capacitors C1 and C2 may be disposed in the layer 1100, and the photoelectric conversion element PD may be disposed in the layer 1200.

In the cross-sectional view described in the present embodiment, the wiring, the electrode, and the contact plug (conductor 81) are components different from each other, but the components electrically connected to each other in the drawings are sometimes recognized as the same in the actual circuit. A component. Further, the manner in which the wiring is connected to the electrodes by the conductor 81 is an example, and the electrodes may be directly connected to the wiring.

An insulating layer 82, an insulating layer 83, and the like serving as a protective film, an interlayer insulating film, or a planarizing film are provided on each of the modules. For example, an inorganic insulating film such as a hafnium oxide film or a hafnium oxynitride film can be used for the insulating layer 82, the insulating layer 83, and the like. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. Preferably, the top surface of the insulating layer 82, the insulating layer 83, and the like is planarized by a CMP (Chemical Mechanical Polishing) method or the like as necessary.

In addition, a part of the wiring or the like shown in the drawings may not be provided, and each layer may include a wiring, a transistor, and the like which are not shown in the drawings. Further, a layer not shown in the drawings is sometimes included. In addition, some of the layers shown in the drawings are sometimes not included.

The transistor 41 to the transistor 46 of the assembly of the pixel 10 preferably use an OS transistor having a low off-state current. The extremely low off-state current of the OS transistor allows for a wide dynamic range of imaging. In the circuit configuration of the pixel 10 shown in FIG. 1, when the intensity of light incident on the photoelectric conversion element PD is large, the potentials of the node AN and the node FD are small. Off-state current due to transistor using oxide semiconductor It is extremely low, so even if the gate potential is extremely small, the current corresponding to the gate potential can be correctly output. Thereby, it is possible to expand the range of illuminance that can be detected, that is, to expand the dynamic range.

Further, since the off-state currents of the transistor 41, the transistor 42, the transistor 43, and the transistor 44 are low, the period during which the charge can be held in the node AN and the node FD can be extremely long. Therefore, it is possible to apply a global shutter method in which charge storage work is simultaneously performed in all pixels without complicating the circuit structure or the operation method. Further, the image pickup apparatus according to an embodiment of the present invention may be driven by a scroll shutter method.

The operation of the imaging device will be described with reference to FIGS. 17A, 17B, and 17C. In FIGS. 17A, 17B, and 17C, "E" indicates a period during which an exposure operation can be performed, and "R" indicates a period during which a reading operation can be performed. Further, n denotes an nth frame of an arbitrary nth (n is a natural number of 2 or more). In addition, (n-1) represents the previous frame of the nth frame, and (n+1) represents the next frame of the nth frame. In addition, Line[1] represents the first line of the pixel array 11, and Line[M] represents the Mth line of the pixel array 11 (in FIGS. 17A to 17C, M represents a natural number of 4 or more).

Fig. 17A schematically shows a method of operating the scroll shutter mode. The scroll shutter method is a working method in which exposure and data reading are sequentially performed in a row. There is no simultaneity in the image in all the pixels, so distortion occurs in the image when shooting a moving object.

Fig. 17B schematically shows the operation of the general global shutter mode. The global shutter mode is a method of simultaneously performing exposure in all pixels and then reading data in rows. Thereby, an image without distortion can be obtained even if a moving object is photographed.

Fig. 17C schematically shows an operation method of an image pickup apparatus which is applied to one embodiment of the present invention. In this working method, all pixels are simultaneously exposed in the nth frame, and the data acquired in the nth frame is read in the (n+1)th frame. Therefore, exposure and reading of the same frame are not performed in one frame period, and unlike the conventional global shutter mode, there is no limitation on the exposure time even if the reading period is increased. Thereby, the exposure time can be extended.

Since the temperature dependence of the variation of the electrical characteristics of the OS transistor is smaller than that of the transistor used for the active region or the active layer, the OS transistor can be used in an extremely wide temperature range. Therefore, an image pickup apparatus and a semiconductor apparatus including an OS transistor are suitable for mounting in automobiles, airplanes, spaceships, and the like.

In addition, the threshold voltage of the OS transistor is higher than that of the Si transistor. In a photoelectric conversion element in which a selenium-based material is used for a photoelectric conversion layer, it is preferable to apply a high voltage (for example, 10 V or more) to operate to utilize avalanche multiplication. Thus, by combining an OS transistor and a photoelectric conversion element using a selenium material for the photoelectric conversion layer, a highly reliable image pickup device can be realized.

Although FIG. 16A shows an example of the manner in which each transistor includes a back gate, as shown in FIG. 16B, the back gate may not be included. In addition, as shown in FIG. 16C, a portion of the transistor, such as only the transistor 41, may also include a back gate. The back gate is sometimes electrically connected to the oppositely disposed front gate. Alternatively, the back gate is sometimes supplied with a constant potential different from that of the front gate. Note that the presence or absence of the back gate can also be applied to other pixel structures described in the present embodiment.

As the photoelectric conversion element PD provided in the layer 1200, various types of elements can be employed. FIG. 16A shows a manner in which a selenium-based material is used for the photoelectric conversion layer 561. The photoelectric conversion element PD using a selenium-based material has high external quantum efficiency for visible light. Further, since the selenium-based material has a high light absorption coefficient, there is an advantage that the photoelectric conversion layer 561 is easily formed thin. The photoelectric conversion element PD formed using a selenium-based material may be a high-sensitivity sensor having a large increase in amplitude using avalanche multiplication. That is, by using a selenium-based material for the photoelectric conversion layer 561, a sufficient photocurrent can be obtained even if the pixel area is small. Therefore, it can be considered that the photoelectric conversion element PD using a selenium-based material is suitable for imaging in a low illumination environment.

As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be formed by heat treatment after forming amorphous selenium. Further, by making the crystal grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between the pixels can be reduced. Further, crystalline selenium has a characteristic of high spectral sensitivity and high light absorption coefficient with respect to visible light as compared with amorphous selenium.

In Fig. 16A, a single-layer photoelectric conversion layer 561 is shown, but as shown in Fig. 18A, gallium oxide, yttrium oxide or In-Ga-Zn oxide or the like may be provided as a hole injection barrier layer 568 on the light-receiving surface side. . Alternatively, as shown in FIG. 18B, nickel oxide, ruthenium sulfide or the like may be provided on the electrode 566 side as the electron injection barrier layer 569. Alternatively, as shown in FIG. 18C, a hole injection barrier layer 568 and an electron injection barrier layer 569 may be provided. Further, as shown in FIGS. 1 and 9, in the pixel 10, a configuration in which the photoelectric conversion elements PD are connected in different directions may be employed. Thus, Figure 18A can be exchanged. The hole injection barrier layer 568 and the electron injection barrier layer 569 are shown in FIG. 18C.

The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, or selenium (CIS), or a layer containing a compound of copper, indium, gallium, or selenium (CIGS). By using CIS and CIGS, it is possible to form a photoelectric conversion element in which avalanche multiplication is similarly used when a single layer of selenium is formed.

As the photoelectric conversion element PD using a selenium-based material, for example, a structure having a photoelectric conversion layer 561 between the electrode 566 formed of a metal material or the like and the light-transmitting conductive layer 562 can be employed. Further, CIS and CIGS are p-type semiconductors, and cadmium sulfide or zinc sulfide of an n-type semiconductor may be provided in contact therewith to form a bond.

In FIG. 16A, the light-transmitting conductive layer 562 is in direct contact with the wiring 71, but as shown in FIG. 19A, the light-transmitting conductive layer 562 may be in contact with the wiring 71 by the wiring 88. Although a structure in which the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are not separated between the pixel circuits is employed in FIG. 16A, a structure separated between circuits may be employed as shown in FIG. 19B. Further, between the pixels, it is preferable to form the partition wall 567 using an insulator in a region having no electrode 566 so as not to cause cracks in the photoelectric conversion layer 561 and the light-transmitting conductive layer 562, but as shown in FIGS. 19C and 19D. It is also possible to adopt a structure in which the partition wall 567 is not provided.

Further, the electrode 566, the wiring 71, and the like may have a multilayer structure. For example, as shown in FIG. 20A, the electrode 566 may also adopt a two-layer structure of the conductive layer 566a and the conductive layer 566b, and the wiring 71 may also adopt a two-layer structure of the conductive layer 71a and the conductive layer 71b. In the structure of FIG. 20A, for example, a low-resistance metal or the like is selected to form the conductive layer 566a and the conductive layer 71a, and a metal having good contact characteristics with the photoelectric conversion layer 561 is selected to form the conductive layer 566b and the conductive layer. 71b. By adopting such a structure, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some kinds of metals may cause electrical corrosion due to contact with the light-transmitting conductive layer 562. Even if such a metal is used for the conductive layer 71a, electrolytic corrosion can be prevented by the conductive layer 71b.

As the conductive layer 566b and the conductive layer 71b, for example, molybdenum or tungsten can be used. Further, as the conductive layer 566a and the conductive layer 71a, for example, aluminum, titanium, or a laminate in which titanium, aluminum, and titanium are laminated in this order may be used.

In addition, as shown in FIG. 20B, the light-transmitting conductive layer 562 can be electrically connected to the conductor 81 and the wiring 88. It is connected to the wiring 71. Further, the insulating layer 82 or the like may also have a multilayer structure. For example, as shown in FIG. 20B, in the case where the insulating layer 82 includes the insulating layer 82a and the insulating layer 82b, and the etching rate and the like of the insulating layer 82a and the insulating layer 82b are different, the electric conductor 81 has a step. In the case where a multilayer structure is employed as the other insulating layer used as the interlayer insulating film or the planarizing film, the conductor 81 similarly has steps. Here, an example in which the insulating layer 82 has a two-layer structure is shown, but the insulating layer 82 and other insulating layers may have a laminated structure of three or more layers.

The partition wall 567 can be formed using an inorganic insulator or an insulating organic resin or the like. Further, the partition wall 567 may be colored in black or the like to shield light irradiated to the transistor or the like and/or to determine the area of the light receiving portion of each pixel.

Further, as the photoelectric conversion element PD, a pin type diode element or the like using an amorphous germanium film or a microcrystalline germanium film or the like may be used.

For example, FIG. 21 is an example in which a pin type thin film photodiode is used as the photoelectric conversion element PD. The photodiode includes an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type semiconductor layer 563 which are sequentially stacked. The i-type semiconductor layer 564 is preferably an amorphous germanium. As the p-type semiconductor layer 563 and the n-type semiconductor layer 565, an amorphous germanium or a microcrystalline germanium or the like containing a dopant imparted to each conductivity type can be used. The photodiode having the amorphous germanium as the photoelectric conversion layer has high sensitivity in the visible light wavelength region, and is easy to detect weak visible light.

In the photoelectric conversion element PD shown in FIG. 21, an n-type semiconductor layer 565 serving as a cathode is in contact with an electrode 566 which is electrically connected to the transistor 41. Further, the p-type semiconductor layer 563 serving as an anode is electrically connected to the wiring 71 by a wiring 88.

Further, when the anode and cathode of the photoelectric conversion element PD and the electrode layer are connected to the wiring in the opposite manner, the structure of the circuit diagram shown in Fig. 9 can be employed.

In either case, it is preferable to form the photoelectric conversion element PD such that the p-type semiconductor layer 563 is a light-receiving surface. By using the p-type semiconductor layer 563 as the light receiving surface, the output current of the photoelectric conversion element PD can be increased.

Further, the structure of the photoelectric conversion element PD having a pin type thin film photodiode is The connection between the photoelectric conversion element PD and the wiring can be as shown in Figs. 22A to 22C. Further, the configuration of the photoelectric conversion element PD and the connection manner of the photoelectric conversion element PD and the wiring are not limited thereto, and other methods may be employed.

FIG. 22A shows a structure in which the light-transmitting conductive layer 562 which is in contact with the p-type semiconductor layer 563 of the photoelectric conversion element PD is provided. The light-transmitting conductive layer 562 is used as an electrode, and the output current of the photoelectric conversion element PD can be increased.

As the light-transmitting conductive layer 562, for example, indium tin oxide, indium tin oxide containing germanium, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, or the like may be used. Containing antimony tin oxide, graphene or graphene oxide. Further, the light-transmitting conductive layer 562 is not limited to a single layer, but may be a laminate of different films.

22B shows a structure in which the light-transmitting conductive layer 562 is connected to the wiring 71 via the conductor 81 and the wiring 88. Further, a structure in which the p-type semiconductor layer 563 of the photoelectric conversion element PD is connected to the wiring 71 by the conductor 81 and the wiring 88 may be employed. In FIG. 22B, the light-transmitting conductive layer 562 may not be provided.

22C shows a structure in which an opening portion that exposes the p-type semiconductor layer 563 is provided in an insulating layer covering the photoelectric conversion element PD, and the light-transmitting conductive layer 562 covering the opening portion is electrically connected to the wiring 71.

Further, as shown in FIG. 23, the photoelectric conversion element PD may also employ a photodiode in which the ruthenium substrate 600 is used as a photoelectric conversion layer.

The photoelectric conversion element PD formed using the above selenium-based material or amorphous germanium or the like can be manufactured through a general semiconductor process such as a film formation process, a photolithography process, or an etching process. Further, since the selenium-based material has high resistance, a structure in which the photoelectric conversion layer 561 is not separated from each other as shown in FIG. 16A can also be employed. Therefore, the image pickup apparatus according to one embodiment of the present invention can be manufactured with high yield and low cost. On the other hand, when forming a photodiode using the tantalum substrate 600 as a photoelectric conversion layer, it is necessary to perform a highly difficult process such as a polishing process or a bonding process.

Further, in the image pickup apparatus according to the embodiment of the present invention, the ruthenium substrate 600 may be laminated, and a circuit is formed in the ruthenium substrate 600. For example, as shown in FIG. 24A, layer 1400 can Overlap of the pixel circuit, the layer 1400 includes a transistor 610 having an active region in the germanium substrate 600 and a transistor 620. Fig. 24B corresponds to a cross-sectional view in the channel width direction of the transistor.

Here, in FIGS. 24A and 24B, a configuration example in which the Si transistor has a fin shape is shown, but as shown in FIG. 25A, a planar structure may be employed. Further, as shown in FIG. 25B, a transistor having an active layer 650 of a tantalum film may also be used. As the active layer 650, a polycrystalline germanium or a single crystal germanium of a SOI (Silicon on Insulator) structure can be used.

The circuit formed on the germanium substrate 600 may have a function of reading out a signal output from the pixel circuit or a process of converting the signal, and the like, and may include, for example, a CMOS inverter as shown in the circuit diagram of FIG. 25C. The gate electrodes of the transistor 610 (n channel type) and the transistor 620 (p channel type) are electrically connected to each other. One of the source and the drain of one of the transistor 610 and the transistor 620 is electrically connected to one of the source and the drain of the other transistor. In addition, the other of the source and the drain of the transistor 610 and the transistor 620 are electrically connected to different wirings, respectively.

The circuit formed on the germanium substrate 600 corresponds to, for example, the circuit 12, the circuit 13, the circuit 14, the circuit 15, the circuit 16, and the like shown in FIGS. 2A and 15B.

Further, the tantalum substrate 600 is not limited to a bulk tantalum substrate, and a substrate made of tantalum, niobium, tantalum carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used.

Here, as shown in FIG. 23 and FIG. 24A and FIG. 24B, insulation is provided between a region where a transistor including an oxide semiconductor is formed and a region where a Si device (Si transistor or Si photodiode) is formed. Layer 80.

The hydrogen disposed in the insulating layer near the active regions of the transistor 610 and the transistor 620 terminates the dangling bonds of the crucible. Therefore, the hydrogen increases the reliability of the transistor 610 and the transistor 620. On the other hand, hydrogen contained in the insulating layer in the vicinity of the oxide semiconductor layer of the active layer of the transistor 41 or the like may be one of the causes of generating a carrier in the oxide semiconductor layer. Therefore, the hydrogen sometimes causes a decrease in the reliability of the transistor 41 or the like. Therefore, when laminating one layer including a transistor using a bismuth-based semiconductor material and another layer including a transistor using an oxide semiconductor, it is preferable to provide an insulating layer 80 having a function of preventing hydrogen diffusion therebetween. By encapsulating hydrogen in one layer by providing the insulating layer 80, the reliability of the transistor 610 and the transistor 620 can be improved. Simultaneously, Since the diffusion of hydrogen from one layer to the other can be suppressed, the reliability of the transistor 41 and the like can be improved.

As the insulating layer 80, for example, alumina, aluminum oxynitride, gallium oxide, gallium oxynitride, cerium oxide, cerium oxynitride, cerium oxide, cerium oxynitride, yttrium yttria (YSZ), or the like can be used.

In the structure shown in FIGS. 24A and 24B, a circuit (for example, a driving circuit), a transistor 41, and the like formed on the germanium substrate 600 may be formed to overlap with the photoelectric conversion element PD, thereby improving pixel integration. degree. In other words, the resolution of the imaging device can be improved. For example, the above configuration can be applied to an image pickup apparatus having a pixel number of 4K2K, 8K4K, or 16K8K. In addition, a structure in which the transistor 45 and the transistor 46 included in the pixel 10 are formed using the Si transistor in a manner overlapping the transistor 41, the transistor 42, the transistor 43, the transistor 44, and the photoelectric conversion element PD or the like may be employed. .

Further, the image pickup apparatus according to an embodiment of the present invention can adopt the configuration shown in FIG. The imaging device shown in FIG. 26 is a modification of the imaging device shown in FIG. 24A, and shows an example in which a CMOS inverter is formed by an OS transistor and a Si transistor.

Here, the transistor 620 of the Si transistor disposed in the layer 1400 is a p-channel type transistor, and the transistor 610 of the OS transistor disposed in the layer 1100 is an n-channel type transistor. By providing only the p-channel type transistor on the ruthenium substrate 600, processes such as formation of a well and formation of an n-type impurity layer can be omitted.

Although the imaging apparatus of FIG. 26 shows an example in which selenium or the like is used for the photoelectric conversion element PD, a configuration using a pin-type thin film photodiode similar to that of FIG. 21 may be employed.

In the image pickup apparatus shown in FIG. 26, the transistor 610 can be fabricated by the same process as the transistor 41 and the transistor 43 formed in the layer 1100. Therefore, the process of the image pickup apparatus can be simplified.

As shown in FIG. 27, an image pickup apparatus according to an embodiment of the present invention may have a structure in which a photoelectric conversion element PD formed in a germanium substrate 660 and an OS transistor formed thereon are bonded. The structure of the body-constituted pixel and the germanium substrate 600 on which the circuit is formed. By adopting the above configuration, the effective area of the photoelectric conversion element PD formed in the ruthenium substrate 660 can be easily increased. Further, by using a miniaturized Si transistor to highly integrate the circuit formed on the germanium substrate 600, it is possible to provide a semiconductor device having high performance.

Further, as a modification of FIG. 27, as shown in FIG. 28, an OS transistor and a Si transistor can be used to form a circuit. By adopting the above configuration, the effective area of the photoelectric conversion element PD formed in the ruthenium substrate 660 can be easily increased. Further, by using a miniaturized Si transistor to highly integrate the circuit formed on the germanium substrate 600, it is possible to provide a semiconductor device having high performance.

When the structure of FIG. 28 is employed, a CMOS circuit can be constituted by an Si transistor formed on the germanium substrate 600 and an OS transistor formed thereon. The off-state current of the OS transistor is extremely low, and it can constitute a CMOS circuit with a very small static leakage current.

Note that the configuration of the transistor and the photoelectric conversion element included in the image pickup apparatus in the present embodiment is an example. Therefore, for example, one or more of the transistor 41 to the transistor 46 may be composed of a transistor in which the active region or the active layer contains ruthenium or the like. Further, two or one of the transistor 610 and the transistor 620 may also be composed of a transistor in which the active layer includes an oxide semiconductor layer.

FIG. 29A is a cross-sectional view showing an example of a configuration in which a color filter or the like is added to an imaging device. This cross-sectional view shows a portion of a region including a pixel circuit equivalent to three pixels. An insulating layer 2500 is formed on the layer 1200 on which the photoelectric conversion element PD is formed. As the insulating layer 2500, a ruthenium oxide film or the like having high visible light transmittance can be used. Further, a tantalum nitride film may be laminated as a passivation film. Further, a dielectric film such as ruthenium oxide may be laminated as an anti-reflection film.

A light shielding layer 2510 may also be formed on the insulating layer 2500. The light shielding layer 2510 has a function of preventing mixing of light transmitted through the upper color filter. The light shielding layer 2510 may be a metal layer of aluminum, tungsten, or the like or a structure in which the metal layer and a dielectric film used as an antireflection film are laminated.

An organic resin layer 2520 used as a planarization film may be provided on the insulating layer 2500 and the light shielding layer 2510. In addition, a color filter 2530 (color filter 2530a, The color filter 2530b and the color filter 2530c). For example, the color filter 2530a, the color filter 2530b, and the color filter 2530c exhibit colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta). Thus, a color image can be obtained.

An insulating layer 2560 or the like having a light transmissive property may be provided on the color filter 2530.

Further, as shown in FIG. 29B, the optical conversion layer 2550 may be used instead of the color filter 2530. By adopting such a configuration, it is possible to form an image pickup apparatus capable of obtaining images in various wavelength regions.

For example, an infrared imaging device can be formed by using a filter that blocks light of a wavelength below the visible light line as the optical conversion layer 2550. Further, by using a filter that blocks light of a wavelength lower than the near infrared ray as the optical conversion layer 2550, a far-infrared imaging device can be formed. Further, by using a filter that blocks light of a wavelength of visible light or more as the optical conversion layer 2550, an ultraviolet imaging device can be formed.

Further, by using the scintillator for the optical conversion layer 2550, it is possible to form an imaging device for obtaining an image for visualizing the radiation intensity for an X-ray imaging device or the like. When radiation such as X-rays incident on a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light due to a phenomenon called photoluminescence. Image data is obtained by detecting the light by the photoelectric conversion element PD. Further, an imaging device of this configuration can also be used for a radiation detector or the like.

The scintillator contains a substance that absorbs the energy of the radiation and emits visible light or ultraviolet rays when the scintillator is irradiated with radiation such as X-rays or gamma rays. For example, Gd ₂ O ₂ S:Tb, Gd ₂ O ₂ S:Pr, Gd ₂ O ₂ S:Eu, BaFCl:Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, A material in which ZnO is dispersed in a resin or ceramic.

In the photoelectric conversion element PD using a selenium-based material, since the radiation such as X-rays can be directly converted into electric charges, the scintillator can be omitted.

Further, as shown in FIG. 29C, a microlens array 2540 may be provided on the color filter 2530a, the color filter 2530b, and the color filter 2530c. The light passing through the respective lenses of the microlens array 2540 is irradiated to the photoelectric conversion element PD via the color filter provided thereunder. In addition, as shown in Figure 29D It is also possible to provide a microlens array 2540 on the optical conversion layer 2550. Further, a region other than the layer 1200 shown in FIGS. 29A, 29B, 29C, and 29D is a layer 1600.

FIG. 30 is a view showing a specific laminated structure example of the pixel 10 and the microlens array 2540 shown in FIG. 29C according to the embodiment of the present invention. Fig. 30 is an example of using the pixel structure shown in Fig. 24A. FIG. 31 is an example of using the pixel structure shown in FIG.

As described above, it is possible to adopt a configuration in which the photoelectric conversion element PD, the circuit included in the pixel 10, and the drive circuit have a region in which they overlap, and thus it is possible to achieve miniaturization of the image pickup apparatus.

Further, as shown in FIGS. 30 and 31, a structure in which the diffraction grating 1500 is provided on the microlens array 2540 can be employed. The image (diffractive image) of the subject matter of the diffraction grating 1500 can be extracted into the pixel, and then the input image (the image of the object) can be formed by the arithmetic processing according to the imaged image in the pixel. Further, by using the diffraction grating 1500 instead of the lens, the cost of the image pickup device can be reduced.

The diffraction grating 1500 may be formed of a material having light transmissivity. For example, an inorganic insulating film such as a hafnium oxide film, a hafnium oxynitride film, or the like can be used. Alternatively, an organic insulating film such as an acrylic resin, a polyimide resin, or the like can also be used. Further, a laminate of the above inorganic insulating film and an organic insulating film may also be used.

The diffraction grating 1500 can be formed by a photolithography process using a photosensitive resin or the like. In addition, the diffraction grating 1500 can also be formed by a photolithography process and an etching process. Further, the diffraction grating 1500 may be formed by a nanoimprint method, a laser dicing method, or the like.

Alternatively, a space X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X may be 1 mm or less, preferably 100 μm or less. The space may be either a space or a material having a light transmissive property as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas is sealed in the space. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided in the space. Alternatively, a liquid such as an oxime oil may be provided. Further, a spacer X may be provided between the color filter 2530 and the diffraction grating 1500 without providing the microlens array 2540.

In addition, the image pickup device can be bent as shown in Figs. 32A1 and 32B1. Fig. 32A1 shows a state in which the image pickup apparatus is bent in the direction of the two-dot chain line X1-X2 in the figure. Fig. 32A2 is a cross-sectional view showing a portion indicated by a chain double-dashed line X1-X2 in Fig. 32A1. Fig. 32A3 is a cross-sectional view showing a portion shown by a chain double-dashed line Y1-Y2 in Fig. 32A1.

Fig. 32B1 shows a state in which the imaging device is bent in the direction of the two-dot chain line X3-X4 in the figure and curved in the direction of the two-dot chain line Y3-Y4 in the figure. Fig. 32B2 is a cross-sectional view of a portion indicated by a chain double-dashed line X3-X4 in Fig. 32B1. Fig. 32B3 is a cross-sectional view of a portion indicated by a chain double-dashed line Y3-Y4 in Fig. 32B1.

By bending the image pickup device, field curvature or astigmatism can be reduced. Therefore, the optical design of a lens or the like used in combination with the imaging device can be easily performed. For example, since the number of lenses for aberration correction can be reduced, miniaturization or weight reduction of a semiconductor device or the like using an image pickup device can be easily realized. In addition, the quality of the captured image can be improved.

In the present embodiment, an embodiment of the present invention has been described. Alternatively, in other embodiments, one embodiment of the invention is described. However, one embodiment of the present invention is not limited thereto. In other words, in the present embodiment and other embodiments, various embodiments of the invention are described. Therefore, one embodiment of the present invention is not limited to a specific embodiment. For example, although an embodiment in which the embodiment of the present invention is applied to an image pickup apparatus is shown as an example, one embodiment of the present invention is not limited thereto. Depending on the situation or situation, one embodiment of the present invention may not be applied to an image pickup apparatus. For example, one embodiment of the present invention can also be applied to a semiconductor device having other functions. For example, as one embodiment of the present invention, an example in which an oxide semiconductor is formed in a channel formation region, a source region, a drain region, and the like of a transistor is shown, but one embodiment of the present invention is not limited thereto. The various transistor, the channel formation region of the transistor, the source region of the transistor, the drain region, and the like of one embodiment of the present invention may include various semiconductors depending on the circumstances or conditions. According to circumstances or conditions, various transistors of the embodiment of the present invention, a channel formation region of the transistor, or a source region, a drain region, or the like of the transistor may include germanium, antimony, bismuth, antimony carbide, gallium arsenide. At least one of aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor. Further, for example, depending on the circumstances or conditions, various transistors of the embodiment of the present invention, a channel formation region of the transistor, a source region of the transistor, a drain region, and the like may not include an oxide semiconductor.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Embodiment 2

In the present embodiment, an imaging device different from that of the first embodiment will be described with reference to the drawings. The detailed description of the portions common to the imaging device described in the first embodiment will be omitted.

One embodiment of the present invention is a circuit configuration and an operation method of an image pickup apparatus capable of determining a saturation state of electrons of a charge detecting portion provided in a pixel and changing an operation mode according to a determination result. First, the first imaging data is acquired, and when the charge detecting portion is not saturated, the capacitance value of the charge detecting portion is not changed. When the charge detecting portion is saturated, the capacitance value of the charge detecting portion is increased. After the above control is performed on all the pixels, the acquisition and reading of the second image data are performed. The second imaging material acquired in a state where the capacitance value of the charge detecting portion is not changed corresponds to the material corresponding to the low illuminance. The second imaging material acquired in a state where the capacitance value of the charge detecting portion is increased corresponds to the material corresponding to the high illuminance.

With the above work, it is possible to acquire an image with a wide dynamic range in which the noise is small and the gray scale is maintained even in a low illumination environment. In addition, even if the image is taken in an environment containing high illumination, the gray scale of the bright portion can be maintained, and an image with a wide dynamic range can be obtained.

Fig. 33 is a circuit diagram of a pixel 20 included in the image pickup apparatus according to the embodiment of the present invention. An example in which an n-ch type transistor is used as a transistor is shown in FIG. 33 and the like, but one embodiment of the present invention is not limited thereto, and a part of the transistor may also use a p-ch type transistor instead of the n-ch type. Transistor.

In the pixel 20, one electrode of the photoelectric conversion element PD is electrically connected to one of the source and the drain of the transistor 741. One of the source and the drain of the transistor 741 is electrically connected to one of the source and the drain of the transistor 742. The other of the source and the drain of the transistor 741 is electrically connected to one of the source and the drain of the transistor 743. The other of the source and the drain of the transistor 741 is electrically connected to one of the source and the drain of the transistor 744. The other of the source and the drain of the transistor 741 is electrically connected to the gate of the transistor 745. The other of the source and the drain of the transistor 741 is electrically connected to one electrode of the capacitor C71. The other of the source and the drain of the transistor 744 One electrode of the capacitor C72 is electrically connected. One of the source and the drain of the transistor 745 is electrically coupled to one of the source and the drain of the transistor 746. The gate of transistor 744 is electrically coupled to one of the source and drain of transistor 747. The gate of the transistor 744 is electrically connected to one electrode of the capacitor C73.

Here, a node AN connecting one electrode of the photoelectric conversion element PD, one of the source and the drain of the transistor 741, and one of the source and the drain of the transistor 742 is referred to as a charge storage portion. In addition, one of the source and the drain of the transistor 741, one of the source and the drain of the transistor 743, one of the source and the drain of the transistor 744, and the gate of the transistor 745 are A node FD to which one electrode of the capacitor C71 is connected is referred to as a charge detecting portion. Further, a node CN connecting the gate of the transistor 744, the source and the drain of the transistor 747 to one electrode of the capacitor C73 is referred to as a signal holding portion.

The other electrode of the photoelectric conversion element PD is electrically connected to a wiring 771 (VPD). The other of the source and the drain of the transistor 742 and the other of the source and the drain of the transistor 743 are electrically connected to the wiring 772 (VRS). The other electrode of the capacitor C71, the other electrode of the capacitor C72, and the other electrode of the capacitor C73 are electrically connected to the wiring 773 (VSS). The other of the source and the drain of the transistor 745 is electrically connected to the wiring 774 (VPI). The other of the source and the drain of the transistor 746 is electrically connected to the wiring 791 (OUT1).

In the connection method of each of the above components, a case where a plurality of transistors or a plurality of capacitors are electrically connected to a common wiring is shown as an example, but a plurality of transistors or a plurality of capacitors may be electrically connected to different wirings, respectively.

The wiring 771 (VPD), the wiring 772 (VRS), the wiring 773 (VSS), and the wiring 774 (VPI) may have the function of a power supply line. For example, the wiring 771 (VPD) and the wiring 773 (VSS) can be used as the low potential power supply line. Wiring 772 (VRS) and wiring 774 (VPI) can be used as a high potential power line.

The gate of the transistor 741 is electrically connected to the wiring 761 (TX). The gate of the transistor 742 is electrically connected to the wiring 762 (GWRS). The gate of the transistor 743 is electrically connected to the wiring 763 (RS). The gate of the transistor 746 is electrically connected to the wiring 764 (SE). The gate of the transistor 747 is electrically connected to the wiring 765 (SE2). The other of the source and the drain of the transistor 747 is electrically connected to the wiring 793 (OUT3).

The wiring 761 (TX), the wiring 762 (GWRS), the wiring 763 (RS), the wiring 764 (SE), and the wiring 765 (SE2) can be used as signal lines for controlling conduction of the transistors connected to these wirings. The wiring 763 (RS), the wiring 764 (SE), and the wiring 765 (SE2) can be controlled in rows.

The transistor 741 can be used as a transistor that transmits the potential of the node AN to the node FD. The transistor 742 can be used as a transistor for resetting the potential of the node AN. The transistor 743 can be used as a transistor for resetting the potential of the node FD. The transistor 744 can be used as a transistor that controls the electrical connection between the node FD and the capacitor C72. The transistor 745 can be used as a transistor that outputs according to the potential of the node FD. A transistor 746 can be used as the transistor for selecting the pixel 20. The transistor 747 can be used as a transistor that maintains the potential of the node CN.

Note that the configuration of the above-described pixel 20 is an example, and sometimes does not include a part of the circuit, a part of the transistor, a part of the capacitor, or a part of the wiring or the like. Further, a circuit, a transistor, a capacitor, a wiring, and the like which are not included in the above configuration may be included. Further, the connection method of a part of the wiring may be different from the connection method of the above structure.

Fig. 34A is a view for explaining an image pickup apparatus according to an embodiment of the present invention. The image pickup apparatus includes: a pixel array 21 including pixels 20 arranged in a matrix; a circuit 22 (row driver) having a function of driving the pixels 20; and CDS (Correlated Double Sampling) operation on an output signal of the pixels 20. Circuit 23 (CDS circuit); circuit 24 having a function of determining the presence or absence of saturation of the node FD, a function of controlling the operation mode of the pixel based on the determination result, and a function of converting the analog data output from the circuit 23 into digital data (A) /D conversion circuit, etc.; and a circuit 25 (column driver) having a function of selecting data read by the circuit 24 to be read. Alternatively, a configuration in which the circuit 23 is not provided may be employed.

FIG. 34B is a circuit diagram of a circuit 23 connected to one column of the pixel array 21 and a block diagram of the circuit 24. The circuit 23 may include a transistor 751, a transistor 752, a transistor 753, a capacitor C74, and a capacitor C75. Additionally, circuit 24 may include comparator circuit 27, decision output circuit 28, and count circuit 29.

The transistor 754 has the function of a current source circuit. One of the source and the drain of the transistor 754 is electrically connected to the wiring 791 (OUT1), and the other of the source and the drain is connected to the power supply line. The electricity The source line can be, for example, a low potential power line. In addition, the gate of transistor 754 is biased uninterrupted.

In the pixel 23, one of the source and the drain of the transistor 751 is electrically connected to one of the source and the drain of the transistor 752. One of the source and the drain of the transistor 751 is electrically connected to one electrode of the capacitor C74. The other of the source and the drain of the transistor 752 is electrically connected to one of the source and the drain of the transistor 753. The other of the source and the drain of the transistor 752 is electrically connected to one electrode of the capacitor C75. The other of the source and the drain of the transistor 752 is electrically connected to the wiring 792 (OUT2). The other of the source and the drain of the transistor 753 and the other electrode of the capacitor C74 are electrically connected to the wiring 791 (OUT1). The other of the source and the drain of the transistor 751 is electrically connected, for example, to a high potential power supply line (CDSVDD) to which a reference potential is supplied. The other electrode of the capacitor C75 is electrically connected, for example, to a low potential power line (CDSVSS).

An operation example of the circuit 23 when connected to the pixel 20 shown in FIG. 33 will be described. First, the transistor 751 and the transistor 752 are turned on. Next, the potential of the image data is output from the pixel 20 to the wiring 791 (OUT1), and the reference potential (CDSVDD) is held in the wiring 792 (OUT2). Then, the transistor 751 is turned off, and the reset potential (here, a potential higher than the potential of the image data, for example, the VDD potential) is output from the pixel 20 to the wiring 791 (OUT1). At this time, the potential of the wiring 792 (OUT2) is a potential obtained by adding the absolute value of the difference between the potential of the artifact data and the reset potential to the reference potential (CDSVDD). Therefore, a potential signal having a small amount of noise obtained by adding a potential of the substantial imaging material to the reference potential (CDSVDD) can be supplied to the circuit 24.

Further, when the reset potential is lower than the potential of the image data (for example, GND potential or the like), the potential of the wiring 792 (OUT2) is the difference between the potential of the image data and the reset potential from the reference potential (CDSVDD). The potential obtained from the absolute value of the value.

Further, when the transistor 753 is turned on, a bypass is formed, whereby the signal of the wiring 791 (OUT1) can be directly output to the wiring 792 (OUT2).

In the circuit 24, the signal potential input from the circuit 23 is compared with the reference potential (REF) by the comparator circuit 27. The signal potential corresponding to the first image data or the second image data is input to the comparator circuit 27 by the wiring 792 (OUT2). Here, the first imaging material is the first exposure data, and is used to determine the presence or absence of saturation of the node FD of the pixel 20. Second camera The material is the second exposure data obtained based on the determination.

First, when the first imaging data is input, the comparator circuit 27 outputs the determination result to the determination output circuit 28. The determination output circuit 28 has a function of adjusting the output timing to remove the noise output from the comparator circuit 27.

The comparator circuit 27 determines whether the first image data saturates the node FD of the pixel 20. At this time, the reference potential (REF) input to the comparator circuit 27 is a fixed potential corresponding to the saturation of the node FD. The presence or absence of saturation is determined by comparing the potential with a signal potential corresponding to the first imaging data. In the present embodiment, the circuit circuit 23 inputs the signal potential corresponding to the first image data to the comparator circuit 27, but the signal potential corresponding to the first image data may be input to the comparator circuit 27 in a manner that does not bypass the circuit 23. .

When it is determined that the node FD is not saturated, it is determined that the output circuit 28 outputs a signal that does not change the capacitance value of the node FD to the above pixel. Specifically, the potential in which the transistor 744 is in a non-conduction state is output to the wiring 793 (OUT3), and the potential is held in the node CN of the pixel 20. At this time, the capacitance value of the node FD does not change.

When it is determined that the node FD is saturated, it is determined that the output circuit 28 outputs a signal for increasing the capacitance value of the node FD to the above pixel. Specifically, the potential at which the transistor 744 is turned on is output to the wiring 793 (OUT3), and the potential is held in the node CN of the pixel 20. At this time, the capacitor C72 is electrically connected to the node FD, whereby the capacitance value of the node FD is increased.

After performing the above work on all the effective pixels, the node FD is reset to acquire the second image data. The signal potential corresponding to the second imaging material is input to the comparator circuit 27 via the circuit 23. The reference potential (REF) input to the comparator circuit 27 has a ramp waveform. The result of comparing the reference potential with the signal potential corresponding to the second imaging material is output to the counter circuit 29. The counting circuit 29 outputs the digital data corresponding to the second imaging material to the wiring 794 (OUT4).

As the determination output circuit 28, for example, the circuit shown in Fig. 35 can be used. The input terminal (IN) of the circuit is electrically connected to the output terminal of the comparator circuit 27. The output terminal (OUT) of this circuit is electrically connected to the wiring 793 (OUT3). The determination output circuit 28 is reset in accordance with the JRES signal in the selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). In addition, It is also possible to input a control signal to the terminal GCN and fix the signal output to the wiring 793 (OUT3).

The circuit shown in Fig. 35 can operate in accordance with the timing chart shown in Fig. 36. The RCK1/2 and RCKB1/2 shown in Fig. 36 are clock signals and inverted clock signals input to the circuit 22 (row driver), JRES and JENB are signals input to the circuit shown in Fig. 35, and EN_CDS is an input. The signal to the gate of the transistor 753 of the circuit 23, SE[1] is the signal of the wiring 764 input to the pixel 20 of the first row, and SE[N] is the signal of the wiring 764 of the pixel 20 input to the last row, SE2[1] is a signal input to the wiring 765 of the pixel 20 of the first row, and SE2[N] is a signal input to the wiring 765 of the pixel 20 of the last row.

The period indicated by frame[n] corresponds to the period of the nth frame (n is a natural number of 2 or more). In the nth frame, a period 401 is a period in which the material of the (n-1)th frame is read, a period 402 is a period in which the first image data is read and a determination is made, and a period 400 is a period in which the row driver does not operate. . Further, the period 403 in the (n+1)th frame is a period in which the material of the nth frame is read.

Next, the operation of the pixel 20 shown in FIG. 33 will be described with reference to the flowchart shown in FIG. 37 and the timing chart shown in FIG. The image pickup apparatus according to an embodiment of the present invention operates in a global shutter mode, and the work in one frame is roughly classified into: acquisition of first image data; determination of first image data; acquisition of second image data; and previous The reading of the camera data of the frame. The acquisition of the first image data and the reading of the image data of the previous frame are performed simultaneously.

In FIGS. 37 and 38, an arbitrary nth frame will be described as a reference. The wiring 771 (VPD) and the wiring 773 (VSS) are at a low potential ("L"), and the wiring 772 (VRS) and the wiring 774 (VPI) are at a high potential ("H").

In FIG. 38, GWRS is the potential of the wiring 762 (GWRS), RS[1] is the potential of the wiring 763 (RS) of the specific pixel 20 of the first row, and RS[N] is the wiring 763 of the specific pixel 20 of the last row. The potential of (RS), CN[1] is the potential of the node CN of the specific pixel 20 of the first row, CN[N] is the potential of the node CN of the specific pixel 20 of the last row, and TX is the potential of the wiring 761 (TX) AN[1] is the potential of the node AN of the specific pixel 20 of the first row, AN[N] is the potential of the node AN of the specific pixel 20 of the last row, and FD[1] is the node of the specific pixel 20 of the first row. The potential of FD, FD[N], is the potential of node FD of the particular pixel 20 of the last row.

First, the acquisition of the first image data and the reading of the image data acquired in the previous frame will be described.

The first camera data is information for determining the illuminance (low illuminance or high illuminance) of the image pickup article. In the imaging mode of the first imaging data, since the imaging is performed under the condition that the node FD is only connected to the capacitor C71 with a low capacitance value, the node FD is saturated in a high illumination environment. Therefore, by determining the presence or absence of saturation of the node FD, it is possible to determine the illuminance of the image pickup article. In the timing chart of FIG. 38, the operation when the node FD of the first row is not saturated by the first image data and the node FD of the Nth row (last row) is saturated by the first image data is shown.

At time T1, when GWRS is set to "H", AN[1:N] is reset to become "H" (potential of wiring 772 (VRS)) (S1).

At time T2, when GWRS is set to "L", AN[1:N] starts to decrease according to illuminance (first exposure, S2)

At time T3, when RS[1:N] is set to "H" and CN[1:N] is set to "H", FD[1:N] is reset to become "H" (wiring 772 ( Potential of VRS) (S3). At this time, the node FD is electrically connected to the capacitor C72 via the transistor 744. In order to set CN[1:N] to "H", the wiring 765 (SE2)[1:N] can be set to "H" and the transistor 747 can be turned on, and the input of the terminal GCN of the output circuit 28 can be determined. The signal is set to "H".

At time T4, when SE2[1:N] is set to "H" and CN[1:N] is set to "L", the transistor 744 becomes non-conductive, whereby between the node FD and the capacitor C72 The electrical connection was cut. In order to set CN[1:N] to "L", the determination output circuit 28 can be set to the reset state and the terminal GCN can be set to "L". After time T4, the transistor 747 is rendered non-conductive by setting SE2[1:N] to "L", and CN[1:N] is held by the capacitor C73 or the like.

Further, at time T4, when RS[1:N] is set to "L" and TX is set to "H", the potential of the node AN is transmitted to the node FD, and the potential of the node FD starts to drop (S4).

At time T5, when TX is set to "L", FD[1:N] is held. Here is the acquisition of the first camera data.

Here, between time T1 and T3, SE[1] to SE[N] are sequentially "H" for a certain period, and the image data determined in the (n-1)th frame is read (S10'). . That is to say, the acquisition of the first image data of the nth frame described above is performed simultaneously with the reading of the image data determined in the (n-1)th frame. By reading the image data in the next frame by the above method, the time for exposure or the like can be extended even if the global shutter mode is employed. Therefore, an image with a wide dynamic range and low noise can be obtained under low illumination.

Fig. 39A is a timing chart for explaining reading of image data in the first line. SH is the potential of the gate of the transistor 752 supplied to the circuit 23, CL is the potential of the gate of the transistor 751 supplied to the circuit 23, and REF (RAMP) is the reference potential supplied to the comparator circuit 27, OUT2 It is the potential of the wiring 792 (OUT2), and COMP_OUT is the potential of the output terminal of the comparator circuit 27.

In FIG. 38, before time T3, RS[1] to RS[N] are sequentially "H" for a certain period of time, and the node FD is reset. This operation is based on the operation of the circuit 23 shown in Fig. 39A.

Next, the determination of the first imaging material and the operation based on the determination result will be described.

In time T6 to T8, SE[1] to SE[N] are sequentially "H" for a certain period of time, and the first image data is read out in rows, thereby saturating the nodes FD of all the effective pixels 20. Whether or not determination is made (S5).

Fig. 39B is a timing chart for explaining the reading of the first image data at times T6 to T8. In the readout period of the first image data, EN_CDS is set to "H" and CL is set to "H", and the bypass circuit 23 inputs the signal output from the pixel 20 to the comparator circuit 27. REF(CONST) is set to a fixed potential, and is a potential slightly higher than the potential output to the wiring 791 (OUT1) when the node FD is saturated. By the above operation, the presence or absence of saturation of the node FD can be determined based on the output of the comparator circuit 27. FIG. 39B shows a state when the node FD of the selected specific pixel 20 is saturated, whereby the potential output from the output terminal of the comparator circuit 27 is "L". Further, EN_CDS can also be set to "L", and the first image data can be read out without the circuit returning circuit 23. At this time, the potential output from the output terminal of the comparator circuit 27 is "H".

At this time, the first image data is used to determine the presence or absence of saturation of the node FD, and is not output to the outside. Therefore, the operation of the output circuit such as the circuit 25 (column driver) required for external output can be stopped.

The determination result of the first imaging data is output to the pixel 20 from which the first imaging material is read by the determination output circuit 28. Here, in order to input the determination result to the node CN of the pixel 20, the wiring 765 (SE2) of the same row is set to "H" for a fixed period in accordance with the output timing of the determination result.

In the pixel 20 whose node FD is not saturated, "L" is input to the node CN, whereby the transistor 744 does not become in an on state. Therefore, the node FD is only electrically connected to the capacitor C71, and the capacitance value of the node FD does not change. That is, the pixel 20 is set to an imaging mode suitable for low illumination imaging.

In the pixel 20 saturated by the determination node FD, "H" is input to the node CN, whereby the transistor 744 is turned on. Therefore, the node FD is electrically connected to the capacitor C71 and the capacitor C72, and the capacitance value of the node FD is increased (S6). That is, the pixel 20 is set to an imaging mode suitable for high illumination imaging. Here, it is the judgment of the first imaging material and the work based on the determination result.

Next, the acquisition of the second imaging material will be described.

The exposure work for acquiring the second image data can be performed before all the determination results are obtained. For example, as shown in FIG. 38, at time T7, GWRS is set to "H" and AN[1:N] is reset (S7). Then, at time T8, GWRS is set to "L", and a second exposure is performed before time T10 (S8). The exposure time of the second exposure may be the same as the exposure time of the first exposure. Alternatively, the exposure time of the second exposure may also be shorter than the exposure time of the first exposure.

At time T9 before the end of the second exposure, when RS[1:N] is set to "H", FD[1:N] is reset to become "H" (potential of wiring 772 (VRS)) ( S9).

At time T10, when the wiring 761 (TX) is set to "H", the potential of the node AN is transmitted to the node FD (S10).

At time T11, when the wiring 761 (TX) is set to "L", FD[1:N] is held. Here is the acquisition of the second camera data. In the (n+1)th frame, the second image data is read as the image data of the nth frame (S11).

By the above operation, the imaging mode of the second imaging material can be set in each of the pixels 20, and even if the image with the light and dark portions is captured, the wide dynamic range image held by the grayscale can be acquired.

The pixel 20 can also have the structure shown in FIG. The pixel 20 shown in FIG. 40 is different from the pixel 20 shown in FIG. 33 in the connection direction of the photoelectric conversion element PD. The pixel 20 shown in FIG. 40 can operate in accordance with the timing chart of FIG. At this time, the wiring 771 (VPD) and the wiring 774 (VPI) are at a high potential ("H"), and the wiring 772 (VRS) and the wiring 773 (VSS) are at a low potential ("L").

In this case, the node AN and the node FD are in an electronic saturation state at the time of resetting, and are in an electronically insufficient state in a high illuminance environment. Therefore, the potential changes of the node AN and the node FD are opposite to those of the pixel 20 shown in FIG. 33 described above.

Further, the pixel 20 may have the configuration shown in FIGS. 41A and 41B. Fig. 41A shows a structure in which the transistor 742 is not provided. In this configuration, the potential of the node AN can be reset by setting the potential of the wiring 771 (VPD) to a high potential. 41B is a structure in which one of the source and the drain of the transistor 745 is connected to the wiring 791 (OUT).

In addition, the transistor for the pixel 20 may have a structure in which a back gate is provided in the transistor 741 to the transistor 747 as shown in FIGS. 43A and 43B. Fig. 43A shows a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. In FIG. 43A, as an example, a case where the back gate is connected to the wiring 771 (VPD), the wiring 773 (VSS), or the wiring 775 (VSS2) that supplies the low potential is mentioned, but the back gate and the above wiring may be employed. The structure of a connection in . In addition, FIG. 43B is a structure in which the same potential as the front gate is applied to the back gate, and by adopting this configuration, the on-state current can be increased and the off-state current can be reduced. Further, the structure and the like shown in FIGS. 43A and 43B may be combined in such a manner that the desired transistor has appropriate electrical characteristics. Alternatively, a transistor having no back gate may be provided. Further, the structures of FIGS. 40, 41A and 41B and FIGS. 43A and 43B can be combined as needed.

As shown in FIG. 44, the pixel 20 may adopt a manner in which a plurality of pixels collectively use the transistor 743 to the transistor 747. 44 shows a structural example in which a plurality of pixels in the vertical direction use the transistor 743 to the transistor 747 in common, and it is also possible to employ a structure in which the plurality of pixels in the horizontal direction or the horizontal vertical direction use the transistor 743 to the transistor 747 in common. By adopting the above structure, the number of transistors each pixel has can be reduced.

In FIG. 44, the manner in which the four pixels collectively use the transistor 743 to the transistor 747 is shown, and the transistor 743 to the transistor 747 may be commonly used for two pixels, three pixels, or more than five pixels. Further, the structure and the structures shown in FIGS. 40, 41A and 41B and FIGS. 43A and 43B can be arbitrarily combined.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Embodiment 3

In the present embodiment, a transistor having an oxide semiconductor which can be used in one embodiment of the present invention will be described with reference to the drawings. Note that in the drawings of the present embodiment, some components are enlarged, reduced, or omitted for the sake of clarity.

45A and 45B are a plan view and a cross-sectional view of a transistor 101 according to an embodiment of the present invention. 45A is a plan view, and a cross section in the direction of the alternate long and short dash line B1-B2 shown in FIG. 45A corresponds to FIG. 45B. In addition, the cross section in the direction of the alternate long and short dash line B3-B4 shown in FIG. 45A corresponds to FIG. 47A. Further, the direction of the alternate long and short dash line B1-B2 is referred to as a channel length direction, and the direction of the alternate long and short dash line B3-B4 is referred to as a channel width direction.

The transistor 101 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 electrically connected to the oxide semiconductor layer 130, and an oxide semiconductor layer 130, and a conductive layer. The insulating layer 160 in contact with the layer 140 and the conductive layer 150, the conductive layer 170 in contact with the insulating layer 160, the insulating layer 175 in contact with the conductive layer 140, the conductive layer 150, the insulating layer 160 and the conductive layer 170, and the insulating layer 175 are in contact with Insulation layer 180. Further, the insulating layer 180 may have a function of planarizing the film as needed.

Here, the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170 can be used separately As a source electrode layer, a gate electrode layer, a gate insulating film, and a gate electrode layer.

In addition, the region 231, the region 232, and the region 233 shown in FIG. 45B can be used as a source region, a drain region, and a channel formation region, respectively. The region 231 is in contact with the conductive layer 140 and the region 232 is in contact with the conductive layer 150. By using the conductive material which is easily bonded to oxygen as the conductive layer 140 and the conductive layer 150, the electric resistance of the region 231 and the region 232 can be lowered.

Specifically, since the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150, oxygen defects are generated in the oxide semiconductor layer 130, and the oxygen defects and hydrogen remaining in the oxide semiconductor layer 130 or diffused from the outside The interaction between the regions 231 and 232 is a low resistance n-type.

Further, the functions of the "source" and "dip" of the transistor may be interchanged when using a transistor having a different polarity or when the current direction changes during operation of the circuit. Therefore, in the present specification, "source" and "drum" can be interchanged. Further, the "electrode layer" may also be referred to as "wiring."

The conductive layer 170 includes two layers of the conductive layer 171 and the conductive layer 172, but may be one or three or more layers. The same can be applied to other transistors described in the present embodiment.

The conductive layer 140 and the conductive layer 150 are a single layer, but may be a laminate of two or more layers. The same can be applied to other transistors described in the present embodiment.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 45C and 45D. 45C is a plan view of the transistor 102, and a cross section in the direction of the chain line C1-C2 shown in FIG. 45C corresponds to FIG. 45D. In addition, the cross section in the direction of the chain line C3-C4 shown in FIG. 45C corresponds to FIG. 47B. In addition, the direction of the chain line C1-C2 is referred to as the channel length direction, and the direction of the chain line C3-C4 is referred to as the channel width direction.

The structure of the transistor 102 is the same as that of the transistor 101 except that the end portion of the insulating layer 160 serving as the gate insulating film is not aligned with the end portion of the conductive layer 170 serving as the gate electrode layer. In the transistor 102, since the wider portion of the conductive layer 140 and the conductive layer 150 is covered by the insulating layer 160, the electric resistance between the conductive layer 140, the conductive layer 150 and the conductive layer 170 is high, and thus the electric crystal The body 102 has a feature that the gate leakage is small.

The transistor 101 and the transistor 102 are top gate structures having regions in which the conductive layer 170 overlaps the conductive layer 140 and the conductive layer 150. In order to reduce the parasitic capacitance, it is preferable to set the width in the channel length direction of the region to be 3 nm or more and less than 300 nm. In this configuration, since the offset region is not formed in the oxide semiconductor layer 130, it is easy to form a transistor having a high on-state current.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 45E and 45F. 45E is a plan view of the transistor 103, and a cross section in the direction of the alternate long and short dash line D1-D2 shown in FIG. 45E corresponds to FIG. 45F. In addition, the cross section in the direction of the alternate long and short dash line D3-D4 shown in FIG. 45E corresponds to FIG. 47A. In addition, the direction of the alternate long and short dash line D1-D2 is referred to as a channel length direction, and the direction of the alternate long and short dash line D3-D4 is referred to as a channel width direction.

The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, and a capping oxide. The insulating layer 175 of the semiconductor layer 130, the insulating layer 160 and the conductive layer 170, and the insulating layer 180 in contact with the insulating layer 175 are electrically connected to the oxide semiconductor layer 130 through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 140 and conductive layer 150. Further, an insulating layer (planarizing film) or the like which is in contact with the insulating layer 180, the conductive layer 140, and the conductive layer 150 may be included as needed.

The conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170 can be used as a source electrode layer, a gate electrode layer, a gate insulating film, and a gate electrode layer, respectively.

A region 231, a region 232, and a region 233 shown in Fig. 45F can be used as a source region, a drain region, and a channel formation region, respectively. The regions 231 and 232 are in contact with the insulating layer 175, and the electrical resistance of the regions 231 and 232 can be reduced, for example, by using an insulating material containing hydrogen as the insulating layer 175.

Specifically, the region 231 and the region 232 become the interaction between the oxygen defects generated in the regions 231 and 232 and the hydrogen diffused from the insulating layer 175 to the regions 231 and 232 through the process until the insulating layer 175 is formed. Low resistance n-type. Further, as the hydrogen-containing insulating material, for example, tantalum nitride, aluminum nitride, or the like can be used.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 46A and 46B. Fig. 46A is a plan view of the transistor 104, and a cross section in the direction of the alternate long and short dash line E1-E2 shown in Fig. 46A corresponds to Fig. 46B. In addition, the cross section in the direction of the alternate long and short dash line E3-E4 shown in FIG. 46A corresponds to FIG. 47A. In addition, the direction of the alternate long and short dash line E1-E2 is referred to as a channel length direction, and the direction of the alternate long and short dash line E3-E4 is referred to as a channel width direction.

The transistor 104 has the same structure as the transistor 103 except that the conductive layer 140 and the conductive layer 150 cover the end portion of the oxide semiconductor layer 130 and are in contact therewith.

A region 331 and a region 334 shown in FIG. 46B can be used as a source region, a region 332 and a region 335 can be used as a drain region, and a region 333 can be used as a channel formation region.

The resistance of the regions 331 and 332 can be reduced in the same manner as the regions 231 and 232 in the transistor 101.

The resistance of the regions 334 and 335 can be reduced in the same manner as the regions 231 and 232 in the transistor 103. Further, when the length of the region 334 and the region 335 in the channel length direction is 100 nm or less, preferably 50 nm or less, since the gate electric field contributes to prevention of a large drop in the on-state current, the region 334 may not be lowered. The resistance of region 335.

The structure of the transistor 103 and the transistor 104 is a self-aligned structure having no region in which the conductive layer 170 overlaps the conductive layer 140 and the conductive layer 150. The self-aligned transistor is suitable for high speed operation because the parasitic capacitance between the gate electrode layer and the source electrode layer and the gate electrode layer is extremely small.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 46C and 46D. Fig. 46C is a plan view of the transistor 105, and a cross section in the direction of the chain line F1-F2 shown in Fig. 46C corresponds to Fig. 46D. In addition, the cross section in the direction of the chain line F3-F4 shown in FIG. 46C corresponds to FIG. 47A. In addition, the direction of the chain line F1-F2 is referred to as the channel length direction, and the direction of the chain line F3-F4 is referred to as the channel width direction.

The transistor 105 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 electrically connected to the oxide semiconductor layer 130, and a conductive layer. 151. An insulating layer 160 that is in contact with the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, a conductive layer 170 that is in contact with the insulating layer 160, and an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, and an insulating layer 160. The insulating layer 175 in contact with the conductive layer 170, the insulating layer 180 in contact with the insulating layer 175, and the conductive layer 142 electrically connected to the conductive layer 141 and the conductive layer 151 through openings provided in the insulating layer 175 and the insulating layer 180, respectively. And a conductive layer 152. Further, an insulating layer or the like which is in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 may be provided as needed.

Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 without being in contact with the side surface.

The transistor 105 includes a conductive layer 141 and a conductive layer 151, and an opening portion including the insulating layer 175 and the insulating layer 180, and a conductive layer 142 electrically connected to the conductive layer 141 and the conductive layer 151 through the opening portion, respectively. Other than the conductive layer 152, the other structure is the same as that of the transistor 101. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) may be used as the source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) may be used as the gate electrode layer.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 46E and 46F. 46E is a plan view of the transistor 106, and a cross section in the direction of the alternate long and short dash line G1-G2 shown in FIG. 46E corresponds to FIG. 46F. In addition, the cross section in the direction of the alternate long and short dash line G3-G4 shown in FIG. 46A corresponds to FIG. 47A. Further, the direction of the alternate long and short dash line G1-G2 is referred to as a channel length direction, and the direction of the alternate long and short dash line G3-G4 is referred to as a channel width direction.

The transistor 106 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 electrically connected to the oxide semiconductor layer 130, and a conductive layer 151 in contact with the oxide semiconductor layer 130. The insulating layer 160, the conductive layer 170 in contact with the insulating layer 160, the insulating layer 175 in contact with the insulating layer 120, the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, and the insulating layer 175 The insulating layer 180 that is in contact with the conductive layer 142 and the conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 by openings provided in the insulating layer 175 and the insulating layer 180, respectively. Further, an insulating layer (planarizing film) or the like which is in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 may be provided as needed.

The conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 without being in contact with the side surface.

The structure of the transistor 106 is the same as that of the transistor 103 except that the conductive layer 141 and the conductive layer 151 are included. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) may be used as the source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) may be used as the gate electrode layer.

In the transistor 105 and the transistor 106, since the conductive layer 140 and the conductive layer 150 are not in contact with the insulating layer 120, oxygen in the insulating layer 120 is not easily taken up by the conductive layer 140 and the conductive layer 150, and oxygen is easily removed from the insulating layer. 120 is supplied to the oxide semiconductor layer 130.

Further, impurities for forming oxygen defects to increase conductivity may be added to the regions 231 and 232 in the transistor 103, the transistor 104, and the regions 334 and 335 in the transistor 106. As the impurity which forms oxygen defects in the oxide semiconductor layer, for example, phosphorus, arsenic, antimony, boron, aluminum, antimony, nitrogen, antimony, krypton, argon, krypton, neon, indium, fluorine, chlorine, titanium, or the like can be used. More than one of zinc and carbon. As a method of adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma-immersion ion implantation method, or the like can be used.

By adding the above element as an impurity element to the oxide semiconductor layer, the bond between the metal element and oxygen in the oxide semiconductor layer is cut to form an oxygen defect. The conductivity of the oxide semiconductor layer can be improved by the interaction between the oxygen defects contained in the oxide semiconductor layer and the hydrogen remaining in the oxide semiconductor layer or added later.

When hydrogen is added to an oxide semiconductor in which an impurity element is added to form an oxygen defect, hydrogen enters an oxygen defect to form a donor energy level in the vicinity of the conduction band. As a result, an oxide conductor can be formed. Here, the oxide conductor is an oxide semiconductor that directs electrochemistry. Further, the oxide conductor has translucency similar to that of the oxide semiconductor.

The oxide conductor is a degenerate semiconductor, and it can be inferred that the conduction band end is identical or substantially identical to the Fermi level. Therefore, the contact between the oxide conductor layer and the conductive layer serving as the source electrode layer and the gate electrode layer is an ohmic contact, and the oxide conductor layer and the conductive layer serving as the source electrode layer and the gate electrode layer can be reduced. Contact resistance between.

A cross-sectional view of the channel length direction as shown in FIGS. 48A to 48F and the passage of FIGS. 47C and 47D As shown in the cross-sectional view in the width direction of the track, the transistor of one embodiment of the present invention may also include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115. By using the conductive layer 173 as the second gate electrode layer (back gate), the on-state current or the control threshold voltage can be increased. Further, in the cross-sectional views shown in FIGS. 48A to 48F, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be shorter than that of the conductive layer 170.

When it is desired to increase the on-state current, for example, the same potential can be supplied to the conductive layer 170 and the conductive layer 173 to realize a double gate transistor. In addition, when it is desired to control the threshold voltage, the conductive layer 173 may be supplied with a constant potential different from that of the conductive layer 170. In order to supply the same potential to the conductive layer 170 and the conductive layer 173, for example, as shown in FIG. 47D, the conductive layer 170 may be electrically connected to the conductive layer 173 by a contact hole.

The transistor 101 to the transistor 106 in FIGS. 45A to 46F are examples in which the oxide semiconductor layer 130 is a single layer, but the oxide semiconductor layer 130 may also be a laminate. The oxide semiconductor layer 130 of the transistor 101 to the transistor 106 can be exchanged with the oxide semiconductor layer 130 shown in FIG. 49B, FIG. 49C or FIG. 49D, FIG. 49E.

49A is a plan view of the oxide semiconductor layer 130, and FIGS. 49B and 49C are cross-sectional views of the oxide semiconductor layer 130 of a two-layer structure. In addition, FIG. 49D and FIG. 49E are cross-sectional views of the oxide semiconductor layer 130 of a three-layer structure.

As the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, an oxide semiconductor layer or the like having different compositions from each other can be used.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 50A and 50B. Fig. 50A is a plan view of the transistor 107, and a cross section in the direction of the chain line H1-H2 shown in Fig. 50A corresponds to Fig. 50B. In addition, the cross section in the direction of the alternate long and short dash line H3-H4 shown in FIG. 50A corresponds to FIG. 52A. In addition, the direction of the chain line H1-H2 is referred to as the channel length direction, and the direction of the chain line H3-H4 is referred to as the channel width direction.

The transistor 107 includes an insulating layer 120 in contact with the substrate 115, a laminate formed of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b in contact with the insulating layer 120, and a conductive layer 140 and a conductive layer 150 electrically connected to the laminate. Contacting the laminate, the conductive layer 140, and the conductive layer 150 The oxide semiconductor layer 130c, the insulating layer 160 in contact with the oxide semiconductor layer 130c, the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 The insulating layer 175 is in contact with the insulating layer 180 in contact with the insulating layer 175. Further, the insulating layer 180 may have a function of planarizing the film as needed.

The transistor 107 has two layers (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b) in the region 231 and the region 232, and three layers of the oxide semiconductor layer 130 in the region 233 (the oxide semiconductor layer). 130a, the oxide semiconductor layer 130b, the oxide semiconductor layer 130c), and other structures other than the portion where the oxide semiconductor layer (the oxide semiconductor layer 130c) is interposed between the conductive layer 140 and the conductive layer 150 and the insulating layer 160 The same as the transistor 101.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 50C and 50D. 50C is a plan view of the transistor 108, and a cross section in the direction of the chain line I1-I2 shown in FIG. 50C corresponds to FIG. 50D. In addition, the cross section in the direction of the alternate long and short dash line I3-I4 shown in FIG. 50C corresponds to FIG. 52B. Further, the direction of the chain line I1-I2 is referred to as the channel length direction, and the direction of the chain line I3-I4 is referred to as the channel width direction.

The transistor 108 differs from the transistor 107 in that the ends of the insulating layer 160 and the oxide semiconductor layer 130c do not coincide with the ends of the conductive layer 170.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 50E and 50F. 50E is a plan view of the transistor 109, and a cross section in the direction of the chain line J1-J2 shown in FIG. 50E corresponds to FIG. 50F. In addition, the cross section in the direction of the chain line J3-J4 shown in FIG. 50E corresponds to FIG. 52A. In addition, the direction of the chain line J1-J2 is referred to as the channel length direction, and the direction of the chain line J3-J4 is referred to as the channel width direction.

The transistor 109 includes an insulating layer 120 in contact with the substrate 115, a laminate formed of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b in contact with the insulating layer 120, an oxide semiconductor layer 130c in contact with the laminate, and oxidation. The insulating layer 160 in contact with the semiconductor layer 130c, the conductive layer 170 in contact with the insulating layer 160, the insulating layer 175 covering the laminate, the oxide semiconductor layer 130c, the insulating layer 160 and the conductive layer 170, and the insulating layer 175 in contact with the insulating layer 175 a layer 180, a conductive layer 140 electrically connected to the stack by an opening provided in the insulating layer 175 and the insulating layer 180, and Conductive layer 150. Further, an insulating layer (planarizing film) or the like which is in contact with the insulating layer 180, the conductive layer 140, and the conductive layer 150 may be included as needed.

The transistor 109 has two layers (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b) in the region 231 and the region 232, and three layers of the oxide semiconductor layer 130 in the region 233 (the oxide semiconductor layer). The structure other than the 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c) is the same as that of the transistor 103.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 51A and 51B. Fig. 51A is a plan view of the transistor 110, and a cross section in the direction of the chain line K1-K2 shown in Fig. 51A corresponds to Fig. 51B. In addition, the cross section in the direction of the chain line K3-K4 shown in FIG. 51A corresponds to FIG. 52A. In addition, the direction of the chain line K1-K2 is referred to as the channel length direction, and the direction of the chain line K3-K4 is referred to as the channel width direction.

The transistor 110 has two layers of the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b) in the region 331 and the region 332, and three layers of the oxide semiconductor layer 130 in the region 333 (the oxide semiconductor layer) The structure other than the 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c) is the same as that of the transistor 104.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 51C and 51D. 51C is a plan view of the transistor 111, and a cross section in the direction of the alternate long and short dash line L1-L2 shown in FIG. 51C corresponds to FIG. 51D. In addition, the cross section in the direction of the alternate long and short dash line L3-L4 shown in FIG. 51C corresponds to FIG. 52A. Further, the direction of the alternate long and short dash line L1-L2 is referred to as a channel length direction, and the direction of the alternate long and short dash line L3-L4 is referred to as a channel width direction.

The transistor 111 includes an insulating layer 120 in contact with the substrate 115, a laminate formed of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b in contact with the insulating layer 120, a conductive layer 141 electrically connected to the laminate, and a conductive layer 151. An oxide semiconductor layer 130c in contact with the laminate, the conductive layer 141 and the conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, and the laminate and the conductive layer 141, the conductive layer 151, the oxide semiconductor layer 130c, the insulating layer 160 and the conductive layer 170 are in contact with the insulating layer 175, the insulating layer 180 in contact with the insulating layer 175, and the opening portion provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are not electrically connected to the conductive layer 141 and the conductive layer 151. In addition, according to needs It is also possible to have an insulating layer (planarizing film) or the like which is in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152.

The transistor 111 has two layers of the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b) in the regions 231 and 232, and three layers of the oxide semiconductor layer 130 in the region 233 (the oxide semiconductor layer). 130a, the oxide semiconductor layer 130b, the oxide semiconductor layer 130c), and other structures other than the portion where the oxide semiconductor layer (the oxide semiconductor layer 130c) is interposed between the conductive layer 141 and the conductive layer 151 and the insulating layer 160 The same as the transistor 105.

The transistor of one embodiment of the present invention can also adopt the structure shown in Figs. 51E and 51F. 51E is a plan view of the transistor 112, and a cross section in the direction of the chain line M1-M2 shown in FIG. 51E corresponds to FIG. 51F. In addition, the cross section in the direction of the chain line M3-M4 shown in FIG. 51E corresponds to FIG. 52A. In addition, the direction of the chain line M1-M2 is referred to as the channel length direction, and the direction of the chain line M3-M4 is referred to as the channel width direction.

The transistor 112 has two layers of the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b) in the region 331, the region 332, the region 334, and the region 335, and the oxide semiconductor layer 130 is three in the region 333. The structure other than the layer (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c) is the same as that of the transistor 106.

As shown in the cross-sectional view of the channel length direction of FIGS. 53A to 53F and the cross-sectional view of the channel width direction of FIGS. 52C and 52D, the transistor of one embodiment of the present invention may also include the oxide semiconductor layer 130 and the substrate 115. Conductive layer 173 between. When the conductive layer is used as the second gate electrode layer (back gate), the on-state current or the control threshold voltage can be further increased. Further, in the cross-sectional views shown in FIGS. 53A to 53F, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be shorter than that of the conductive layer 170.

Further, the transistor of one embodiment of the present invention can adopt the structure shown in FIGS. 54A and 54B. 54A is a plan view, and FIG. 54B is a cross-sectional view corresponding to the chain line N1-N2 and the chain line N3-N4 shown in FIG. 54A. In addition, in the plan view of Fig. 54A, a part of the assembly is omitted for the sake of clarity.

The transistor 113 shown in FIGS. 54A and 54B includes a substrate 115, an insulating layer 120 on the substrate 115, and an oxide semiconductor layer 130 on the insulating layer 120 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor). The layer 130c); the conductive layer 140 and the conductive layer 150 in contact with the oxide semiconductor layer 130 and spaced apart from each other; the insulating layer 160 in contact with the oxide semiconductor layer 130c; and the conductive layer 170 in contact with the insulating layer 160. Further, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are provided in the opening portion which is formed in the insulating layer 190 on the transistor 113 and reaches the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the insulating layer. Layer 120.

In the structure of the transistor 113, in the structure of the transistor 113, the region where the conductor serving as the source electrode or the drain electrode overlaps with the conductor serving as the gate electrode is small, whereby the parasitic capacitance can be made small. Thus, the transistor 113 is suitable for components of circuits that require high speed operation. As shown in FIG. 54B, the top surface of the transistor 113 is preferably planarized by a CMP method or the like, but it may not be planarized.

As shown in the top view shown in FIGS. 55A and 55B (only the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150 are shown), the conductive layer 140 (source electrode) in the transistor of one embodiment of the present invention can be made. The width (W _SD ) of the layer) and the conductive layer 150 (the drain electrode layer) is longer or shorter than the width (W _OS ) of the oxide semiconductor layer 130. When meeting W _OS When W _SD (W _SD is W _OS or less), the gate electric field is easily applied to the entire oxide semiconductor layer, and the electrical characteristics of the transistor can be improved. Further, as shown in FIG. 55C, the conductive layer 140 and the conductive layer 150 may be formed only in a region overlapping the oxide semiconductor layer 130.

In any of the transistors (the transistor 101 to the transistor 113) of one embodiment of the present invention, the conductive layer 170 as the gate electrode layer is interposed as the insulating layer 160 of the gate insulating film in the channel width direction. The oxide semiconductor layer 130 is electrically surrounded, whereby the on-state current can be increased. This transistor structure is referred to as a surrounded channel (s-channel) structure.

In the transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b and the transistor having the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the oxide semiconductor layer is appropriately selected by arranging Two or three layers of material of 130 may flow current through the oxide semiconductor layer 130b. Since the current flows through the peroxide semiconductor layer 130b, it is not easily affected by the interface scattering, so that a large on-state current can be obtained. Thereby, the on-state current is sometimes increased by increasing the thickness of the oxide semiconductor layer 130b.

By adopting the above structure, the electrical characteristics of the transistor can be improved.

The structure shown in this embodiment can be implemented in appropriate combination with the structure shown in the other embodiment.

Embodiment 4

In the present embodiment, the module of the transistor shown in the second embodiment will be described in detail.

As the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate on which the surface is insulated, or the like can be used. Alternatively, as the substrate 115, a germanium substrate on which a transistor or a photodiode is formed may be used, and an insulating layer, a wiring, a conductor used as a contact plug, and the like are formed on the substrate. Further, when a p-channel type transistor is formed for the germanium substrate, it is preferable to use a germanium substrate having an n ^- -type conductivity type. In addition, an SOI substrate including an n ^- type or i-type germanium layer can also be used. Further, when the transistor provided for the germanium substrate is a p-channel type transistor, it is preferable to use a germanium substrate in which the crystal alignment of the surface on which the transistor is formed is the (110) plane. The mobility can be improved by forming a p-channel type transistor on the (110) plane.

The insulating layer 120 may have a function of supplying oxygen to the oxide semiconductor layer 130 in addition to a function of preventing impurities from diffusing from components included in the substrate 115. Therefore, the insulating layer 120 is preferably an oxygen-containing insulating film, more preferably an insulating film containing more oxygen than a stoichiometric composition. In the insulating layer 120, the amount of oxygen released in terms of oxygen atoms measured by a TDS (Thermal Desorption Spectroscopy) method is preferably 1.0 × 10 ¹⁹ atoms/cm ³ or more. Note that the surface temperature of the film at the time of the above TDS analysis is 100 ° C or more and 700 ° C or less or 100 ° C or more and 500 ° C or less. Further, when the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 also functions as an interlayer insulating film. In this case, it is preferable to perform a planarization process by a CMP method or the like to flatten the surface.

For example, as the insulating layer 120, an oxide insulating film such as aluminum oxide, magnesium oxide, cerium oxide, cerium oxynitride, gallium oxide, cerium oxide, cerium oxide, zirconium oxide, cerium oxide, cerium oxide, cerium oxide or cerium oxide can be used. a nitride insulating film such as tantalum nitride, niobium oxynitride, aluminum nitride or aluminum oxynitride or These are the mixed materials. Further, a laminate of the above materials can also be used.

In the present embodiment, the oxide semiconductor layer 130 of the transistor has a three-layer structure in which the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side. The main and detailed description.

Further, when the oxide semiconductor layer 130 is a single layer, a layer corresponding to the oxide semiconductor layer 130b described in the present embodiment can be used.

Further, when the oxide semiconductor layer 130 is two layers, a stack of a layer corresponding to the oxide semiconductor layer 130a and the layer corresponding to the oxide semiconductor layer 130b stacked in this order from the insulating layer 120 side may be used. Floor. When this structure is employed, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can also be exchanged.

When the oxide semiconductor layer 130 is four or more layers, for example, a structure in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having the three-layer structure described in the present embodiment can be employed.

For example, the oxide semiconductor layer 130b uses an electron affinity (energy difference between the vacuum level and the conduction band bottom) to be larger than that of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c. The electron affinity is a value obtained by subtracting the energy difference (energy gap) between the bottom of the conduction band and the top of the valence band from the energy difference (free potential) between the vacuum level and the top of the valence band.

The oxide semiconductor layer 130a and the oxide semiconductor layer 130c preferably contain one or more metal elements constituting the oxide semiconductor layer 130b. For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c preferably have an energy of a conduction band bottom closer to a vacuum energy level of 0.05 eV, 0.07 eV, 0.1 eV or 0.15 than the conduction band bottom of the oxide semiconductor layer 130b. An oxide semiconductor having an eV or more and 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less is formed.

In the above structure, when an electric field is applied to the conductive layer 170, the channel is formed in the oxide semiconductor layer 130b having the lowest energy of the conduction band bottom in the oxide semiconductor layer 130. Thus, it can be said that the oxide semiconductor layer 130b has a region to be used as a semiconductor, and the oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a function of being used as an insulator or a semi-insulator.

Further, since the oxide semiconductor layer 130a includes one or more metal elements constituting the oxide semiconductor layer 130b, the oxide semiconductor layer 130b is compared with the interface between the oxide semiconductor layer 130b and the insulating layer 120. The interface of the oxide semiconductor layer 130a does not easily form an interface level. The above-mentioned interface energy level sometimes forms a channel, and thus sometimes causes a variation in the threshold voltage of the transistor. Therefore, by providing the oxide semiconductor layer 130a, variation in electrical characteristics such as threshold voltage of the transistor can be suppressed. In addition, the reliability of the transistor can be improved.

Further, since the oxide semiconductor layer 130c includes one or more metal elements constituting the oxide semiconductor layer 130b, compared with the interface between the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160), Carrier scattering is less likely to occur in the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c. Therefore, by providing the oxide semiconductor layer 130c, the field effect mobility of the transistor can be improved.

For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c may use a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf and having an atomic ratio of the element higher than that of the oxide semiconductor The material of layer 130b. Specifically, the atomic ratio of the above element is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more of the oxide semiconductor layer 130b. Since the above element is strongly bonded to oxygen, it has a function of suppressing generation of oxygen defects in the oxide semiconductor layer. From this, it can be said that oxygen defects are less likely to occur in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c than the oxide semiconductor layer 130b.

Further, the oxide semiconductor which can be used for the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably contains at least In or Zn. Alternatively, it is preferred to contain both In and Zn. Further, in order to reduce variations in electrical characteristics of the transistor using the oxide semiconductor, it is preferable to further include a stabilizer in addition to the above elements.

Examples of the stabilizer include Ga, Sn, Hf, Al, and Zr. Further, examples of the other stabilizer include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

For example, as the oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide can be used. , In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In- Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb- Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxidation , In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxidation , In-Hf-Al-Zn oxide.

Here, for example, In—Ga—Zn oxide refers to an oxide containing In, Ga, and Zn as a main component. Further, a metal element other than In, Ga, or Zn may be contained. Further, in the present specification, a film made of an In—Ga—Zn oxide is referred to as an IGZO film.

Further, a material represented by InMO ₃ (ZnO) _m (m>0, and m is not an integer) may also be used. M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce or Nd. Further, a material represented by In ₂ SnO ₅ (ZnO) _n (n>0, and n is an integer) may also be used.

Further, it is preferable that the indium content of the oxide semiconductor layer 130b is larger than the indium content of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c. In an oxide semiconductor, the s-orbital domain of a heavy metal mainly contributes to carrier conduction, and the overlap of the s-orbital domain is increased by increasing the ratio of In, whereby the ratio of In is more than that of M. The ratio of In is equal to or less than the oxide of M. Therefore, by using an oxide having a high indium content for the oxide semiconductor layer 130b, a transistor having a high field efficiency mobility can be realized.

The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of the oxide semiconductor layer 130b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, and more preferably 10 nm or more and 100 nm or less. Further, the thickness of the oxide semiconductor layer 130c is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less. Further, the oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 130c.

In order to impart stable electrical characteristics to a transistor using an oxide semiconductor layer as a channel, it is effective to make the oxide semiconductor layer essential (i-type) or substantially essential by reducing the impurity concentration in the oxide semiconductor layer. . Here, "substantially essential" means that the oxide semiconductor layer has a carrier density of less than 1 × 10 ¹⁹ /cm ³ , less than 1 × 10 ¹⁵ /cm ³ , less than 1 × 10 ¹³ /cm ³ , or low. It is 1 × 10 ⁸ /cm ³ and 1 × 10 ^-9 /cm ³ or more.

Further, for the oxide semiconductor layer, hydrogen, nitrogen, carbon, germanium, and a metal element other than the main component are impurities. For example, hydrogen and nitrogen cause the formation of a donor energy level and increase the carrier density. Further, germanium causes formation of an impurity level in the oxide semiconductor layer. This impurity level becomes a trap, and it is possible to deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration of the interface in the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c or in each layer.

In order to make the oxide semiconductor layer essentially or substantially intrinsic, the oxide semiconductor layer is controlled in such a manner that the hydrogen concentration measured by SIMS (Secondary Ion Mass Spectrometry) is 2×. 10 ²⁰ atoms/cm ³ or less, preferably 5 × 10 ¹⁹ atoms/cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, further preferably 5 × 10 ¹⁸ atoms / cm ³ or less, and a region of 1 × 10 ¹⁷ atoms/cm ³ or more; a nitrogen concentration of less than 5 × 10 ¹⁹ atoms/cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less. Further, it is preferably 5 × 10 ¹⁷ atoms / cm ³ or less, and is a region of 5 × 10 ¹⁶ atoms / cm ³ or more.

Further, when ruthenium or carbon is contained at a high concentration, it is possible to lower the crystallinity of the oxide semiconductor layer. In order not to lower the crystallinity of the oxide semiconductor layer, the oxide semiconductor layer is controlled so as to have a germanium concentration of less than 1 × 10 ¹⁹ atoms/cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ^3, and is 1 × 10 ¹⁸ atoms or more regions of the ³ / cm; a carbon concentration less than ^{1 × 10 19 atoms / cm 3} , preferably less than ^{5 × 10 18 atoms / cm 3} , more preferably less than 1 ×10 ¹⁸ atoms/cm ³ and a region of 6 × 10 ¹⁷ atoms/cm ³ or more.

Further, the off-state current of the transistor in which the highly purified oxide semiconductor layer is used for the channel formation region as described above is extremely small. For example, it is possible to reduce the off-state current per channel width of the transistor when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V to several yA/μm to several zA/μm.

As the gate insulating film of the transistor, an insulating film containing germanium is often used. Therefore, it is preferable that the region serving as a channel of the oxide semiconductor layer is not in contact with the gate insulating film as in the transistor of one embodiment of the present invention. . In addition, when the channel is formed in the gate insulating film and the oxide semiconductor layer In the case of the interface, carrier scattering occurs at the interface, and the field effect mobility of the transistor is lowered. From the above viewpoint, it can be said that it is preferable to separate the region serving as the channel of the oxide semiconductor layer from the gate insulating film.

Therefore, by providing the oxide semiconductor layer 130 with a laminated structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, it is possible to form a channel in the oxide semiconductor layer 130b, thereby being able to form A transistor with high field-effect mobility and stable electrical characteristics.

In the energy band structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the energy of the conduction band bottom continuously changes. This is also understood from the case where the compositions of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are similar to each other, and oxygen is easily diffused in the above three. In this way, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are laminates having different compositions, but they are continuous in physical properties. Therefore, in the drawing, the interface of each of the stacked oxide semiconductor layers is indicated by a broken line.

The oxide semiconductor layer 130 in which the main components are the same and laminated is not simply laminated, but to form a continuous bond (here, especially a U-shape in which the energy of the conduction band bottom between the layers continuously changes) (U-shape) Well) structure) formed in a way. In other words, the laminated structure is formed in such a manner that impurities of a defect level such as a trapping center or a recombination center are not formed between the interfaces of the respective layers. If impurities are mixed between the layers of the stacked oxide semiconductor layers, the energy band loses continuity, and thus the carriers are trapped or recombined at the interface to disappear.

For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c may use In:Ga:Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5 , In:Ga-Zn oxide such as 1:6:4, 1:9:6, 1:10:1 or a value (atomic ratio), or Ga:Zn=10:1 or a value in the vicinity thereof Ga-Zn oxide such as (atomic ratio). The oxide semiconductor layer 130b may use In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, 3:1:2, 4:2:3, 4:2:4.1 or In-Ga-Zn oxide or the like having a value (atomic ratio) in the vicinity. In addition, when the film is formed by using the oxide as a sputtering target, the atomic ratio of the sputtering target and the atomic ratio of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are formed. Not necessarily the same.

The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and a channel is formed in the oxide semiconductor layer 130b. The energy of the conduction band bottom of the oxide semiconductor layer 130 is continuously changed. Therefore, the oxide semiconductor layer 130 may be referred to as a U-type well. Further, the channel having the above structure may also be referred to as a buried channel.

Further, although it is possible to form a trap level due to impurities or defects between the insulating layer such as the oxide semiconductor layer 130a and the hafnium oxide film and the interface between the insulating layer such as the oxide semiconductor layer 130c and the hafnium oxide film, The oxide semiconductor layer 130a and the oxide semiconductor layer 130c are provided to separate the oxide semiconductor layer 130b from the trap level.

Note that the energy difference between the energy of the conduction band bottom of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and the energy of the conduction band bottom of the oxide semiconductor layer 130b is small, and the electrons of the oxide semiconductor layer 130b sometimes pass the energy. The difference reaches the trap level. When electrons are trapped by the trap level, a negative charge is generated at the interface of the insulating layer, causing the threshold voltage of the transistor to drift in the positive direction.

The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably include a crystal portion. In particular, by using c-axis alignment crystallization, it is possible to impart stable electrical characteristics to the transistor. Further, the crystal of the c-axis alignment is resistant to bending, whereby the reliability of the semiconductor device using the flexible substrate can be improved.

As the conductive layer 140 serving as the source electrode layer and the conductive layer 150 serving as the gate electrode layer, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and the like can be used. A single layer or laminate of materials in the alloy of the metallic material. Typically, it is particularly preferable to use Ti which is easily bonded to oxygen or a W which has a high melting point which can be treated at a higher temperature later. Further, it is also possible to use a low-resistance alloy such as Cu or Cu-Mn and a laminate of the above materials. In the transistor 105, the transistor 106, the transistor 111, and the transistor 112, for example, W can be used as the conductive layer 141 and the conductive layer 151, and a laminated film of Ti and Al can be used as the conductive layer 142 and the conductive layer 152.

The above material has a property of extracting oxygen from the oxide semiconductor layer. Thereby, in a region of a part of the oxide semiconductor layer in contact with the above material, oxygen in the oxide semiconductor layer is desorbed, and oxygen defects are formed in the oxide semiconductor layer. A trace amount of hydrogen contained in the film is bonded to the oxygen defect to make the region significantly n-type. Therefore, the n-type region can be used as the source or drain of the transistor.

In addition, when the conductive layer 140 and the conductive layer 150 are formed using W, the conductive layer 140 and the conductive layer 150 may be doped with nitrogen. By doping nitrogen, the nature of the extracted oxygen can be moderately reduced, whereby the n-type region can be prevented from expanding to the channel region. Further, by laminating the conductive layer 140 and the conductive layer 150 on the n-type semiconductor layer to bring the n-type semiconductor layer into contact with the oxide semiconductor layer, it is possible to prevent the n-type region from spreading to the channel region. As the n-type semiconductor layer, an In-Ga-Zn oxide to which nitrogen is added, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like can be used.

As the insulating layer 160 used as the gate insulating film, aluminum oxide, magnesium oxide, cerium oxide, cerium oxynitride, cerium oxynitride, cerium nitride, gallium oxide, cerium oxide, cerium oxide, zirconium oxide, or oxidation may be used. One or more insulating films of cerium, cerium oxide, cerium oxide and cerium oxide. Further, the insulating layer 160 may also be a laminate of the above materials. Further, the insulating layer 160 may contain La, N, Zr or the like as an impurity.

Further, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 contains, for example, oxygen, nitrogen, helium, neon, or the like. Specifically, it is preferable to contain cerium oxide and cerium oxide or cerium oxide and cerium oxynitride.

The relative dielectric constant of cerium oxide and aluminum oxide is higher than that of cerium oxide or cerium oxynitride. Therefore, the thickness of the insulating layer 160 can be made larger than in the case of using yttrium oxide, whereby the leakage current caused by the tunneling current can be reduced. That is to say, a transistor having a small off-state current can be realized. Further, cerium oxide including a crystalline structure has a high relative dielectric constant as compared with cerium oxide including an amorphous structure. Therefore, in order to form a transistor having a small off-state current, it is preferable to use ruthenium oxide having a crystal structure. Examples of the crystal structure include a monoclinic crystal structure, a cubic crystal structure, and the like. However, one embodiment of the present invention is not limited thereto.

Further, as the insulating layer 120 and the insulating layer 160 that are in contact with the oxide semiconductor layer 130, a film having a small amount of release of nitrogen oxides is preferably used. When the insulating layer having a large amount of released nitrogen oxides is in contact with the oxide semiconductor, the energy density may be increased due to the nitrogen oxide. As the insulating layer 120 and the insulating layer 160, for example, an oxide insulating layer such as a hafnium oxynitride film or an aluminum oxynitride film having a small amount of release of nitrogen oxides can be used.

The yttrium oxynitride film having a small amount of released nitrogen oxides is a film having a larger amount of ammonia released than the amount of nitrogen oxides released by TDS analysis, and typically has an ammonia release amount of 1 × 10 ¹⁸ cm ^-3 or more and 5 ×10 ¹⁹ cm ^-3 or less. Further, the amount of ammonia released is a release amount obtained by heat treatment of a film surface temperature of 50 ° C or more and 650 ° C or less, preferably 50 ° C or more and 550 ° C or less.

By using the above oxide insulating layer as the insulating layer 120 and the insulating layer 160, the drift of the threshold voltage of the transistor can be reduced, whereby the variation in the electrical characteristics of the transistor can be reduced.

As the conductive layer 170 used as the gate electrode layer, for example, a conductive film of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W can be used. Further, an alloy of the above materials or a conductive nitride of the above materials may also be used. Further, a laminate of a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials may be used. Typically, a laminate of tungsten, tungsten, and titanium nitride, a laminate of tungsten and tantalum nitride, or the like can be used. Further, an alloy such as low-resistance Cu or Cu-Mn or a laminate of the above materials and an alloy such as Cu or Cu-Mn may be used. In the present embodiment, tantalum nitride is used as the conductive layer 171, and tungsten is used as the conductive layer 172 to form the conductive layer 170.

As the insulating layer 175, a hydrogen-containing tantalum nitride film or an aluminum nitride film or the like can be used. In the transistor 103, the transistor 104, the transistor 106, the transistor 109, the transistor 110, and the transistor 112 shown in Embodiment 2, an oxide semiconductor layer can be formed by using an insulating film containing hydrogen as the insulating layer 175. Part of the n-type. Further, the nitride insulating film is also used as a film for blocking moisture or the like, and the reliability of the transistor can be improved.

Further, an aluminum oxide film can also be used as the insulating layer 175. In particular, it is preferable to use an aluminum oxide film as the insulating layer 175 in the transistor 101, the transistor 102, the transistor 105, the transistor 107, the transistor 108, and the transistor 111 shown in the second embodiment. The aluminum oxide film has a high barrier effect of not transmitting impurities such as hydrogen and moisture and oxygen. Therefore, the aluminum oxide film is suitably used as a protective film having an effect of preventing impurities such as hydrogen and moisture from being mixed into the oxide semiconductor layer 130 in the process of manufacturing the transistor and after manufacturing the transistor; preventing release of oxygen from the oxide semiconductor layer Preventing unwanted release of oxygen from the insulating layer 120. Further, oxygen contained in the aluminum oxide film may be diffused into the oxide semiconductor layer.

Further, an insulating layer 180 is preferably formed on the insulating layer 175. As the insulating layer, magnesium oxide, cerium oxide, cerium oxynitride, cerium oxynitride, cerium nitride, gallium oxide, cerium oxide, or the like may be used. One or more insulating films of cerium oxide, zirconium oxide, cerium oxide, cerium oxide, cerium oxide, and cerium oxide. Further, the insulating layer may also be a laminate of the above materials.

Here, the insulating layer 180 preferably contains more oxygen than the stoichiometric composition as the insulating layer 120. Oxygen released from the insulating layer 180 can be diffused through the insulating layer 160 to the channel forming region of the oxide semiconductor layer 130, so that oxygen can be filled in the oxygen deficiency formed in the channel forming region. Thereby, stable transistor electrical characteristics can be obtained.

In order to achieve high integration of a semiconductor device, it is necessary to perform miniaturization of the transistor. On the other hand, it is known that with the miniaturization of the transistor, the electrical characteristics of the transistor are deteriorated, and in particular, the shortening of the channel width causes a decrease in the on-state current.

In the transistor 107 to the transistor 112 of one embodiment of the present invention, the oxide semiconductor layer 130c is formed in such a manner as to cover the oxide semiconductor layer 130b in which the channel is formed, and the channel forming layer is not in contact with the gate insulating film. Therefore, carrier scattering generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-state current of the transistor can be increased.

Further, in the transistor of one embodiment of the present invention, as described above, the gate electrode layer (conductive layer 170) is formed so as to electrically surround the oxide semiconductor layer 130 in the channel width direction, and thus the oxide The semiconductor layer 130 is applied with a gate electric field in addition to a gate electric field in a direction perpendicular to the top surface, and a direction perpendicular to the side surface. In other words, a gate electric field is applied to the entire channel forming layer and the effective channel width is enlarged, whereby the on-state current can be further increased.

Further, in the transistor in which the oxide semiconductor layer 130 of the embodiment of the present invention has a two-layer or three-layer structure, by forming the oxide semiconductor layer 130b on which the channel is formed on the oxide semiconductor layer 130a, it is possible to obtain It is not easy to form an interface level effect. Further, in the transistor in which the oxide semiconductor layer 130 of the embodiment of the present invention has a three-layer structure, by disposing the oxide semiconductor layer 130b in the middle of the three-layer structure, it is simultaneously obtained to eliminate impurities mixed from above and below. The effect of the effect, etc. Therefore, in addition to increasing the on-state current of the above transistor, stabilization of the threshold voltage and a decrease in the S value (sub-critical value) can be achieved. Therefore, the current when the gate voltage VG is 0 V can be reduced, and the power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Further, the transistor of one embodiment of the present invention can suppress deterioration of electrical characteristics due to miniaturization, thereby It is said to be suitable for a semiconductor device with high integration.

Although various films such as a metal film, a semiconductor film, and an inorganic insulating film described in the present embodiment can be typically formed by a sputtering method or a plasma CVD method, they may be formed by other methods such as a thermal CVD method. Examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Vapor Deposition) method and an ALD (Atomic Layer Deposition) method.

Since the thermal CVD method is a film formation method that does not use plasma, it has an advantage of not causing defects caused by plasma damage.

Further, film formation by a thermal CVD method may be performed by simultaneously supplying a source gas and an oxidant into a chamber, and setting a pressure in the chamber to atmospheric pressure or a reduced pressure to cause a reaction in the vicinity of the substrate or on the substrate.

Film formation by the ALD method can be carried out by setting the pressure in the chamber to atmospheric pressure or reduced pressure, introducing the source gas for the reaction into the chamber and reacting, and repeatedly introducing the gas in this order. It is also possible to introduce the source gas together with an inert gas (argon or nitrogen, etc.) as a carrier gas. For example, two or more source gases may be sequentially supplied into the chamber. At this time, an inert gas is introduced after the first source gas reacts, and then a second source gas is introduced to prevent mixing of the plurality of source gases. Alternatively, the first source gas may be discharged by vacuum evacuation without introducing an inert gas, and then the second source gas may be introduced. The first source gas adheres to the surface of the substrate and reacts to form a first layer, and the second source gas introduced thereafter adheres and reacts, whereby the second layer is laminated on the first layer to form a thin film. By introducing the gas a plurality of times in this order repeatedly until a desired thickness is obtained, a film having good step coverage can be formed. Since the thickness of the film can be adjusted according to the number of times the gas is repeatedly introduced, the ALD method can accurately adjust the thickness and is suitable for manufacturing a micro FET.

Various films such as a metal film, a semiconductor film, and an inorganic insulating film disclosed in the above-described embodiments can be formed by a thermal CVD method such as an MOCVD method or an ALD method. For example, when an In-Ga-Zn-O film is formed, it can be used. Trimethyl indium (In(CH ₃ ) ₃ ), trimethylgallium (Ga(CH ₃ ) ₃ ), and dimethyl zinc (Zn(CH ₃ ) ₂ ). Not limited to the above combination, triethylgallium (Ga(C ₂ H ₅ ) ₃ ) may be used instead of trimethylgallium, and diethyl zinc (Zn(C ₂ H ₅ ) ₂ ) may be used instead of dimethyl zinc. .

For example, when a ruthenium oxide film is formed using a film forming apparatus using an ALD method, the following two gases are used: by a liquid containing a solvent and a ruthenium precursor (nonyl alkoxide, tetramethylammonium oxime (TDMAH, Hf) a source gas obtained by gasification of [N(CH ₃ ) ₂ ] ₄ ) or a guanamine such as tetrakis(ethylmethylguanamine); and ozone (O ₃ ) used as an oxidizing agent.

For example, when an aluminum oxide film is formed using a film forming apparatus using an ALD method, the following two gases are used: by a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH ₃ ) ₃ ), etc.) a source gas obtained by gasification; and H ₂ O used as an oxidizing agent. Other materials include tris(dimethylammonium)aluminum, triisobutylaluminum, and aluminumtris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, when a silicon oxide film is formed using a ALD deposition method means that hexachloro-disilane is attached to the deposition surface, supplying an oxidizing gas (O _2, nitrous oxide) is reacted with a radical deposit Reacts.

For example, when a tungsten film is formed using a film forming apparatus using an ALD method, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are sequentially introduced to form a tungsten film. Note that it is also possible to use SiH ₄ gas instead of B ₂ H ₆ gas.

For example, when an oxide semiconductor layer such as an In-Ga-Zn-O layer is formed using a film forming apparatus using an ALD method, In(CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced to form an In-O layer, and then Ga is sequentially introduced. The (CH ₃ ) ₃ gas and the O ₃ gas form a GaO layer, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are sequentially introduced to form a ZnO layer. Note that the order of these layers is not limited to the above examples. These gases may also be used to form a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, a Ga-Zn-O layer, or the like. Note that although H ₂ O gas obtained by bubbling with an inert gas such as Ar may be used instead of O ₃ gas, it is preferable to use O ₃ gas not containing H.

When an oxide semiconductor layer is formed, a counter target sputtering apparatus can also be used. The film forming method using the counter target sputtering apparatus may also be referred to as VDSP (vapor deposition SP).

By forming the oxide semiconductor layer using the opposite target sputtering apparatus, it is possible to reduce plasma damage generated when the oxide semiconductor layer is formed. Therefore, oxygen deficiency in the film can be reduced. In addition, By using a counter target sputtering apparatus, film formation can be performed at a low pressure, whereby the impurity concentration (for example, hydrogen, rare gas (argon or the like), water, and the like) in the formed oxide semiconductor layer can be reduced.

The structure shown in this embodiment can be implemented in appropriate combination with the structure shown in the other embodiment.

Embodiment 5

Hereinafter, the structure of the oxide semiconductor layer which can be used in one embodiment of the present invention will be described.

In the present specification, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, the state in which the angle is -5 or more and 5 or less is also included. Further, "vertical" means a state in which the angle of the two straight lines is 80° or more and 100° or less. Therefore, the state in which the angle is 85° or more and 95° or less is also included.

Note that in the present specification, the hexagonal system includes a trigonal system and a rhombohedral system.

<Structure of Oxide Semiconductor>

Next, the structure of the oxide semiconductor will be described.

Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. As non-single-crystal oxide semiconductors, there are CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and non- A crystalline oxide semiconductor or the like.

From other viewpoints, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

In general, an amorphous structure has the following characteristics: isotropic and has an uneven structure; is in a quasi-steady state and the atomic configuration is not immobilized; the bond angle is not fixed; and has a short-range order Sex without long-term order; etc.

From the opposite point of view, a stable oxide semiconductor cannot be referred to as a completely amorphous oxide semiconductor. In addition, an oxide semiconductor which is not isotropic (for example, has a periodic structure in a minute region) cannot be referred to as a completely amorphous oxide semiconductor. On the other hand, a-like OS does not have an isotropic but unstable structure with voids. On the point of instability, the a-like OS is close in physical properties to the amorphous oxide semiconductor.

<CAAC-OS>

First, explain CAAC-OS.

CAAC-OS is one of oxide semiconductors containing a plurality of c-axis aligned crystal portions (also referred to as particles).

A case where the CAAC-OS is analyzed using an X-ray Diffraction (XRD) apparatus will be described. For example, when the structure of the CAAC-OS including the InGaZnO ₄ crystal classified into the space group R-3m is analyzed by the out-of-plane method, as shown in Fig. 56A, a peak appears around the diffraction angle (2θ) of 31°. . Since this peak is derived from the (009) plane of the InGaZnO ₄ crystal, it can be confirmed that the crystal has a c-axis orientation in CAAC-OS, and the c-axis faces a plane substantially perpendicular to the film forming CAAC-OS (also referred to as The direction in which the face is formed or the top surface. Note that in addition to the peak in the vicinity of 31° of 2θ, a peak may occur even when 2θ is around 36°. The peak in the vicinity of 2θ of 36° is caused by the crystal structure classified into the space group Fd-3m. Therefore, it is preferable that the peak does not occur in the CAAC-OS.

On the other hand, when the structure of the CAAC-OS is analyzed by the in-plane method in which X-rays are incident on the sample in a direction parallel to the surface to be formed, a peak appears in the vicinity of 2θ of 56°. This peak is derived from the (110) plane of the InGaZnO ₄ crystal. Further, even if 2θ is fixed at around 56° and analysis is performed under the condition that the sample is rotated by the normal vector of the sample surface (Φ axis), the Φ scan is not observed as shown in FIG. 56B. Peak. On the other hand, when the single crystal InGaZnO ₄ is fixed to the 2θ near 56 ° to Φ scan, as shown in FIG observed a peak derived from crystal plane equivalent to six of the (110) plane 56C. Therefore, it was confirmed by structural analysis using XRD that the alignment of the a-axis and the b-axis in CAAC-OS has no regularity.

Next, CAAC-OS using electron diffraction analysis will be described. For example, when an electron beam having a beam diameter of 300 nm is incident on a CAAC-OS containing InGaZnO ₄ crystal in a direction parallel to the formed face of CAAC-OS, a diffraction pattern shown in FIG. 56D may occur (also referred to as Selected area electronic diffraction pattern). Spots resulting from the (009) plane of the InGaZnO ₄ crystal are included in the diffraction pattern. Therefore, electron diffraction also shows that the particles contained in the CAAC-OS have a c-axis orientation, and the c-axis faces a direction substantially perpendicular to the surface to be formed or the top surface. On the other hand, Fig. 56E shows a diffraction pattern when an electron beam having a beam diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample face. An annular diffraction pattern is observed from Fig. 56E. Therefore, electron diffraction using an electron beam having a beam diameter of 300 nm also shows that the a-axis and the b-axis of the particles contained in the CAAC-OS do not have an orientation. It can be considered that the first ring in Fig. 56E is caused by the (010) plane and the (100) plane of the InGaZnO ₄ crystal. In addition, it can be considered that the second ring in FIG. 56E is caused by a (110) plane or the like.

In addition, observation of a composite analysis image (also referred to as high-resolution TEM image) of the obtained bright-field image of CAAC-OS and a diffraction pattern by a transmission electron microscope (TEM: Transmission Electron Microscope) can be observed. Multiple particles. However, even in high-resolution TEM images, a clear boundary between particles and particles, that is, a grain boundary, is sometimes not observed. Therefore, it can be said that in the CAAC-OS, the decrease in the electron mobility due to the grain boundary is less likely to occur.

Fig. 57A shows a high-resolution TEM image of a cross section of the acquired CAAC-OS viewed from a direction substantially parallel to the sample surface. High-resolution TEM images are obtained using the Spherical Aberration Corrector function. In particular, a high-resolution TEM image acquired by the spherical aberration correction function is referred to as a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be observed using an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From Fig. 57A, particles in which metal atoms are arranged in a layer shape can be confirmed. Further, it is understood that the size of one particle is 1 nm or more or 3 nm or more. Therefore, the particles can also be referred to as nanocrystals (nc: nanocrystal). Further, CAAC ^- OS may also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The particles reflect the convex or concave of the formed face or top surface of the CAAC-OS and are parallel to the formed face or top face of the CAAC-OS.

57B and 57C show Cs-corrected high-resolution TEM images of the plane of the acquired CAAC-OS viewed from a direction substantially perpendicular to the sample surface. 57D and 57E are images obtained by performing image processing on Figs. 57B and 57C. The method of image processing will be described below. First, an FFT image is acquired by performing a Fast Fourier Transform (FFT) process on FIG. 57B. Next, the mask processing is performed so as to preserve the range from the origin of 2.8 nm ^-1 to 5.0 nm ^-1 in the acquired FFT image. Then, the masked FFT image is subjected to Inverse Fast Fourier Transform (IFFT) processing to obtain a processed image. The acquired image is referred to as an FFT filtered image. The FFT filtered image is an image from which a periodic component is extracted from a Cs corrected high resolution TEM image, which shows a lattice arrangement.

In Fig. 57D, the portion where the lattice arrangement is disturbed is shown by a broken line. The area surrounded by the dotted line is a particle. Also, the portion shown by a broken line is a junction of particles and particles. The dotted line shows a hexagon, and it is thus known that the particles are hexagonal. Note that the shape of the particles is not limited to a regular hexagon, and it is not a case of a regular hexagon.

In Fig. 57E, a portion between the regions in which the lattice arrangement is uniform and the regions in which the lattice arrangements are identical is shown by dotted lines. . A clear grain boundary cannot be confirmed near the dotted line. When the lattice points around the lattice point near the dotted line are connected, a distorted hexagon, a pentagon, and/or a heptagon may be formed. That is, it can be seen that the formation of grain boundaries can be suppressed by distorting the lattice arrangement. This may be because CAAC-OS can tolerate distortion due to the low density of the atomic arrangement in the a-b plane direction or the change in the bonding distance between atoms due to the substitution of the metal element.

As described above, CAAC-OS has a c-axis orientation, and a plurality of particles (nanocrystals) are connected in the a-b plane direction to have a crystal structure having distortion. Therefore, CAAC-OS can also be referred to as an oxide semiconductor having CAA crystal (c-axis-aligned a-b-plane-anchored crystal).

CAAC-OS is an oxide semiconductor having high crystallinity. The crystallinity of the oxide semiconductor may be lowered by the incorporation of impurities or the formation of defects, etc. From the opposite viewpoint, it can be said that CAAC-OS is an oxide semiconductor having few impurities or defects (oxygen defects, etc.).

Further, the impurities refer to elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, ruthenium, and transition metal elements. For example, the bonding force with oxygen is greater than the metal element constituting the oxide semiconductor An element such as a strong lanthanum robs oxygen in the oxide semiconductor, thereby disturbing the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity. Further, since the atomic radius (or molecular radius) of heavy metals such as iron or nickel, argon, carbon dioxide, and the like is large, the atomic arrangement of the oxide semiconductor is disturbed, and the crystallinity is lowered.

When an oxide semiconductor contains impurities or defects, its characteristics sometimes fluctuate due to light or heat. For example, impurities contained in an oxide semiconductor may sometimes become a carrier trap or a carrier generation source. For example, an oxygen defect in an oxide semiconductor may become a carrier trap or a carrier generating source due to trapping hydrogen.

CAAC-OS having less impurities and oxygen defects is an oxide semiconductor having a low carrier density. Specifically, a carrier density of less than 8 × 10 ¹¹ cm ^-3 , preferably less than 1 × 10 ¹¹ cm ^-3 , more preferably less than 1 × 10 ¹⁰ cm ^-3 , and 1 × 10 ^-9 cm can be used. ³ or more oxide semiconductors. Such an oxide semiconductor is referred to as an oxide semiconductor of high purity nature or substantially high purity. CAAC-OS has low impurity concentration and defect state density. That is, it can be said that CAAC-OS is an oxide semiconductor having stable characteristics.

<nc-OS>

Next, the nc-OS will be described.

The case where the nc-OS is analyzed using an XRD apparatus will be described. For example, when the structure of the nc-OS is analyzed by the out-of-plane method, no peak indicating the orientation is present. In other words, the crystallization of nc-OS does not have an orientation.

Further, for example, when an nc-OS containing InGaZnO ₄ crystal is thinned, and an electron beam having a beam diameter of 50 nm is incident on a region having a thickness of 34 nm in a direction parallel to the surface to be formed, it is observed as shown in Fig. 58A. An annular diffraction pattern (nano beam electron diffraction pattern) is shown. In addition, FIG. 58B shows a diffraction pattern (nano beam electron diffraction pattern) when an electron beam having a beam diameter of 1 nm is incident on the same sample. A plurality of spots in the annular region are observed from Fig. 58B. Therefore, nc-OS does not observe order when an electron beam having a beam diameter of 50 nm is incident, but order is confirmed when an electron beam having a beam diameter of 1 nm is incident.

Further, when an electron beam having a beam diameter of 1 nm is incident on a region having a thickness of less than 10 nm, as shown in Fig. 58C, an electron diffraction pattern in which a spot is arranged in a quasi-negative hexagon shape is sometimes observed. From this It is known that nc-OS contains a highly ordered region, that is, crystallization, in a range of thickness less than 10 nm. Note that since the crystals are oriented in various directions, there is also no area where the regular electronic diffraction pattern is observed.

Fig. 58D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS viewed from a direction substantially parallel to the surface to be formed. In the high-resolution TEM image of the nc-OS, a region where the crystal portion can be observed and a region where the crystal portion is not observed can be observed as indicated by the auxiliary line. The size of the crystal portion included in the nc-OS is 1 nm or more and 10 nm or less, and particularly preferably 1 nm or more and 3 nm or less. Note that an oxide semiconductor whose crystal portion has a size larger than 10 nm and is 100 nm or less is sometimes referred to as a micro crystalline oxide semiconductor. For example, in a high-resolution TEM image of nc-OS, grain boundaries may not be clearly observed. Note that the source of nanocrystals may be the same as the particles in CAAC-OS. Therefore, the crystal portion of the nc-OS is sometimes referred to as a pellet below.

As described above, in the nc-OS, the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less) has periodicity. In addition, nc-OS does not observe the regularity of crystal orientation between different particles. Therefore, no alignment property was observed in the entire film. Therefore, sometimes nc-OS does not differ from a-like OS or amorphous oxide semiconductor in some analytical methods.

In addition, since the crystal orientation is irregular between particles (nanocrystals), nc-OS can also be referred to as an oxide semiconductor including RANC (Random Aligned nanocrystals) or NANC (Non) -Aligned nanocrystals: oxide semiconductors with no aligned nanocrystals.

nc-OS is an oxide semiconductor having a higher regularity than an amorphous oxide semiconductor. Therefore, the defect state density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductor. However, the regularity of crystal alignment was not observed between different particles in nc-OS. Therefore, the density state of the defect state of nc-OS is higher than that of CAAC-OS.

<a-like OS>

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

Figures 59A and 59B show high resolution cross-sectional TEM images of a-like OS. Fig. 59A shows a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. Fig. 59B shows a high-resolution cross-sectional TEM image of the a-like OS after irradiation of electrons (e ^- ) of 4.3 × 10 ⁸ e ^- /nm ² . As can be seen from Fig. 59A and Fig. 59B, the a-like OS is observed as a strip-shaped bright region extending in the longitudinal direction from the start of electron irradiation. In addition, it is understood that the shape of the bright region changes after the electrons are irradiated. Bright areas are estimated to be empty or low density areas.

Since the a-like OS contains holes, its structure is unstable. In order to demonstrate that the a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

As a sample, a-like OS, nc-OS, and CAAC-OS were prepared. Each sample is an In-Ga-Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample was obtained. It can be seen from the high-resolution cross-sectional TEM image that each sample has a crystal portion.

It is known that a unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers of three In-O layers and six Ga-Zn-O layers are laminated in a c-axis direction. The spacing between the layers close to each other is almost equal to the lattice surface spacing (also referred to as d value) of the (009) plane, and the value is 0.29 nm as determined by crystal structure analysis. Therefore, in the following, a portion in which the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal portion of InGaZnO ₄ . The lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

Fig. 60 shows an example in which the average size of the crystal portions (22 to 30) of each sample was investigated. Note that the crystal portion size corresponds to the length of the above lattice fringe. As can be seen from FIG. 60, in the a-like OS, the crystal portion gradually increases in accordance with the cumulative irradiation amount of electrons for acquiring a TEM image or the like. As can be seen from FIG. 60, a crystal portion (also referred to as an initial crystal nucleus) having an initial size of about 1.2 nm observed by TEM is grown when the cumulative irradiation amount of electrons (e ^- ) is 4.2 × 10 ⁸ e ^- / nm ² . About 1.9nm. On the other hand, it is understood that nc-OS and CAAC-OS have a cumulative irradiation amount of electrons of 4.2 × 10 ⁸ e ^- /nm ² at the start of electron irradiation, and the size of the crystal portion does not change. As is clear from Fig. 60, the crystal portion sizes of nc-OS and CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative irradiation amount of electrons. Further, electron beam irradiation and TEM observation were performed using a Hitachi transmission electron microscope H-9000 NAR. As the electron beam irradiation conditions, the acceleration voltage was 300 kV; the current density was 6.7 × 10 ⁵ e ^- / (nm ² .s); and the diameter of the irradiation region was 230 nm.

As such, electron irradiation sometimes causes the growth of the crystal portion in the a-like OS. On the other hand, in nc-OS and CAAC-OS, there is almost no growth of crystal parts caused by electron irradiation. That is to say, the a-like OS has an unstable structure compared to CAAC-OS and nc-OS.

In addition, since the a-like OS contains holes, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the single crystal oxide semiconductor having the same composition. The density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the single crystal oxide semiconductor having the same composition. Note that it is difficult to form an oxide semiconductor whose density is less than 78% of the density of the single crystal oxide semiconductor.

For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor whose atomic ratio satisfies In:Ga:Zn=1:1:1, the density of the a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ³ . Further, for example, in an oxide semiconductor whose atomic ratio satisfies In:Ga:Zn=1:1:1, the density of nc-OS and the density of CAAC-OS are 5.9 g/cm ³ or more and less than 6.3 g/cm. ³ .

Note that when a single crystal oxide semiconductor of the same composition is not present, the density of a single crystal oxide semiconductor corresponding to a desired composition can be estimated by combining different single crystal oxide semiconductors in an arbitrary ratio. The density of the single crystal oxide semiconductor corresponding to the desired composition may be estimated using a weighted average according to the combination ratio of the single crystal oxide semiconductors having different compositions. Note that it is preferable to estimate the density by reducing the kind of the combined single crystal oxide semiconductor as much as possible.

As described above, the oxide semiconductor has various structures and various characteristics. Note that the oxide semiconductor may be, for example, a laminated film including two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

The structure shown in this embodiment can be implemented in appropriate combination with the structure shown in the other embodiment.

Embodiment 6

In the present embodiment, an example of a package accommodating an image sensor wafer and a camera module will be described. The structure of the image pickup apparatus of one embodiment of the present invention can be applied to the image sensor wafer.

Figure 61A is a perspective view showing the appearance of the top side of the package accommodating the image sensor wafer. The package includes a package substrate 810 that fixes the image sensor wafer 850, a cover glass 820, and an adhesive 830 that bonds both.

Fig. 61B is a perspective view showing the appearance of the bottom surface side of the package. The bottom surface of the package has a BGA (Ball Grid Array) structure in which the solder balls are bumps 840. However, it is not limited to the BGA structure, and a structure such as an LGA (Land Grid Array) or a PGA (Pin Grid Array) may be employed.

61C is a perspective view of a package omitting a portion of the glass cover 820 and the adhesive 830, and FIG. 61D is a cross-sectional view of the package. A disk electrode 860 is formed on the package substrate 810, and the disk electrode 860 is electrically connected to the bump 840 through the via 880 and the pad 885. The disk electrode 860 is electrically connected to the electrode of the image sensor wafer 850 by a wire 870.

In addition, FIG. 62A is a perspective view showing the appearance of the top surface side of the camera module, in which the image sensor wafer is housed in a lens-integrated package. The camera module includes a package substrate 811 that fixes the image sensor wafer 851, a lens cover 821, a lens 835, and the like. Further, an IC chip 890 having functions such as a drive circuit of an image pickup device and a signal conversion circuit is also provided between the package substrate 811 and the image sensor wafer 851. Thus, a SiP (System in Package) is formed.

Fig. 62B is a perspective view showing the appearance of the bottom surface side of the camera module. A QFN (Quad flat no-lead package) having a pad 841 for mounting is provided on the bottom surface of the package substrate 811 and its four side faces. Further, the configuration is an example, and a QFP (Quad flat package) and the above BGA may be used.

62C is a perspective view of a module omitting a part of the lens cover 821 and the lens 835, and FIG. 62D is a cross-sectional view of the camera module. A portion of the pad 841 is used as the disk electrode 861, and the disk electrode 861 is electrically connected to the electrodes included in the image sensor wafer 851 and the IC wafer 890 by the wire 871.

By accommodating the image sensor wafer in the package of the above-described type, it is easy to mount on a printed circuit board or the like, and the image sensor wafer is mounted in various semiconductor devices and electronic devices.

The structure shown in this embodiment can be implemented in appropriate combination with the structure shown in the other embodiment.

Embodiment 7

Examples of the electronic device that can use the imaging device according to one embodiment of the present invention and the semiconductor device including the imaging device include a display device, a personal computer, an image memory device and a video reproduction device including a storage medium, and a mobile phone, including Portable game consoles, portable data terminals, e-book readers, camera devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, Digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in Figs. 63A to 63F.

Fig. 63A is a surveillance camera including a housing 951, a lens 952, a support portion 953, and the like. As one of the members for acquiring an image in the surveillance camera, an imaging device according to an embodiment of the present invention may be provided. Note that "monitor camera" is a generic name and is not limited to its purpose. For example, a device having the function of monitoring a camera is called a camera or a video camera.

Fig. 63B is a video camera including a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connecting portion 976, and the like. The operation keys 974 and the lens 975 are disposed in the first housing 971, and the display portion 973 is disposed in the second housing 972. As one of the members for acquiring video in the video camera, an imaging device according to an embodiment of the present invention may be provided.

Fig. 63C is a digital camera including a housing 961, a shutter button 962, a microphone 963, a light emitting portion 967, a lens 965, and the like. As one of the members for acquiring an image in the digital camera, an imaging device according to an embodiment of the present invention may be provided.

Fig. 63D is a watch type information terminal including a housing 931, a display portion 932, a wristband 933, an operation button 935, a crown 936, a camera 939, and the like. The display portion 932 may also be a touch panel. As one of the means for acquiring an image in the information terminal, an imaging device according to an embodiment of the present invention may be provided.

63E is a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus pen 908, a camera 909, and the like. Note that although the portable game machine illustrated in FIG. 63E includes two display portions 903 and a display portion 904, the number of display portions included in the portable game machine is not limited thereto. As one of the members for acquiring images in the portable game machine, an image pickup apparatus according to an embodiment of the present invention may be provided.

FIG. 63F is a portable data terminal. The portable data terminal includes a housing 911, a display portion 912, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. As one of the means for acquiring an image in the portable data terminal, an image pickup apparatus according to an embodiment of the present invention may be provided.

This embodiment can be combined as appropriate with other embodiments shown in the present specification.

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Claims (20)

An image pickup apparatus comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a photoelectric conversion element; and a first capacitor and a second capacitor, wherein An electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor and a source and a drain of the second transistor, a source of the first transistor One of the other of the drain and one of the source and the drain of the third transistor, one of the source and the drain of the fourth transistor, the gate electrode of the fifth transistor, and the first One electrode of the capacitor is electrically connected, and the other of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor, and one of a source and a drain of the fifth transistor The source of the six transistors is electrically connected to one of the drains, and the first transistor, the second transistor, the third transistor, and the fourth transistor comprise an oxide semiconductor. The image pickup device of claim 1, wherein the fifth transistor and the sixth transistor each comprise the oxide semiconductor. The image pickup device according to claim 1, wherein the oxide semiconductor contains In, Zn, and M (M is one of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf). The image pickup device according to claim 1, wherein the photoelectric conversion element includes selenium or a compound containing selenium in the photoelectric conversion layer. A module comprising a camera device and a lens of claim 1 of the patent application. An electronic device comprising the imaging device and the display device of claim 1 of the patent application. An imaging device includes: a pixel including a charge storage portion and a charge detecting portion; and a first circuit, a second circuit, a third circuit, a fourth circuit, and a fifth circuit, wherein: the pixel and the first circuit and the first The fifth circuit is electrically connected, the first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the third circuit and the fourth circuit, The third circuit is electrically connected to the fifth circuit, and the pixel acquires the first image data or the second image data, and stores the first image data or the second image data in the charge storage portion, and stores the charge The first imaging data or the second imaging data in the storage unit is transmitted to the charge detecting unit, and the first circuit outputs a first potential corresponding to the second imaging data and a reset potential corresponding to the charge detecting unit. a first signal obtained by adding an absolute value of the difference between the second potentials to the reference potential or a first signal obtained by subtracting the absolute value from the reference potential, the second circuit determining whether the charge detecting portion is due to The first image data is saturated with electrons, and the third circuit outputs a second signal that does not acquire the second image data to the pixel by the fifth circuit when the charge detecting portion is not electronically saturated. Dissolving the saturation of the charge detecting portion when the charge detecting portion is saturated by the electron, and outputting the third signal for acquiring the second image data to the pixel by the fifth circuit, the second circuit and the Four circuit converts the signal from the bit number data output by the first circuit. A module comprising a camera device and a lens of claim 7 of the patent application. An electronic device comprising the image pickup device and the display device of claim 7 of the patent application. A method of operating an image pickup apparatus, comprising the steps of: resetting a potential of a charge storage portion during an nth frame period (n is a natural number of 1 or more); storing a charge in the charge storage portion; and performing charge detection Resetting the potential of the portion; transferring the first potential of the charge storage portion to the charge detecting portion; and reading a first signal corresponding to the first potential, and determining whether the charge detecting portion is electronically based on the first signal Saturation, when the charge detecting portion is saturated with electrons, the working method includes the steps of: resetting the first potential of the charge storage portion; storing the charge in the charge storage portion; increasing the capacity of the charge detecting portion And eliminating the saturation of the charge detecting portion; and transmitting the second potential of the charge storage portion to the charge detecting portion, in the (n+1)th frame period, when the charge detecting portion is saturated with electrons, The working method further includes the steps of: reading a second signal corresponding to the second potential while resetting the potential of the charge storage portion and storing the charge, When the charge detecting portion is not saturated with electrons, the working method further includes the step of reading the first signal while resetting the potential of the charge storing portion and storing the electric charge. An image pickup apparatus comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; a photoelectric conversion element; and a first capacitor, a second capacitor and a third capacitor, wherein: one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, One of a source and a drain of the first transistor and one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, the fifth The gate electrode of the crystal is electrically connected to one electrode of the first capacitor, and the other of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor, and the source of the fifth transistor One of the drain and the drain is electrically connected to one of the source and the drain of the sixth transistor, one of the source and the drain of the seventh transistor and the gate electrode of the fourth transistor and the gate electrode One electrode of the third capacitor is electrically connected, the first transistor, the Two transistors, the third transistor, the fourth transistor and the seventh transistor including an oxide semiconductor. The image pickup device of claim 11, wherein the fifth transistor and the sixth transistor both comprise the oxide semiconductor. The image pickup device according to claim 11, wherein the oxide semiconductor comprises In, Zn, and M (M is one of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf). The image pickup device according to claim 11, wherein the photoelectric conversion element includes selenium or a compound containing selenium in the photoelectric conversion layer. A module comprising a camera device and a lens of claim 11 of the patent application. An electronic device comprising the image pickup device and the display device of claim 11 of the patent application. An imaging device includes: a pixel including a charge storage portion, a charge detecting portion, a first capacitor, and a second capacitor; and a first circuit, a second circuit, a third circuit, and a fourth circuit, Wherein: the charge detecting portion is electrically connected to the first capacitor and the second capacitor, the pixel is electrically connected to the first circuit and the third circuit, and the first circuit is electrically connected to the second circuit, the second circuit Electrically connecting with the third circuit and the fourth circuit, the pixel acquires a first camera data or a second camera data, and stores the first camera data or the second camera data in the charge storage unit, where the pixel is stored The first image data or the second image data in the charge storage portion is transferred to the charge detecting portion, and the first circuit outputs a first potential corresponding to the second image data and a reset potential of the charge detecting portion a first signal obtained by adding an absolute value of a difference between the corresponding second potentials to the reference potential or a first signal obtained by subtracting the absolute value from the reference potential, the second circuit determining whether the charge detecting portion is Since the first imaging material is electronically saturated, the third circuit outputs a second signal that does not electrically connect the charge detecting portion and the second capacitor to the case where the charge detecting portion is not electronically saturated. a pixel, when the charge detecting portion is electronically saturated, outputs a third signal electrically connecting the charge detecting portion and the second capacitor to the pixel, and the pixel receives the second image data from the charge after the determining The storage unit is transferred to the charge detecting unit, and the second circuit and the fourth circuit convert the signal output from the first circuit into digital data. A module comprising a camera device and a lens of claim 17 of the patent application. An electronic device comprising the image pickup device and the display device of claim 17 of the patent application. A method of operating an image pickup apparatus, comprising the steps of: resetting a potential of a charge storage portion during an nth frame period (n is a natural number of 1 or more); storing a charge in the charge storage portion; and performing charge detection Resetting the potential of the portion; transferring the first potential of the charge storage portion to the charge detecting portion; and reading a first signal corresponding to the first potential, and determining whether the charge detecting portion is electronically based on the first signal Saturated, when the charge detecting portion is saturated with electrons, the working method includes the steps of: increasing a capacity of the charge detecting portion; resetting the first potential of the charge detecting portion; Transmitting the second potential of the charge storage portion to the charge detecting portion, and when the charge detecting portion is not saturated with electrons, the working method further includes the step of resetting the first potential of the charge detecting portion; The first potential of the charge storage portion is reset; the charge is stored in the charge storage portion; and the second potential of the charge storage portion is transferred to the charge detection portion, during the (n+1)th frame period, The second signal corresponding to the second potential is read while the potential of the charge storage portion is reset and the charge is stored.