JP2021082775A - Imaging device and manufacturing method for the same - Google Patents

Abstract

To provide an imaging device with a novel structure.SOLUTION: A transistor of a fully-depleted type formed on an SOI substrate, which is called FD-SOI, is used to reduce the off-leak current in a selection transistor. A first semiconductor substrate where a photoelectric conversion region and a transfer transistor are provided and a second semiconductor substrate including the FD-SOI are attached together to form an imaging device. By using the FD-SOI at least as the selection transistor, the leakage can be reduced.SELECTED DRAWING: Figure 1

Description

This specification describes a semiconductor device and the like.

One aspect of the present invention is not limited to the above technical fields. The technical fields of one aspect of the present invention disclosed in the present specification and the like include semiconductor devices, imaging devices, display devices, light emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, and input / output devices. Devices, their driving methods, or their manufacturing methods can be mentioned as an example.

Metal oxides are attracting attention as semiconductors applicable to transistors. In-Ga-Zn oxides called "IGZO", "Exo" and the like are typical of multidimensional metal oxides. In the study on IGZO, CAAC (c-axis aligned crystalline) structure and nc (nanocrystalline) structure, which are neither single crystal nor amorphous, were found (for example, Non-Patent Document 1).

Transistors having metal oxide semiconductors in the channel formation region (hereinafter, may be referred to as "oxide semiconductor transistors" or "OS transistors") have been reported to have a minimum off-current (for example, non-minimum off-current). Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).

The manufacturing process of the OS transistor can be incorporated into a CMOS process with a transistor (Si transistor) having silicon in the channel forming region, and the OS transistor can be laminated on the Si transistor. For example, Patent Document 1 discloses a configuration in which a plurality of layers of a memory cell array having an OS transistor are laminated on a substrate provided with a Si transistor.

In a logic circuit manufactured by a CMOS process, it is preferable that the characteristic variation such as the threshold voltage of the p-channel transistor and the n-channel transistor is small in order to realize low voltage drive. Patent Document 2 discloses a configuration called a transistor in which a well region under an embedded insulating layer directly under a thin silicon film is used as a back gate in a completely depleted SOI (FD-SOI: Fully-Depleted Silicon On Insulator). ing. Since the transistor hardly imparts an impurity element that imparts conductivity to the channel forming region, it is said to have advantages such as being able to reduce characteristic variations such as threshold voltage and current and being excellent in short channel characteristics.

In addition, image sensors are widely used as components for imaging such as digital cameras and video cameras. It is also used as part of security equipment such as security cameras.

Further, Patent Document 3 discloses an image pickup apparatus having a configuration in which a transistor having an oxide semiconductor is used as a part of a pixel circuit.

U.S. Patent Application Publication No. 2012/0063208 Japanese Unexamined Patent Publication No. 2015-103555 JP-A-2017-55403

S. Yamazaki et al. , "Properties of crystalline In-Ga-Zn-oxide semiconductor and it transistor characteristics," Jpn. J. Apple. Phys. , Vol. 53,04ED18 (2014). K. Kato et al. , "Evaluation of Off-State Current Chemicals of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide," Jpn. J. Apple. Phys. , Vol. 51,021201 (2012). S. Amano et al. , "Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency," SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). T. Ishizu et al. , "Embedded Oxide Semiconductor Mechanisms: A Key Enabler for Low-Power ULSI," ECS Train. , Vol. 79, pp. 149-156 (2017).

One object of the present invention is to provide an image pickup apparatus capable of performing image processing. Another object of the present invention is to provide an imaging device capable of high-speed operation. Another object of the present invention is to provide an image pickup device having low power consumption. Another issue is to provide a new device structure.

The configuration of the invention disclosed in the present specification is an image pickup apparatus having a bonding surface between a first silicon substrate, a second silicon substrate, and a first silicon substrate and a second silicon substrate, and the first silicon substrate is The second silicon substrate has a photoelectric conversion region and a transfer transistor electrically connected to the photoelectric conversion region, and the second silicon substrate includes a reset transistor electrically connected to the transfer transistor, an amplification transistor, an amplification transistor, and an electrical transfer transistor. It is an image pickup apparatus having a selection transistor connected to, and having a back gate control circuit for controlling the threshold values of the selection transistor, the amplification transistor, and the reset transistor.

In the above configuration, the first silicon substrate is a single crystal silicon substrate, and the second silicon substrate is an SOI substrate.

Further, the configuration of another invention is an image pickup apparatus having a bonding surface between the first semiconductor substrate, the second semiconductor substrate, the first semiconductor substrate and the second semiconductor substrate, and the first semiconductor substrate is a photoelectric. It has a conversion region and a transfer transistor electrically connected to the photoelectric conversion region, and the second semiconductor substrate is electrically connected to a reset transistor, an amplification transistor, and an amplification transistor which are electrically connected to the transfer transistor. It is an image pickup apparatus which has a selection transistor to be used, and has a back gate control circuit for controlling a selection transistor, an amplification transistor, and a reset transistor threshold.

In order to reduce the off-leakage current of the selected transistor, a completely depleted transistor is used, which is a transistor formed on an SOI substrate and is called FD-SOI, specifically SOTB (Silicon On Thin Oxide).

A first semiconductor substrate provided with a photoelectric conversion region and a transfer transistor and a second semiconductor substrate having FD-SOI are bonded together to form an image pickup apparatus. The image sensor is a back-illuminated solid-state image sensor.

One pixel configuration includes a transfer transistor, a reset transistor electrically connected to the transfer transistor, a selection transistor, and an amplification transistor electrically connected to the selection transistor.

Leakage can be reduced by using at least the selected transistor as FD-SOI.

Leakage can also be reduced by a configuration having a back gate control circuit that controls the threshold values of the selection transistor, the amplification transistor, and the reset transistor.

Further, by laminating, the first semiconductor substrate and the second semiconductor substrate having FD-SOI can be laminated to reduce the pixel area.

Further, a configuration may be configured in which a first wiring layer including a transistor having an oxide semiconductor as a channel is provided between the bonded surface and the first semiconductor substrate.

Further, a second wiring layer including a transistor having an oxide semiconductor as a channel may be provided between the bonded surface and the second semiconductor substrate.

The oxide semiconductor has a metal oxide, and the metal oxide preferably contains In, Ga, and Zn.

Further, of the first semiconductor substrate or the second semiconductor substrate, at least one of them may be a substrate having FD-SOI, and the other may be a single crystal silicon substrate, a single crystal Ge substrate, SiGe, ZnSe, CdS, GaAs, A compound semiconductor substrate such as InP, GaN, SiC, or GaAlAs may be used. Further, when two semiconductor substrates made of different materials are bonded together, it can also function as a buffer layer at the time of bonding by arranging a wiring layer including a transistor having an oxide semiconductor as a channel in between. ..

One aspect of the present invention can provide a miniaturized semiconductor device excellent in reducing the circuit area. Alternatively, one aspect of the present invention can provide a semiconductor device excellent in low power consumption. Alternatively, a semiconductor device having a new configuration can be provided.

FIG. 1A is an example showing a block diagram showing one aspect of the present invention, and FIG. 1B is an example of an equivalent circuit diagram. It is an example of the cross-sectional view of the image pickup apparatus which shows one aspect of this invention. This is an example of a schematic cross-sectional view showing one aspect of the present invention. 13 (A), (B), (C), and (D) are cross-sectional views illustrating an OS transistor. FIG. 5 is a perspective view and a cross-sectional view of the package containing the imaging device. FIG. 6 is a perspective view and a cross-sectional view of a package containing the imaging device. 7 (A), 7 (B), 7 (C), 7 (D), 7 (E), and 7 (F) are views showing a usage pattern of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be changed in various ways. Further, the present invention is not construed as being limited to the description contents of the embodiments shown below.

(Embodiment 1)
In the present embodiment, the image pickup apparatus according to one aspect of the present invention will be described with reference to the drawings.

One aspect of the present invention is an imaging device having a plurality of stacked devices. The image pickup apparatus is formed by laminating a first laminate (first semiconductor substrate) and a second laminate (second semiconductor substrate) on which a plurality of devices are laminated. Therefore, even in a configuration in which a plurality of circuits having different functions are laminated, the polishing process and the bonding process can be reduced, and the yield can be improved.

FIG. 1A describes in a block diagram the details of the connection relationship between the photoelectric conversion unit 240, the pixel circuit 331, the read circuit 311 and the memory circuit 321. Further, in FIG. 1A, layers are described separately for each circuit having a different function, and the first layer 200, the second layer 203, the third layer 202, and the fourth layer 201 are stacked in this order. doing.

The photoelectric conversion unit 240 has a photoelectric conversion region and a transfer transistor that is electrically connected to the photoelectric conversion region. The photoelectric conversion unit 240 is provided on the first layer 200. The photoelectric conversion unit 240 preferably has sensitivity to visible light. For example, a Si photodiode that uses silicon for the photoelectric conversion layer can be used in the photoelectric conversion unit 240.

FIG. 1B is a circuit diagram illustrating an example of the pixel circuit 331. The pixel circuit 331 can include a photoelectric conversion unit 240, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. The capacitor 108 may not be provided.

The transistor 103 has a function of controlling the potential of the node FD. The transistor 104 has a function of resetting the potential of the node FD. The transistor 105 functions as a source follower circuit, and the potential of the node FD can be output to the wiring 352 as image data.

The transistor 106 has a function of selecting a pixel for outputting image data, and can be called a selection transistor. The semiconductor layer of the selection transistor is silicon. That is, the selection transistor is a Si transistor. The selection transistor uses an SOI (Silicon On Insulator) substrate having an insulating layer (also referred to as a BOX (Burried oxide) layer) formed by embedding oxidation in a silicon substrate and a thin film of single crystal silicon on the insulating layer. It is a transistor that is formed. In this specification, an example in which the SOI substrate is produced by the SIMOX (Specified by Implanted Oxygen) method will be described, but an SOI substrate produced by the smart cut method may be used.

A region (well region) to which an impurity element that imparts conductivity is added can be overlapped on the silicon substrate in the region where the selection transistor is provided. FIG. 2 shows an example of the cross-sectional structure of the image pickup apparatus. In FIG. 2, the n-type well region 533 and the BOX layer 532 are also shown, and the same reference numerals are used for the portions common to those in FIG. The p-type well region 534 shown in FIG. 2 can function as a back gate electrode by independently changing the potential of the p-type well region. Therefore, the threshold voltage of the Si transistor can be controlled. In particular, by applying a positive potential to the p-type well region, the threshold voltage of the Si transistor can be made larger and the off-current can be reduced. Therefore, by applying a positive potential to the p-type well region, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be reduced. Further, since it is not necessary to add an impurity element to the channel forming region for the purpose of controlling the threshold voltage, the variation in the threshold voltage can be reduced and the power supply voltage can be lowered.

In the present embodiment, the second semiconductor substrate is provided with the transistors 104, 105, 106 and the capacitor 108. By setting at least the transistor 106 to be FD-SOI, specifically SOTB, the off-leakage current of the transistor 106 can be reduced by the back gate bias (Vbn2) of the SOTB while maintaining the read speed. These elements are provided in the second layer 203.

In FIG. 1B, the other electrode (anode) of the photoelectric conversion unit 240 is electrically connected to the wiring 121. The gate of the transistor 103 is electrically connected to the wiring 127. The other of the source or drain of the transistor 104 is electrically connected to the wire 122. The other of the source or drain of the transistor 105 is electrically connected to the wire 123. The gate of the transistor 104 is electrically connected to the wiring 126. The gate of the transistor 106 is electrically connected to the wiring 128. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring. The other of the source or drain of the transistor 106 is electrically connected to the wiring 352.

Wiring 127, 126, 128 can have a function as a signal line for controlling the continuity of each transistor. The wiring 352 can have a function as an output line.

Wiring 121, 122, 123 can have a function as a power supply line. In the configuration shown in FIG. 1B, the cathode side of the photoelectric conversion unit 240 is electrically connected to the transistor 103, and the node FD is reset to a high potential for operation. Therefore, the potential VDD of the wiring 122 is set. It is assumed to have a high potential (a potential higher than that of the wiring 121).

Further, the back gate bias (Vbn1) of the transistor 104 and the back gate bias (Vbn2) of the transistor 105 can be set to different potentials.

Further, the pixel circuit 331 is electrically connected to the read circuit 311 (RC) via the wiring 352. The readout circuit 311 includes a correlated double sampling circuit (CDS circuit) that reduces noise and an A / D converter that converts analog data into digital data. The read-out circuit 311 is provided in the fourth layer 201.

The read circuit 311 is electrically connected to the memory circuit 321 (MEM) via the wiring 353. The memory circuit 321 has m (m is an integer of 1 or more) in a column, n (n is an integer of 1 or more) in a row, and a total of m × n memory cells 321a, and the memory cells 321a have a matrix shape. Is located in. The memory circuit 321 can hold the digital data output from the read circuit 311. Alternatively, digital data can be output directly to the outside from the read circuit 311. The memory circuit 321 (MEM) is provided in the third layer 202.

FIG. 3A shows an example in which the first semiconductor substrate 301 and the second semiconductor substrate 302 are bonded together. In the present embodiment, the first semiconductor substrate 301 is provided with a photoelectric conversion unit 240 and a transistor 103. The first layer 200 includes a photoelectric conversion unit 240 and a transistor 103.

The conductors that can be used as wiring, electrodes, and plugs used for electrical connection between the transistor 103 of the first semiconductor substrate 301 and the transistor of the second semiconductor substrate 302 include aluminum, chromium, copper, and silver. , Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, lanthanum, etc. An alloy containing an element or an alloy combining the above-mentioned metal elements may be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers made of different materials.

Next, bonding of the first semiconductor substrate 301 and the second semiconductor substrate 302 will be described.

For bonding between metal layers, a surface-activated bonding method can be used in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. .. Alternatively, a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that excellent bonding can be obtained not only electrically but also mechanically.

Further, in order to bond the insulating layers to each other, after obtaining high flatness by polishing or the like, the surfaces treated with hydrophilicity by oxygen plasma or the like are brought into contact with each other for temporary bonding, and then main bonding is performed by dehydration by heat treatment. A joining method or the like can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.

In the first layer 200 in which the photoelectric conversion unit 240 and the transistor 103 are provided on the first semiconductor substrate 301, the surfaces on which the electrode surfaces are exposed are flattened so that the heights of the electrodes are the same. Further, the exposed surfaces of the electrodes of the second semiconductor substrate 302 are also flattened so that their heights match. Since the electrode surface provided on the first semiconductor substrate 301 and the electrode surface of the second semiconductor substrate 302 are aligned so that their respective electrode surfaces coincide with each other, the main components of the electrode surfaces are the same metal. It is preferably an element.

For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au and the like can be used. Cu, Al, W, or Au is preferably used because of the ease of joining. With this configuration, bonding can be performed with the boundary between the first layer 200 and the second layer 203 as the joining position. In the bonding where the boundary between the first layer 200 and the second layer 203 is the bonding position, an insulating layer and a metal layer are mixed on each bonding surface. Therefore, for example, a surface activation bonding method and a hydrophilic bonding method. It may be done in combination.

Further, in the present embodiment, it is an example that the second semiconductor substrate 302 is provided with the second layer 203, the third layer 202, and the fourth layer 201. However, it is at least the second layer 203 that is laminated with the first layer 200, and the third layer 202 and the fourth layer 201 are not stacked but arranged in parallel.

Further, a signal processing circuit such as a logic circuit can also be manufactured on the second semiconductor substrate 302 including the FD-SOI. For example, based on the data obtained by the photoelectric conversion element of the first semiconductor substrate 301, the autofocus function is mounted by performing distance measurement, lens position calculation, etc. by the signal processing circuit provided on the second semiconductor substrate 302. You can also do it.

Another example is shown in FIG. 3 (B).

FIG. 3B is an example in which a laminate 303 including an OS transistor is provided between the first semiconductor substrate 301 and the second semiconductor substrate 302.

For example, the laminate 303 including the OS transistor may be formed in contact with the first semiconductor substrate 301 to form the transistor 104. Then, the transistor 106 is formed on the second semiconductor substrate 302. In this case, the image pickup apparatus can be manufactured by laminating the laminated body 303 and the second semiconductor substrate 302.

Further, the laminated body 303 including the OS transistor may be formed in contact with the second semiconductor substrate 302, and then the laminated body 303 and the first semiconductor substrate 301 may be bonded to each other in a process sequence.

Another example is shown in FIG. 3 (C).

FIG. 3B is an example in which the laminates 303 and 304 including the OS transistor are provided between the first semiconductor substrate 301 and the second semiconductor substrate 302.

For example, the laminate 303 including the OS transistor may be formed in contact with the first semiconductor substrate 301 to form the transistor 104. Then, the transistor 106 is formed on the second semiconductor substrate 302. , The laminated body 304 including the OS transistor is formed in contact with the second semiconductor substrate 302. A transistor 105 is provided in the laminated body 304. In this case, the laminated body 303 including the OS transistor and the laminated body 304 including the OS transistor are bonded together. Further, here, an example in which a plurality of transistors of the pixel circuit are divided into separate layers has been described, but the present invention is not particularly limited, and the memory and the read circuit may be formed by being divided into separate layers.

By stacking the circuit configurations, the size of the image pickup apparatus can be reduced.

(Embodiment 2)
In this embodiment, the details of the OS transistor used in FIGS. 3 (B) and 3 (C) are shown. In the OS transistor shown in FIG. 4A, an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and an opening reaching the oxide semiconductor layer is provided to form a source electrode 705 and a drain electrode 706. It is a self-aligned configuration.

The OS transistor may have a channel forming region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the groove.

As shown in FIG. 4B, the OS transistor may have a self-aligned configuration in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.

Alternatively, as shown in FIG. 4C, it may be a non-self-aligned top gate type transistor having a region where the source electrode 705 or the drain electrode 706 and the gate electrode 701 overlap.

Although the OS transistor shows a structure having a back gate 535, it may have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite to each other as shown in the cross-sectional view of the transistor in the channel width direction shown in FIG. 4 (D). Note that FIG. 4 (D) shows the cross section of B1-B2 shown in FIG. 4 (A) as an example, but the same applies to transistors having other structures. Further, the back gate 535 may be configured to be able to supply a fixed potential different from that of the front gate.

As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS, which will be described later, can be used. CAAC-OS is suitable for transistors and the like in which the atoms constituting the crystal are stable and reliability is important. Further, since CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like that performs high-speed driving.

Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits an extremely low off-current characteristic of several yA / μm (current value per 1 μm of channel width). Further, the OS transistor has features different from those of the Si transistor such as impact ionization, avalanche breakdown, and short channel effect, and can form a circuit having high withstand voltage and high reliability. In addition, variations in electrical characteristics due to crystallinity non-uniformity, which is a problem with Si transistors, are unlikely to occur with OS transistors.

The semiconductor layer of the OS transistor is In-M containing, for example, indium, zinc and M (one or more metals such as indium, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It can be a film represented by −Zn-based oxide. The In—M—Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by using an ALD (Atomic layer deposition) method.

The atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn-based oxide by the sputtering method preferably satisfies In ≧ M and Zn ≧ M. The atomic number ratio of the metal element of such a sputtering target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 1. 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 and the like are preferable. The atomic number ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor having a low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, and more preferably 1 × 10 ¹¹ / cm. ³ or less, more preferably less than 1 × ^{10 10} / cm ^3, it is possible to use an oxide semiconductor of 1 × ¹⁰ -9 / cm ³ or more carrier density. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It can be said that the oxide semiconductor is an oxide semiconductor having a low defect level density and stable characteristics.

Not limited to these, a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer are appropriate. ..

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen deficiency increases and the mixture becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, alkali metals and alkaline earth metals may generate carriers when combined with oxide semiconductors, which may increase the off-current of the transistor. Therefore, the concentration of alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

Further, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have a normally-on characteristic. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is ^{preferably 5 × 10 18} atoms / cm ³ or less.

Further, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen deficiency, the transistor may have a normally-on characteristic. In addition, a defect containing hydrogen in an oxygen deficiency may function as a donor and generate electrons as carriers. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have a normally-on characteristic.

Defects containing hydrogen in oxygen deficiencies can function as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the oxide semiconductor, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as the "donor concentration".

Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) ^{is less than 1 × 10 20} atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm. ^{It is} less than 3, more preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and even more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

Further, the semiconductor layer may have a non-single crystal structure, for example. Non-single crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure, or amorphous structure having crystals oriented on the c-axis. In the non-single crystal structure, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and has no crystal portion.

Even if the semiconductor layer is a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.

Hereinafter, the configuration of the CAC (Cloud-Aligned Company) -OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

The CAC-OS is, for example, a composition of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size close thereto. In the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The state of being mixed with is also called a mosaic shape or a patch shape.

The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.

For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO in CAC-OS) is indium oxide (hereinafter, InO). _X1 (X1 is a real number greater than 0), or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium. With oxide (hereinafter, GaO _X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers larger than 0)) The material is separated into a mosaic-like structure, and the mosaic-like InO _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter, also referred to as cloud-like). is there.

That is, CAC-OS is a composite oxide semiconductor having a structure in which a region _{containing GaO X3} as a main component and a region _{containing In X2} Zn _Y2 O _Z2 or InO _{X1 as a main component are mixed.} In the present specification, for example, the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that of region 2.

In addition, IGZO is a common name, and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.

On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is a region that is partially observed as nanoparticles containing Ga as a main component and nanoparticles containing In as a main component in a material composition containing In, Ga, Zn, and O. The regions observed in a shape refer to a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary element.

The CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between the region containing GaO _X3 as the main component and the region _{containing In X2} Zn _Y2 O _Z2 or InO _{X1 as the main component.}

Instead of gallium, select from aluminum, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. When one or more of these are contained, CAC-OS has a region observed in the form of nanoparticles containing the metal element as a main component and a nano having In as a main component. The regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not heated. When CAC-OS is formed by a sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. Good. Further, the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable. For example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..

CAC-OS is characterized by the fact that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c-axis direction is not observed.

Further, CAC-OS has a ring-shaped region with high brightness (ring region) and the ring in an electron diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam). Multiple bright spots are observed in the area. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, GaO _X3 is the main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It _{can be confirmed that the region and the region containing In X2} Zn _Y2 O _Z2 or InO _X1 as the main component have a structure in which they are unevenly distributed and mixed.

CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is _{phase-separated into a region containing GaO X3} or the like as a main component and a region _{containing In X2} Zn _Y2 O _Z2 or InO _X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.

Here, the _{region in which In X2} Zn _Y2 O _Z2 or InO _X1 is the main component is a region having higher conductivity than the region in which _{GaO X3 or the like is the main component.} That is, _{when the carrier flows through the region where In X2} Zn _Y2 O _Z2 or InO _X1 is the main component, the conductivity as an oxide semiconductor is exhibited. Therefore, a high field effect mobility (μ) can be realized by distributing the region containing _{In X2} Zn _Y2 O _Z2 or InO _{X1 as the main component in the oxide semiconductor in a cloud shape.}

On the other hand, _{the region in which GaO X3} or the like is the main component is a region having higher insulating property than the region in which _{In X2} Zn _Y2 O _Z2 or InO _{X1 is the main component.} That is, since _{the region containing GaO X3} or the like as the main component is distributed in the oxide semiconductor, the leakage current can be suppressed and a good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulation property caused by _{GaO X3 and the like and the conductivity caused by In X2} Zn _Y2 O _Z2 or InO _X1 act in a complementary manner, resulting in high efficiency. On current (I _on ) and high field effect mobility (μ) can be achieved.

Further, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

(Embodiment 3)
In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. For the image sensor chip, for example, the configuration of the image pickup apparatus of the first embodiment shown in FIG. 1 can be used.

FIG. 5A is an external perspective view of the upper surface side of the package containing the image sensor chip. The package has a package substrate 810 for fixing the image sensor chips 850a and 850b, a cover glass 820, an adhesive 830 for adhering both, and the like. The image sensor chips 850a and 850b are formed by laminating a first semiconductor substrate and a second semiconductor substrate. The image sensor chip 850a shows a component of the first semiconductor substrate, and the image sensor chip 850b shows a component of the second semiconductor substrate.

FIG. 5B is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) configuration in which solder balls are bumps 840. In addition, it is not limited to BGA, and may be LGA (Land grid array), PGA (Pin grid array), or the like.

FIG. 5C is a perspective view of the package shown by omitting a part of the cover glass 820 and the adhesive 830, and FIG. 5D is a cross-sectional view of the package. An electrode pad 860 is formed on the package substrate 810, and the electrode pad 860 and the bump 840 are electrically connected to each other via a through hole 880 and a land 885. The electrode pad 860 is electrically connected to the electrode of the image sensor chip 850b by a wire 870.

Further, FIG. 6A is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 811 for fixing the image sensor chips 851a and 851b, a lens cover 821, a lens 835, and the like. The image sensor chips 851a and 851b are formed by laminating a first semiconductor substrate and a second semiconductor substrate. The image sensor chip 851a shows a component of the first semiconductor substrate, and the image sensor chip 851b shows a component of the second semiconductor substrate. Further, in the image sensor chip 851b, a circuit having functions such as a drive circuit of an image pickup device and a signal conversion circuit is configured by FD-SOI, and has a configuration as SiP (System in package). The autofocus function can also be mounted by the image sensor chips 851a and 851b.

FIG. 6B is an external perspective view of the lower surface side of the camera module. The lower surface and the four side surfaces of the package substrate 811 have a QFN (Quad flat no-lead package) configuration in which a land 841 for mounting is provided. The configuration is an example, and may be a QFP (Quad flat package), the above-mentioned BGA, or the like.

FIG. 6C is a perspective view of the module shown by omitting a part of the lens cover 821 and the lens 835, and FIG. 6D is a cross-sectional view of the camera module. A part of the land 841 is used as an electrode pad 861, and the electrode pad 861 is electrically connected to the electrodes of the image sensor chip 851 and the IC chip 890 by a wire 871.

By housing the image sensor chip in a package having the above-mentioned form, it can be easily mounted on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

(Embodiment 4)
An example of an electronic device provided with an imaging device according to one aspect of the present invention will be described with reference to FIG.

As an electronic device using the image pickup device according to one aspect of the present invention, it is stored in a display device such as a television or a monitor, a lighting device, a desktop or notebook type personal computer, a word processor, or a recording medium such as a DVD (Digital Versaille Disc). Image playback devices, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, mobile phones, car phones, portable game machines, etc. Large game machines such as tablet terminals and pachinko machines, calculators, portable information terminals (also called "portable information terminals"), electronic notebooks, electronic book terminals, electronic translators, voice input devices, video cameras, digital stills High-frequency heating devices such as cameras, electric shavers, and microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, fans, hair dryers, air conditioners, humidifiers, dehumidifiers, and other air conditioning equipment, dishwashers, etc. Examples thereof include tableware dryers, clothes dryers, duvet dryers, electric refrigerators, electric freezers, electric freezers and refrigerators, DNA storage freezers, tools such as flashlights and chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, power leveling and power storage devices for smart grids.

In addition, mobile objects propelled by electric motors using electric power from power storage devices are also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an infinite track, and an electric assist. Motorized bicycles including bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary explorers, spacecraft, etc.

Electronic devices include sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, It may have a function of measuring flow rate, humidity, inclination, vibration, odor or infrared rays).

7 (A) to 7 (F) show an example of an electronic device.

FIG. 7A shows an example of a wristwatch-type portable information terminal. The mobile information terminal 6100 includes a housing 6101, a display unit 6102, a band 6103, an operation button 6105, and the like. Further, the portable information terminal 6100 includes a secondary battery and an image pickup device or an electronic component according to an aspect of the present invention inside the portable information terminal 6100. For example, the image pickup device according to one aspect of the present invention can be installed in a part of a wristwatch-type portable information terminal to incorporate a TOF camera.

FIG. 7B shows an example of a mobile phone. The personal digital assistant 6200 includes an operation button 6203, a speaker 6204, a microphone 6205, and the like, in addition to the display unit 6202 incorporated in the housing 6201.

Further, the mobile information terminal 6200 includes a fingerprint sensor 6209 in an area overlapping the display unit 6202. The fingerprint sensor 6209 may be an organic light sensor. Since the fingerprint differs depending on the individual, the fingerprint sensor 6209 can acquire the fingerprint pattern and perform personal authentication. Light emitted from the display unit 6202 can be used as a light source for acquiring the fingerprint pattern by the fingerprint sensor 6209.

Further, the portable information terminal 6200 includes a secondary battery and an image pickup device or an electronic component according to an aspect of the present invention. For example, the image pickup device according to one aspect of the present invention can be installed in a part of the portable information terminal 6200 to incorporate a TOF camera. Personal authentication can be performed by acquiring information corresponding to the user's appearance (including unevenness such as a face) using a TOF camera.

FIG. 7C shows an example of a cleaning robot. The cleaning robot 6300 has a display unit 6302 arranged on the upper surface of the housing 6301, a plurality of cameras 6303 arranged on the side surface, a brush 6304, an operation button 6305, various sensors, and the like. Although not shown, the cleaning robot 6300 is provided with tires, suction ports, and the like. The cleaning robot 6300 is self-propelled, can detect dust 6310, and can suck dust from a suction port provided on the lower surface.

For example, the cleaning robot 6300 can analyze the image taken by the camera 6303 and determine the presence or absence of obstacles such as walls, furniture, and steps. Further, when an object that is likely to be entangled with the brush 6304 such as wiring is detected by image analysis, the rotation of the brush 6304 can be stopped. The camera 6303 may use a plurality of types of image pickup devices, and by using the image pickup device according to one aspect of the present invention for one of the cameras 6303, distance information is acquired from the captured information, and the cleaning robot 6300 Malfunction can be reduced.

FIG. 7D shows an example of a robot. The robot 6400 shown in FIG. 7D includes an arithmetic unit 6409, an illuminance sensor 6401, a microphone 6402, an upper camera 6403, a speaker 6404, a display unit 6405, a lower camera 6406, an obstacle sensor 6407, and a moving mechanism 6408.

The microphone 6402 has a function of detecting a user's voice, environmental sound, and the like. Further, the speaker 6404 has a function of emitting sound. The robot 6400 can communicate with the user by using the microphone 6402 and the speaker 6404.

The display unit 6405 has a function of displaying various information. The robot 6400 can display the information desired by the user on the display unit 6405. The display unit 6405 may be equipped with a touch panel. Further, the display unit 6405 may be a removable information terminal, and by installing the display unit 6405 at a fixed position of the robot 6400, charging and data transfer are possible.

The upper camera 6403 and the lower camera 6406 have a function of photographing the surroundings of the robot 6400. As the upper camera 6403 and the lower camera 6406, a plurality of types of image pickup devices may be used, and the image pickup device according to one aspect of the present invention is used for one of the upper camera 6403 and the lower camera 6406. Distance information can be acquired from the information, and malfunctions when the robot 6400 moves can be reduced. Further, the obstacle sensor 6407 can detect the presence or absence of an obstacle in the traveling direction when the robot 6400 moves forward by using the moving mechanism 6408. The robot 6400 can recognize the surrounding environment and move safely by using the upper camera 6403, the lower camera 6406, and the obstacle sensor 6407.

FIG. 7 (E) shows an example of an air vehicle. The flying object 6500 shown in FIG. 7 (E) has a propeller 6501, a camera 6502, a battery 6503, and the like, and has a function of autonomously flying.

For example, the image data taken by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of an obstacle when moving. As the camera 6502, a plurality of types of image pickup devices may be used, and by using the image pickup device according to one aspect of the present invention for one of the cameras 6502, distance information is acquired from the captured information and the flying object is used. It is possible to reduce malfunctions when moving the 6500.

FIG. 7F shows an example of an automobile. The automobile 7160 has an engine, tires, brakes, a steering device, a plurality of cameras, and the like. By using an imaging device according to one aspect of the present invention for one or more of a plurality of cameras installed in the automobile 7160, distance information between the automobile and an object in the outside world can be obtained from the captured information, and the automobile can be obtained. It is possible to recognize the traveling direction of the 7160 or the positional relationship with an object around the automobile 7160. By using the imaging device according to one aspect of the present invention for the automobile 7160, the autopilot function of the automobile 7160 can be assisted.

The configuration, structure, method and the like shown in the present embodiment can be used in appropriate combination with the configuration, structure, method and the like shown in other embodiments.

103 Transistor 104 Transistor 105 Transistor 106 Transistor 108 Capacitor 121 Wiring 122 Wiring 123 Wiring 126 Wiring 127 Wiring 128 Wiring 200 Hierarchy 201 Hierarchy 202 Hierarchy 203 Hierarchy 240 Photoelectric conversion unit 301 First semiconductor board 302 Second semiconductor board 303 Laminated 304 311 circuit 321 memory circuit 321a memory cell 331 pixel circuit 352 wiring 353 wiring 532 BOX layer 533 n-type well area 534 p-type well area 535 back gate 701 gate electrode 702 gate insulation film 703 source area 704 drain area 705 source electrode 706 drain electrode 707 Oxide semiconductor layer 810 Package substrate 811 Package substrate 820 Cover glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 Land 850a Image sensor chip (first semiconductor substrate side)
850b image sensor chip (second semiconductor substrate side)
851a Image sensor chip (first semiconductor substrate side)
851b image sensor chip (second semiconductor substrate side)
860 Electrode Pad 861 Electrode Pad 870 Wire 871 Wire 880 Through Hole 885 Land 6100 Mobile Information Terminal 6101 Housing 6102 Display 6103 Band 6105 Operation Button 6200 Mobile Information Terminal 6201 Housing 6202 Display 6203 Operation Button 6204 Speaker 6205 Microphone 6209 Fingerprint Sensor 6300 Cleaning robot 6301 Housing 6302 Display 6303 Camera 6304 Brush 6305 Operation button 6310 Dust 6400 Robot 6401 Illumination sensor 6402 Microphone 6403 Upper camera 6404 Speaker 6405 Display 6406 Lower camera 6407 Obstacle sensor 6408 Moving mechanism 6409 Computing device 6500 Aircraft 6501 Propeller 6502 Camera 6503 Battery 6504 Electronic Components 7160 Automobile

Claims (5)

1st silicon substrate and
With the second silicon substrate
An image pickup apparatus having a bonded surface between the first silicon substrate and the second silicon substrate.
The first silicon substrate has a photoelectric conversion region and a transfer transistor electrically connected to the photoelectric conversion region.
The second silicon substrate has a reset transistor that is electrically connected to the transfer transistor, an amplification transistor, and a selection transistor that is electrically connected to the amplification transistor.
An imaging device including the selection transistor, the amplification transistor, and a back gate control circuit that controls a threshold value of the reset transistor. In claim 1, the second silicon substrate is an imaging device that is an SOI substrate. With the first semiconductor substrate,
With the second semiconductor substrate,
An image pickup apparatus having a bonding surface between the first semiconductor substrate and the second semiconductor substrate.
The first semiconductor substrate has a photoelectric conversion region and a transfer transistor electrically connected to the photoelectric conversion region.
The second semiconductor substrate has a reset transistor that is electrically connected to the transfer transistor, an amplification transistor, and a selection transistor that is electrically connected to the amplification transistor.
An imaging device including the selection transistor, the amplification transistor, and a back gate control circuit that controls a threshold value of the reset transistor. The imaging apparatus according to claim 3, further comprising a first wiring layer including a transistor having an oxide semiconductor as a channel between the bonded surface and the first semiconductor substrate. The imaging apparatus according to claim 3 or 4, further comprising a second wiring layer including a transistor having an oxide semiconductor as a channel between the bonded surface and the second semiconductor substrate.

Images