TW201714174A - 雙列直插記憶體模組固態硬碟系統晶片及方法 - Google Patents

雙列直插記憶體模組固態硬碟系統晶片及方法 Download PDF

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Publication number
TW201714174A
TW201714174A TW105118476A TW105118476A TW201714174A TW 201714174 A TW201714174 A TW 201714174A TW 105118476 A TW105118476 A TW 105118476A TW 105118476 A TW105118476 A TW 105118476A TW 201714174 A TW201714174 A TW 201714174A
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TW
Taiwan
Prior art keywords
dual
memory module
line memory
solid state
hard disk
Prior art date
Application number
TW105118476A
Other languages
English (en)
Chinese (zh)
Inventor
克雷格 韓森
Original Assignee
三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 三星電子股份有限公司 filed Critical 三星電子股份有限公司
Publication of TW201714174A publication Critical patent/TW201714174A/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Dram (AREA)
TW105118476A 2015-10-07 2016-06-14 雙列直插記憶體模組固態硬碟系統晶片及方法 TW201714174A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562238659P 2015-10-07 2015-10-07
US14/973,720 US9666263B2 (en) 2015-10-07 2015-12-17 DIMM SSD SoC DRAM byte lane skewing

Publications (1)

Publication Number Publication Date
TW201714174A true TW201714174A (zh) 2017-04-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW105118476A TW201714174A (zh) 2015-10-07 2016-06-14 雙列直插記憶體模組固態硬碟系統晶片及方法

Country Status (5)

Country Link
US (1) US9666263B2 (enExample)
JP (1) JP6775353B2 (enExample)
KR (1) KR102457095B1 (enExample)
CN (1) CN106569967B (enExample)
TW (1) TW201714174A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
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US10845866B2 (en) * 2017-06-22 2020-11-24 Micron Technology, Inc. Non-volatile memory system or sub-system
JP2022512058A (ja) 2018-12-21 2022-02-02 イルミナ インコーポレイテッド ヌクレアーゼを利用したｒｎａ枯渇
KR102721961B1 (ko) 2020-07-22 2024-10-28 삼성전자주식회사 메모리 모듈 및 이를 포함하는 메모리 시스템
KR20230045861A (ko) * 2021-09-29 2023-04-05 삼성전자주식회사 메모리 모듈의 반도체 메모리 장치의 동작을 설계 레벨에서 검증하는 시뮬레이션 방법 및 시스템

Family Cites Families (14)

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KR20020010300A (ko) * 2000-07-29 2002-02-04 박종섭 반도체 소자의 클럭 테스트 장치
US7289386B2 (en) * 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
JP5156932B2 (ja) * 2004-03-31 2013-03-06 ラウンド ロック リサーチ、エルエルシー 集積回路における信号タイミングの再構成
KR100725783B1 (ko) * 2004-12-14 2007-06-08 한국전자통신연구원 Ｓｎｍｐ를 이용한 망 관리 에이전트로 구성된홈게이트웨이 시스템 및 홈게이트웨이 시스템에서ｓｎｍｐ를 이용한 망 관리 에이전트 구성 방법
KR20060081522A (ko) 2005-01-10 2006-07-13 삼성전자주식회사 피씨아이 익스프레스의 바이트 스큐 보상방법 및 이를위한 피씨아이 익스프레스 물리 계층 수신기
US7457978B2 (en) 2005-05-09 2008-11-25 Micron Technology, Inc. Adjustable byte lane offset for memory module to reduce skew
KR101300854B1 (ko) * 2007-03-05 2013-08-27 삼성전자주식회사 직교 주파수 다중 접속 무선 통신 시스템에서 자원 할당장치 및 방법
US7725783B2 (en) * 2007-07-20 2010-05-25 International Business Machines Corporation Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs
KR100897298B1 (ko) * 2007-12-27 2009-05-14 (주)인디링스 읽기 신호 타이밍을 조정하는 플래시 메모리 장치 및플래시 메모리 장치의 읽기 제어 방법
US7975164B2 (en) 2008-06-06 2011-07-05 Uniquify, Incorporated DDR memory controller
US8073090B2 (en) 2008-07-11 2011-12-06 Integrated Device Technology, Inc. Synchronous de-skew with programmable latency for multi-lane high speed serial interface
US8472279B2 (en) * 2010-08-31 2013-06-25 Micron Technology, Inc. Channel skewing
KR20150006560A (ko) * 2013-07-09 2015-01-19 주식회사 에스원 디지털 도어 락의 소비 전력 감소를 통한 배터리 수명 연장 방법 및 이를 이용한 디지털 도어락 시스템
KR102147228B1 (ko) * 2014-01-23 2020-08-24 삼성전자주식회사 타겟 모듈의 라이트 레벨링을 제어하는 라이트 레벨링 제어 회로 및 그에 따른 라이트 레벨링 제어방법

Also Published As

Publication number Publication date
JP2017073122A (ja) 2017-04-13
US20170103796A1 (en) 2017-04-13
CN106569967A (zh) 2017-04-19
JP6775353B2 (ja) 2020-10-28
US9666263B2 (en) 2017-05-30
KR102457095B1 (ko) 2022-10-20
CN106569967B (zh) 2019-11-22
KR20170041615A (ko) 2017-04-17

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