TW201712830A - Package substrate, package structure and method for manufacturing the package substrate and the package structure - Google Patents

Abstract

A package substrate includes a dielectric layer, a first wiring layer, a first pad, a second wiring layer, a carrier, and a resist layer. The dielectric layer defines a plurality of first conductive vias and second conductive vias. The first and second conductive vias are substantially coaxial. The first and second wiring layers are located at opposite sides of the dielectric layer, and are electrically connected to each other through the first and second conductive vias. The first wiring layer defines a plurality of first pads protruding from first wiring layer. the first pads correspond to the first conductive vias respectively. The carrier covers the first wiring layer and the dielectric layer exposed therefrom. The resist layer is formed on the second wiring layer. The resist layer defines a plurality of openings to exposing portions of the second wiring layer to define a plurality of second pads.

Description

Package substrate, package structure and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing technology, and in particular, to a package substrate, a package structure including the package substrate, a method for fabricating the package substrate, and a method for fabricating the package structure including the package substrate.

As electronic products become thinner and lighter, the package substrates of wafers are gradually moving toward a thinner direction. However, due to the thinness and thinness of the package substrate, the package substrate is prone to abnormal phenomena such as breakage and bending during the manufacturing process, and corresponding problems occur in the subsequent packaging process, resulting in a serious shortage of the final packaged product.

In view of the above, it is necessary to provide a package substrate, a package structure, a package substrate fabrication method, and a package structure fabrication method that overcome the above problems.

A package substrate includes a dielectric layer, a first conductive circuit layer, a first electrical connection pad, a second conductive circuit layer, a carrier plate, and a solder resist layer. First and second conductive holes coaxially disposed and communicating with each other are formed in the dielectric layer. The first and second conductive circuit layers are respectively located on opposite sides of the dielectric layer, and are electrically connected by the first and second conductive holes. The first electrical connection pad protrudes from the first conductive circuit layer and corresponds to the first conductive hole. The carrier plate covers the first electrical connection pad, the first conductive circuit layer, and a portion of the dielectric layer exposed from the first conductive circuit layer. The solder resist layer is formed on the second conductive wiring layer. The solder resist layer is provided with a plurality of openings. A portion of the second conductive circuit layer is exposed from the opening to form a second electrical connection pad.

A package structure includes a package substrate, a wafer, and a primer. The package substrate includes a dielectric layer, a first conductive circuit layer, a first electrical connection pad, a second conductive circuit layer, a carrier plate, and a solder resist layer. First and second conductive holes coaxially disposed and communicating with each other are formed in the dielectric layer. The first and second conductive circuit layers are respectively located on opposite sides of the dielectric layer, and are electrically connected by the first and second conductive holes. The first electrical connection pad protrudes from the first conductive circuit layer and corresponds to the first conductive hole. The carrier plate covers the first electrical connection pad, the first conductive circuit layer, and a portion of the dielectric layer exposed from the first conductive circuit layer. The solder resist layer is formed on the second conductive wiring layer. The solder resist layer is provided with a plurality of openings. A portion of the second conductive circuit layer is exposed from the opening to form a second electrical connection pad. The wafer is mounted on the package substrate. The wafer includes a plurality of electrode pads. The electrode pads are electrically connected to the second electrical connection pads in one-to-one correspondence. The primer is filled between the wafer and the package substrate.

A method of fabricating a package substrate, comprising the steps of: providing a substrate, the substrate comprising a dielectric layer and a removable support plate, the dielectric layer comprising opposite first and second surfaces, the support plate being in contact with the second surface Opening a first blind via from the first surface to the dielectric layer; forming the first blind via to form a first conductive via, and forming a first conductive trace layer on the first surface; and the first conductive trace Forming a first electrical connection pad at a position corresponding to the first conductive hole; pressing the carrier plate on the first conductive circuit layer and the first electrical connection pad; removing the support plate to expose the second surface; The second surface defines a second blind hole in the dielectric layer, the second blind hole is coaxial with the first blind hole and communicates with each other; the second blind hole is formed into a second conductive hole and in the second Forming a second conductive circuit layer on the surface, the second conductive circuit layer is electrically connected to the first conductive circuit layer through the second conductive hole and the first conductive hole; and forming an opening on the second conductive circuit layer a solder resist layer, part of the second conductive circuit layer from the opening Forming a second electrical connection pad.

A package structure manufacturing method includes the steps of: providing a substrate, the substrate comprising a dielectric layer and a removable support plate, the dielectric layer comprising opposite first and second surfaces, the support plate and the second surface a first blind via is formed in the dielectric layer from the first surface; the first blind via is formed to form a first conductive via, and a first conductive trace layer is formed on the first surface; Forming a first electrical connection pad at a position corresponding to the first conductive hole; bonding the carrier plate on the first conductive circuit layer and the first electrical connection pad; removing the support plate to expose the second surface; Opening a second blind hole from the second surface to the dielectric layer, the second blind hole is coaxial with the first blind hole and communicating with each other; forming the second blind hole to form a second conductive hole and Forming a second conductive circuit layer on the second surface, the second conductive circuit layer is electrically connected to the first conductive circuit layer through the second conductive hole and the first conductive hole; forming an opening on the second conductive circuit layer a solder resist layer from which the second conductive circuit layer is opened Forming a second exposed conductive pads, to obtain a package substrate; and the wafer is mounted on the package substrate, the wafer comprising a plurality of electrode pads, the electrode pad and the second conductive pads are electrically connected to one correspondence.

Compared with the prior art, the package substrate and the package structure provided by the present invention can support the package substrate and the sealing structure by including the carrier plate, so that no abnormal phenomenon such as folding or bending occurs; The method for fabricating a package substrate and the method for fabricating a package structure provided by the invention provide support at different stages of the process by the support plate and the carrier plate during the manufacturing process, and therefore, an abnormal phenomenon such as folding or bending does not occur.

1 is a schematic cross-sectional view of a support plate according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a first release layer of the support plate of FIG. 1 after a dielectric layer is laminated.

3 is a cross-sectional view showing the first blind via in the dielectric layer of FIG. 2.

4 is a schematic cross-sectional view showing the first plating barrier layer formed on the second release layer of the support plate of FIG. 3.

5 is a schematic cross-sectional view showing the first surface of the dielectric layer of FIG. 4, the hole wall of the first blind via, and the surface of the first peeling layer exposed from the first blind via.

6 is a schematic cross-sectional view showing a second plating barrier layer formed on the first plating seed layer of FIG. 5.

Figure 7 is a schematic cross-sectional view showing the first plating layer formed on the first plating seed layer exposed from the second plating barrier layer of Figure 6.

Figure 8 is a schematic cross-sectional view showing the formation of a third plating barrier layer on the second plating barrier layer of Figure 7.

Figure 9 is a schematic cross-sectional view showing the first electrical connection pad formed on the first plating layer exposed from the opening of the third plating barrier layer of Figure 8.

Figure 10 is a cross-sectional view showing the removal of the second and third plating barrier layers of Figure 9 to expose the first plating seed layer shielded by the second plating barrier.

Figure 11 is a cross-sectional view showing the first electroplated seed layer exposed in Figure 10 after the first conductive circuit layer is formed.

Figure 12 is a cross-sectional view showing the first conductive layer of Figure 11 after the carrier plate is pressed.

Figure 13 is a schematic cross-sectional view showing the first plating barrier layer of Figure 12 removed and the support panel peeled from the second release layer.

Figure 14 is a cross-sectional view showing the second peeling layer of Figure 13 after rapid etching removal, exposing the second surface and forming a second blind via.

15 is a cross-sectional view showing the second surface of the dielectric layer of FIG. 14, the hole wall of the second blind via, and the second plating seed layer formed on the first plating layer exposed from the second blind via.

Figure 16 is a schematic cross-sectional view showing the formation of a patterned fourth plating barrier layer on the second plating seed layer of Figure 15.

Figure 17 is a schematic cross-sectional view showing the formation of a second plating layer on the second plating seed layer exposed from the fourth plating barrier layer of Figure 16 .

18 is a cross-sectional view showing the removal of the fourth plating resist layer of FIG. 17 to expose the second plating seed layer shielded by the fourth plating barrier layer and removing the second conductive wiring layer.

Figure 19 is a schematic cross-sectional view showing the formation of a solder resist layer on the second conductive wiring layer of Figure 18.

Figure 20 is a schematic cross-sectional view showing the formation of solder balls on the second electrical connection pad of Figure 19.

21 is a schematic cross-sectional view showing the wafer mounted on the package substrate of FIG. 20.

22 is a schematic cross-sectional view showing the filling of the primer between the wafer and the package substrate of FIG. 21.

Figure 23 is a cross-sectional view showing the carrier of Figure 22 after grinding to expose the first electrical connection pads.

The package substrate, the package structure, the method for fabricating the package substrate, and the method for fabricating the package structure provided by the present invention will be described in detail below with reference to specific embodiments.

The manufacturing method of the package structure 100 provided by the present invention comprises the following steps:

In the first step, referring to Figure 1, a support plate 11 is provided.

The support plate 11 includes a first insulating layer 111, a first copper foil layer 112, a second copper foil layer 113, a first peeling layer 114, and a second peeling layer 115. The first copper foil layer 112 and the second copper foil layer 113 are respectively located on opposite sides of the first insulating layer 111. The first peeling layer 114 is located on a side of the first copper foil layer 112 facing away from the first insulating layer 111. The first peeling layer 114 can be peeled off from the first copper foil layer 112. The second peeling layer 115 is located on a side of the second copper foil layer 113 facing away from the first insulating layer 111. The second peeling layer 115 may be peeled off from the second copper foil layer 113. The first peeling layer 114 and the second peeling layer 115 may be a conductive metal layer such as a copper layer or an aluminum layer. In the present embodiment, the first release layer 114 and the second release layer 115 are both copper layers. The support plate 11 is mainly used to provide support for subsequent processes. Each of the first copper foil layer 112 and the second copper foil layer 113 has a thickness ranging from 18 micrometers. Each of the first release layer 114 and the second release layer 115 has a thickness ranging from 3 micrometers. The thickness of the first insulating layer 111 ranges from 100 to 200 microns.

In the second step, referring to FIG. 2, a dielectric layer 12 is crimped onto the support plate 11 to obtain a substrate.

The dielectric layer 12 includes opposing first and second surfaces 121, 122. In this embodiment, the dielectric layer 12 is crimped on the surface of the first peeling layer 114 away from the first insulating layer 111. The second surface 122 is in contact with the first release layer 114. In this embodiment, the dielectric layer 12 is an ABF (Ajinomoto Bond Film) material to facilitate formation of fine lines thereon. The thickness of the dielectric layer 12 ranges from 15 to 30 microns.

In other embodiments, a substrate including the dielectric layer 12 and the removable support plate 11 may be directly provided.

In the third step, referring to FIG. 3, a first blind via 123 is opened in the dielectric layer 12.

In the embodiment, the first blind via 123 is opened from the first surface 121 into the dielectric layer 12 . The first blind via 123 penetrates through the dielectric layer 12 . A portion of the first peeling layer 114 is exposed from the first blind hole 123. The first blind via 123 has a pore size ranging from 50 to 70 microns. The first blind hole 123 can be opened by laser ablation or mechanical drilling. In this embodiment, the first blind via 123 is formed by laser ablation.

In the fourth step, referring to FIG. 4, a first plating barrier layer 131 is formed on the surface of the second peeling layer 115.

The first plating barrier layer 131 completely covers the second peeling layer 115. The first plating barrier layer 131 may be formed of a dry film by an exposure process.

It can be understood that in other embodiments, the first plating barrier layer 131 may not be formed on the surface of the second peeling layer 115.

In the fifth step, referring to FIG. 5, a first plating seed layer 141 is formed on the first surface 121, the hole wall of the first blind hole 123, and the surface of the first peeling layer 114 exposed from the first blind hole 123.

The first plating seed layer 141 has a thickness of about 0.5 microns. The first plating seed layer 141 can be formed by electroplating or chemical deposition.

In a sixth step, referring to FIG. 6, a patterned second plating barrier layer 132 is formed on the first plating seed layer 141.

A portion of the first plating seed layer 141 is exposed from the second plating barrier layer 132. A portion of the first plating seed layer 141 partially exposed from the second plating barrier layer 132 includes a portion corresponding to the first blind via 123. The second plating barrier layer 132 has a thickness of about 25 microns. The second plating barrier layer 132 can be formed by a dry film by exposure and development.

In a seventh step, referring to FIG. 7, a first plating layer 151 is formed on the first plating seed layer 141 exposed from the second plating barrier layer 132.

The first plating layer 151 fills the first blind via 123 to form a first conductive via 124. The first plating layer 151 also protrudes from the dielectric layer 12. The first plating layer 151 protrudes from the dielectric layer 12 to a thickness of about 15 microns.

In the eighth step, referring to FIG. 8, a third plating barrier layer 133 is formed on the second plating barrier layer 132.

The third plating barrier layer 133 covers the first plating layer 151 and the second plating barrier layer 132. The third plating barrier layer 133 is provided with a plurality of openings 1331. A portion of the first plating layer 151 is exposed from the opening 1331. In the embodiment, the opening 1331 corresponds to the first conductive hole 124. The diameter of the opening 1331 is larger than the diameter of the first conductive hole 124. The third plating barrier layer 133 is formed in the same manner as the second plating barrier layer 132.

In a ninth step, referring to FIG. 9, a first electrical connection pad 1611 is formed on the first plating layer 151 exposed from the opening 1331.

In this embodiment, the first electrical connection pad 1611 has a thickness of about 30 micrometers. The first electrical connection pad 1611 can be formed by electroplating.

In the tenth step, referring to FIG. 10, the second plating barrier layer 132 and the third plating barrier layer 133 are removed to expose the first plating seed layer 141 masked by the second plating barrier layer 132.

In this embodiment, the second plating barrier layer 132 and the third plating barrier layer 133 are removed by chemical treatment.

In an eleventh step, referring to FIG. 11, the exposed first plating seed layer 141 is removed to form a first conductive wiring layer 161.

A portion of the dielectric layer 12 is exposed from the first conductive wiring layer 161. The exposed first plating seed layer 141 can be removed by rapid etching.

In the twelfth step, referring to FIG. 12, the carrier board 17 is press-fitted on the first conductive wiring layer 161.

The carrier plate 17 covers the first conductive wiring layer 161 and the dielectric layer 12 exposed from the first conductive wiring layer 161. The carrier plate 17 includes a carrier layer 171 and a third copper foil layer 172. The carrier layer 171 is closer to the first conductive wiring layer 161 than the third copper foil layer 172. In this embodiment, the thickness of the carrier layer 171 ranges from 100 to 150 micrometers. The third copper foil layer 172 has a thickness of about 18 microns.

It can be understood that, in other embodiments, the first conductive circuit layer 161 and the dielectric layer 12 exposed from the first conductive circuit layer 161 may be before the carrier layer 17 is pressed on the first conductive circuit layer 161. A surface roughening treatment is performed to increase the bonding strength between the carrier sheet 17 and the first conductive wiring layer 161 and the dielectric layer 12 exposed from the first conductive wiring layer 161.

Referring to FIG. 13, the first plating barrier layer 131 is removed, and the second copper foil layer 113 of the support plate 11 is peeled off from the second peeling layer 115 to expose the second peeling layer 115. .

In a fourteenth step, referring to FIG. 14, the second peeling layer 115 is quickly etched to expose the second surface 122 and form a second blind via 125.

The second blind hole 125 is disposed coaxially with the first blind hole 123. The aperture of the second blind hole 125 is smaller than the aperture of the first blind hole 123. In this embodiment, the second blind hole 125 has a hole diameter of about 50 micrometers. The first plating layer 151 in the first blind via 123 is exposed from the second blind via 125.

In a fifteenth step, referring to FIG. 15, a second plating seed layer 142 is formed on the second surface 122, the hole wall of the second blind hole 125, and the first plating layer 151 exposed from the second blind hole 125.

The second plating seed layer 142 is formed in the same manner as the first plating seed layer 141.

In a sixteenth step, referring to FIG. 16, a patterned fourth plating barrier layer 134 is formed on the second plating seed layer 142.

A portion of the second plating seed layer 142 is exposed from the fourth plating barrier layer 134. A portion of the second plating seed layer 142 partially exposed from the fourth plating barrier layer 134 includes a portion corresponding to the second blind via 125. The fourth plating barrier layer 134 is formed in the same manner as the second plating barrier layer 132.

In a seventeenth step, referring to FIG. 17, a second plating layer 152 is formed on the second plating seed layer 142 exposed from the fourth plating barrier layer 134.

The second plating layer 152 fills the second blind via 125 to form a second conductive via 126. The second plating layer 152 also protrudes from the second surface 122.

In an eighteenth step, referring to FIG. 18, the fourth plating barrier layer 134 is removed to expose the second plating seed layer 142 masked by the fourth plating barrier layer 134 and the exposed second plating seed layer 142 is removed. To form the second conductive wiring layer 162.

In this embodiment, the fourth plating barrier layer 134 is removed by chemical treatment. The portion of the second plating seed layer 142 that is shielded by the fourth plating barrier layer 134 can be removed by rapid etching. The line width of the wires of the second conductive wiring layer 162 and the spacing between the wires are both less than 15 micrometers.

In the nineteenth step, referring to FIG. 19, a solder resist layer 18 is formed on the second conductive wiring layer 162 to obtain the package substrate 10.

In the present embodiment, the solder resist layer 18 has a thickness ranging from 15 to 20 micrometers. The solder resist layer 18 is provided with an opening 181. A portion of the second conductive circuit layer 162 is exposed from the opening 181 to form a second electrical connection pad 1621.

It can be understood that, referring to FIG. 20, the manufacturing method of the package substrate 10 further includes forming solder balls 19 on the second electrical connection pads 1621. The method of fabricating the package substrate 10 may further include forming a metal protective layer such as a nickel gold layer or a tin plating layer on the surface of the second electrical connection pad 1621 before the solder ball 19 is formed on the second electrical connection pad 1621. .

In the twenty-first step, referring to FIG. 21, the wafer 20 is mounted on the package substrate 10.

The wafer 20 can be a logic wafer or a functional wafer. The wafer 20 includes a plurality of electrode pads 21. The electrode pads 21 are in one-to-one correspondence with the second electrical connection pads 1621 and are electrically connected by solder balls 19.

In a twenty-first step, referring to FIG. 22, a primer 30 is filled between the wafer 20 and the package substrate 10 to obtain a package structure 100.

The primer 30 is filled between the solder balls 19 and fills a gap between the bottom surface of the wafer 20 and the package substrate 10.

It can be understood that, referring to FIG. 23, the manufacturing method of the package structure further includes grinding and removing a portion of the thickness of the carrier plate 17 to expose the first electrical connection pad 1611. The remaining carrier plate 17 can protect the second conductive circuit layer 162 as a solder mask. Of course, the manufacturing method of the package structure further includes forming solder balls 40 on the first electrical connection pads 1611.

Referring to FIG. 22 again, the present invention further provides a package structure 100 obtainable by the above method, comprising a package substrate 10, a wafer 20, and a primer 30.

The package substrate 10 includes a dielectric layer 12, a first conductive wiring layer 161, a first electrical connection pad 1611, a second conductive wiring layer 162, a carrier plate 17, a solder resist layer 18, and solder balls 19.

The dielectric layer 12 includes opposing first and second surfaces 121, 122. In the present embodiment, the dielectric layer 12 is an ABF (Ajinomoto Bond Film) material. The thickness of the dielectric layer 12 ranges from 15 to 30 microns. The dielectric layer 12 is formed with a first conductive via 124 and a second conductive via 126 that are coaxially disposed and electrically connected to each other. The first conductive via 124 extends from the first surface 121 toward the inside of the dielectric layer 12 . The first conductive via 124 has a pore size ranging from 50 to 70 micrometers. The second conductive via 126 extends from the second surface 122 toward the interior of the dielectric layer 12. The aperture of the second conductive via 126 is smaller than the aperture of the first conductive via 124.

The first conductive circuit layer 161 is located on the first surface 121. The first conductive circuit layer 161 is electrically connected to the first conductive via 124.

The first electrical connection pad 1611 is protruded from the first conductive circuit layer 161. The first electrical connection pads 1611 are in one-to-one correspondence with the first conductive holes 124.

The carrier plate 17 is formed on the first conductive circuit layer 161 and the first electrical connection pad 1611. The carrier plate 17 has a thickness ranging from 170 to 220 microns. In the present embodiment, the carrier plate 17 covers the first electrical connection pad 1611, the first conductive wiring layer 161, and the dielectric layer 12 exposed from the first conductive wiring layer 161. The carrier plate 17 includes a carrier layer 171 and a copper foil layer 172. The carrier layer 171 is closer to the first conductive wiring layer 161 than the copper foil layer 172. The thickness of the carrier layer 171 ranges from 100 to 150 microns.

The second conductive wiring layer 162 is formed on the second surface 122. The line width of the wires of the second conductive wiring layer 162 and the spacing between the wires are both less than 15 micrometers. The second conductive via layer 162 is electrically connected to the second conductive via 126 and electrically connected to the first conductive via layer 161 via the second conductive via 126 and the first conductive via 124 .

The solder resist layer 18 is formed on the second conductive wiring layer 162.

In the present embodiment, the solder resist layer 18 has a thickness ranging from 15 to 20 micrometers. The solder resist layer 18 is provided with an opening 181. A portion of the second conductive circuit layer 162 is exposed from the opening 181 to form a second electrical connection pad 1621.

The solder ball 19 is formed on the second electrical connection pad 1621.

It can be understood that, in other embodiments, the package substrate 10 further includes a metal protective layer. The metal protective layer is formed between the second electrical connection pad 1621 and the solder ball 19. The metal protective layer may be a nickel gold layer or a tin plating layer or the like.

The wafer 20 is mounted on the package substrate 10.

The wafer 20 can be a logic wafer or a functional wafer. The wafer 20 includes a plurality of electrode pads 21. The electrode pads 21 are in one-to-one correspondence with the second electrical connection pads 1621 and are electrically connected by solder balls 19.

The primer 30 is filled between the solder balls 19 and fills a gap between the bottom surface of the wafer 20 and the package substrate 10.

The package substrate and the package structure provided by the present invention can support the package substrate and the sealing structure by including a carrier plate, so that no abnormal phenomenon such as folding or bending occurs; and the package substrate provided by the present invention is manufactured. The method and the method for manufacturing the package structure, in the manufacturing process, the support plate and the carrier plate respectively provide support at different stages of the process, and therefore, there is no abnormal phenomenon such as folding or bending.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only for the preferred embodiment of the present invention and the data listed therein are used for testing and reference, and the scope of patent application in this case cannot be limited thereby. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧Package structure

11‧‧‧Support board

112‧‧‧First copper foil layer

111‧‧‧First insulation

113‧‧‧Second copper foil layer

114‧‧‧First peeling layer

115‧‧‧Second stripping layer

12‧‧‧Dielectric layer

121‧‧‧ first surface

122‧‧‧ second surface

123‧‧‧First blind hole

131‧‧‧First plating barrier

141‧‧‧First plating seed layer

132‧‧‧Second plating barrier

151‧‧‧First plating

133‧‧‧ Third plating barrier

1331, 181‧‧‧ openings

124‧‧‧First conductive hole

1611‧‧‧First electrical connection pad

161‧‧‧First conductive circuit layer

17‧‧‧Loading board

171‧‧‧bearing layer

172‧‧‧ Third copper foil layer

125‧‧‧second blind hole

142‧‧‧Second plating seed layer

134‧‧‧4th plating barrier

152‧‧‧Second plating

126‧‧‧Second conductive hole

162‧‧‧Second conductive circuit layer

18‧‧‧ solder mask

1621‧‧‧Second electrical connection pad

19, 40‧‧‧ solder balls

20‧‧‧ wafer

21‧‧‧electrode pads

30‧‧‧Bottom glue

no

100‧‧‧Package structure

10‧‧‧Package substrate

12‧‧‧Dielectric layer

121‧‧‧ first surface

122‧‧‧ second surface

123‧‧‧First blind hole

141‧‧‧First plating seed layer

151‧‧‧First plating

181‧‧‧ openings

124‧‧‧First conductive hole

1611‧‧‧First electrical connection pad

161‧‧‧First conductive circuit layer

17‧‧‧Loading board

171‧‧‧bearing layer

172‧‧‧ Third copper foil layer

125‧‧‧second blind hole

142‧‧‧Second plating seed layer

152‧‧‧Second plating

126‧‧‧Second conductive hole

162‧‧‧Second conductive circuit layer

18‧‧‧ solder mask

1621‧‧‧Second electrical connection pad

19‧‧‧ solder balls

20‧‧‧ wafer

21‧‧‧electrode pads

30‧‧‧Bottom glue

Claims (10)

A method for manufacturing a package substrate, comprising the steps of:
Providing a substrate comprising a dielectric layer and a removable support plate, the dielectric layer comprising opposite first and second surfaces, the support plate being in contact with the second surface;
Opening a first blind hole from the first surface into the dielectric layer;
Forming the first blind via to form a first conductive via, and forming a first conductive trace layer on the first surface;
Forming a first electrical connection pad at a position where the first conductive circuit layer corresponds to the first conductive hole;
Pressing the carrier plate on the first conductive circuit layer and the first electrical connection pad;
Removing the support plate to expose the second surface;
Opening a second blind hole from the second surface into the dielectric layer, the second blind hole being coaxial with the first blind hole and communicating with each other;
Forming a second via hole to form a second conductive via and forming a second conductive circuit layer on the second surface, the second conductive trace layer and the first conductive via layer through the second conductive via and the first conductive via Electrically connecting; and forming a solder resist layer having an opening on the second conductive circuit layer, and a portion of the second conductive circuit layer is exposed from the opening to form a second electrical connection pad. The method for fabricating a package substrate according to claim 1, wherein the first blind via is formed to form a first conductive via, and a first conductive trace layer is formed on the first surface, and the first conductive trace layer is corresponding to the first conductive via layer. The position of the first conductive hole forms a first electrical connection pad, and the steps include:
Forming a first plating seed layer on the first surface and the first blind hole surface;
Forming a patterned second plating barrier layer on the first plating seed layer, and a portion of the first plating seed layer is exposed from the plating barrier layer;
Forming a first plating layer on the exposed first plating seed layer, the first plating layer filling the first blind hole to form a first conductive hole, the first plating layer also protruding from the dielectric layer;
Forming, in the second plating barrier layer, a third plating barrier having an opening, the first conductive hole being exposed from the opening;
Forming a first electrical connection pad on the first conductive via;
The second and third plating barrier layers are removed to expose the first plating seed layer that is masked by the second plating barrier layer and the exposed first plating seed layer is removed to form a first conductive wiring layer. The method of fabricating a package substrate according to claim 1, wherein the support plate further comprises a peeling layer which is peelable and is a conductive metal, the peeling layer is in contact with the dielectric layer, and the support plate is removed to expose the second surface. , including the steps:
Removing the support plate from the release layer to expose the release layer;
The release layer is removed by rapid etching to expose the second surface. The method for fabricating a package substrate according to claim 1, wherein the method for fabricating the package substrate further comprises forming a solder ball on the second electrical connection pad. A method of fabricating a package structure, comprising the method of fabricating a package substrate according to any one of claims 1 to 4, wherein the method for fabricating the package structure further comprises mounting a wafer on the package substrate, the wafer comprising a plurality of electrode pads, The electrode pads are electrically connected to the second electrical connection pads in one-to-one correspondence. The method for fabricating a package structure according to claim 5, further comprising filling a primer between the wafer and the package substrate. The method for fabricating a sealing structure according to claim 5, further comprising: grinding the carrier plate to expose the first electrical connection pad, so that the ground carrier plate and the first electrical connection pad are flat. A package substrate includes a dielectric layer, a first conductive circuit layer, a first electrical connection pad, a second conductive circuit layer, a carrier plate and a solder resist layer, wherein the dielectric layer is formed with a first coaxially disposed and interconnected first And the second conductive vias, the first and second conductive circuit layers are respectively located on opposite sides of the dielectric layer, and are electrically connected by the first and second conductive vias, the first electrical connection pad is convex Provided on the first conductive circuit layer and corresponding to the first conductive hole, the carrier plate covers the first electrical connection pad, the first conductive circuit layer and a portion of the dielectric exposed from the first conductive circuit layer The solder resist layer is formed on the second conductive circuit layer, and the solder resist layer is provided with a plurality of openings, and a portion of the second conductive circuit layer is exposed from the opening to form a second electrical connection pad. The package substrate of claim 8, wherein the package substrate further comprises a metal protective layer formed on the second electrical connection pad. A package structure, comprising the package substrate of claim 8-9, further comprising a wafer and a primer, the wafer being mounted on the package substrate, the wafer comprising a plurality of electrode pads, the electrode pads and the second electrode The connection pads are electrically connected one by one, and the primer is filled between the wafer and the package substrate.