JP2013058545A - Electronic device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable electronic device which has fine through electrodes, each of which has a desired minor diameter, even if a versatile insulation material is used in sealing an electronic component and enables further microfabrication.SOLUTION: An electronic component built-in substrate 20 includes: first insulation layers 4A, 4B (containing an inorganic filler 9a having a large diameter); electronic components 2A, 2B provided at the first insulation layers 4A, 4B; and through electrodes 8 penetrating through the first insulation layers 4A, 4B. A second insulation layer 6 (containing an inorganic filler 9b having a diameter smaller than that of the inorganic filler 9a) is embedded in first through holes 5 formed at the first insulation layers 4A, 4B, and second through holes 7, each of which has a diameter smaller than the first through hole 5, are formed at the second insulation layer 6. Then, conductive materials 8a, 8b are disposed in the second through holes. Through electrodes 8 are formed through these processes.

Description

  The present invention relates to an electronic device and a manufacturing method thereof.

  In recent years, so-called three-dimensional mounting technology in which chips such as various semiconductor elements are built in a substrate has been developed in order to meet demands for further enhancement in performance and size of electronic devices. Among these, a so-called electronic component built-in module in which an electronic component typified by a semiconductor bare chip is embedded with a mold resin has attracted attention as a packaging technology for realizing high density and low cost. In the electronic component built-in module, a through electrode (through via) penetrating the mold resin is provided in order to electrically connect electrodes positioned on the upper and lower surfaces of the mold resin.

JP 2007-67053 A Japanese Patent No. 3892259

  With the demand for miniaturization of the electronic component built-in module, it is necessary to form the through via with a small diameter. As the insulating resin of the mold resin in which the through via is formed, a resin containing an inorganic filler having a thermal expansion coefficient close to that of the electronic component material is used in order to reduce the difference in thermal expansion coefficient from the electronic component material such as Si. . In order to ensure that the coefficient of thermal expansion is sufficiently close to the electronic component material, in order to ensure a high proportion of the inorganic filler in the insulating resin, an insulating resin containing 80% by weight or more of the inorganic filler is widely used.

  In the electronic component built-in module, when the through via is formed, a through hole penetrating the mold resin is formed. When the through hole is formed with a small diameter, the following problems are caused.

  As shown in FIG. 26A, a case where a through hole 101a having a diameter of, for example, 100 μm is formed in the mold resin 101 will be described. The inorganic filler 102 contained in the widely used mold resin 101 has a maximum particle size of about 50 μm to 75 μm. The inorganic filler 102 is so large that it cannot be ignored by a relative comparison with the diameter of the through hole 101a. Therefore, when the through-hole 101a is formed, there is a problem that the inner wall surface of the through-hole 101a does not have the desired shape due to the inorganic filler 102 present at the formation position. That is, when the through hole 101a is formed, the inorganic filler 102 present at the formation position is different from the resin in material, hardness, etc., so that it falls off due to processing of the mold resin 101, or at least part of it remains. On the inner wall surface of the through-hole 101a, when the inorganic filler 102 is dropped, an extended portion 101b that extends the diameter of the through-hole 101a reflecting the inorganic filler 102 existing at the formation position of the through-hole 101a is formed. . On the other hand, when the inorganic filler 102 remains, a reduced portion 101c is formed in which the inorganic filler 102 protrudes into the through hole 101a and reduces the diameter of the through hole 101a. Thus, the inner wall surface of the through hole 101a has an unexpected shape having an unexpectedly expanded portion 101b and a reduced portion 101c.

  When the through-hole 101a is formed as described above, as shown in FIG. 26B, when the conductive layer 103 is formed on the inner wall surface of the through-hole 101a, it is complicated due to the expanded portion 101b and the reduced portion 101c. A conductive layer 103 is formed on the shaped inner wall surface. Therefore, a through via having a non-uniform thickness of the conductive layer 103 is formed. This through-via has a problem that the conductive layer 103 is likely to be disconnected mainly due to the non-uniform thickness of the conductive layer 103 when the conductive layer 103 is formed or the electronic component built-in module is used. It is considered that the disconnection of the conductive layer 103 is likely to occur particularly at the portions where the extended portions 101b and the reduced portions 101c are formed, or at the edge portions of the extended portions 101b and the reduced portions 101c. In addition, in such an electronic component built-in module having through vias with non-uniform film thickness, impedance is not uniform for each through via, which increases transmission loss.

  The present invention has been made in view of the above problems. The object of the present invention is to reduce the transmission loss by using a highly versatile insulating material for sealing electronic parts, but having a fine through electrode with a desired small diameter and enabling further miniaturization. Another object of the present invention is to provide a highly reliable electronic device and a method for manufacturing the same.

  One aspect of the electronic device includes an insulating layer including a first insulating material, an electronic component provided in the insulating layer, a second insulating material provided through the insulating layer, and the second A through electrode penetrating the insulating material.

  One aspect of the method for manufacturing an electronic device includes a step of forming a first through hole in an insulating layer including a first insulating material, in which an electronic component is provided, and the first through hole is formed into a second A step of embedding with an insulating material, a step of forming a second through hole having a smaller diameter than the first through hole in the second insulating material, and a conductive material disposed in the second through hole Forming an electrode.

  According to each aspect described above, although a highly versatile insulating material is used for sealing an electronic component, a transmission loss that has a fine through electrode having a desired small diameter and enables further miniaturization is provided. Reduced and highly reliable electronic devices are realized.

It is a schematic sectional drawing which shows the manufacturing method of the electronic component built-in substrate by this embodiment in order of a process. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1, illustrating the method for manufacturing the electronic component built-in substrate according to the present embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view illustrating the method of manufacturing the electronic component built-in substrate according to the present embodiment in order of processes following FIG. 2. FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3, illustrating the method for manufacturing the electronic component built-in substrate according to the present embodiment in the order of steps. FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the electronic component built-in substrate according to the present embodiment in order of processes following FIG. 4. FIG. 6 is a schematic cross-sectional view subsequent to FIG. 5, illustrating the method for manufacturing the electronic component built-in substrate according to the present embodiment in the order of steps. It is a schematic sectional drawing for demonstrating the process of FIG. 6 in detail. FIG. 7 is a schematic cross-sectional view illustrating the manufacturing method of the electronic component built-in substrate according to the present embodiment in order of processes following FIG. 6. It is a schematic sectional drawing which shows a mode that a part of formed 1st through-hole was expanded. It is a schematic sectional drawing which shows a mode that some 1st through-holes filled with the insulating resin of the resin sheet were expanded. It is a schematic sectional drawing which shows a mode that a part of 2nd through-hole formed in this embodiment was expanded. It is a schematic sectional drawing which shows a mode that a part of penetration via formed in this embodiment was expanded. It is a schematic sectional drawing which shows the manufacturing method of the electronic component built-in board | substrate by the modification 1 of this embodiment in order of a process. FIG. 14 is a schematic cross-sectional view subsequent to FIG. 13, illustrating a method for manufacturing the electronic component built-in substrate according to Modification 1 of the embodiment in the order of steps. FIG. 15 is a schematic cross-sectional view illustrating the method of manufacturing the electronic component built-in substrate according to Modification 1 of the embodiment in order of processes subsequent to FIG. 14. FIG. 16 is a schematic cross-sectional view illustrating, in the order of steps, the method for manufacturing the electronic component built-in substrate according to the first modification of the present embodiment, following FIG. 15. FIG. 17 is a schematic cross-sectional view illustrating, in the order of steps, the method for manufacturing the electronic component built-in substrate according to the first modification of the present embodiment, following FIG. 16. FIG. 18 is a schematic cross-sectional view illustrating, in the order of steps, the method for manufacturing the electronic component built-in substrate according to the first modification of the present embodiment, following FIG. 17. FIG. 19 is a schematic cross-sectional view illustrating, in the order of steps, the method for manufacturing the electronic component built-in substrate according to the first modification of the present embodiment, following FIG. 18. FIG. 20 is a schematic cross-sectional view illustrating, in the order of steps, the method for manufacturing the electronic component built-in substrate according to the first modification of the present embodiment, following FIG. 19. FIG. 21 is a schematic cross-sectional view subsequent to FIG. 20, illustrating a method for manufacturing the electronic component built-in substrate according to Modification 1 of the embodiment in the order of steps. FIG. 22 is a schematic cross-sectional view illustrating, in the order of steps, the method for manufacturing the electronic component built-in substrate according to the first modification of the present embodiment, following FIG. 21. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the electronic component built-in board | substrate by the modification 2 of this embodiment. FIG. 24 is a schematic cross-sectional view showing the main steps of the method for manufacturing the electronic component built-in substrate according to Modification 2 of the embodiment, following FIG. 23. FIG. 25 is a schematic cross-sectional view showing main steps of the method for manufacturing the electronic component built-in substrate according to the second modification of the present embodiment, following FIG. 24. It is a schematic sectional drawing which shows a mode that some conventional penetration vias were expanded.

  Hereinafter, an electronic component built-in substrate is disclosed as an electronic device, and the configuration and manufacturing method thereof will be described in detail with reference to the drawings.

As the electronic component of the electronic component built-in substrate applied to this embodiment, it was selected from a semiconductor bare chip, a MEMS element, a sensor element, a thin chip passive component, a thin-film passive component formed on an inorganic material, and the like. There is at least one species. In this embodiment, the case where a semiconductor bare chip is used is illustrated.
1 to 8 are schematic cross-sectional views showing the method of manufacturing the electronic component built-in substrate according to the present embodiment in the order of steps. Note that some of the constituent members are different from actual sizes, thicknesses, and the like for convenience of illustration.

First, as shown to Fig.1 (a), the some 1st bare chip 2A is adhere | attached on the adhesive sheet 1b stuck on the support body 1a.
Specifically, a pressure-sensitive adhesive sheet 1b that can be peeled off by heating or irradiation with ultraviolet rays is attached to a support 1a such as a metal plate such as aluminum or a glass plate. A plurality of first bare chips 2A are mounted and fixed to the adhesive sheet 1b so that the surface of the terminal 2Aa is in contact with the surface of the adhesive sheet 1b.

Subsequently, as shown in FIG. 1B, the first bare chip 2A is embedded with a mold resin 3A.
For example, the metal plate 1 is covered with a mold resin 3A that is an insulating resin composition such as an epoxy resin, and the first bare chip 2A is embedded with the mold resin 3A. As the mold resin 3A, an insulating resin that is widely used for mold resin use and contains 80% or more of a filler, for example, a granular inorganic filler having a maximum particle size of about 50 μm to 75 μm is used here. The inorganic filler preferably contains one selected from alumina, silica, aluminum hydroxide, and aluminum nitride.

Subsequently, as shown in FIG. 1C, the back surface of the mold resin 3A is ground.
The mold resin 3A on the back surface of the mold resin 3A, that is, the back surface side of the first bare chip 2A is ground by, for example, grinding and flattened. Here, as shown in FIG. 1C, the mold resin 3A is flattened on the back surface of the first bare chip 2A so as to remain, for example, in a thickness of about 0.1 mm or more, here about 0.2 mm. The portion removed by this flattening is indicated by a broken line in FIG. You may grind and planarize until the back surface of the 1st bare chip 2A is exposed.

Subsequently, as shown in FIG. 2A, the support 1a is removed.
For example, as the pressure-sensitive adhesive sheet 1b, the pressure-sensitive adhesive sheet 1b is peeled from the mold substrate 4A by heating when it is peeled off by heating, or when it is peeled off by ultraviolet light irradiation. . At this time, the adhesive sheet 1b is removed together with the support 1a. Thereby, the terminal 2Aa existing on the surface of the first bare chip 2A is exposed on the surface of the remaining mold resin 3A (the surface exposed by removing the support 1a and the adhesive sheet 1b). The support 1a and the adhesive sheet 1b may be removed before the back surface of the mold resin 3A is ground by grinding.

  As described above, the mold substrate 4A in which the plurality of first bare chips 2A is reconstructed into a wafer state by the mold resin 3A is formed. Here, the shape of the reconstruction may be a rectangular shape instead of the round shape of the wafer state like the mold substrate 4A. If it is a round shape, it is possible to use existing semiconductor manufacturing equipment for the subsequent wiring formation process, and if it is rectangular, it is possible to use existing manufacturing equipment for printed wiring boards.

  According to the steps for forming the mold substrate 4A, it is possible to embed an electronic component including a passive component, which is relatively difficult to form, for example, a stud bump, with a mold resin. Moreover, after removing the support body 1a and the adhesive sheet 1b as needed, it is made to perform the process which grinds the back surface of the mold resin 3A by grinding following the complete curing process of the mold resin 3A or the complete curing process. Also good.

Similarly, the processes of FIG. 1A to FIG. 2A are executed for the plurality of second bare chips 2B.
Thereby, the mold substrate 4B shown in FIG. 2B is formed in the same manner as the mold substrate 4A. In the mold substrate 4B, by removing the support 1a and the pressure-sensitive adhesive sheet 1b, the surface of the remaining mold resin 3B (the surface exposed by removing the support 1a and the pressure-sensitive adhesive sheet 1b) is present on the surface of the second bare chip 2B. The terminal 2Ba is exposed.

  In FIG. 2B, the mold substrate 4B corresponds to the mold substrate 4A shown in FIG. The second bare chip 2B having the terminal 2Ba corresponds to the first bare chip 2A having the terminal 2Aa. Each second bare chip 2B on the mold substrate 4B is disposed at the same position as each first bare chip 2A on the mold substrate 4A. The mold resin 3B corresponds to the mold resin 3A, and is made of an insulating resin containing an inorganic filler, similar to the mold resin 3A.

  In the present embodiment, a mold substrate using a bare chip that does not have stud bumps is illustrated, but the present invention is not limited to this form. For example, a bare chip having a stud bump formed on a surface terminal is pressure-bonded to a support such as a metal plate using an insulating resin such as NCP (Non-Conductive Paste), and a mold substrate is formed in the same manner as described above. It can also be formed.

Subsequently, as shown in FIG. 3A, mold substrates 4A and 4B are arranged.
Specifically, the mold substrate 4A and the mold substrate 4B are made to face each other, and the first bare chips 2A of the mold substrate 4A and the second bare chips 2B of the mold substrate 4B are aligned with each other on the back surface. Arrange to face each other.

Subsequently, as shown in FIG. 3B, the mold substrates 4 </ b> A and 4 </ b> B are overlapped to form the first through hole 5.
Specifically, the mold substrates 4A and 4B with the back surfaces facing each other are overlapped. In this state, the first through hole 5 is formed in a predetermined portion between the pair of first and second bare chips 2A and 2B in the mold substrates 4A and 4B, for example, by drilling. The first through hole 5 is formed in the mold resins 3A and 3B with a diameter of 100 μm or more, for example, a diameter of 200 μm. In the first through hole 5, the formation part in the mold resin 3A is defined as an opening 5a, and the formation part in the mold resin 3B is defined as an opening 5b.

Subsequently, as shown in FIG. 4A, the resin sheet 6 is inserted and disposed between the mold substrates 4A and 4B.
Specifically, the superimposed first and second mold substrates 4A and 4B are separated from each other, and an insulating sheet, here, a resin sheet 6 is disposed between the mold substrates 4A and 4B. The mold substrates 4A and 4B are overlapped again via the resin sheet 6 so that the openings 5a and 5b are aligned. The resin sheet 6 has a thickness of about 50 μm to 150 μm, and an insulating resin made of, for example, an epoxy resin is used. The insulating resin of the resin sheet 6 contains a granular (for example, substantially spherical) inorganic filler having a smaller diameter than the inorganic filler contained in the mold resins 3A and 3B. This inorganic filler preferably contains one selected from alumina, silica, aluminum hydroxide, and aluminum nitride.

The width of the melt viscosity of the insulating resin of the resin sheet 6 used in the present embodiment is defined as follows.
As will be described later, the insulating resin of the resin sheet 6 fills the first through-hole 5 when the mold substrates 4A and 4B are bonded together. For this reason, the insulating resin is required to have an appropriate melt viscosity. When the melt viscosity of the insulating resin is too low, the fluidity of the insulating resin is high and the state in which the first through holes 5 are filled cannot be maintained. In order to maintain the state in which the first through hole 5 is filled, it is necessary that the minimum melt viscosity of the insulating resin is, for example, 800 P (poise) or more as a CGS unit system at a temperature of 100 ° C. to 200 ° C. On the other hand, if the melt viscosity of the insulating resin is too high, the fluidity of the insulating resin is low and the filling of the first through holes 5 with the insulating resin is incomplete. In addition, when a void is generated in the insulating resin in the first through-hole 5, there is a concern that the void is not easily removed if the fluidity of the insulating resin is low. In order to reliably fill the inside of the first through-hole 5 and easily remove the generated void, the maximum melt viscosity of the insulating resin needs to be 3000 P or less at a temperature of 100 ° C. to 200 ° C.

  From the above, in this embodiment, the insulating resin (containing the inorganic filler) of the resin sheet 6 is an insulating resin whose melt viscosity is a value in the range of 800P to 3000P, for example, about 2000P at a temperature of 100 ° C to 200 ° C. Resin is used. Thereby, even if a void occurs in the insulating resin in the first through hole 5, it can be easily removed, and good filling properties in the first through hole 5 can be obtained by the insulating resin.

The size and content of the inorganic filler contained in the insulating resin of the resin sheet 6 used in the present embodiment are defined as follows.
The inorganic filler contained in the insulating resin of the resin sheet 6 is substantially equal to the hole diameter of the second through-hole when the second through-hole having a smaller diameter than the first through-hole 5 is formed, as will be described later. The particle size is required to be small enough not to fluctuate. For that purpose, the diameter of the said inorganic filler needs to be about 25 micrometers or less. On the other hand, an inorganic filler having a very small diameter is not inexpensive and has a problem of increasing manufacturing costs. In order to keep the manufacturing cost low, it is necessary to use an inorganic filler having a diameter of about 1 μm or more.

  In addition, since the inorganic filler contained in the insulating resin of the resin sheet 6 is in contact with the mold substrates 4A and 4B, it is required to suppress a difference in thermal expansion coefficient between the mold resins 3A and 3B and the insulating resin. When this difference in coefficient of thermal expansion is large, there is a concern that the resin sheet 6 may crack or peel off. In order to suppress the difference in thermal expansion coefficient, it is necessary that the content of the inorganic filler in the insulating resin is 20% by weight or more. On the other hand, if the content of the inorganic filler is large, the melt viscosity of the insulating resin increases, and there is a concern that the melt viscosity exceeds 3000P at a temperature of 100 ° C to 200 ° C. In order to moderately suppress the melt viscosity of the insulating resin, the content of the inorganic filler in the insulating resin is required to be 50% by weight or less.

  As mentioned above, in this embodiment, as an inorganic filler which the insulating resin of the resin sheet 6 contains, the diameter is a value within the range of about 1 μm to 25 μm, the average particle size is, for example, about 2 μm, and the content is 20 weight % To 50% by weight, for example, about 40% by weight is used. As a result, the expected second through-hole is formed at a low cost and does not substantially change the diameter of the second through-hole, and the inside of the first through-hole 5 made of insulating resin is good. Can be obtained. Further, when a void is generated in the insulating resin in the first through hole 5, the concern that the void cannot be removed is eliminated.

  The insulating resin of the resin sheet 6 is not suitable as a mold resin for sealing the first bare chip 2A. In the insulating resin of the resin sheet 6, the particle size of the inorganic filler contained is small, and a large amount of small-diameter inorganic filler that is not as inexpensive as the large-diameter inorganic filler (such as exceeding 80% by weight in the insulating resin) is used. This is not particularly preferable from the viewpoint of manufacturing cost. Therefore, if an insulating resin containing a small-diameter inorganic filler is used as a mold resin for sealing the first bare chip 2A, the difference in thermal expansion coefficient from the substrate of the first bare chip 2A becomes large, and cracks or peeling occur. Is concerned. For sealing the first bare chip 2A, an insulating resin having a large particle size of the inorganic filler contained and a large proportion of the inorganic filler in the resin is suitable.

Subsequently, as illustrated in FIG. 4B, the mold substrates 4 </ b> A and 4 </ b> B are bonded together with the resin sheet 6, and the first through hole 5 is filled with the insulating resin of the resin sheet 6.
Specifically, the mold substrates 4A and 4B sandwiching the resin sheet 6 are pressed while being heated. For example, using a device such as a vacuum press, vacuum laminate, normal pressure press, or normal pressure laminate, the resin sheet 6 is cured by heating and pressing at a temperature of about 100 ° C. to 230 ° C. At this time, the mold substrate 4A and the mold substrate 4B are securely bonded to each other by pressing the mold substrates 4A and 4B, and the insulating resin of the resin sheet 6 enters the first through-hole 5 and is satisfactorily filled. . In this state, the insulating resin of the resin sheet 6 is cured, and the mold substrates 4A and 4B are bonded together. A structure in which the mold substrates 4A and 4B are bonded together with the resin sheet 6 is referred to as a bonded mold substrate 4. Here, in order not to cause a void in the insulating resin in the first through hole 5, it is preferable to use a vacuum press or a vacuum laminate for the pressure contact of the mold substrates 4A and 4B.

  In the present embodiment, by using the resin sheet 6, the process of bonding the mold substrates 4 </ b> A and 4 </ b> B and the process of filling the first through hole 5 with the insulating resin of the resin sheet 6 are performed simultaneously. Thereby, although the number of processes is reduced, the mold substrates 4A and 4B can be securely bonded and the first through hole 5 can be reliably filled with the insulating resin.

Subsequently, as illustrated in FIG. 5A, the second through hole 7 is formed in the insulating resin of the resin sheet 6 that fills the first through hole 5.
Specifically, the insulating resin of the resin sheet 6 filling the first through hole 5 of the bonded mold substrate 4 has a smaller diameter than the first through hole 5, for example, about 50 μm to 150 μm, and here, for example, a diameter of about 100 μm. The second through-hole 7 is formed. The second through-hole 7 is formed in a shape along the first through-hole 5 in the first through-hole 5. Drilling can be used to form the second through-hole 7, but laser processing such as a carbon dioxide laser, UV-YAG laser, or excimer laser is used to form a through-hole having a diameter smaller than about 100 μm. It is preferable to use it.

Subsequently, as shown in FIG. 5B, a conductive layer 8 a and a conductive resin 8 b are formed in the second through hole 7.
Specifically, a plating seed layer is formed on the inner wall surface of the second through-hole 7 by a method such as electroless plating, sputtering, or CVD, followed by electroplating of a conductive material such as Cu. As a result, a conductive layer 8a is formed in the second through hole 7 so as to cover the inner wall surface and partially protrude from the surfaces of the mold substrates 4A and 4B.
A predetermined conductive resin 8b is filled in a void portion of the second through hole 7 in which the conductive layer 8a is formed on the inner wall surface. Instead of the conductive resin 8b, it may be filled with an insulating resin. In particular, the above-described void portion may be left without filling with resin or the like. It is also preferable to form the conductive layer 8 a so as to fill not only the inner wall surface of the second through-hole 7 but also the second through-hole 7.
As described above, the through via 8 formed by covering the inner wall surface of the second through hole 7 with the conductive layer 8a and filling the conductive resin 8b is formed.

  Here, the situation where the through vias 8 are formed in the mold substrates 4A and 4B will be described in detail with reference to FIGS. FIG. 9 shows a state in which a part of the formed first through hole 5 is enlarged. FIG. 10 shows a state in which a part of the first through hole 5 filled with the epoxy resin of the resin sheet 6 is enlarged. FIG. 11 shows a state in which a part of the formed second through hole 7 is enlarged. FIG. 12 shows a state in which a part of the formed through via 8 is enlarged.

  As described above, the epoxy resin of the mold resin 3A (3B) contains the large-diameter inorganic filler 9a. Therefore, for example, as shown in FIG. 9, the first through hole 5 has a shape in which the inner wall surface has an expanded portion 5 c and a reduced portion 5 d. The extended portion 5c is a portion reflecting the inorganic filler 9a existing at the position where the first through hole 5 of the mold resin 3A (3B) is formed, and the diameter of the first through hole 5 is locally increased. Expand. The reduced portion 5d is a portion from which the inorganic filler 9a remaining at the position where the first through hole 5 is formed protrudes, and locally reduces the diameter of the first through hole 5.

  As described above, the epoxy resin of the resin sheet 6 contains the inorganic filler 9b having a smaller diameter than the inorganic filler 9a, for example, an average particle diameter of about 2 μm. Therefore, as shown in FIG. 10, the insulating resin of the resin sheet 6 enters the first through hole 5 by the pressure contact of the mold substrates 4A and 4B with the resin sheet 6 interposed therebetween, and the expanded portion 5c and the reduced portion 5d The inside of the first through hole 5 including the periphery of is reliably filled.

  As shown in FIG. 11, the second through hole 7 is formed in the insulating resin of the resin sheet 6 filling the inside of the first through hole 5, and the first through hole 5 has a smaller diameter than the first through hole 5. Formed along. In the insulating resin of the resin sheet 6, the contained inorganic filler 9 b has a smaller diameter than the inorganic filler 9 a, and has a particle size that is small enough not to affect the hole diameter of the second through-hole 7 due to its presence. As described above, in the small-diameter inorganic filler 9b, the second through-hole 7 is not formed with an expanded portion or a reduced portion having a size that is evaluated to change the hole diameter. The desired uniform pore diameter is formed.

  As shown in FIG. 12, in the through via 8, the conductive layer 8 a covers the inner wall surface of the second through hole 7 that is smooth and has a uniform diameter, so that there is no occurrence of a non-uniform thickness, and as a whole It is formed to the desired uniform thickness. Therefore, there is no fear of disconnection in the conductive layer 8a of the through via 8, and the impedance is uniform for each through via 8 and transmission loss is reduced.

  The through via described above is applied when the first insulating layer used when embedding an electronic component such as a bare chip cannot directly form a desired small diameter through hole. Is done. In the present embodiment, it is assumed that a highly versatile and inexpensive insulating resin that contains a large amount of large-diameter filler and is suitable for sealing electronic components is used as the first insulating layer. In this case, first, a first through hole is formed in the first insulating layer, and the first through hole is filled with a second insulating layer capable of forming a desired small diameter through hole. In this embodiment, the 2nd insulating layer contains the filler of a particle size very small compared with the filler which the 1st insulating layer contains. A second through hole having a smaller diameter than the first through hole is formed in the second insulating layer. Even if the small-diameter filler is present on the inner wall surface of the second through-hole, it does not substantially change the diameter of the second through-hole. Thus, by using the second insulating layer together with the first insulating layer, the second through hole can be indirectly formed in the first insulating layer with a uniform predetermined diameter. The desired fine through electrode can be formed in the two through holes.

  Subsequently, steps after the through via 8 is formed will be described. As shown in FIG. 6, multilayer wiring layers 11 and 12 are formed on the front and back surfaces of the bonded mold substrate 4. In FIG. 6, for convenience of illustration, the multilayer wiring layers 11 and 12 are simplified.

The process of FIG. 6 for forming the multilayer wiring layer 11 on the surface of the bonded mold substrate 4 will be described in detail with reference to FIG.
As shown in FIG. 7A, a photosensitive resin such as a photosensitive epoxy resin, a photosensitive polybenzoxazole resin, or a photosensitive polyimide resin is formed on the surface of the bonded mold substrate 4 (the surface of the mold substrate 4A). Is applied to form the insulating layer 13. The insulating layer 13 is developed and cured, and plasma treatment is performed as necessary. As a result, the insulating layer 13 is formed with openings 13a exposing the terminals 2Aa of the first bare chip 2A and part of the through vias 8 respectively.

  As shown in FIG. 7B, a close contact underlayer 14 and a Cu seed layer 15 are sequentially formed on the insulating layer 13 by sputtering so as to cover the bottom and side surfaces of the opening 13a. Titanium (Ti), chromium (Cr), or the like is used as the material for the adhesion base layer 14.

  As shown in FIG. 7C, a resist is applied on the seed layer 15, and the resist is processed by lithography to form a resist mask 16 having an opening 16a that exposes a portion corresponding to the opening 13a on the seed layer 15. Form. Cu electroplating is performed using the seed layer 15. Thereby, the opening 16a of the resist mask 16 is filled with Cu17.

  As shown in FIG. 7D, after the resist mask 16 is removed by a stripping solution treatment or the like, the adhesion base layer 14 and the seed layer 15 remaining under the resist mask 16 are removed. For the removal, wet etching or dry etching may be used. After removing the adhesion base layer 14 and the seed layer 15, a predetermined surface treatment or the like is added as necessary for the purpose of improving the adhesion of the copper wiring. As a result, the first layer 21 having the wiring 21a electrically connected to the terminal 2Aa or the through via 8 through the adhesion base layer 14 is formed.

  Steps similar to those shown in FIGS. 7A to 7D are performed to form the desired number of layers. In the present embodiment, a second layer 22 having a via 22a electrically connected to the wiring 21a of the first layer 21, and a third layer having a wiring 23a electrically connected to the via 22a of the second layer 22 are used. The case where 23 is formed is illustrated. As described above, the multilayer wiring layer 11 is formed on the surface of the bonded mold substrate 4 (surface of the mold substrate 4A).

  Through the same process as the multilayer wiring layer 11, the back surface of the bonded mold substrate 4 (the surface of the mold substrate 4B) is electrically connected to the terminals 2Ba and the through vias 8 formed on the surface of the second bare chip 2B. A multilayer wiring layer 12 is formed.

Here, in the multilayer wiring layer 11 and the multilayer wiring layer 12, it is preferable to form the same number of layers and the same thickness from the viewpoint of reducing warpage of the bonded mold substrate 4.
In addition, in the multilayer wiring layer 11 and the multilayer wiring layer 12, each layer may be alternately formed. For example, after the first layer 21 is formed on the surface of the bonded mold substrate 4, the first layer 21 is formed on the back surface of the bonded mold substrate 4, and the second layer 22 and the third layer 23 are sequentially formed on the front surface and the back surface. Form. In this case, in order to prevent damage on one side, a protective film covering each layer may be formed sequentially. By forming each layer alternately on the front surface and the back surface, the occurrence of warpage of the bonded mold substrate 4 is further suppressed.

  Subsequently, for example, a solder resist is formed on the front and back surfaces of the bonded mold substrate 4, and nickel and gold are processed on the opened wiring surface. Thereby, as shown in FIG. 6, the electronic component built-in wafer 10 provided with the multilayer wiring layers 11 and 12 on the front surface and the back surface of the bonded mold substrate 4 is formed.

  Thereafter, the electronic component built-in wafer 10 is cut into individual pieces. As described above, as shown in FIG. 8, the electronic component incorporating the pair of first and second bare chips 2 </ b> A and 2 </ b> B facing each other on the back surface together with the multilayer wiring layers 11 and 12 electrically connected by the through via 8. A built-in substrate 20 is formed. A plurality of pairs of first and second bare chips 2A and 2B may be built in the electronic component built-in substrate.

As described above, according to the present embodiment, although the highly versatile mold resins 3A and 3B are used for sealing the first and second bare chips 2A and 2B, the minute penetration with the desired small diameter is used. The via 8 can be reliably formed. Thereby, the highly reliable electronic component built-in substrate 20 with reduced transmission loss that enables further miniaturization is realized.
Moreover, since the multilayer wiring layers 11 and 12 are formed on both surfaces of the reconstructed bonded mold substrate 4, the amount of warpage of the electronic component built-in wafer 10 is reduced, and the electronic component built-in substrate 20 is further reduced in thickness and made finer. Is possible.

-Modification-
Hereinafter, various modifications of the present embodiment will be disclosed.

(Modification 1)
In this example, the configuration and manufacturing method of the electronic component built-in substrate are disclosed in the same manner as in this embodiment, but are different in that the through via is formed. In addition, about the structural member etc. corresponding to this embodiment, the same code | symbol is attached | subjected.
13 to 22 are schematic cross-sectional views illustrating the method of manufacturing the electronic component built-in substrate according to the first modification of the present embodiment in the order of steps. Note that some of the constituent members are different from actual sizes, thicknesses, and the like for convenience of illustration.

  First, the same processes as in FIGS. 1A to 2B in the present embodiment are performed. Thereby, the mold substrates 4A and 4B shown in FIGS. 2A and 2B are formed.

  Subsequently, as shown in FIG. 13A, a multilayer wiring layer 31 is formed on the surface of the mold substrate 4A. Similarly, as shown in FIG. 13B, a multilayer wiring layer 32 is formed on the surface of the mold substrate 4B. 13A and 13B, for convenience of illustration, the multilayer wiring layers 31 and 32 are shown in a simplified manner.

  The process of FIG. 13A for forming the multilayer wiring layer 31 on the surface of the mold substrate 4A will be described in detail with reference to FIG. The process of FIG. 13B for forming the multilayer wiring layer 32 on the surface of the mold substrate 4B is the same.

  As shown in FIG. 14A, the insulating layer 13 is applied to the surface of the mold substrate 4A by applying a photosensitive resin such as a photosensitive epoxy resin, a photosensitive polybenzoxazole resin, or a photosensitive polyimide resin. Form. The insulating layer 13 is developed and cured, and plasma treatment is performed as necessary. As a result, an opening 13a is formed in the insulating layer 13 to expose the terminal 2Aa of the first bare chip 2A.

  As shown in FIG. 14B, an adhesion base layer 14 and a Cu seed layer 15 are sequentially formed on the insulating layer 13 by sputtering so as to cover the bottom surface and side surfaces of the opening 13a. Titanium (Ti), chromium (Cr), or the like is used as the material for the adhesion base layer 14.

  As shown in FIG. 14C, a resist is applied on the seed layer 15, and the resist is processed by lithography to form a resist mask 16 having an opening 16a that exposes a portion corresponding to the opening 13a on the seed layer 15. Form. Cu electroplating is performed using the seed layer 15. Thereby, the opening 16a of the resist mask 16 is filled with Cu17.

  As shown in FIG. 14D, after the resist mask 16 is removed by a stripping solution treatment or the like, the adhesion base layer 14 and the seed layer 15 remaining under the resist mask 16 are removed. For the removal, wet etching or dry etching may be used. After removing the adhesion base layer 14 and the seed layer 15, a predetermined surface treatment or the like is added as necessary for the purpose of improving the adhesion of the copper wiring. In this way, the first layer 21 having the wiring 21a electrically connected to the terminal 2Aa through the adhesion base layer 14 is formed.

  Steps similar to those shown in FIGS. 14A to 14D are executed to form the desired number of layers. In the present embodiment, a second layer 22 having a via 22a electrically connected to the wiring 21a of the first layer 21, and a third layer having a wiring 23a electrically connected to the via 22a of the second layer 22 are used. The case where 23 is formed is illustrated. Thus, the multilayer wiring layer 31 is formed on the surface of the mold substrate 4A.

  By a process similar to that of the multilayer wiring layer 11, a multilayer wiring layer 32 is formed on the surface of the mold substrate 4B and is electrically connected to the terminals 2Ba formed on the surface of the second bare chip 2B.

Subsequently, as shown in FIG. 15, mold substrates 4A and 4B are arranged.
Specifically, the back surface of the mold substrate 4A having the multilayer wiring layer 31 formed on the surface and the mold substrate 4B having the multilayer wiring layer 32 formed on the surface are opposed to each other. At this time, the first bare chips 2A of the mold substrate 4A and the second bare chips 2B of the mold substrate 4B are aligned so as to face each other on the back surface.

Subsequently, as shown in FIG. 16, the mold substrates 4 </ b> A and 4 </ b> B are overlapped to form the first through hole 33.
Specifically, the mold substrates 4A and 4B with the back surfaces facing each other are overlapped. In this state, the first through hole 33 is formed in a predetermined portion between the pair of first and second bare chips 2A and 2B on the mold substrates 4A and 4B on which the multilayer wiring layers 31 and 32 are formed, for example, by drilling. Form. The first through hole 33 has a diameter of 100 μm or more, for example, a diameter of 200 μm, and is formed so as to penetrate the multilayer wiring layer 31, the mold resins 3A and 3B, and the multilayer wiring layer 32. In the first through-hole 33, the formation part in the multilayer wiring layer 31 and the mold resin 3A is defined as an opening 33a, and the formation part in the mold resin 3B and the multilayer wiring layer 32 is defined as an opening 33b.

Then, as shown in FIG. 17, the resin sheet 6 is inserted and arranged between the mold substrates 4A and 4B.
Specifically, the superimposed first and second mold substrates 4A and 4B are separated from each other, and an insulating sheet, here, a resin sheet 6 is disposed between the mold substrates 4A and 4B. The mold substrates 4A and 4B are overlapped again via the resin sheet 6 so that the openings 33a and 33b are aligned. The resin sheet 6 has a thickness of about 50 μm to 150 μm, and an insulating resin made of, for example, an epoxy resin is used. The insulating resin of the resin sheet 6 contains a granular (for example, substantially spherical) inorganic filler having a smaller diameter than the inorganic filler contained in the mold resins 3A and 3B. This inorganic filler preferably contains one selected from alumina, silica, aluminum hydroxide, and aluminum nitride.

The insulating resin of the resin sheet 6 has a melt viscosity of a value in the range of 800 P to 3000 P, for example, about 2000 P, at a temperature of 100 ° C. to 200 ° C., as in this embodiment.
In addition, the inorganic filler contained in the insulating resin of the resin sheet 6 has a value in the range of about 1 μm to 25 μm and an average particle size of, for example, about 2 μm, and a content rate of 20 as in the present embodiment. A value within the range of 50% by weight to 50% by weight, for example, about 40% by weight.

Subsequently, as shown in FIG. 18, the mold substrates 4 </ b> A and 4 </ b> B are bonded together with the resin sheet 6, and the first through hole 33 is filled with the insulating resin of the resin sheet 6.
Specifically, the mold substrates 4A and 4B sandwiching the resin sheet 6 are pressed while being heated. For example, using a device such as a vacuum press, vacuum laminate, normal pressure press, or normal pressure laminate, the resin sheet 6 is cured by heating and pressing at a temperature of about 100 ° C. to 230 ° C. At this time, the mold substrate 4A and the mold substrate 4B are securely bonded to each other by pressing the mold substrates 4A and 4B, and the insulating resin of the resin sheet 6 penetrates into the first through-hole 33 and fills well. . In this state, the insulating resin of the resin sheet 6 is cured, and the mold substrates 4A and 4B are bonded together. A structure in which the mold substrates 4 A and 4 B having the multilayer wiring layers 31 and 32 are bonded together with the resin sheet 6 is referred to as a bonded mold substrate 30. Here, in order not to cause a void in the insulating resin in the first through-hole 33, it is preferable to use a vacuum press or a vacuum laminate for the pressure contact of the mold substrates 4A and 4B.

Subsequently, as shown in FIG. 19, the second through hole 34 is formed in the insulating resin of the resin sheet 6 filling the first through hole 33.
Specifically, the insulating resin of the resin sheet 6 filling the first through hole 33 of the bonded mold substrate 30 has a smaller diameter than the first through hole 33, for example, about 50 μm to 150 μm, and here, for example, a diameter of about 100 μm. The second through hole 34 is formed. The second through hole 34 is formed in a shape along the first through hole 33 in the first through hole 33. Drilling can be used to form the second through-hole 34. To form a through-hole having a diameter smaller than about 100 μm, laser processing such as a carbon dioxide laser, UV-YAG laser, or excimer laser is used. It is preferable to use it.

Subsequently, as shown in FIG. 20, a conductive layer 35 a and a conductive resin 35 b are formed in the second through hole 34.
Specifically, a plating seed layer is formed on the inner wall surface of the second through-hole 34 by a method such as electroless plating, sputtering, or CVD, followed by electroplating of a conductive material such as Cu. As a result, a conductive layer 35 a is formed in the second through-hole 34 so as to cover the inner wall surface and partially protrude from each surface of the multilayer wiring layers 31 and 32.
A predetermined conductive resin 35b is filled in a void portion of the second through hole 34 in which the conductive layer 35a is formed on the inner wall surface. Instead of the conductive resin 35b, it may be filled with an insulating resin. In particular, the above-described void portion may be left without filling with resin or the like. It is also preferable to form the conductive layer 35 a so as to fill not only the inner wall surface of the second through hole 34 but also the second through hole 34.
As described above, the through via 35 is formed by covering the inner wall surface of the second through hole 34 with the conductive layer 35a and filling the conductive resin 35b.

Subsequently, as shown in FIG. 21, a fourth layer 24 of wiring is formed.
For the multilayer wiring layer 31, the same steps as in FIGS. 7A to 7D in the present embodiment are performed. As a result, the fourth layer 24 having the wiring 24 a electrically connected to the through via 35 via the adhesion base layer is formed on the multilayer wiring layer 31.
For the multilayer wiring layer 32, the same steps as in FIGS. 7A to 7D in the present embodiment are executed. As a result, the fourth layer 24 having the wiring 24 a electrically connected to the through via 35 via the adhesion base layer is formed on the multilayer wiring layer 32.
Thus, the electronic component built-in wafer 40 is formed.

  Thereafter, the electronic component built-in wafer 40 is cut into individual pieces. As described above, as shown in FIG. 22, a pair of first and second bare chips 2A and 2B facing each other on the back side is built in, and an electronic component built-in substrate 50 having a through via 35 in the bonded mold substrate 30 is formed. The A plurality of pairs of first and second bare chips 2A and 2B may be built in the electronic component built-in substrate.

  As described above, according to the present example, although the highly versatile mold resins 3A and 3B are used for sealing the first and second bare chips 2A and 2B, a fine through via having an intended small diameter is used. 35 can be reliably formed. As a result, a highly reliable electronic component-embedded substrate 50 with reduced transmission loss that enables further miniaturization is realized.

(Modification 2)
In this example, the configuration and manufacturing method of the electronic component built-in substrate are disclosed in the same manner as in this embodiment, but are different in that the through via is formed. In addition, about the structural member etc. corresponding to this embodiment, the same code | symbol is attached | subjected.
23 to 25 are schematic cross-sectional views illustrating main processes of the method for manufacturing the electronic component built-in substrate according to the second modification of the present embodiment. Note that some of the constituent members are different from actual sizes, thicknesses, and the like for convenience of illustration.

  In this example, an electronic component built-in substrate is obtained through the same steps as in FIGS. 1 to 8 of the first embodiment. However, the first is that a resin sheet made of an insulating resin not containing a small-diameter inorganic filler is used. It is different from the embodiment.

  The situation where the through vias 8 are formed in the mold substrates 4A and 4B will be described in detail with reference to FIGS. FIG. 23 shows a state in which a part of the first through hole 5 filled with the epoxy resin of the resin sheet 6 is enlarged. FIG. 24 shows a state in which a part of the formed second through hole 7 is enlarged. FIG. 25 shows a state in which a part of the formed through via 8 is enlarged.

  As described above, the epoxy resin of the mold resin 3A (3B) contains the large-diameter inorganic filler 9a. Therefore, for example, as in FIG. 9 of the first embodiment, the first through-hole 5 has a shape in which the inner wall surface has an expanded portion 5c and a reduced portion 5d. The extended portion 5c is a portion reflecting the inorganic filler 9a existing at the position where the first through hole 5 of the mold resin 3A (3B) is formed, and the diameter of the first through hole 5 is locally increased. Expand. The reduced portion 5d is a portion from which the inorganic filler 9a remaining at the position where the first through hole 5 is formed protrudes, and locally reduces the diameter of the first through hole 5.

  The epoxy resin of the resin sheet 6 does not contain an inorganic filler. Therefore, as shown in FIG. 23, the insulating resin of the resin sheet 6 penetrates into the first through-hole 5 due to the pressure contact of the mold substrates 4A and 4B with the resin sheet 6 interposed therebetween, and the expanded portion 5c and the reduced portion 5d. The inside of the first through hole 5 including the periphery of is reliably filled.

  As shown in FIG. 24, the second through hole 7 is formed in the insulating resin of the resin sheet 6 filling the inside of the first through hole 5, and the first through hole 5 has a smaller diameter than the first through hole 5. Formed along. Since the insulating resin of the resin sheet 6 does not contain an inorganic filler, the second through-hole 7 is not formed with an expanded portion or a reduced portion having a size that is evaluated to change the hole diameter. The through-holes 7 are formed to have a uniform hole diameter as a whole.

  As shown in FIG. 25, in the through via 8, the conductive layer 8 a covers the inner wall surface of the second through hole 7 that is smooth and has a uniform diameter. It is formed to the desired uniform thickness. Therefore, there is no fear of disconnection in the conductive layer 8a of the through via 8, and the impedance is uniform for each through via 8 and transmission loss is reduced.

As described above, according to the present example, although the highly versatile mold resins 3A and 3B are used for sealing the first and second bare chips 2A and 2B, a fine through via having an intended small diameter is used. 8 can be reliably formed. Thereby, the highly reliable electronic component built-in substrate 20 with reduced transmission loss that enables further miniaturization is realized.
Moreover, since the multilayer wiring layers 11 and 12 are formed on both surfaces of the reconstructed bonded mold substrate 4, the amount of warpage of the electronic component built-in wafer 10 is reduced, and the electronic component built-in substrate 20 is further reduced in thickness and made finer. Is possible.

  Hereinafter, specific examples of the electronic component built-in substrate and the manufacturing method thereof according to the present embodiment will be described.

Example 1
10 bare silicon chips with a size of 5 mm x 5 mm and a thickness of 0.2 mm are attached to a 0.15 mm thick φ100 mm stainless steel metal plate with a heat release type adhesive sheet attached at regular intervals. It was made to adhere on the terminal side.
An epoxy resin containing an inorganic filler having a maximum particle size of about 50 μm to 75 μm was used as the mold resin, and the back and side surfaces of the bare chip were embedded with the mold resin. The mold resin was cured to produce first and second mold substrates having a thickness of 0.35 mm and a diameter of 100 mm.

  It heated to 180 degreeC and the stainless steel metal plate which affixed the adhesive sheet was removed. At this time, it was confirmed that the terminal surfaces of the bare chips were exposed in the first and second mold substrates. After removing the stainless steel metal plate, heat treatment was performed at 210 ° C. for 1 hour in order to completely cure the mold resin.

The first and second mold substrates were overlapped so that the surfaces (surfaces from which the terminals were exposed) were outside, and a first through hole having a diameter of 200 μm was formed by drilling. After that, each mold substrate is overlapped again with a resin sheet having a thickness of 70 μm in a semi-cured state, heated at 180 ° C. for 60 minutes by a vacuum press, and the first and second mold substrates are attached to the resin sheet. Combined. At the same time, the resin of the resin sheet was filled in the first through hole of the mold substrate to produce a bonded mold substrate. The resin sheet was made of an epoxy resin containing 40 wt% of an inorganic filler having a melt viscosity of 800 P to 3000 P at a temperature of 100 ° C. to 200 ° C. and an average particle diameter of about 2 μm.
A second through via with a diameter of 100 μm is formed on the epoxy resin filled in the first through hole with a carbon dioxide gas laser, and the surface residue is washed, and then a Cu layer is formed using electroless copper plating and electrolytic plating. And through-via.

  A photosensitive epoxy varnish for spin coating was applied to the surface of the bonded mold substrate (the surface on which the terminals of the first mold substrate were exposed), and pre-baking, exposure, development, curing, and oxygen plasma treatment were sequentially performed. Thus, an insulating layer having a film thickness of 8 μm and an opening of φ30 μm exposing the terminal of the first bare chip and an opening of φ100 μm exposing the end of the through via was formed.

  Ti and Cu were formed into a thickness of 0.1 μm and 0.3 μm by a sputtering method to form an adhesion underlayer and a seed layer. Thereafter, a resist mask having an opening exposing a portion corresponding to the opening on the seed layer was formed, and Cu electroplating was performed using the previously formed seed layer. After electroplating, the resist mask was removed, and the seed layer remaining under the resist mask was removed by wet etching and dry etching. Thereby, the first layer of the multilayer wiring layer was formed on the surface of the mold substrate.

  The surface of the bonded mold substrate is protected with a protective film, and the process from the application of the photosensitive epoxy varnish to the etching removal of the seed layer is repeated twice on the back surface (the surface on which the terminals of the second mold substrate are exposed). Thus, the first layer and the second layer were formed. As described above, a multilayer wiring layer formed by laminating the first layer and the second layer was formed on the back surface of the bonded mold substrate.

  The protective film on the surface of the bonded mold substrate is peeled off, the back surface is protected with a protective film, and the process from the application of the photosensitive epoxy varnish to the etching removal of the seed layer is performed on the surface of the bonded mold substrate. Two layers were formed. As described above, a multilayer wiring layer formed by laminating the first layer and the second layer was formed on the surface of the bonded mold substrate.

  After the protective film on the back surface of the mold substrate was peeled off, a solder resist was formed on both surfaces, and the surface of each multilayer wiring layer was treated with nickel (Ni) and gold (Au). As described above, the electronic component built-in wafer in which the multilayer wiring layers are respectively arranged on the front surface and the back surface of the mold substrate was formed. Then, the electronic component built-in wafer was cut into individual pieces to complete individual electronic component built-in substrates.

(Example 2)
15 silicon-germanium (SiGe) bare chips with a size of 5 mm x 5 mm and a thickness of 0.3 mm are attached at equal intervals on a stainless steel metal plate with a thickness of 0.15 mm and φ100 mm, to which a heat-peeling type adhesive sheet is attached. It was made to adhere on the terminal surface side of the bare chip.
An epoxy resin containing an inorganic filler having a maximum particle size of about 50 μm to 75 μm was used as the mold resin, and the back and side surfaces of the bare chip were embedded with the mold resin. The mold resin was cured to produce first and second mold substrates having a thickness of 0.3 mm and a diameter of 100 mm.
It heated to 180 degreeC and the stainless steel metal plate which affixed the adhesive sheet was removed. At this time, it was confirmed that the terminal surfaces of the bare chips were exposed in the first and second mold substrates. After removing the stainless steel metal plate, heat treatment was performed at 210 ° C. for 1 hour in order to completely cure the mold resin.

The first and second mold substrates were overlapped so that the surfaces (terminals were exposed) were on the outside, and a first through hole having a diameter of 150 μm was formed by drilling. Thereafter, each mold substrate was laminated again with a 50 μm-thick resin sheet in a semi-cured state, and laminated at 150 ° C. for 10 minutes by vacuum lamination. The epoxy resin was cured by heating at 190 ° C. for 1 hour, and the first and second mold substrates were bonded together with a resin sheet. At the same time, the resin of the resin sheet was filled in the first through hole of the mold substrate to produce a bonded mold substrate. The resin sheet was made of an epoxy resin containing 40 wt% of an inorganic filler having a melt viscosity of 800 P to 3000 P at a temperature of 100 ° C. to 200 ° C. and an average particle diameter of about 2 μm.
A second through via having a diameter of 70 μm is formed in the epoxy resin filled in the first through hole with a UV-YAG laser, and the surface residue is washed. Then, a Cu layer is formed by using electroless copper plating and electrolytic plating. The through via was formed.

  A photosensitive polybenzoxazole varnish for spin coating was applied to the surface of the bonded mold substrate (the surface from which the terminals of the first mold substrate were exposed), and pre-baking, exposure, development, curing, and oxygen plasma treatment were sequentially performed. . Thus, an insulating layer having a film thickness of 6 μm and an opening of φ30 μm exposing the stud bump of the first bare chip and an opening of φ50 μm exposing the end of the through via was formed.

  Ti and Cu were formed into a thickness of 0.1 μm and 0.2 μm by a sputtering method to form an adhesion underlayer and a seed layer. Thereafter, a resist mask having an opening exposing a portion corresponding to the opening on the seed layer was formed, and Cu electroplating was performed using the previously formed seed layer. After electroplating, the resist mask was removed, and the seed layer remaining under the resist mask was removed by wet etching and dry etching. As described above, the first layer of the multilayer wiring layer was formed on the surface of the mold substrate.

  The process from the application of the photosensitive polybenzoxazole varnish to the etching removal of the seed layer is performed on the back surface (the surface on which the terminals of the second mold substrate are exposed) by protecting the surface of the bonded mold substrate with a protective film. Repeatedly, a first layer and a second layer were formed. As described above, a multilayer wiring layer formed by laminating the first layer and the second layer was formed on the back surface of the bonded mold substrate.

  The protective film on the surface of the bonded mold substrate is peeled off, the back surface is protected with a protective film, and the process from application of photosensitive polybenzoxazole varnish to etching removal of the seed layer is performed on the surface of the bonded mold substrate. A second layer was formed. As described above, a multilayer wiring layer formed by laminating the first layer and the second layer was formed on the surface of the bonded mold substrate.

  After the protective film on the back surface of the mold substrate was peeled off, a solder resist was formed on both surfaces, and the surface of each multilayer wiring layer was treated with Ni and Au. As described above, the electronic component built-in wafer in which the multilayer wiring layers are respectively arranged on the front surface and the back surface of the mold substrate was formed. Then, the electronic component built-in wafer was cut into individual pieces to complete individual electronic component built-in substrates.

(Example 3)
Ten bare silicon (Si) chips each having a size of 6 mm × 6 mm and a thickness of 0.2 mm and having Cu stud bumps are bonded onto an aluminum metal plate having a thickness of 0.3 mm and a diameter of 100 mm by pressure welding using NCP. Bonded to the interval.
An epoxy resin containing an inorganic filler having a maximum particle size of about 50 μm to 75 μm was used as the mold resin, and the back and side surfaces of the bare chip were embedded with the mold resin. The mold resin was cured to produce first and second mold substrates having a thickness of 0.3 mm and a diameter of 100 mm.
The metal plate was removed by etching using hydrochloric acid. At this time, it was confirmed that the exposed stud bump was not etched.

The first and second mold substrates were overlapped so that the surfaces (exposed stud bumps) were outside, and a first through hole having a diameter of 200 μm was formed by drilling. After that, each mold substrate is overlapped again with a resin sheet having a thickness of 70 μm in a semi-cured state, heated at 180 ° C. for 60 minutes by a vacuum press, and the first and second mold substrates are attached to the resin sheet. Combined. At the same time, the resin of the epoxy resin sheet was filled in the first through hole of the mold substrate to produce a bonded mold substrate. The resin sheet was made of an epoxy resin containing 40 wt% of an inorganic filler having a melt viscosity of 800 P to 3000 P at a temperature of 100 ° C. to 200 ° C. and an average particle diameter of about 2 μm.
A second through via with a diameter of 100 μm is formed on the epoxy resin filled in the first through hole with a carbon dioxide gas laser, and the surface residue is washed, and then a Cu layer is formed using electroless copper plating and electrolytic plating. And through-via.

  A photosensitive epoxy varnish for spin coating was applied to the surface of the bonded mold substrate (the surface on which the stud bumps of the first mold substrate were exposed), and pre-baking, exposure, development, curing, and oxygen plasma treatment were sequentially performed. As a result, an insulating layer having a thickness of 8 μm and an opening of φ30 μm exposing the stud bump of the first bare chip and an opening of φ100 μm exposing the end of the through via was formed.

  Ti and Cu were formed into a thickness of 0.1 μm and 0.3 μm by a sputtering method to form an adhesion underlayer and a seed layer. Thereafter, a resist mask having an opening exposing a portion corresponding to the opening on the seed layer was formed, and Cu electroplating was performed using the previously formed seed layer. After electroplating, the resist mask was removed, and the seed layer remaining under the resist mask was removed by wet etching and dry etching. As described above, the first layer of the multilayer wiring layer was formed on the surface of the mold substrate.

  The surface of the bonded mold substrate is protected with a protective film, and the process from the application of the photosensitive epoxy varnish to the removal of the seed layer by etching is performed twice on the back surface (the surface on which the stud bump of the second mold substrate is exposed). Repeatedly, the first layer and the second layer were formed. As described above, a multilayer wiring layer formed by laminating the first layer and the second layer was formed on the back surface of the bonded mold substrate.

  The protective film on the surface of the bonded mold substrate is peeled off, the back surface is protected with a protective film, and the process from the application of the photosensitive epoxy varnish to the etching removal of the seed layer is performed on the surface of the bonded mold substrate. Two layers were formed. As described above, a multilayer wiring layer formed by laminating the first layer and the second layer was formed on the surface of the bonded mold substrate.

  After the protective film on the back surface of the mold substrate was peeled off, a solder resist was formed on both surfaces, and the surface of each multilayer wiring layer was treated with nickel (Ni) and Au. As described above, the electronic component built-in wafer in which the multilayer wiring layers are respectively arranged on the front surface and the back surface of the mold substrate was formed. Then, the electronic component built-in wafer was cut into individual pieces to complete individual electronic component built-in substrates.

  Hereinafter, various aspects of the electronic device and the manufacturing method thereof will be collectively described as additional notes.

(Appendix 1) an insulating layer including a first insulating material;
An electronic component provided in the insulating layer;
A second insulating material provided through the insulating layer;
An electronic device comprising: a through electrode penetrating the second insulating material.

  (Additional remark 2) The said through-electrode has the said 2nd insulating material embedded in the 1st through-hole formed in the said insulating layer, and has a diameter smaller than the said 1st through-hole in the 2nd insulating material. 2. The electronic device according to appendix 1, wherein two through holes are formed and a conductive material is disposed in the second through hole.

  (Supplementary note 3) The electronic device according to Supplementary note 1 or 2, wherein the first insulating material contains 80% or more of a first filler having a maximum particle size of 50 μm to 75 μm.

  (Additional remark 4) The said 2nd insulating material contains the 2nd filler in the range whose particle size is 1 micrometer-25 micrometers, The electronic device of Additional remark 3 characterized by the above-mentioned.

  (Additional remark 5) The electronic device of Additional remark 4 characterized by the content rate of a said 2nd filler being a value within the range of 20 weight%-50 weight% with respect to a said 2nd insulating material.

  (Additional remark 6) The said 2nd insulating material is the value in the range of 800P-3000P at the temperature of 100 to 200 degreeC, The said 1st insulating material is any one of Additional remark 1-5 characterized by the above-mentioned. Electronic devices.

  (Supplementary note 7) The electronic device according to any one of supplementary notes 1 to 6, wherein the pair of insulating layers are arranged such that the electronic components face each other on the back side.

  (Supplementary Note 8) The second insulating material is disposed from the pair of first insulating layers to the first through hole, and joins the first insulating layers to each other and the second through hole. The electronic device according to appendix 7, wherein a hole is formed.

(Additional remark 9) The process of forming a 1st through-hole in the insulating layer containing the 1st insulating material in which the electronic component was provided inside,
Filling the first through hole with a second insulating material;
Forming a second through hole having a smaller diameter than the first through hole in the second insulating material;
And a step of forming a through electrode by disposing a conductive material in the second through hole.

  (Additional remark 10) The said 1st insulating material contains 80% or more of 1st fillers with a largest particle size of 50 micrometers-75 micrometers, The manufacturing method of the electronic device of Additional remark 9 characterized by the above-mentioned.

  (Additional remark 11) The said 2nd insulating material contains the 2nd filler in the range whose particle size is 1 micrometer-25 micrometers, The manufacturing method of the electronic device of Additional remark 10 characterized by the above-mentioned.

  (Supplementary note 12) The electronic device according to Supplementary note 10 or 11, wherein the content of the second filler is a value within a range of 20 wt% to 50 wt% with respect to the second insulating material. Manufacturing method.

  (Supplementary Note 13) In the step of forming the first through-hole, the pair of the first insulating layers having the electronic components are bonded and overlapped so that the electronic components face each other on the back side. The method for manufacturing an electronic device according to any one of appendices 9 to 12, wherein the first through hole is formed in the first insulating layer.

  (Supplementary Note 14) The step of embedding the first through hole with the second insulating material includes the step of inserting the first through hole in a state where the sheet-like second insulating material is disposed between the pair of first insulating layers. 14. The electronic device according to appendix 13, wherein the holes are aligned and pressed, the first insulating layers are bonded to each other, and the first through hole is filled with the second insulating material. Production method.

  (Additional remark 15) Said 2nd insulating material is the value in the range of 800P-3000P in the melt viscosity at the temperature of 100 to 200 degreeC, It is any one of Additional remarks 9-14 characterized by the above-mentioned. Electronic device manufacturing method.

DESCRIPTION OF SYMBOLS 1a Support body 1b Adhesive sheet 2A 1st bare chip 2B 2nd bare chip 2Aa, 2Ba Terminal 3A, 3B Mold resin 4,30 Bonding mold board | substrate 4A, 4B Mold board | substrate 5,33 1st through-hole 5a, 5b, 33a 33b Open hole 5c Expanded portion 5d Reduced portion 6 Resin sheet 7, 34 Second through hole 8, 35 Through via 8 a Conductive layer 8 b Conductive resin 9 a, 9 b Inorganic filler 10, 40 Electronic component built-in wafers 11, 12, 31 , 32 Multi-layer wiring layer 13 Insulating layers 13a, 16a Opening 14 Adhesion underlayer 15 Seed layer 16 Resist mask 17 Cu
20, 50 Electronic component built-in substrate 21 First layer 21a, 23a, 24a Wiring 22 Second layer 22a Via 23 Third layer 24 Fourth layer

Claims (6)

An insulating layer comprising a first insulating material;
An electronic component provided in the insulating layer;
A second insulating material provided through the insulating layer;
An electronic device comprising: a through electrode penetrating the second insulating material.   In the through electrode, the second insulating material is embedded in a first through hole formed in the insulating layer, and the second through hole has a smaller diameter than the first through hole in the second insulating material. The electronic device according to claim 1, wherein a conductive material is disposed in the second through hole.   3. The electronic device according to claim 1, wherein the second insulating material has a melt viscosity of a value in a range of 800 P to 3000 P at a temperature of 100 ° C. to 200 ° C. 4. Forming a first through hole in an insulating layer including a first insulating material provided with an electronic component therein;
Filling the first through hole with a second insulating material;
Forming a second through hole having a smaller diameter than the first through hole in the second insulating material;
And a step of forming a through electrode by disposing a conductive material in the second through hole.   The method for manufacturing an electronic device according to claim 4, wherein the first insulating material contains 80% or more of a first filler having a maximum particle size of 50 μm to 75 μm. In the step of forming the first through hole, the pair of the first insulating layers having the electronic components are bonded so that the electronic components are opposed to each other on the back surface, and the superimposed first insulation is performed. Forming the first through hole in a layer;
The step of embedding the first through holes with the second insulating material positions the first through holes in a state where the sheet-like second insulating material is disposed between the pair of first insulating layers. 6. The electronic device according to claim 4, wherein the first insulating layers are bonded to each other while being aligned and pressed together, and the first through hole is filled with the second insulating material. Method.

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