TW201705461A - 半導體裝置、及電子機器 - Google Patents

半導體裝置、及電子機器 Download PDF

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Publication number
TW201705461A
TW201705461A TW105105725A TW105105725A TW201705461A TW 201705461 A TW201705461 A TW 201705461A TW 105105725 A TW105105725 A TW 105105725A TW 105105725 A TW105105725 A TW 105105725A TW 201705461 A TW201705461 A TW 201705461A
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Taiwan
Prior art keywords
substrate
floating metal
metal
bonding surface
floating
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TW105105725A
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English (en)
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TWI692092B (zh
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Yukihiro Ando
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Sony Corp
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Publication of TWI692092B publication Critical patent/TWI692092B/zh

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  • Solid State Image Pick-Up Elements (AREA)
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Abstract

本揭示係關於一種可減少電晶體特性之變動及劣化之半導體裝置、及電子機器。 於第1基板之貼合面，形成連接第1配線之第1連接墊、及相對於第1連接墊較大之第1浮動金屬，且於第2基板之貼合面，形成連接第2配線之第2連接墊、及相對於第2連接墊較大之第2浮動金屬。將第1接合墊與第2浮動金屬、第2浮動金屬與第1浮動金屬、第1浮動金屬與第2接合墊連接，並將形成於第1基板及第2基板之各第1浮動金屬及第2浮動金屬貼合。本揭示例如可應用於相機等攝像裝置所使用之CMOS固體攝像裝置。

Description

半導體裝置、及電子機器
本揭示係關於一種半導體裝置、及電子機器，尤其關於一種可降低電晶體特性之變動及劣化之半導體裝置、及電子機器。
提出有將2片晶圓(基板)貼合，將各自之配線彼此連接之技術(參照專利文獻1)。
於此種技術中，為了確保貼合之重疊裕度，露出於貼合面之金屬部較大者較佳。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2000-299379號公報
然而，以乾式蝕刻形成露出於貼合面之較大之金屬部時，若通過基底配線連接於電晶體，則產生電晶體特性之變動及劣化之風險變高。
本揭示係鑒於此種情形而完成者，可降低電晶體特性之變動及劣化。
本技術之一態樣之半導體裝置具備形成於基板之貼合面之浮動金屬，且將上述浮動金屬貼合而作為電流路徑利用。
上述浮動金屬與連接於與上述基板之貼合面貼合之其他基板之貼合面之基底配線之金屬相比，面積形成得較大。
本發明之半導體裝置具備：第1基板之貼合面之第1浮動金屬；第2基板之貼合面之第2浮動金屬；第1金屬，其連接於上述第1基板之貼合面之基底配線；及第2金屬，其連接於上述第2基板之貼合面之基底配線；且將上述第1浮動金屬與上述第2金屬貼合，將上述第2浮動金屬與上述第1金屬貼合，將上述第1浮動金屬與上述第2浮動金屬貼合。
上述第1浮動金屬係空出上述第1浮動金屬之中央部即第1中央部，包圍形成於上述第1中央部之上述第1金屬而形成，上述第2浮動金屬係空出上述第2浮動金屬之中央部即第2中央部，包圍形成於上述第2中央部之上述第2金屬而形成。
上述第1浮動金屬及上述第1金屬係於上述第1基板之貼合面形成為矩形，上述第2浮動金屬及上述第2金屬係於上述第2基板之貼合面形成為矩形。
上述第1浮動金屬係於上述第1基板之貼合面，以於空出上述第1中央部之矩形之橫向及縱向中之任一方向存在朝向另一方向之複數個狹縫之形狀構成，上述第2浮動金屬係於上述第2基板之貼合面，以於空出上述第2中央部之矩形之上述另一方向存在上述朝向一方向之複數個狹縫之形狀構成。
上述第1浮動金屬係於上述第1基板之貼合面，以空出上述第1中央部，且複數個區塊與至少1個相鄰之區塊以角彼此重疊之形狀構成，上述第2浮動金屬係於上述第2基板之貼合面，以空出上述第2中央部，且複數個區塊與至少1個相鄰之區塊以角彼此重疊之形狀構成。
本發明之半導體裝置具備第1基板之貼合面之浮動金屬、及連接 於第2基板之貼合面之基底配線之至少2個以上之金屬，且將上述浮動金屬與上述至少2個以上之金屬貼合。
上述半導體裝置係固體攝像裝置。
本技術之一態樣之電子機器具有：固體攝像裝置，其具備形成於基板之貼合面之浮動金屬，且將上述浮動金屬貼合而作為電流路徑利用；信號處理電路，其處理自上述固體攝像裝置輸出之輸出信號；及光學系統，其將入射光入射至上述固體攝像裝置。
於本技術之一態樣中，將形成於基板之貼合面之浮動金屬貼合而作為電流路徑利用。
根據本技術，可降低電晶體特性之變動及劣化。
再者，本說明書所記載之效果僅為例示，本技術之效果並不限定於本說明書所記載之效果，亦具有附加效果。
1‧‧‧固體攝像裝置
2‧‧‧像素
3‧‧‧像素區域
4‧‧‧垂直驅動電路
5‧‧‧行信號處理電路
6‧‧‧水平驅動電路
7‧‧‧輸出電路
8‧‧‧控制電路
9‧‧‧垂直信號線
10‧‧‧水平信號線
11‧‧‧半導體基板
12‧‧‧輸入輸出端子
21‧‧‧基板
22‧‧‧基板
31‧‧‧連接墊
32‧‧‧絕緣膜
41‧‧‧連接墊
42‧‧‧絕緣膜
50‧‧‧基板
51‧‧‧Si基板
52‧‧‧絕緣膜
53‧‧‧閘極電極
54~57‧‧‧配線
58‧‧‧連接墊
100‧‧‧固體攝像裝置
101‧‧‧基板
101a‧‧‧貼合面
102‧‧‧基板
102a‧‧‧貼合面
111‧‧‧浮動金屬
111-1~111-5‧‧‧長方形
112‧‧‧連接墊
113‧‧‧配線
121‧‧‧浮動金屬
121-1~121-5‧‧‧長方形
122‧‧‧連接墊
123‧‧‧配線
131‧‧‧接合界面
132‧‧‧電流路徑
200‧‧‧固體攝像裝置
201‧‧‧基板
202‧‧‧基板
211‧‧‧浮動金屬
221‧‧‧連接墊
222‧‧‧連接墊
223‧‧‧基底配線
224‧‧‧閘極電極
225‧‧‧基底配線
226‧‧‧矽基板
231‧‧‧接合界面
500‧‧‧電子機器
501‧‧‧固體攝像裝置
502‧‧‧光學透鏡
503‧‧‧快門裝置
504‧‧‧驅動電路
505‧‧‧信號處理電路
圖1係表示應用本技術之固體攝像裝置之概略構成例之方塊圖。
圖2A~D係表示將2片基板貼合時之連接部之構造之剖視圖。
圖3係圖2之基板之構造之剖視圖。
圖4係表示應用本技術之固體攝像裝置之構造之圖。
圖5係表示貼合後之2片基板之圖。
圖6係表示浮動金屬之其他形狀之圖。
圖7A、B係說明貼合後之電流路徑之圖。
圖8係表示浮動金屬之其他形狀之圖。
圖9係表示浮動金屬之其他形狀之圖。
圖10係表示應用本技術之固體攝像裝置之構造之圖。
圖11係表示應用本技術之電子機器之構成例之方塊圖。
以下，對用以實施本揭示之形態(以下為實施形態)進行說明。
<固體攝像裝置之概略構成例>
圖1係表示應用於本技術之各實施形態之CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)固體攝像裝置之一例之概略構成例。
如圖1所示，固體攝像裝置(元件晶片)1構成為具有：像素區域(所謂之攝像區域)3，其係於半導體基板11(例如矽基板)上包含複數個光電轉換元件之像素2有規則地2維排列而形成；及周邊電路部。
像素2係具有光電轉換元件(例如光電二極體)、及複數個像素電晶體(所謂之MOS電晶體)而成。複數個像素電晶體例如可由傳送電晶體、重設電晶體及放大電晶體之3個電晶體構成，進而亦可追加選擇電晶體，而以4個電晶體構成。各像素2(單位像素)之等效電路與一般者同樣，因而此處省略詳細說明。
又，像素2亦可設為像素共有構造。像素共有構造包含複數個光電二極體、複數個傳送電晶體、共有之1個浮動擴散區、及共有之逐個之其他像素電晶體。光電二極體係光電轉換元件。
周邊電路部包含垂直驅動電路4、行信號處理電路5、水平驅動電路6、輸出電路7、及控制電路8。
控制電路8接收指令輸入時脈、或動作模式等之資料，且輸出固體攝像裝置1之內部資訊等資料。具體而言，控制電路8基於垂直同步信號、水平同步信號及主時脈，產生成為垂直驅動電路4、行信號處理電路5及水平驅動電路6之動作之基準之時脈信號或控制信號。繼而，控制電路8將該等信號輸入至垂直驅動電路4、行信號處理電路5、及水平驅動電路6。
垂直驅動電路4係例如藉由移位暫存器構成，選擇像素驅動配線，對所選擇之像素驅動配線供給用以驅動像素2之脈衝，並以列為 單位驅動像素2。具體而言，垂直驅動電路4以列為單位沿垂直方向依序選擇掃描像素區域3之各像素2，通過垂直信號線9，將基於各像素2之光電轉換元件中根據受光量所產生之信號電荷之像素信號供給至行信號處理電路5。
行信號處理電路5配置於像素2之例如每一行，於每像素行，對自1列之像素2輸出之信號進行雜訊去除等信號處理。具體而言，行信號處理電路5進行用以除去像素2固有之固定圖案雜訊之CDS(Correlated Double Sampling：相關雙重取樣)、或信號放大、A/D轉換(Analog/Digital：類比/數位)等信號處理。於行信號處理電路5之輸出段，將水平選擇開關(未圖示)連接於與水平信號線10之間而設置。
水平驅動電路6係例如由移位暫存器構成，且藉由按序輸出水平掃描脈衝，而依次選擇行信號處理電路5之各者，且自行信號處理電路5之各者將像素信號輸出至水平信號線10。
輸出電路7對自行信號處理電路5之各者通過水平信號線10而依序供給之信號，進行信號處理並輸出。輸出電路7例如有僅進行緩衝之情形，亦有進行黑位準調整、行不均修正、各種數位信號處理等之情形。
輸入輸出端子12係為了進行與外部之信號交換而設置。
<連接部之構造例>
圖2係表示將2片基板(晶圓)貼合時之連接部之構造之剖視圖。於基板21中，於絕緣膜32形成有連接墊31。於基板22中，於絕緣膜42形成有連接墊41。如圖2A所示，藉由將連接墊31與連接墊41連接而成為電流路徑，形成意欲之1個電路構成。
但是，若產生貼合之對準偏差，則如圖2B所示，連接墊31與連接墊41呈開放，而無法進行意欲之電路動作，從而引起良率下降。
因此，於將2片基板21與基板22貼合而形成電流路徑時，如圖2C及圖2D所示，為了使貼合偏差具有裕度，必須預先以大面積形成至少單側之連接墊31。
然而，如圖3所示，若形成大面積之連接墊31，則PID(Plasma Induced Damage：電漿損傷)之影響變大。
於圖3之例中，表示有基板50之構造之剖面。於基板50中，於Si基板51形成絕緣膜52，且設置有閘極電極53。自閘極電極53按序形成配線54至配線57，且於基板50之貼合面，設置有連接於配線57之大面積之連接墊58。
因形成該大面積之連接墊58之步驟之蝕刻、濺鍍或CVD(Chemical Vapor Deposition：化學氣相沈積)等製程所使用之電漿放電，而有已充電之電荷誘發場效電晶體之閘極絕緣膜之劣化等之虞。
為了回避該情形，作為設計規則而提出有將天線比(配線之上表面之面積/閘極之氧化膜之面積)設計得較小之方法，但若連接墊之面積較小，則會失去對於貼合偏差之裕度。
因此，本技術中，於連接墊之形成時，於貼合之基板之兩側之貼合面，形成與連接於基底配線之連接墊相比面積較大之浮動金屬並貼合，藉此將浮動金屬作為電流路徑而利用。
<本技術之第1構成例>
圖4係表示應用本技術之固體攝像裝置之構造之圖。固體攝像裝置100以包含基板101及基板102之方式構成。
於圖4之例中，表示有以使貼合面101a及102a彼此對向之方式定位之貼合前之基板101及基板102。再者，自圖之上方按序表示有基板101側之上表面圖、基板101側之剖視圖、基板102側之剖視圖、基板102之上表面圖。
如圖4所示，於基板101之貼合面101a，形成有連接有配線113之連接墊112、及相對於連接墊112較大之浮動金屬111。又，於基板102之貼合面102a，形成連接有配線123之連接墊122、及相對於連接墊122較大之浮動金屬121。浮動金屬111與連接墊112、及浮動金屬121與連接墊122係分別以未接觸之方式相隔而配置。再者，連接墊112、浮動金屬111、連接墊122、浮動金屬121係例如使用日本專利特開2004-63859號公報等記載之形成方法而形成。
其次，如圖5所示，基板101及基板102係以貼合面101a與貼合面102a貼合。基板101及基板102例如使用電漿接合、常溫接合等任意方法而接合。
於圖5之例中，表示將貼合面101a及102a貼合後之基板101及基板102。又，自上按序表示基板101側之上表面圖、基板101側之剖視圖、基板102側之剖視圖、基板102之上表面圖，進而於最下方表示基板101及102之貼合上表面圖。
將貼合基板101及102之面於下文中稱為接合界面131。如圖5所示，接合墊112與浮動金屬121、浮動金屬121與浮動金屬111、浮動金屬111與接合墊122連接，且形成於基板101及基板102之各者之浮動金屬111及121貼合，藉此將浮動金屬111及121作為電流路徑132而使用。
藉此，可縮小與場效電晶體連接之基底配線所連接之連接墊之面積，且可降低因形成連接墊之步驟中之蝕刻、濺鍍或CVD等製程所使用之電漿放電而導致已充電之電荷使場效電晶體之閘極絕緣膜劣化。
<變化例>
於上述之圖4及圖5中，表示浮動金屬之形狀為長方形之例，但本技術並未限定為長方形。例如，如圖6所示，亦可以環形形狀形成 浮動金屬111及時浮動金屬121，且於該環形之孔部分分別形成圓形連接墊112及連接墊122。
再者，於圖6之例中，將浮動金屬111及浮動金屬121之環形形狀中之內側及外側，以及連接墊112及連接墊122之形狀設為圓形，但並未限定為圓形。
圖7係表示具備圖6之例之浮動金屬111及浮動金屬121之基板101及基板102貼合之情形時之電流路徑之圖，於圖7之例中，自上表示有上表面圖與剖視圖。
圖7之A係就貼合時基板101及102之位置大致相合之情形時之電流路徑進行說明之圖。圖7之B係就貼合時基板101及102之位置偏移之情形時之電流路徑進行說明之圖。
如圖7之A所示，於基板101及102之位置大致相合之情形時，將基板101之連接墊112、與基板102之連接墊122作為電流路徑132而利用。
與此相對，如圖7之B所示，於貼合時基板101及102之位置偏移之情形時，將基板101之連接墊112、基板102之浮動金屬121、基板101之浮動金屬111、基板102之連接墊122以該順序(或相反順序)作為電流路徑132而利用。
圖8係表示浮動金屬之其他形狀之圖。於圖8之例中，基板101之浮動金屬111係空出中央部，將縱向較長之複數個(圖8之例之情形為5個)長方形111-1至111-5於橫向上排列而構成，且於其中央部形成有連接墊112。換言之，浮動金屬111以於空出中央部之矩形之橫向上存在縱向之複數個狹縫之形狀構成。
又，基板102之浮動金屬121係空出中央部，將橫向較長之複數個(圖8之例之情形為5個)長方形121-1至121-5於縱向上排列而構成，且於其中央部形成有連接墊122。換言之，浮動金屬121以於空出中央 部之矩形之縱向上存在橫向之複數個狹縫之形狀構成。
圖8A至圖8D係表示基板101與基板102貼合時，分別為基板101相對於基板102於左上、上、右上、左產生之貼合偏差(以下稱為重疊偏差)之例之圖。圖8E表示基板101相對於基板102無重疊偏差之例之圖。圖8F至圖8I係表示基板101與基板102貼合時，分別為基板101相對於基板102於右、左下、下、右下產生之重疊偏差之例之圖。
由於僅圖8E之情形時無重疊偏差，故而基板101之連接墊112與基板102之連接墊122被作為電流路徑132而利用。
與此相對，圖8F之情形時，自基板101之連接墊112至基板102之長方形121-3、基板101之長方形111-2及111-4、基板102之長方形121-4、基板102之長方形111-1、連接墊122被作為電流路徑132而利用。
圖8H之情形時，自基板101之連接墊112至基板102之長方形121-5、基板101之長方形111-2及111-4、基板102之長方形121-4、基板101之長方形111-3、連接墊122被作為電流路徑132而利用。
圖8J之情形時，自基板101之連接墊112至基板102之長方形121-5、基板101之長方形111-1及111-2、基板102之長方形121-4、基板101之長方形111-1、連接墊122被作為電流路徑132而利用。
再者，為了便於說明，於該等以外之圖中未圖示電流路徑，但其他亦同樣地將浮動金屬作為電流路徑而利用。
圖9係表示浮動金屬之進而其他形狀之圖。於圖9之例中，基板101之浮動金屬111及基板102之浮動金屬121於空出中央部之矩形內，複數個區塊(圖9之情形為20個)與至少1個相鄰之區塊以角彼此重疊。
圖9A至圖9D係表示於將基板101與基板102貼合時，分別為基板101相對於基板102於左上、上、右上、左產生之重疊偏差之例之圖。圖9E表示基板101相對於基板102無重疊偏差之例之圖。圖9F至圖9I係將表示基板101與基板102貼合時，分別為基板101相對於基板102於 右、左下、下、右下產生之重疊偏差之例之圖。
由於僅圖9E之情形時無重疊偏差，故而基板101之連接墊112與連接墊122被作為電流路徑132而利用。
與此相對，於圖9F、圖9H、圖9I之情形時，如各者之電流路徑132所示，自基板101之連接墊112至基板102之浮動金屬121、連接墊122被作為電流路徑132而利用。
再者，為了便於說明，於該等以外之圖中未圖示電流路徑，但其他亦同樣地將浮動金屬作為電流路徑而利用。
又，於上述說明中，雖對於基板101及基板102以成對之方式形成連接墊與浮動金屬之例進行了說明，但並未限定於此，亦可如下形成。
<本技術之第2構成例>
圖10係表示應用本技術之固體攝像裝置之構造之圖。固體攝像裝置200以包含基板201及基板202之方式構成。
於圖10之例中，表示有於接合界面231，使各自之貼合面對向貼合之貼合後之基板201及基板202。再者，自圖之上方按序表示有基板201側之上表面圖、基板201側之剖視圖、基板202側之剖視圖、基板202之上表面圖。
如圖10所示，於基板201之貼合面(即，接合界面231)，形成有浮動金屬211。
於基板202之接合界面231(即，接合界面231)，形成有分別連接於基底配線223及225之連接墊221及222。於基底配線223，連接有形成於矽基板226上之閘極電極。
因此，藉由將基板201及202於接合界面231貼合，而自基板202之閘極電極224至基底配線223、連接墊221、基板201之浮動金屬211、基板201之連接墊222、及基底配線225被作為電流路徑232而利 用。
如上所述，於圖10之固體攝像裝置200中，亦可縮小連接於場效電晶體之基底配線所連接之連接墊之面積。因此，可降低因形成連接墊之步驟中之蝕刻、濺鍍或CVD等製程所使用之電漿放電而導致已充電之電荷使場效電晶體之閘極絕緣膜劣化。
又，若增大未與基底配線連接之浮動金屬，則可確保貼合裕度。
再者，於上述說明中，雖說明瞭2層基板之積層之例，但未限定於2層。
再者，以上，對將本技術應用於CMOS固體攝像裝置之構成進行了說明，亦可應用於CCD(Charge Coupled Device，電荷耦合器件)固體攝像裝置等固體攝像裝置。又，並不限定於固體攝像裝置，本技術亦可應用於半導體裝置。
又，本技術並非限定於應用於固體攝像裝置或半導體裝置，亦可應用於攝像裝置。此處，所謂攝像裝置係指數位靜態相機或數位攝影機等相機系統、或行動電話等具有攝像功能之電子機器。再者，亦有將搭載於電子機器之模組狀之形態、即照相機模組設為攝像裝置之情形。
<電子機器之構成例>
此處，參照圖11，說明應用了本技術之電子機器之構成例。
圖11所示之電子機器500具備固體攝像裝置(元件晶片)501、光學透鏡502、快門裝置503、驅動電路504、及信號處理電路505。作為固體攝像裝置501，設置上述之本技術之固體攝像裝置。藉此，可提供降低電晶體特性之變動及劣化之性能較佳之電子機器500。
光學透鏡502使來自被攝體之像光(入射光)成像於固體攝像裝置501之攝像面上。藉此，於固體攝像裝置501內以固定期間蓄積信號電 荷。快門裝置503控制對固體攝像裝置501之光照射期間及遮光期間。
驅動電路504供給控制固體攝像裝置501之信號傳送動作及快門裝置503之快門動作之驅動信號。根據自驅動電路504供給之驅動信號(時序信號)，固體攝像裝置501進行信號傳送。信號處理電路505對自固體攝像裝置501輸出之信號進行各種信號處理。已被進行信號處理之影像信號被記憶於記憶體等記憶媒體或被輸出至監視器。
再者，於本說明書中，記述上述一連串處理之步驟當然包含依照所記載之順序按時間序列進行之處理，亦包含即便未必按時間序列處理，亦並行或個別執行之處理。
又，本揭示之實施形態並非限定於上述實施形態，能夠於不脫離本揭示之主旨之範圍內進行各種變更。
又，亦可分割以上作為1個裝置(或處理部)說明之構成，而作為複數個裝置(或處理部)構成。相反，亦可將以上作為複數個裝置(或處理部)說明之構成合併而作為1個裝置(或處理部)構成。又，當然亦可於各裝置(或各處理部)之構成中附加上述以外之構成。進而，若作為系統整體之構成或動作實質性相同，則亦可將某裝置(或處理部)之構成之一部分包含於其他裝置(或其他處理部)之構成。即，本技術並不限定於上述實施形態，能夠於不脫離本技術之主旨之範圍內進行各種變更。
以上，一面參照隨附圖式一面對本揭示之較佳實施形態詳細地進行了說明，但揭示不限於上述例。可明確只要係具有本揭示所屬之技術領域中之一般知識者，則可於申請專利範圍所記載之技術思想範疇內想到各種變更例或修正例，且應瞭解該等當然亦屬於本揭示之技術範圍內。
再者，本技術亦可採取如下構成。
(1)一種半導體裝置，其具備： 浮動金屬，其形成於基板之貼合面；且將上述浮動金屬貼合而作為電流路徑利用。
(2)如上述(1)之半導體裝置，其中上述浮動金屬與連接於與上述基板之貼合面貼合之其他基板之貼合面之基底配線之金屬相比，面積形成得較大。
(3)如上述(1)或(2)之半導體裝置，其具備：第1基板之貼合面之第1浮動金屬；第2基板之貼合面之第2浮動金屬；第1金屬，其連接於上述第1基板之貼合面之基底配線；及第2金屬，其連接於上述第2基板之貼合面之基底配線；且將上述第1浮動金屬與上述第2金屬貼合；將上述第2浮動金屬與上述第1金屬貼合；將上述第1浮動金屬與上述第2浮動金屬貼合。
(4)如上述(3)之半導體裝置，其中上述第1浮動金屬係空出上述第1浮動金屬之中央部即第1中央部，且包圍形成於上述第1中央部之上述第1金屬而形成；上述第2浮動金屬係空出上述第2浮動金屬之中央部即第2中央部，且包圍形成於上述第2中央部之上述第2金屬而形成。
(5)如上述(3)或(4)之半導體裝置，其中上述第1浮動金屬及上述第1金屬於上述第1基板之貼合面形成為圓形，上述第2浮動金屬及上述第2金屬於上述第2基板之貼合面形成為圓形。
(6)如上述(3)或(4)之半導體裝置，其中上述第1浮動金屬及上述第1金屬於上述第1基板之貼合面形成為矩形，上述第2浮動金屬及上述第2金屬於上述第2基板之貼合面形成為矩形。
(7)如上述(3)至(6)中任一項之半導體裝置，其中上述第1浮動金屬係於上述第1基板之貼合面，於空出上述第1中央部之矩形之橫向及 縱向中之任一方向上，以朝向另一方向之複數個狹縫之形狀構成；上述第2浮動金屬係於上述第2基板之貼合面，於空出上述第2中央部之矩形之上述另一方向上，以朝向上述一方向之複數個狹縫之形狀構成。
(8)如上述(3)至(6)中任一項之半導體裝置，其中上述第1浮動金屬係於上述第1基板之貼合面，以空出上述第1中央部，且複數個區塊與至少1個相鄰之區塊角彼此重疊之形狀構成；上述第2浮動金屬係於上述第2基板之貼合面，以空出上述第2中央部，且複數個區塊與至少1個相鄰之區塊角彼此重疊之形狀構成。
(9)如上述(1)或(2)之半導體裝置，其具備：第1基板之貼合面之浮動金屬；及至少2個以上之金屬，其等連接於第2基板之貼合面之基底配線；且將上述浮動金屬與上述至少2個以上之金屬貼合。
(10)如上述(1)至(9)中任一項之半導體裝置，其中上述半導體裝置係固體攝像裝置。
(11)一種電子機器，其具有：固體攝像裝置，其具備形成於基板之貼合面之浮動金屬，且貼合上述浮動金屬而作為電流路徑利用；信號處理電路，其處理自上述固體攝像裝置輸出之輸出信號；及光學系統，其將入射光入射至上述固體攝像裝置。
100‧‧‧固體攝像裝置
101‧‧‧基板
101a‧‧‧貼合面
102‧‧‧基板
102a‧‧‧貼合面
111‧‧‧浮動金屬
112‧‧‧連接墊
113‧‧‧配線
121‧‧‧浮動金屬
122‧‧‧連接墊
123‧‧‧配線

Claims (11)

  1. 一種半導體裝置，其包含：浮動金屬，其形成於基板之貼合面；且將上述浮動金屬貼合而作為電流路徑利用。
  2. 如請求項1之半導體裝置，其中上述浮動金屬與連接於與上述基板之貼合面貼合之其他基板之貼合面之基底配線之金屬相比，面積形成得較大。
  3. 如請求項2之半導體裝置，其包含：第1基板之貼合面之第1浮動金屬；第2基板之貼合面之第2浮動金屬；第1金屬，其連接於上述第1基板之貼合面之基底配線；及第2金屬，其連接於上述第2基板之貼合面之基底配線；且將上述第1浮動金屬與上述第2金屬貼合；將上述第2浮動金屬與上述第1金屬貼合；將上述第1浮動金屬與上述第2浮動金屬貼合。
  4. 如請求項3之半導體裝置，其中上述第1浮動金屬係空出上述第1浮動金屬之中央部即第1中央部，且包圍形成於上述第1中央部之上述第1金屬而形成；上述第2浮動金屬係空出上述第2浮動金屬之中央部即第2中央部，且包圍形成於上述第2中央部之上述第2金屬而形成。
  5. 如請求項4之半導體裝置，其中上述第1浮動金屬及上述第1金屬於上述第1基板之貼合面形成為圓形，上述第2浮動金屬及上述第2金屬於上述第2基板之貼合面形成為圓形。
  6. 如請求項4之半導體裝置，其中上述第1浮動金屬及上述第1金屬於上述第1基板之貼合面形成為矩形，上述第2浮動金屬及上述 第2金屬於上述第2基板之貼合面形成為矩形。
  7. 如請求項4之半導體裝置，其中上述第1浮動金屬係於上述第1基板之貼合面，於空出上述第1中央部之矩形之橫向及縱向中之任一方向上，以朝向另一方向之複數個狹縫之形狀構成；上述第2浮動金屬係於上述第2基板之貼合面，於空出上述第2中央部之矩形之上述另一方向上，以朝向上述一方向之複數個狹縫之形狀構成。
  8. 如請求項4之半導體裝置，其中上述第1浮動金屬係於上述第1基板之貼合面，以空出上述第1中央部，且複數個區塊與至少1個相鄰之區塊角彼此重疊之形狀構成；上述第2浮動金屬係於上述第2基板之貼合面，以空出上述第2中央部，且複數個區塊與至少1個相鄰之區塊角彼此重疊之形狀構成。
  9. 如請求項3之半導體裝置，其包含：第1基板之貼合面之浮動金屬；及至少2個以上之金屬，其等連接於第2基板之貼合面之基底配線；且將上述浮動金屬與上述至少2個以上之金屬貼合。
  10. 如請求項2之半導體裝置，其中上述半導體裝置為固體攝像裝置。
  11. 一種電子機器，其包含：固體攝像裝置，其包含形成於基板之貼合面之浮動金屬，且貼合上述浮動金屬而作為電流路徑利用；信號處理電路，其處理自上述固體攝像裝置輸出之輸出信號；及光學系統，其將入射光入射至上述固體攝像裝置。
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US10985081B2 (en) 2021-04-20
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US20190296061A1 (en) 2019-09-26
US10355036B2 (en) 2019-07-16
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KR20230010002A (ko) 2023-01-17
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US20180047767A1 (en) 2018-02-15
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