TW201703231A - 可回復式記憶體裝置 - Google Patents
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Abstract
一種可回復式記憶體裝置包含基底、複數個晶粒以及至少一局部內連線層。晶粒被嵌入於基底之中。區域性內連性層被設置於基底的上表面上,且配置用以將晶粒繞線連接至位於局部內連線層相對於基底的最頂端之表面上的複數個電性端點。
Description
本揭露是有關於一種記憶體裝置,特別是有關於可回復式記憶體裝置。
應用多晶片封裝技術,記憶體產品可被更密集地形成積體,且於微縮至更小尺寸的情形下提供更佳的執行效能。傳統上,一般多晶片封裝體內的晶粒藉由引線鍵合於晶粒以便互相連接,且被固定於基底上。因此,需要複雜製作流程,以便在製作記憶體產品的封裝體時,於晶粒之間形成電性連接。更進一步地來說,當晶粒被固定於基底上時,要自基底或封裝體內的晶粒中移除其中任意一個晶粒,都是非常困難的事。如果封裝體內的晶粒發生故障,可能會危害整個封裝體的功能,或必須要經過有非常高風險可能會破壞整個記憶體產品的製程來移除晶粒。
由此可見,上述具有記憶體基底的封裝體架構,顯然仍存在不便與缺陷,而有待加以進一步改進。為了解决上述問題,相關領域莫不費盡心思來謀求解决之道,但長久以來一直未見適用的方式被發展完成。因此,如何能活躍解决上述問題,實屬當前重要研發課題之一,亦成為當前相關領域亟需改進的目標。
本發明之一技術態樣是有關於一種可回復式記憶體裝置。可回復式記憶體裝置可藉由至少一局部內連線層,沿規劃線路選擇性地繞線連接(route)可回復式記憶體裝置內含的晶粒至位於局部內連線層相對於基底的最頂端之表面上的複數個電性端點。如此一來,可揀選可回復式記憶體裝置內具有良好功能的晶粒連接至電性端點與其他元件相連接,如邏輯元件、控制元件等,而封存故障之晶粒,藉此賦予可回復式記憶體裝置可回復性。
根據本發明一或多個實施方式,提供一種可回復式記憶體裝置包含基底、複數個晶粒以及至少一局部內連線層。複數個晶粒嵌入於基底內。局部內連線層設置於基底的上表面上。局部內連線層可配置用以將複數個晶粒繞線連接至位於局部內連線層相對於基底的最頂端之表面上的複數個電性端點。
在本發明一或多個實施方式中,上述之基底具有複數個晶粒容置模槽,形成於基底的上表面以內,且晶粒被嵌入於晶粒容置模槽內。
在本發明一或多個實施方式中,上述之局部內連線層可包含重分佈層。
在本發明一或多個實施方式中,上述之局部內連線層可包含中介層以及複數個矽穿孔。中介層,具有前側表面以及後側表面。複數個矽穿孔於中介層的前側表面以及後側表面之間延伸。
在本發明一或多個實施方式中,上述之局部內連線層可包含篩選層。篩選層可用以將對應的晶粒繞線連接至位於局部內連線層相對於基底的最頂端之表面上的電性端點。
在本發明一或多個實施方式中,上述之複數個晶粒可包含活躍晶粒以及非活躍晶粒,且篩選層被配置用以將活躍晶粒繞線連接至位於局部內連線層相對於基底的最頂端之表面上的電性端點。
在本發明一或多個實施方式中,上述之篩選層可為局部內連線層中相對於基底的最頂端的一層。
在本發明一或多個實施方式中,上述之篩選層可位於局部內連線層中相對於基底的最頂端的一層以及基底之間。
在本發明一或多個實施方式中,上述之可回復式記憶體裝置可更包含半導體元件與電性端點電性連接。
在本發明一或多個實施方式中,上述之半導體元件可包含邏輯元件、控制元件或邏輯元件與控制元件的組合。
在本發明一或多個實施方式中,上述之可回復式記憶體裝置可更包含複數個連接凸塊。連接凸塊形成於該些電性端點的一端。半導體元件透過連接凸塊電性連接電性端點。
在本發明一或多個實施方式中,上述之可回復式記憶體裝置可更包含矩陣式重分佈層。矩陣式重分佈層設置於局部內連線層上。矩陣式重分佈層可用以沿規劃線路將位於局部內連線層之對應的電性端點連接至矩陣式重分佈層的上表面上。電性端點可被重新排列形成連接墊陣列。連接凸塊形成於連接墊陣列上。
在本發明一或多個實施方式中,上述之半導體元件可包含接腳陣列,排列於半導體元件的背側。接腳陣列中的接腳配置,可用以耦接至連接凸塊中對應的連接凸塊。
在本發明一或多個實施方式中,上述之局部內連線層可更包含電性互連線。電性互連線可用以沿規劃線路繞線連接於複數個半導體元件之間。
100‧‧‧可回復式記憶體裝置
110‧‧‧基底
112‧‧‧晶粒容置模槽
120‧‧‧晶粒
130‧‧‧局部內連線層
132‧‧‧篩選層
134‧‧‧重分佈層
136‧‧‧中介層
138‧‧‧矽穿孔
140‧‧‧連接凸塊
150‧‧‧半導體元件
160‧‧‧電性端點
200‧‧‧可回復式記憶體裝置
220A‧‧‧活躍晶粒
220B‧‧‧非活躍晶粒
300‧‧‧可回復式記憶體裝置
400‧‧‧可回復式記憶體裝置
500‧‧‧可回復式記憶體裝置
600‧‧‧可回復式記憶體裝置
700‧‧‧可回復式記憶體裝置
720‧‧‧電性互連線
800‧‧‧可回復式記憶體裝置
820‧‧‧矩陣式重分佈層
840‧‧‧連接墊陣列
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖到第8圖為根據多個不同的實施方式之可回復式記憶體裝置的側視剖面圖。
除非有其他表示,在不同圖式中相同之號碼與符號通常被當作相對應的部件。該些圖示之繪示為清楚表達該些實施方式之相關關聯而非繪示該實際尺寸。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
當一個元件被稱為『在…上』時,它可泛指該元件直接在其他元件上,也可以是有其他元件存在於兩者之中。相反地,當一個元件被稱為『直接在』另一元件,它是不能有其他元件存在於兩者之中間。如本文所用,詞彙『與/或』包含了列出的關聯項目中的一個或多個的任何組合。
第1圖依據本揭露的一個實施方式概略地繪示可回復式記憶體裝置100的側視剖面圖。可回復式記憶體裝置100包含基底110、複數個晶粒120以及至少一局部內連線層130。複數個晶粒120被嵌入於基底110內。在多個實施方式中,晶粒120可被貼合至基底100。在多個實施方式中,基底110可為記憶體基底、快閃記憶體基底、隨機存取記憶體基底或其他記憶體基底。局部內連線層130被設置於基底的上表面上,且被配置用以沿已規劃之連接線路將複數個晶粒120繞線
連接至位於局部內連線層130相對於基底110的最頂端之表面上的複數個電性端點160。因此,電訊號可透過局部內連線層130被傳遞於晶粒120以及電性端點160之間。舉例來說,電訊號可包含輸出輸入(input/output,I/O)訊號及/或與晶粒120運作相關的電源或接地訊號。在多個實施方式中,可回復式記憶體裝置可更包含複數個連接凸塊140,設置於電性端點160上,且複數個半導體元件150被耦接至複數個連接凸塊140,連接凸塊140與半導體元件150將被詳盡描述於後。在多個實施方式中,基底110具有複數個晶粒容置模槽112,也將如後詳述。
第2圖依據本揭露的一個實施方式概略地繪示可回復式記憶體裝置200的側視剖面圖。可回復式記憶體裝置200可包含活躍晶粒220A、非活躍晶粒220B以及篩選層132。如同第2圖所示,局部內連線層130可更包含篩選層132,用以將複數個晶粒120中對應的活躍晶粒220A繞線連接至局部內連線層130最頂端之表面上的電性端點160。值得注意的是,此處所述之篩選層132並非用以限制篩選層132之結構為單層結構,篩選層132也可為多層結構,不連續地或連續地設置於局部內連線層130內,以便沿規劃的連接線路將對應的晶粒120繞線連接至電性端點160。亦即,只要局部內連線層130其中的一層,可被用來選擇性地沿規劃的連接線路將下方層的電性連接線繞線連接至局部內連線層130最頂端之表面上的電性端點160,則局部內連線層130內,選擇性地電性連接晶粒
120與電性端點160的此層可被視為篩選層132。因此,當可回復式記憶體裝置200採用篩選層132時,可更具有彈性。
如同第2圖所示,額外的外加層,像是篩選層132,可被輕易地製造於如第1圖所繪示之可回復式記憶體裝置100中已先形成之局部內連線層130上,以便形成新的局部內連線層130。在可回復式記憶體裝置200中,當額外的外加層被製造之後,新的局部內連線層130之電性端點160可被轉換形成新的排列方式。更進一步地來說,無論是可回復式記憶體裝置100或可回復式記憶體裝置200都可具有更多額外的外加層被製造,且形成於已先形成之局部內連線層130上。因此,具有局部內連線層130的可回復式記憶體裝置可藉由修改局部內連線層130的版面配線,以輕易地達致對記憶體產品的多種不同需求。可回復式記憶體裝置100的局部內連線層130簡化製造形成記憶體產品的積體製程,且改進記憶體產品的製造速率以及電性參數。
在多個實施方式中,晶粒120包含活躍晶粒220A以及非活躍晶粒220B。篩選層132被配置用以將活躍晶粒220A繞線連接至局部內連線層130最頂端之表面上的電性端點160。晶粒120可具有好的晶粒或損毀的晶粒,可透過對晶粒120進行測試而得知,而可回復式記憶體裝置200具有預備之晶粒,以防止活躍晶粒220A經檢測後,被認定為損毀的晶粒,可使用預備之非活躍晶粒220B取代損毀的活躍晶粒220A。在多個實施方式中,非活躍晶粒220B可被當作替活躍晶粒220A所預備之備用的晶粒。當活躍晶粒220A被發現是損
毀的晶粒時,局部內連線層130可沿規劃的連接線路,形成電性連線繞接連接至非活躍晶粒220B中好的晶粒,以取代損毀的活躍晶粒220A。因此,非活躍晶粒220B變成另一個活躍晶粒220A。在多個實施方式中,可於可回復式記憶體裝置200自晶圓被切割成單體之前或之後的階段,決定晶粒120中的活躍晶粒220A以及非活躍晶粒220B的分配情形,提供可回復式記憶體裝置200更大的彈性空間。在多個實施方式中,可於可回復式記憶體裝置200自晶圓被切割成單體之前或之後的階段,決定篩選層132中的線路配置,同樣也提供可回復式記憶體裝置200更大的彈性空間。
第3圖依據本揭露的一個實施方式概略地繪示示例性的可回復式記憶體裝置300的側視剖面圖,其中篩選層132被設置作為局部內連線層130的最頂端的一層。在多個實施方式中,篩選層132可為局部內連線層130中相對於基底110的最頂端的一層。如同第3圖所示,篩選層132沿規劃的連接線路,將下方層的電性連線選擇性地繞接連接至局部內連線層130中相對於基底110的最頂端的一層,亦即篩選層132,以形成電性端點160,使得被選擇的晶粒120可透過電性端點160被電性連接。
第4圖依據本揭露的一個實施方式概略地繪示示例性的可回復式記憶體裝置400的側視剖面圖,其中篩選層132被設置於局部內連線層130中相對於基底110的最頂端的一層以及基底110之間。在多個實施方式中,篩選層132被設置於局部內連線層130中相對於基底110的最頂端的一層以及
基底110之間。如同第4圖所示,篩選層132被夾心於局部內連線層130的其他層之間,然後,篩選層132沿規劃的連接線路,將位於下方層的電性連線選擇性地繞接連接至局部內連線層130中更高的層,接著藉由被形成於更高的層中之電性連線,將被篩選層132挑選的晶粒120繞接連接至局部內連線層130最頂端之表面上的電性端點160。
第5圖依據本揭露的一個實施方式概略地繪示示例性的可回復式記憶體裝置500的側視剖面圖,其中局部內連線層130包含重分佈層134以及具有矽穿孔138的中介層136。第6圖依據本揭露的一個實施方式概略地繪示示例性的可回復式記憶體裝置600的側視剖面圖,其中具有矽穿孔138的中介層136被設置於重分佈層134上。在多個實施方式中,重分佈層134可包含一或多個金屬層或更多的金屬層。在多個實施方式中,重分佈層134可被透過單鑲嵌製程或雙鑲嵌製程製造。值得注意的是,此處所述之重分佈層134並非用以限制重分佈層134的結構,重分佈層134可具有多個重分佈線軌設置於重分佈層134內,以便傳輸電訊號,且重分佈線軌被配置用以電性連線繞接連接於夾心層之間或多個電性連線之間。
在多個實施方式中,局部內連線層130包含中介層136。中介層136具有前側表面以及後側表面,且複數個矽穿孔138於中介層136的前側表面以及後側表面之間延伸。在多個實施方式中,局部內連線層130可包含重分佈層134、具有矽穿孔138的中介層136、其他提供電性連線的合適結構或前述之組合。在多個實施方式中,篩選層132可為重分佈層
134、具有矽穿孔138的中介層136或其他提供電性連線的合適結構。
第7圖依據本揭露的一個實施方式概略地繪示示例性的可回復式記憶體裝置700的側視剖面圖。在多個實施方式中,基底110具有複數個晶粒容置模槽112,形成於基底110的上表面以內,且複數個晶粒120被嵌入於晶粒容置模槽112內。在多個實施方式中,晶粒120可被貼附到晶粒容置模槽112。
在多個實施方式中,可回復式記憶體裝置700更包含複數個半導體元件150。半導體元件150藉由局部內連線層130的電性端點160電性連接至複數個晶粒120中對應的晶粒120。在多個實施方式中,半導體元件150可包含邏輯元件、其他合適的處理器半導體元件或前述元件的組合。在多個實施方式中,局部內連線層130可更包含電性互連線720,用以沿規劃線路於半導體元件之間傳輸電訊號。
在多個實施方式中,可回復式記憶體裝置700更包含複數個連接凸塊140。連接凸塊140形成於該些電性端點160的一端,其中半導體元件150透過耦合連接凸塊140電性連接至電性端點160。
第8圖依據本揭露的一個實施方式概略地繪示示例性的可回復式記憶體裝置800的側視剖面圖,其中可回復式記憶體裝置800包含矩陣式重分佈層820。在多個實施方式中,可回復式記憶體裝置800更包含矩陣式重分佈層820設置於局部內連線層130上,用以將下方位於局部內連線層130之
對應的電性端點160繞線連接至上方的矩陣式重分佈層820的上表面上。在多個實施方式中,電性端點160可被依照特定排列模式(圖未繪示)重新排列形成連接墊陣列840。連接凸塊140形成於連接墊陣列840上。
在多個實施方式中,半導體元件150包含接腳陣列860,排列於半導體元件150的背側。接腳陣列860中的單一接腳860被配置用以電性以及物理耦接至對應的連接凸塊140。
綜上所述,本揭露提供一種可回復式記憶體裝置。可回復式記憶體裝置包含基底、複數個晶粒以及至少一局部內連線層。複數個晶粒被嵌入於基底內。局部內連線層設置於基底的上表面上,且配置用以將複數個晶粒繞線連接至位於局部內連線層相對於基底的最頂端之表面上的複數個電性端點。因此,半導體元件可藉由電性端點與晶粒電性連接。
雖然本揭露的多個實施方式及其優點已於本文中詳盡敘述,使得本領域的技術人員可更瞭解本揭露的多個面向。本領域的技術人員應瞭解到,可使用本揭露作為基礎去設計或修改其他製造流程與結構,以執行同樣之目的及/或達至與此處所介紹之實施例中相同的優點。本領域的技術人員應可同樣瞭解到,均等之更動和潤飾並未脫離本揭露的精神與範圍,且本領域的技術人員可於未脫離本揭露的精神與範圍下,做出多種不同的變化、替換以及更動。
100‧‧‧可回復式記憶體裝置
110‧‧‧基底
112‧‧‧晶粒容置模槽
120‧‧‧晶粒
130‧‧‧局部內連線層
140‧‧‧連接凸塊
150‧‧‧半導體元件
160‧‧‧電性端點
Claims (14)
- 一種可回復式記憶體裝置,包含:一基底;複數個晶粒,嵌入於該基底內;以及至少一局部內連線層,設置於該基底的一上表面上,且配置用以將該些晶粒繞線連接至位於該局部內連線層相對於該基底的最頂端之一表面上的複數個電性端點。
- 如申請專利範圍第1項所述之可回復式記憶體裝置,其中該基底具有複數個晶粒容置模槽,形成於該基底的該上表面以內,且該些晶粒被嵌入於該些晶粒容置模槽內。
- 如申請專利範圍第1項所述之可回復式記憶體裝置,其中該局部內連線層包含一重分佈層。
- 如申請專利範圍第1項所述之可回復式記憶體裝置,其中該局部內連線層包含:一中介層,具有一前側表面以及一後側表面;以及複數個矽穿孔,於該中介層的該前側表面以及該後側表面之間延伸。
- 如申請專利範圍第1項所述之可回復式記憶體裝置,其中該局部內連線層包含一篩選層,用以沿規劃線 路將對應的該些晶粒連接至位於該局部內連線層相對於該基底的最頂端之該表面上的該些電性端點。
- 如申請專利範圍第5項所述之可回復式記憶體裝置,其中該些晶粒包含一活躍晶粒以及一非活躍晶粒,且該篩選層被配置用以沿規劃線路將該活躍晶粒連接至位於該局部內連線層相對於該基底的最頂端之該表面上的該些電性端點。
- 如申請專利範圍第5項所述之可回復式記憶體裝置,其中該篩選層為該局部內連線層中相對於該基底的最頂端的一層。
- 如申請專利範圍第5項所述之可回復式記憶體裝置,其中該篩選層位於該局部內連線層中相對於該基底的最頂端的一層以及該基底之間。
- 如申請專利範圍第1項所述之可回復式記憶體裝置,更包含複數個半導體元件與該些電性端點電性連接。
- 如申請專利範圍第9項所述之可回復式記憶體裝置,其中該些半導體元件包含一邏輯元件、一控制元件或該邏輯元件與該控制元件的組合。
- 如申請專利範圍第9項所述之可回復式記憶體裝置,更包含複數個連接凸塊形成於該些電性端點的一端,其中該些半導體元件透過該些連接凸塊電性連接該些電性端點。
- 如申請專利範圍第11項所述之可回復式記憶體裝置,更包含一矩陣式重分佈層,設置於該局部內連線層上,用以沿規劃線路將位於該局部內連線層之對應的該些電性端點連接至該矩陣式重分佈層的一上表面上,其中該些電性端點被重新排列形成連接墊的一矩陣,且該些連接凸塊形成於該些連接墊上。
- 如申請專利範圍第12項所述之可回復式記憶體裝置,其中該些半導體元件包含接腳的一矩陣,該些接腳排列於該些半導體元件的一背側,其中該些接腳的該矩陣中的一接腳配置用以耦接至該些連接凸塊中對應的該連接凸塊。
- 如申請專利範圍第9項所述之可回復式記憶體裝置,其中該局部內連線層更包含一電性互連線,用以沿規劃線路連接於該些半導體元件之間。
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