TW201701467A - Metal oxide semiconductor field effect transistor and method of fabricating the same - Google Patents

Abstract

Provided is a metal oxide semiconductor field effect transistor including a drain region of a first conductivity type, a source region of the first conductivity type, a gate structure, a first top doped region of a second conductivity type and an insertion layer of the second conductivity type. The drain region is located in a substrate. The source region is located in the substrate and surrounded the drain region. The gate structure is located on the substrate between the source region and the drain region. The first top doped region is located in the substrate between the gate and the drain region. The insertion layer is located on the first top doped region between the gate structure and the drain region.

Description

Gold oxygen half field effect transistor and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a gold oxide half field effect transistor and a method of fabricating the same.

In general, high voltage components are mainly used in power switch circuits, such as power switch devices for power switch switching. There are currently two parameters that influence the market for power switching: the breakdown voltage and the ON-state resistance, which can vary with different requirements. The main goal of designing high voltage components is to reduce the on-state resistance while maintaining a high breakdown voltage. In fact, if the designer wants to meet the specification of the breakdown voltage, it usually sacrifices the on-state resistance, so the breakdown voltage is in a trade-off relationship with the on-state resistance.

During the reliability test, the charge balance in the high voltage component is one of the important factors controlling the breakdown voltage. The reasons for affecting the charge balance are as follows: Passivation contamination, Molding compound And process contamination. While developing a better passivation layer material and encapsulating colloidal material, how to provide a high voltage component and a manufacturing method thereof to maintain the charge balance in the high voltage component and thereby improve product reliability will become an important issue in the future.

The invention provides a gold oxide half field effect transistor and a manufacturing method thereof, which can maintain the charge balance in the gold oxide half field effect transistor, thereby improving product reliability.

The present invention provides a gold oxide half field effect transistor, comprising: a drain region having a first conductivity type, a source region having a first conductivity type, a gate structure, a first top doping region having a second conductivity type, and An intercalation doped layer having a second conductivity type. The bungee zone is located in the base. The source region is located in the substrate and surrounds the periphery of the drain region. The gate structure is located on the substrate between the drain region and the source region. The first top doped region is located in the substrate between the source region and the drain region. The intervening doped layer is on the first top doped region between the gate structure and the drain region.

The invention provides a method for manufacturing a gold oxide half field effect transistor, the steps of which are as follows. A gate structure is formed on the substrate. A drain region having a first conductivity type is formed in the substrate on the first side of the gate structure. A source region having a first conductivity type is formed in the substrate on the second side of the gate structure. The source area surrounds the bungee area. A first top doped region having a second conductivity type is formed in the substrate between the source region and the drain region. An intercalation doping layer having a second conductivity type is formed on the first top doped region between the gate structure and the drain region. The intervening doped layer partially overlaps the first top doped region.

The above described features and advantages of the invention will be apparent from the following description.

10, 10a, 10b‧‧‧ base

12‧‧‧First doped area

14‧‧‧Top doped area

15‧‧‧ gate structure

16‧‧‧ gate

18‧‧‧gate dielectric layer

20‧‧‧Bungee Area

22‧‧‧ source area

24a, 24b, 24c‧‧‧ isolation structure

28‧‧‧Four doped area

30‧‧‧Second doped area

32‧‧‧ Third doped area

34, 36‧‧‧Densely doped area

42‧‧‧ sixth doping area

44‧‧‧ seventh doped area

46‧‧‧ eighth doped area

50‧‧‧Mat oxide layer

52‧‧‧ Cover layer

54, 58, 114‧‧‧ openings

56, 62, 66‧‧‧ patterned mask layer

60‧‧‧Overlapping areas

64‧‧‧Doped area

100,200‧‧‧Gold oxygen half-field effect transistor

102, 202‧‧‧ Insert doped layer

104‧‧‧Top doped area

106, 108, 110, 112‧‧‧Metal interconnection

1 is a top view of a gold oxide half field effect transistor according to an embodiment of the invention.

Figure 2 is a cross-sectional view showing the first embodiment of the line I-I of Figure 1.

Figure 3 is a cross-sectional view showing a second embodiment of the line I-I of Figure 1.

4A to 4G are schematic cross-sectional views showing the manufacturing flow of Fig. 2.

5A to 5B are schematic cross-sectional views showing the manufacturing flow of Fig. 3.

1 is a top view of a gold oxide half field effect transistor according to an embodiment of the invention. Figure 2 is a cross-sectional view showing the first embodiment of the line I-I of Figure 1. For the sake of clarity of the drawing, only the source region, the drain region and the top doping region are illustrated in FIG.

Referring to FIG. 1 and FIG. 2, a gold-oxygen half field effect transistor 100 according to an embodiment of the invention includes a gate structure 15, a source region 22, a drain region 20, and a top doping region 14. The drain region 20 is located in the substrate 10. In another embodiment, the above-mentioned metal oxide half field effect transistor 100 may further include a first doping region 12, a second doping region 30, a third doping region 32, a fourth doping region 28, and a heavily doped region. 34, 36.

Substrate 10 can be a semiconductor substrate 10a, such as a germanium substrate. The substrate 10 may have a P-type doping or an N-type doping. The P-type dopant can be a Group IIIA ion, such as a boron ion. The N-type dopant may be a VA group ion such as an arsenic ion or a phosphorus ion. In another embodiment of the present invention, the substrate 10 may also include a semiconductor substrate 10a and an epitaxial layer 10b positioned thereabove. In this embodiment, the semiconductor substrate 10a is a P-type substrate, and the epitaxial layer 10b may be an N-type epitaxial layer (N-epi).

The first doped region 12 (eg, the first N-type well region) has a first conductivity type, located in the substrate 10, such that the top doped region 14, the fourth doped region (eg, the second N-type well region) 28, is thick The doped region 36 and the drain region 20 are located therein. The fourth doped region 28 has a first conductivity type adjacent to the top doped region 14. The doping concentration of the fourth doping region 28 is higher than that of the first doping region 12.

The heavily doped region 36 has a first conductivity type and is located within the fourth doped region 28. The doping concentration of the heavily doped region 36 is higher than that of the fourth doping region 28 to reduce the series resistance.

The drain region 20 has a first conductivity type and is located in the heavily doped region 36. The doping concentration of the drain region 20 is higher than that of the heavily doped region 36. The shape of the drain region 20 projected onto the surface of the substrate 10 is, for example, at least one U-shape. In another embodiment, the shape projected by the drain region 20 onto the surface of the substrate 10 may be composed of two U-shaped or more U-shapes, or other shapes, but the invention is not limited thereto.

The second doped region (which may be, for example, HVNW) 30 has a first conductivity type and is located in the substrate 10. The second doped region 30 has a third doped region (eg, P-type well region) 32, a heavily doped region 34, and a source region 22 located therein. The third doping region 32 has a second conductivity type and is located in the second doping region 30. a heavily doped region 34 located in the third doped region 32, used to reduce the series resistance.

The gate structure 15 includes a gate 16 and a gate dielectric layer 18. Gate 16 is located on substrate 10 between source region 22 and drain region 20. More specifically, in one embodiment, the gate 16 extends from the source region 22 toward the drain region 20, covering the first doped region 12 and a portion of the top doped region 14. In another embodiment, the gate 16 is from the source region 22, covering the heavily doped region 34, the third doped region 32, the second doped region 30, the first doped region 12, and a partially doped region. 14. The gate 16 is a stacked layer of a conductive material such as a metal, a polysilicon, a doped polysilicon, a polycrystalline metal, or a combination thereof. In an embodiment, the gate structure 15 and the top doped region 14 are separated by an isolation structure (or referred to as a drift isolation structure) 24a. By covering the structure of the partial isolation structure 24a through the gate structure 15, the position of the maximum electric field strength in the electric field formed between the drain region 20 and the source region 22 can be shifted below the isolation structure 24a instead of falling on the gate. Below the dielectric layer 18, the thin gate dielectric layer 18 is prevented from being broken by an excessive electric field. The isolation structure 24a is, for example, a partial thermal oxidation isolation structure made of an insulating material such as hafnium oxide. The gate dielectric layer 18 is between the gate 16 and the substrate 10.

The top doped region 14 has a second conductivity type on the first side of the gate structure 15. More specifically, the top doped region 14 is located in the first doped region 12 between the gate structure 15 and the drain region 20, adjacent to the fourth doped region 28, and a portion of the top doped region 14 is The gate structures 15 overlap. In an embodiment, the doping concentration gradient in the top doped region 14 can be linear. That is, the doping concentration in the top doped region 14 decreases linearly from near the gate structure 15 to near the drain region 20. The doped region of the top doped region 14 is gradually reduced in depth from the gate structure 15 to the drain region 20, and the bottom portion of the top doped region 14 is contoured. It is roughly linear. In an embodiment, the doping region of the top doped region 14 may be the same depth from the gate structure 15 to the drain region 20.

It should be noted that, in this embodiment, the MOS field-effect transistor 100 further includes an interposer layer 102 having a second conductivity type and a top doping region 104 having a first conductivity type. The intervening doped layer 102 is between the gate structure 15 and the drain region 20 and is located on the top doped region 14 below the isolation structure 24a and the interposed doped layer 102 partially overlaps the top doped region 14. The depth of the intercalation layer 102 is, for example, less than 500 nm. In an embodiment, the depth of the doped layer 102 is, for example, 200 nm to 500 nm. Since the interposer doped layer 102 is located on the top doped region 14 below the isolation structure 24a, it can balance the interface charge between the isolation structure 24a and the substrate 10 to improve product reliability. In addition, when the doped layer 102 is formed, its dopant also penetrates the isolation structure 24a. Therefore, a portion of the dopant penetrating the isolation structure 24a can also balance the fixed charge in the isolation structure 24a to improve product reliability. In an embodiment, the Gaussian distribution of the doping concentration of the doped layer 102 is different from the Gaussian distribution of the doping concentration of the top doped region 14. Specifically, the doping depth of the intercalation doping layer 102 may be greater than the doping concentration of the top doping region 14 at a doping depth (ie, a top surface extending downward distance of the substrate 10) of between 200 nm and 500 nm. In this embodiment, the top doped region 14 can be charge balanced such that the device reaches its breakdown voltage. Inserting the doped layer 102 is resistant to passivation contamination, encapsulation colloid, and process contamination to improve component reliability.

In an embodiment, the top doped region 104 is between the interposer doped layer 102 and the top doped region 14 and between the isolation structure 24a and the top doped region 14. The top doping region 104 can lower the on-state resistance of the MOS field-effect transistor 10. But the invention does not To this end, in other embodiments, the top doping region 104 may not be formed between the interposer doped layer 102 and the top doped region 14.

The source region 22 has a first conductivity type and is located in the heavily doped region 34 on the second side of the gate structure 15. The doping concentration of the source region 22 is higher than that of the heavily doped region 34. The source region 22 surrounds the drain region 20. More specifically, the source region 22 surrounds the periphery of the top doped region 14.

In addition, the third doping region 32 of the above-mentioned metal oxide half field effect transistor 100 further includes a sixth doping region 42 having a second conductivity type, which serves as a junction of the third doping region 32. Further, a seventh doping region 44 and an eighth doping region 46 (shown in FIG. 2) are included in the substrate 10. The seventh doping region 44 has a second conductivity type and is located around the second doping region 30. The eighth doped region 46 has a second conductivity type and is located in the seventh doping region 44. The sixth doped region 42 and the eighth doped region 46 have an isolation structure 24b; and the other side of the eighth doped region 46 also has an isolation structure 24c.

In addition, the metal oxide half field effect transistor 100 further includes metal interconnects 106, 108, 110, 112. The metal interconnect 106 is electrically connected to the drain region 20. The metal interconnect 108 is electrically connected to the source region 22. The metal interconnect 110 is electrically connected to the sixth doped region 42. The metal interconnect 112 is electrically connected to the eighth doped region 46. There is at least one opening 114 between the metal interconnect 106 and the metal interconnect 108. The opening 114 is disposed above the top doping region 14. The metal interconnects 106, 108 above the isolation structure 24a, which may be considered as field plates, in addition to being used as metal interconnects. Thus, the metal interconnects 106, 108 above the isolation structure 24a reduce the surface electric field to effectively increase the breakdown voltage and reduce the on-state resistance. In an embodiment, use The size of the opening 114 above the top doped region 14 can be adjusted as needed to optimize the breakdown voltage of the component and the open state resistance. Although the metal interconnects 106, 108, 110, and 112 in FIG. 2 have only two conductor layers, the present invention is not limited thereto. In other embodiments, the metal interconnects 106, 108, 110, and 112 are also It can be a layer of conductor or a layer of conductors.

The first conductivity type may be a P type or an N type; and the second conductivity type may be an N type or a P type. In the present embodiment, the first conductivity type is N-type; the second conductivity type is P-type as an example, but the invention is not limited thereto.

Figure 3 is a cross-sectional view showing a second embodiment of the line I-I of Figure 1.

Referring to FIG. 3, the metal oxide half field effect transistor 200 of the second embodiment of the present invention is similar to the gold oxide half field effect transistor 100 of the first embodiment, and the difference is that the insertion of the gold oxide half field effect transistor 200 is performed. The hybrid layer 202 is further located in the substrate 10 that is not covered by the gate structure 15. In detail, the interposer layer 202 is not only located on the top doping region 14 between the gate structure 15 and the drain region 20, but also in the drain region 20, the source region 22, the fourth doping region 28, and the The second doped region 30, the third doped region 32, the heavily doped region 36, the sixth doped region 42, the seventh doped region 44, and the eighth doped region 46. Additionally, the intervening doped layer 202 is also located in the substrate 10 below the isolation structure 24b and the isolation structure 24c.

4A to 4G are schematic cross-sectional views showing the manufacturing flow of Fig. 2.

Referring to FIG. 4A, a first doping region 12, a second doping region 30, and a seventh doping region 44 are formed in the substrate 10. The substrate 10 is, for example, a semiconductor substrate 10a and an epitaxial layer 10b has been formed on the semiconductor substrate 10a. The semiconductor substrate 10a is a P-type substrate, and the epitaxial layer 10b is an N-type epitaxial layer (N-epi). The first doping region 12, the second doping region 30, and the seventh doping region 44 may respectively form an ion implantation mask on the substrate 10, and implant the dopant into the epitaxial layer 10b by ion implantation. And then through the tempering process to form. The order in which the first doping region 12, the second doping region 30, and the fifth doping region 44 are formed may be adjusted according to actual needs, and is not particularly limited. Doping dose of the first doped region 12, for example, ^{5 × 10 11 ~ 2 × 10} 13 / cm 2. The doping amount of the second doping region 30 is, for example, 1 × 10 ¹² to 5 × 10 ¹³ /cm ² . A pad oxide layer 50 may be formed on the substrate 10 prior to the ion implantation process. The method of forming the pad oxide layer 50 is, for example, a thermal oxidation method.

Thereafter, referring to FIG. 4B, a third doping region 32 is formed in the second doping region 30. The third doping region 32 may also form an ion implantation mask first, and the dopant is implanted into the second doping region 30 by ion implantation, and then formed by a tempering process. The doping amount of the third doping region 32 is, for example, 5 × 10 ¹² to 1 × 10 ¹⁴ /cm ² .

Thereafter, a mask layer 52 is formed on the pad oxide layer 50. The mask layer 52 has a plurality of openings 54. An isolation structure is predetermined on the substrate 10 below the opening 54. Thereafter, a patterned mask layer 56 is formed on the substrate 10. The patterned mask layer 56 can include at least three regions. Each zone has a plurality of openings 58. The size of the above-described opening 58 of each zone is gradually reduced from the predetermined gate formation to the predetermined formation of the drain region (Fig. 4B is left to right). The spacing between the aforementioned openings 58 of each zone (i.e., the patterned mask layer 56) tapers from the predetermined gate formation to the predetermined formation of the drain region (Fig. 4B from left to right). The patterned mask layer 56 can be a hard mask or a photoresist layer. The material of the hard mask layer is, for example, tantalum nitride, and the method of forming is, for example, via chemical vapor deposition. The mask material layer is deposited by the integrated method and then patterned by lithography and etching. If a photoresist material is used as the mask layer, it can be directly patterned by lithography.

Thereafter, the patterned mask layer 56 is used as an ion implantation mask to perform a single ion implantation process, and the dopant is implanted in the first doping region 12 to form in the first doping region 12. A plurality of doped regions 64. Two adjacent doped regions 64 overlap each other under the corresponding patterned mask layer 56 to form an overlap region 60. The size of the overlap region 60 is related to the spacing between adjacent two openings 58 (i.e., the patterned mask layer 56).

Then, referring to FIG. 4C, the patterned mask layer 56 is removed. Then temper. When tempering is performed, the overlap region 60 is uniformly diffused, and the top doped region 14 is formed together with the non-overlapping region. The tempering temperature is, for example, 900 degrees Celsius to 1150 degrees Celsius.

In one embodiment, the dopant concentration gradient of each region of the top doped region 14 is linear. That is, the dopant concentration from the predetermined gate to the predetermined formation of the drain region (from left to right in FIG. 4C) is linearly decreasing. Each region of the top doped region 14 is gradually reduced in depth from a predetermined gate formation to a predetermined formation of the drain region (from left to right in the drawing), and the contour of the bottom portion of the top doped region 14 is smooth and substantially linear. In addition, the doping concentration gradient of the top doping region 14 is different in each region. Through the adjustment of the size and spacing of the mask opening, a single ion implantation process can be used to form different dopant concentration gradients in a single or multiple regions, which greatly simplifies the process without increasing the process cost. In one embodiment, the top doped region 14 has a doping concentration near the predetermined gate structure 15 of 1.67×10 ¹⁶ to 2.5×10 ¹⁷ /cm ³ and a depth of 2 to 3 μm; The doping concentration at the region 20 is 3 × 10 ¹⁵ to 1.67 × 10 ¹⁷ /cm ³ and the depth is 0.3 to 1 μm.

Thereafter, a heavily doped region 36 is formed in the fourth doped region 28, and a heavily doped region 34 is formed in the third doped region 32. The method for forming the heavily doped regions 34 and 36 can also form an ion implantation mask first, and implant the dopants into the fourth doping region 28 and the third doping region 32 by ion implantation, respectively, and then pass back through. The fire process is formed.

Thereafter, referring to FIG. 4D, a top doped region 104 is formed on the top doped region 14. In detail, the patterned mask layer 62 is used as an ion implantation mask to perform a single ion implantation process, and the dopant is implanted on the top doping region 14 to form on the top doping region 14. Top doped region 104. The top doped region 104 partially overlaps the top doped region 14. In one embodiment, the top doped region 104 has a doping concentration of 2 x 10 ¹⁵ /cm ³ to 6 x 10 ¹⁶ /cm ³ and a depth of 0.4 to 0.8 μm.

Referring to FIGS. 4D and 4E, after the patterned mask layer 62 is removed, isolation structures 24a, 24b, 24c are formed on the substrate 10. The method of forming the isolation structures 24a, 24b, 24c may utilize a local thermal oxidation process to form a local thermal oxide layer in the exposed openings 54 of the mask layer 52. The mask layer 52 and the pad oxide layer 50 are then removed. However, the invention is not limited thereto.

Next, referring to FIG. 4F, a gate structure 15 is formed on the substrate 10. The gate structure 15 includes a gate dielectric layer 18 and a gate 16. The gate dielectric layer 18 can be formed from a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. A low dielectric constant material refers to a dielectric material having a dielectric constant of less than 4, such as cerium oxide or cerium oxynitride. The high dielectric constant material refers to a dielectric material having a dielectric constant higher than 4, such as HfAlO, HfO ₂ , Al ₂ O ₃ or Si ₃ N ₄ . The thickness of the gate dielectric layer 18 varies depending on the choice of dielectric material. For example, if the gate dielectric layer 18 is yttria, the thickness can be from 12 nm to 200 nm. The gate 16 is a conductive material such as a metal, polysilicon, doped polysilicon, polycrystalline metal or a combination thereof. The gate dielectric layer 18 and the gate electrode 16 can be formed by first forming a gate dielectric material layer and a gate conductor, and then patterning by a lithography and etching process. Thereafter, a drain region 20 and a source region 22 are formed in the heavily doped regions 34, 36, respectively. In one embodiment, the doping amount of the drain region 20 and the source region 22 is, for example, 5 × 10 ¹⁴ to 8 × 10 ¹⁵ /cm ² .

Next, a patterned mask layer 66 is formed on the substrate 10. The patterned mask layer 66 exposes the surface of the isolation structure 24a between the drain region 20 and the gate structure 15. With the patterned mask layer 66 as a mask, an ion implantation process is performed to form an intercalation doping layer 102 on the top doping region 14. In detail, the interposer doping layer 102 partially overlaps the top doping region 14 and the top doping region 104, respectively. In an embodiment, the partially doped doped layer 102 may also be formed in the fourth doped region 28 and the heavily doped region 36. In one embodiment, the doping layer 102 has a doping concentration of 6×10 ¹⁵ /cm ³ to 2×10 ¹⁷ /cm ³ and a depth of 200 nm to 500 nm. The patterned mask layer 66 can be a hard mask layer or a photoresist layer. The material of the hard mask layer is, for example, tantalum nitride, metal salicide or a combination thereof. Next, the patterned mask layer 66 is removed.

Referring to FIG. 4G, metal interconnects 106, 108, 110, 112 are formed on the substrate 10. The metal interconnect 106 is electrically connected to the drain region 20. The metal interconnect 108 is electrically connected to the source region 22. The metal interconnect 110 is electrically connected to the sixth doped region 42. The metal interconnect 112 is electrically connected to the eighth doped region 46. Metal interconnect 106 There is at least one opening 114 between the metal interconnect 108 and the metal interconnect 108. The opening 114 is disposed above the top doping region 14. In an embodiment, the material of the metal interconnects 106, 108, 110, 112 may be, for example, aluminum, copper, or a combination thereof.

5A to 5B are schematic cross-sectional views showing the manufacturing flow of Fig. 3.

Referring to FIG. 5A, the substrate 10, the first doping region 12, the second doping region 30, the third doping region 32, the fourth doping region 28, and the rich doping are formed according to the manufacturing method of FIGS. 4A to 4E. The doped regions 34, 36, the top doped region 14, the gate structure 15, the drain region 20, the source region 22, the isolation structures 24a, 24b, 24c, and the top doped region 104. Next, the substrate 10 is subjected to an ion implantation process to form an intercalation doping layer 202 in the substrate 10 that is not covered by the gate structure 15. In detail, the intervening doped layer 202 is not only located on the top doping region 14 between the gate structure 15 and the drain region 20, but also in the drain region 20, the source region 22, the fourth doping region 28, The second doped region 30, the third doped region 32, the heavily doped region 36, the sixth doped region 42, the seventh doped region 44, and the eighth doped region 46. Additionally, the intervening doped layer 202 is also located in the substrate 10 below the isolation structure 24b and the isolation structure 24c. Thus, the insertion of the doped layer 202 can balance the interface charge between the isolation structure 24b and the substrate 10 under the isolation structure 24c. In addition, the doped layer 202 may also balance the drain region 20, the source region 22, the fourth doping region 28, the second doping region 30, the third doping region 32, the heavily doped region 36, and the sixth doping. The fixed charge in the impurity region 42, the seventh doping region 44, and the eighth doping region 46 is to improve product reliability. In one embodiment, the doping layer 202 has a doping concentration of 6×10 ¹⁵ /cm ³ to 2×10 ¹⁷ /cm ³ and a depth of 200 nm to 500 nm.

Referring to FIG. 5B, a metal is formed on the substrate 10 as described above with reference to FIG. 4G. The interconnects 106, 108, 110, 112. The material and connection relationship of the metal interconnects 106, 108, 110, 112 are described in the above paragraphs, and will not be described herein.

In summary, the gold-oxygen half field effect transistor of the present invention balances the interface charge between the isolation structure and the substrate by inserting a doped layer in the top doped region, and isolates the fixed charge in the structure to enhance the product. Reliability. Alternatively, the intervening doped layer can be located not only in the top doped region between the gate structure and the drain region, but also in the substrate not covered by the gate structure. Therefore, the insertion of the doped layer can also balance the fixed charges in the drain region, the source region, and other doped regions, further improving product reliability. In addition, the gold-oxygen half field effect transistor of the present invention further comprises an N-type top doping region between the P-type interposer and the P-type doped region, which can reduce the on-state resistance of the MOS field-effect transistor. .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 10a, 10b‧‧‧ base

12‧‧‧First doped area

14‧‧‧Top doped area

15‧‧‧ gate structure

16‧‧‧ gate

18‧‧‧gate dielectric layer

20‧‧‧Bungee Area

22‧‧‧ source area

24a, 24b, 24c‧‧‧ isolation structure

28‧‧‧Four doped area

30‧‧‧Second doped area

32‧‧‧ Third doped area

34, 36‧‧‧Densely doped area

42‧‧‧ sixth doping area

44‧‧‧ seventh doped area

46‧‧‧ eighth doped area

114‧‧‧ openings

100‧‧‧Gold oxygen half-field effect transistor

102‧‧‧ Insert doped layer

104‧‧‧Top doped area

106, 108, 110, 112‧‧‧Metal interconnection

Claims (20)

A gold-oxygen half-field effect transistor, comprising: a drain region having a first conductivity type, located in a substrate; a source region having the first conductivity type, located in the substrate, surrounding the drain region Surrounding; a gate structure on the substrate between the drain region and the source region; a first top doped region having a second conductivity type, located in the source region and the drain region Between the substrates; and an intervening doped layer having the second conductivity type on the first top doped region between the gate structure and the drain region. The gold oxide half field effect transistor of claim 1, wherein the intervening doped layer at least partially overlaps the first top doped region. The gold oxide half field effect transistor of claim 1, wherein the intervening doped layer is further located in the substrate not covered by the gate structure. The gold oxide half field effect transistor of claim 1, wherein the Gaussian distribution of the doping concentration of the intercalated doping layer is different from the Gaussian distribution of the doping concentration of the first top doping region. The gold oxide half field effect transistor according to claim 1, wherein the intercalation doping layer has an ion implantation depth of between 200 nm and 500 nm. The gold-oxygen half-field effect transistor according to claim 1, wherein the doping layer has a doping concentration of between 6×10 ¹⁵ /cm ³ and 2×10 ¹⁷ /cm ³ . For example, the gold-oxygen half-field effect transistor described in claim 1 of the patent scope includes A second top doped region having the first conductivity type is located between the intervening doped layer and the first top doped region. The gold-oxygen half-field effect transistor according to claim 1, further comprising: a first doped region having the first conductivity type, located in the substrate around the drain region, such that the first top a doped region and the drain region are located in the first doped region; a second doped region having the first conductivity type, located in the substrate around the source region; and a third doped region having The second conductivity type is located in the first conductivity type second doping region; a fourth doping region having the first conductivity type is located in the first conductivity type first doping region, and the first a top doped region is adjacent to each other; the second doped region has the first conductivity type, respectively located in the fourth doped region and the third doped region, and the source region and the drain region are respectively Located therein; and a fifth doped region having the second conductivity type, the fifth doped region adjoining the drain region. The gold-oxygen half-field effect transistor according to claim 1, further comprising an isolation structure on the top doped region, wherein a portion of the gate structure covers a portion of the isolation structure. The gold-oxygen half-field effect transistor according to claim 1, further comprising: a first metal interconnect, electrically connected to the drain region; a second metal interconnect is electrically connected to the source region, wherein the first metal interconnect and the second metal interconnect have at least one opening, the opening being located in the first top doped region Above. A method for manufacturing a gold-oxygen half-field effect transistor, comprising: forming a gate structure on a substrate; forming a drain region having a first conductivity type in the substrate on a first side of the gate structure; Forming a source region having the first conductivity type in the substrate on a second side of the gate structure, the source region surrounding the drain region; and the source region and the drain region Forming a first top doped region having a second conductivity type in the substrate; and forming the second conductivity type on the first top doping region between the gate structure and the drain region An intervening layer is interposed, wherein the intervening doped layer partially overlaps the first top doped region. The method for fabricating a gold oxide half field effect transistor according to claim 11, wherein the method for forming the intercalation doping layer comprises: performing an ion on the substrate after forming the drain region and the source region An implantation process is formed to form the intercalated doped layer in the substrate not covered by the gate structure. The method for manufacturing a gold-oxygen half-field effect transistor according to claim 12, wherein the ion implantation process has an ion implantation depth of between 200 nm and 500 nm, and an ion implantation concentration of 6×10 ¹⁵ / cm ³ to 2 × 10 ¹⁷ / cm ^3. The method for fabricating a gold-oxygen half field effect transistor according to claim 11, further comprising forming an isolation structure on the first top doped region, wherein a portion of the gate structure covers a portion of the isolation structure. The method for fabricating a gold-oxygen half-field effect transistor according to claim 14, wherein the method of forming the intervening doped layer comprises: forming a patterned mask layer on the substrate, the patterned mask The layer exposes the isolation structure between the drain region and the gate structure; using the patterned mask layer as a mask, performing an ion implantation process to form the insertion doping layer; and removing the Patterned mask layer. The method for manufacturing a gold oxide half field effect transistor according to claim 15, wherein the ion implantation process has an ion implantation depth of between 200 nm and 500 nm, and the ion implantation concentration is between 6×10 ¹⁵ / Cm ³ to 2 × 10 ¹⁷ /cm ³ . The method for fabricating a gold-oxygen half field effect transistor according to claim 11, after forming the first top doping region, further comprising forming between the interposer doped layer and the first top doped region. A second top doped region having the first conductivity type. The method for manufacturing a gold-oxygen half field effect transistor according to claim 11, further comprising: forming a first doped region having the first conductivity type in the substrate around the drain region; The first top doping region and the drain region are located in the first doping region; a second doping region having the first conductivity type is formed in the substrate around the source region; Forming a third doped region having the second conductivity type in the second doped region; forming a fourth doped region having the first conductivity type in the first doped region, the fourth a doped region is adjacent to the first top doped region; and a concentrated doped region having the first conductive type is formed in the fourth doped region and the third doped region, respectively, to enable the source region It is located in the bungee zone. The method for fabricating a gold oxide half field effect transistor according to claim 18, wherein an epitaxial layer having the first conductivity type is formed in the substrate, the first doping region and the second doping layer. The area is located in it. The method for manufacturing a gold-oxygen field-effect transistor according to claim 11, after forming the interposer layer, further comprising: forming a first metal interconnect on the substrate, electrically connected to a draining region; and forming a second metal interconnect on the substrate, electrically connected to the source region, wherein the first metal interconnect and the second metal interconnect have at least one An opening located above the first top doped region.