CN106298930A - Metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- CN106298930A CN106298930A CN201610012076.5A CN201610012076A CN106298930A CN 106298930 A CN106298930 A CN 106298930A CN 201610012076 A CN201610012076 A CN 201610012076A CN 106298930 A CN106298930 A CN 106298930A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title abstract description 12
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 5
- 150000004706 metal oxides Chemical class 0.000 title abstract description 5
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 230000005669 field effect Effects 0.000 claims abstract description 43
- 238000003780 insertion Methods 0.000 claims abstract description 18
- 230000037431 insertion Effects 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000002955 isolation Methods 0.000 claims description 35
- 238000000059 patterning Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000009826 distribution Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 7
- 238000011109 contamination Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000005496 tempering Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a metal oxide semiconductor field effect transistor and a manufacturing method thereof. The metal oxide semiconductor field effect transistor includes: the semiconductor device includes a drain region having a first conductivity type, a source region having the first conductivity type, a gate structure, a first top doped region having a second conductivity type, and an intervening doped layer having the second conductivity type. The drain region is located in the substrate. The source region is located in the substrate and surrounds the drain region. The gate structure is located on the substrate between the drain region and the source region. The first top doped region is located in the substrate between the source region and the drain region. The insertion doped layer is positioned on the first top doped region between the gate structure and the drain region.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and in particular to a kind of metal-oxide
Semiconductor field effect transistor and manufacture method thereof.
Background technology
It is said that in general, high voltage device is mainly applied switches (Power switch) circuit at power, such as every power supply
Managing device provide on and off switch switching be used.There is about two kinds of parameters the market of power switching at present: breakdown potential
Pressure (Breakdown voltage) and opening resistance (ON-state resistance), can be along with different demands
Fixed.The main target designing high voltage device is then to reduce opening resistance, and keeps high-breakdown-voltage simultaneously.Thing
In reality, designer is to reach the specification requirement of breakdown voltage, it will usually sacrifice opening resistance, therefore breakdown potential
Pressure and opening resistance are in a kind of trade-off relationship.
When carrying out reliability test, the charge balance in high voltage device is one of key factor controlling breakdown voltage.
And the reason that affects charge balance is as follows: (Passivation contamination), packing colloid (Molding are polluted in passivation
And process contamination (Process contamination) compound).Develop preferably passivation material and
While packing colloid material, how to provide a kind of high voltage device and manufacture method thereof, to maintain the electricity in high voltage device
Lotus balances, and then improving product reliability will become a following important subject topic.
Summary of the invention
The present invention provides a kind of mos field effect transistor and manufacture method thereof, and it can maintain metal oxygen
Charge balance in compound semiconductor field effect transistor, and then improving product reliability.
The present invention provides a kind of mos field effect transistor, including: there is the drain electrode of the first conductivity type
District, there is the source area of the first conductivity type, grid structure, there is the first top doped region and having of the second conductivity type
The insertion doped layer of the second conductivity type.Drain region is positioned in substrate.Source area is positioned in substrate, and is surrounded on drain region
Around.On grid structure substrate between drain region and source area.First top doped region is positioned at source area and drain electrode
In substrate between district.Insert on the doped layer the first top doped region between grid structure and drain region.
The present invention provides the manufacture method of a kind of mos field effect transistor, and its step is as follows.In lining
Grid structure is formed at the end.The drain region with the first conductivity type is formed in the substrate of the first side of grid structure.In
The substrate of the second side of grid structure is formed the source area with the first conductivity type.Source area is surrounded on drain region week
Enclose.Substrate between source area and drain region is formed the first top doped region with the second conductivity type.Tie in grid
The insertion doped layer with the second conductivity type is formed on the first top doped region between structure and drain region.Insert doped layer with
First top doped region partly overlaps.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Accompanying drawing explanation
Fig. 1 is according to a kind of mos field effect transistor depicted in one embodiment of the invention
Top view.
Fig. 2 is the generalized section of the first embodiment of the I-I hatching of Fig. 1.
Fig. 3 is the generalized section of the second embodiment of the I-I hatching of Fig. 1.
Fig. 4 A to Fig. 4 G is the generalized section of the manufacturing process of Fig. 2.
Fig. 5 A to Fig. 5 B is the generalized section of the manufacturing process of Fig. 3.
Drawing reference numeral
10,10a, 10b: substrate
12: the first doped regions
14: top doped region
15: grid structure
16: grid
18: gate dielectric layer
20: drain region
22: source area
24a, 24b, 24c: isolation structure
28: the four doped regions
30: the second doped regions
32: the three doped regions
34,36: dense doped region
42: the six doped regions
44: the seven doped regions
46: the eight doped regions
50: pad oxide
52: mask layer
54,58,114: opening
56,62,66: the mask layer of patterning
60: overlapping region
64: doped region
100,200: mos field effect transistor
102,202: insert doped layer
104: top doped region
106,108,110,112: metal interconnecting
Detailed description of the invention
Fig. 1 is according to a kind of mos field effect transistor depicted in one embodiment of the invention
Top view.Fig. 2 is the generalized section of the first embodiment of the I-I hatching of Fig. 1.For the sake of understanding for drawing,
Fig. 1 only shows source area, drain region and top doped region.
Refer to Fig. 1, Fig. 2, the mos field effect transistor 100 of one embodiment of the invention includes
Grid structure 15, source area 22, drain region 20 and top doped region 14.Drain region 20 is positioned in substrate 10.
In another embodiment, above-mentioned mos field effect transistor 100 can further include the first doped region
12, the second doped region the 30, the 3rd doped region the 32, the 4th doped region 28 and dense doped region 34,36.
Substrate 10 can be Semiconductor substrate 10a, e.g. silicon substrate.Substrate 10 can be there is p-type doping
Or n-type doping.P-type doping can be Group IIIA ion, e.g. boron ion.N-type doping can be VA race
Ion e.g. arsenic ion or phosphonium ion.In an alternative embodiment of the invention, substrate 10 can also include quasiconductor
Substrate 10a and the epitaxial layer 10b being positioned above.In this embodiment, Semiconductor substrate 10a is P type substrate,
Epitaxial layer 10b can be N-type epitaxy layer (N-epi).
First doped region 12 (the such as first N-type trap) has the first conductivity type, is positioned in substrate 10, makes top adulterate
District the 14, the 4th doped region (the such as second N-type trap) 28, dense doped region 36 are located therein with drain region 20.The
Four doped regions 28 have the first conductivity type, adjacent with top doped region 14.The doping content of the 4th doped region 28 is higher than
First doped region 12.
Dense doped region 36 has the first conductivity type, is positioned at the 4th doped region 28.The doping content of dense doped region 36
Higher than the 4th doped region 28, in order to reduce series resistance.
Drain region 20 has the first conductivity type, is positioned among dense doped region 36.The doping content of drain region 20 is higher than
Dense doped region 36.Drain region 20 projects to the shape on substrate 10 surface e.g. U-shaped at least one.Real at another
Executing in example, the shape that drain region 20 projects to substrate 10 surface can be by two U-shaped or more U-shaped institute structures
Become, or other shapes, but the present invention is not limited to this.
Second doped region (can be such as HVNW) 30 has the first conductivity type, is positioned in substrate 10.Second doping
District 30 makes the 3rd doped region (such as p-type trap) 32, dense doped region 34 and source area 22 be located therein.3rd
Doped region 32 has the second conductivity type, is positioned among the second doped region 30.Dense doped region 34, is positioned at the 3rd doping
In district 32, in order to reduce series resistance.
Grid structure 15 includes grid 16 and gate dielectric layer 18.Grid 16 is positioned at source area 22 and drain region 20
Between substrate 10 on.More specifically, in one embodiment, grid 16 is from source area 22, to drain region
20 directions extend, and cover the first doped region 12 and the top doped region 14 of part.In another embodiment, grid
16 from source area 22, covers dense doped region the 34, the 3rd doped region the 32, second doped region the 30, first doped region
12 and part top doped region 14.Grid 16 is conductive material such as metal, polysilicon, DOPOS doped polycrystalline silicon, polycrystalline
Metal silicide or the stack layer of a combination thereof.In one embodiment, grid structure 15 and top doped region 14 between with
Isolation structure (or referred to as drift isolation structure) 24a is separated by.By grid structure 15 covering part isolation structure 24a
Framework, the position of maximum field intensity can be made in the electric field formed between drain region 20 and source area 22 toward isolation
Offset below structure 24a, rather than fall below gate dielectric layer 18, it is to avoid the gate dielectric layer 18 of thinner thickness is too strong
Electric field breakdown.Isolation structure 24a e.g. partial thermal oxidation isolation structure, its material is insulant, e.g.
Silicon oxide.Gate dielectric layer 18 is between grid 16 and substrate 10.
Top doped region 14 has the second conductivity type, is positioned at the first side of grid structure 15.More specifically, top doping
It is in the district 14 first doped region 12 between grid structure 15 and drain region 20, adjacent with the 4th doped region 28,
And the top doped region 14 of part is overlapping with grid structure 15.In one embodiment, the doping in the doped region 14 of top is dense
Degree gradient can be linearly.That is, the doping content in the doped region 14 of top drains to close from grid structure 15
At district 20 the most decrescence.Push up the doped region of doped region 14 from grid structure 15 to drain region 20 degree of depth decrescence,
The profile of the bottom of top doped region 14 is substantially linear.In one embodiment, the doped region of top doped region 14 is from grid
Electrode structure 15 to drain region 20 degree of depth also can be identical.
It should be noted that in the present embodiment, mos field effect transistor 100 further includes to be had
The inserting doped layer 102 and there is the top doped region 104 of the first conductivity type of second conductivity type.Insert doped layer 102
Between grid structure 15 and drain region 20, and on the top doped region 14 of the lower section being positioned at isolation structure 24a and
Insert doped layer 102 to partly overlap with top doped region 14.Insert the degree of depth of doped layer 102 e.g. less than 500nm.
In one embodiment, the degree of depth e.g. 200nm～500nm of doped layer 102 is inserted.Owing to inserting doped layer 102
On the top doped region 14 of the lower section being positioned at isolation structure 24a, it can balance between isolation structure 24a and substrate 10
Interface charge, with improving product reliability.Additionally, formed insert doped layer 102 time, its admixture also can penetrate every
From structure 24a.Therefore, the part admixture penetrating isolation structure 24a also can balance the fixing electricity in isolation structure 24a
Lotus, with improving product reliability.In one embodiment, Gauss distribution and the top of the doping content of doped layer 102 are inserted
The Gauss distribution of the doping content of doped region 14 is different.Specifically, at doping depth (that is the end face of substrate 10
Downwardly extend distance) it is between 200nm～500nm, the doping content inserting doped layer 102 can be more than top doped region
The doping content of 14.In the present embodiment, top doped region 14 can be with charge balance so that element reaches its breakdown potential
Pressure.Inserting doped layer 102 is then can to resist passivation pollution, packing colloid and process contamination, with lift elements
Reliability.
In one embodiment, top doped region 104 is inserting between doped layer 102 and top doped region 14 and isolation
Between structure 24a and top doped region 14.Top doped region 104 can reduce mos field effect transistor
The opening resistance of 10.But the present invention is not limited, in other embodiments, top doped region can be also formed without
104 in inserting between doped layer 102 and top doped region 14.
Source area 22 has the first conductivity type, among the dense doped region 34 of the second side being positioned at grid structure 15.Source
The doping content of polar region 22 is higher than dense doped region 34.Source area 22 is surrounded on around drain region 20.More specifically,
Source area 22 is surrounded on the periphery of top doped region 14.
It addition, the 3rd doped region 32 of above-mentioned mos field effect transistor 100 also includes having
6th doped region 42 of the second conductivity type, it is in order to the contact as the 3rd doped region 32.Additionally, at substrate 10
Include the 7th doped region 44 and the 8th doped region 46 (being illustrated in Fig. 2).7th doped region 44 has the second conduction
Type, is positioned at around the second doped region 30.8th doped region 46 has the second conductivity type, is positioned at the 7th doped region 44
Among.Between 6th doped region 42 and the 8th doped region 46, there is isolation structure 24b；And the 8th doped region 46
Opposite side also has isolation structure 24c.
Additionally, mos field effect transistor 100 further include metal interconnecting 106,108,110,
112.Metal interconnecting 106 is electrically connected to drain region 20.Metal interconnecting 108 is electrically connected to source area 22.Metal
Intraconnections 110 is electrically connected to the 6th doped region 42.Metal interconnecting 112 is electrically connected to the 8th doped region 46.Metal
There is between intraconnections 106 and metal interconnecting 108 at least one opening 114.Opening 114 is configured at top doped region 14
Top.Being positioned at the metal interconnecting 106,108 above isolation structure 24a, it is except in order to connect as in metal
Outside line, can also be regarded as field plate.Therefore, it is positioned at the metal interconnecting 106,108 above isolation structure 24a can drop
Low surface field, effectively to promote breakdown voltage and to reduce opening resistance.In one embodiment, user can
Adjust the size pushing up the opening 114 above doped region 14 on demand, with breakdown voltage and the unlatching of optimization element
State resistance.Although the only only two-layer conductor layer of the metal interconnecting 106,108,110,112 in Fig. 2, but this
Invention is not limited, and in other embodiments, metal interconnecting 106,108,110,112 also can be one layer leads
Body layer or multi-layer conductive layer.
Above-mentioned first conductivity type can be p-type or N-type；Above-mentioned second conductivity type can be N-type or p-type.At this
In embodiment, it is with the first conductivity type as N-type；Second conductivity type is it to be described as a example by p-type, but, the present invention
This is not limited.
Fig. 3 is the generalized section of the second embodiment of the I-I hatching of Fig. 1.
Refer to Fig. 3, the mos field effect transistor 200 and first of second embodiment of the invention is real
The mos field effect transistor 100 executing example is similar, and its difference is: metal-oxide is partly led
The doped layer 202 that inserts of body field-effect transistor 200 is more positioned in the substrate 10 not covered by grid structure 15.
In detail, insert doped layer 202 and be not only located on the top doped region 14 between grid structure 15 and drain region 20,
More it is positioned at drain region 20, source area the 22, the 4th doped region the 28, second doped region the 30, the 3rd doped region 32, dense
On doped region the 36, the 6th doped region the 42, the 7th doped region 44 and the 8th doped region 46.It addition, insert doping
Layer 202 is also positioned in the substrate 10 below isolation structure 24b and isolation structure 24c.
Fig. 4 A to Fig. 4 G is the generalized section of the manufacturing process of Fig. 2.
Refer to Fig. 4 A, substrate 10 is formed the first doped region the 12, second doped region 30 and the 7th doped region
44.Epitaxial layer 10b has been formed in substrate 10 e.g. Semiconductor substrate 10a and Semiconductor substrate 10a.Quasiconductor
Substrate 10a is P type substrate, and epitaxial layer 10b is N-type epitaxy layer (N-epi).First doped region 12, second mix
Miscellaneous district 30 and the 7th doped region 44 can be initially formed the most over the substrate 10 and mask is ion implanted, and utilize ion to plant
Enter after admixture is implanted in epitaxial layer 10b by method, then form it by tempering process.First doped region 12,
The formation order of two doped regions 30 and the 5th doped region 44 can need adjustment according to actual, there is no particularly limit
System.The dopant dose e.g. 5 × 10 of the first doped region 1211/cm2～2 × 1013/cm2.The doping of the second doped region 30
Dosage e.g. 1 × 1012/cm2～5 × 1013/cm2.Before carrying out ion implantation technology, over the substrate 10 can be first
Form pad oxide 50.The forming method of pad oxide 50 e.g. thermal oxidation method.
Afterwards, refer to Fig. 4 B, the second doped region 30 is formed the 3rd doped region 32.3rd doped region 32 is also
Can be initially formed and mask is ion implanted, after utilizing ionic-implantation that admixture is implanted in the second doped region 30, then lead to
Cross tempering process to form it.The dopant dose e.g. 5 × 10 of the 3rd doped region 3212/cm2～1 × 1014/cm2。
Thereafter, pad oxide 50 forms mask layer 52.Mask layer 52 has multiple opening 54.Opening 54
Predetermined formation isolation structure on the substrate 10 of lower section.Afterwards, the mask layer 56 of patterning is formed over the substrate 10.
The mask layer 56 of patterning can include at least three kinds of regions.Each region has multiple opening 58.The above-mentioned opening in each district
At the most predetermined grid formed of the size of 58 at the most predetermined formation drain region decrescence (Fig. 4 B is from left to right).Each district
Above-mentioned opening 58 between spacing (mask layer 56 i.e. patterned) formed to predetermined at the predetermined grid formed
At drain region, (Fig. 4 B is from left to right) decrescence.The mask layer 56 of patterning can be hard mask layer (hard mask)
Or photoresist layer.The material of hard mask layer e.g. silicon nitride, the method for formation is e.g. via chemical vapour deposition technique
Deposition of mask material layer, is then patterned with photoetching and etching method.According to Other substrate materials as mask layer,
Then can directly be patterned in the way of photoetching.
Afterwards, using patterning mask layer 56 as mask is ion implanted, carry out single ionic implant technique, will mix
Matter is implanted in the first doped region 12, to form multiple doped region 64 among the first doped region 12.Two is adjacent
Doped region 64 overlaps each other below the mask layer 56 of corresponding pattern, and forms overlapping region 60.Overlapping region
Spacing (mask layer 56 i.e. patterned) between the size of 60 with adjacent two openings 58 is relevant.
Then, refer to Fig. 4 C, remove the mask layer 56 of patterning.It is tempered afterwards.When being tempered,
Overlapping region 60 can be spread uniformly, and is collectively forming top doped region 14 with Non-overlapping Domain.The temperature of tempering is such as
It it is 900 degrees Celsius to 1150 degrees Celsius.
In one embodiment, the dopant concentration gradient in each region of top doped region 14 is linearly.That is, from preboarding
The dopant concentration of (Fig. 4 C is from left to right) is formed at drain region the most decrescence to predetermined at the grid become.Top is mixed
Each region in miscellaneous district 14 forms (graphic is from left to right) degree of depth at drain region to predetermined at the predetermined grid formed
Decrescence, and the contour smoothing of the bottom of top doped region 14, it is substantially linear.Additionally, top doped region 14 is in each region
Dopant concentration gradient different.By aforementioned mask open size and the regulation and control of spacing, can be planted by single ion
Enter technique, form different dopant concentration gradients in single or multiple region, be greatly simplified technique, and work will not be increased
Skill cost.In one embodiment, top doped region 14 close to the doping content at the predetermined grid structure 15 formed is being
1.67×1016/cm3～2.5 × 1017/cm3, the degree of depth is 2 μm～3 μm；And close to the doping content at drain region 20
It is 3 × 1015/cm3～1.67 × 1017/cm3, the degree of depth is 0.3 μm～1 μm.
Afterwards, among the 4th doped region 28, form dense doped region 36, and form dense mixing in the 3rd doped region 32
Miscellaneous district 34.The forming method of dense doped region 34,36 is equally initially formed and mask is ion implanted, and is utilized respectively ion
After admixture is implanted in the 4th doped region 28 and the 3rd doped region 32 by implantation, then formed by tempering process
It.
Thereafter, refer to Fig. 4 D, on the doped region 14 of top, form top doped region 104.In detail, first with pattern
The mask layer 62 changed, as mask is ion implanted, carries out single ionic and implants technique, admixture is implanted in top doped region
On 14, to form top doped region 104 on the doped region 14 of top.Top doped region 104 partly overlaps with top doped region 14.
In one embodiment, the doping content of top doped region 104 is 2 × 1015/cm3To 6 × 1016/cm3, the degree of depth is 0.4 μm
～0.8 μm.
Refer to Fig. 4 D and Fig. 4 E, after the mask layer 62 that will be patterned into removes, form isolation structure over the substrate 10
24a、24b、24c.The forming method of isolation structure 24a, 24b, 24c can utilize partial thermal oxidation method, is covering
Partial thermal oxidation layer is formed among the opening 54 that film layer 52 is exposed.The most again by mask layer 52 and pad oxide
50 remove.But, the present invention is not limited thereto.
Then, refer to Fig. 4 F, form grid structure 15 over the substrate 10.Grid structure 15 includes gate dielectric layer
18 and grid 16.Gate dielectric layer 18 can be to be made up of single material layer.Single material layer e.g. low-k
Material or high dielectric constant material.Advanced low-k materials refers to that dielectric constant is less than the dielectric material of 4, e.g.
Silicon oxide or silicon oxynitride.High dielectric constant material refers to the dielectric material that dielectric constant is higher than 4, e.g. HfAlO,
HfO2、Al2O3Or Si3N4.The thickness of gate dielectric layer 18 is different according to the selection of different dielectric material, citing
For, if if gate dielectric layer 18 is silicon oxide, its thickness can be 12nm to 200nm.Grid 16 is conduction
Material, such as metal, polysilicon, DOPOS doped polycrystalline silicon, multi-crystal silicification metal or the stack layer of a combination thereof.Grid are situated between
After the forming method of electric layer 18 and grid 16 can be initially formed grid dielectric materials layer and grid conductor, then pass through
Photoetching patterns with etching technics.Afterwards, among dense doped region 34,36, drain region 20 and source are formed respectively
Polar region 22.In one embodiment, the dopant dose of drain region 20 and source area 22 is e.g.
5×1014/cm2～8 × 1015/cm2。
Then, on substrate 10, form the mask layer 66 of patterning.The mask layer 66 of patterning exposes drain region
The surface of the isolation structure 24a between 20 and grid structure 15.With patterning mask layer 66 as mask, carry out
Ion implantation technology, inserts doped layer 102 to be formed on the doped region 14 of top.In detail, doped layer 102 is inserted
Partly overlap with top doped region 14 and top doped region 104 respectively.In one embodiment, partial insertion doped layer 102
Also can be formed in the 4th doped region 28 and dense doped region 36.In one embodiment, mixing of doped layer 102 is inserted
Miscellaneous concentration is 6 × 1015/cm3To 2 × 1017/cm3, the degree of depth is 200nm～500nm.The mask layer 66 of patterning can
For hard mask layer or photoresist layer.The material of hard mask layer e.g. silicon nitride, metal silicide (salicide) or its
Combination.Then, the mask layer 66 of patterning is removed.
Refer to Fig. 4 G, on substrate 10, form metal interconnecting 106,108,110,112.Metal interconnecting
106 are electrically connected to drain region 20.Metal interconnecting 108 is electrically connected to source area 22.Metal interconnecting 110 is electrically connected
It is connected to the 6th doped region 42.Metal interconnecting 112 is electrically connected to the 8th doped region 46.Metal interconnecting 106 and gold
Belong to, between intraconnections 108, there is at least one opening 114.Opening 114 is configured at the top of top doped region 14.One
In embodiment, the material of metal interconnecting 106,108,110,112 can be for example aluminum, copper or a combination thereof.
Fig. 5 A to Fig. 5 B is the generalized section of the manufacturing process of Fig. 3.
Refer to Fig. 5 A, according to the manufacture method of Fig. 4 A to Fig. 4 E formed substrate the 10, first doped region 12,
Second doped region the 30, the 3rd doped region the 32, the 4th doped region 28, dense doped region 34,36, top doped region 14,
Grid structure 15, drain region 20, source area 22, isolation structure 24a, 24b, 24c and top doped region 104.
Then, substrate 10 is carried out ion implantation technology, to be formed in the substrate 10 not covered by grid structure 15
Insert doped layer 202.In detail, insert doped layer 202 to be not only located between grid structure 15 and drain region 20
Top doped region 14 on, be also located at drain region 20, source area the 22, the 4th doped region the 28, second doped region 30,
On 3rd doped region 32, dense doped region the 36, the 6th doped region the 42, the 7th doped region 44 and the 8th doped region 46.
Also it is positioned in the substrate 10 below isolation structure 24b and isolation structure 24c it addition, insert doped layer 202.Cause
This, insert doped layer 202 and can balance the boundary between the substrate 10 below isolation structure 24b and isolation structure 24c
Surface charge.Additionally, insert doped layer 202 also can balance drain region 20, source area 22, the 4th doped region 28, the
Two doped regions 30, the 3rd doped region 32, dense doped region 36, the 6th doped region 42, the 7th doped region 44 and
Fixed charge in eight doped regions 46, with improving product reliability.In one embodiment, doped layer 202 is inserted
Doping content is 6 × 1015/cm3To 2 × 1017/cm3, the degree of depth is 200nm～500nm.
Refer to Fig. 5 B, described in above-mentioned Fig. 4 G, formed on substrate 10 metal interconnecting 106,108,110,
112.The material of metal interconnecting 106,108,110,112 and annexation are to illustrate in above-mentioned paragraph, in this just
Repeat no more.
In sum, the mos field effect transistor of the present invention is by being positioned at the insertion in the doped region of top
Doped layer balances the interface charge between isolation structure and substrate, and the fixed charge in isolation structure, to promote
Production reliability.On the other hand, insert doped layer and not only can be located in the top doped region between grid structure and drain region,
Also may extend in the substrate not covered by grid structure.Therefore, insert doped layer and also can balance drain region, source electrode
Fixed charge in district and other doped regions, further improving product reliability.Additionally, the metal of the present invention
Oxide semiconductor field effect transistor further includes and inserts the N-type between doped layer and p-type top doped region in p-type
Top doped region, it can reduce the opening resistance of mos field effect transistor.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when making a little change and retouching, therefore this
The protection domain of invention is when being as the criterion depending on as defined in claim.
Claims (20)
1. a mos field effect transistor, it is characterised in that including:
One drain region, has one first conductivity type, is positioned in a substrate；
Source region, has this first conductivity type, is positioned in this substrate, be surrounded on around this drain region；
One grid structure, on this substrate between this drain region and this source area；
One first top doped region, has one second conductivity type, in this substrate between this source area and this drain region；
And
One inserts doped layer, has this second conductivity type, this first top between this grid structure and this drain region
On doped region.
2. mos field effect transistor as claimed in claim 1, it is characterised in that this insertion
Doped layer is least partially overlapped with this first top doped region.
3. mos field effect transistor as claimed in claim 1, it is characterised in that this insertion
Doped layer is more positioned in this substrate not covered by this grid structure.
4. mos field effect transistor as claimed in claim 1, it is characterised in that this insertion
The Gauss distribution of the doping content of doped layer is different from the Gauss distribution of the doping content of this first top doped region.
5. mos field effect transistor as claimed in claim 1, it is characterised in that this insertion
The degree of depth that is ion implanted of doped layer is 200nm～500nm.
6. mos field effect transistor as claimed in claim 1, it is characterised in that this insertion
The doping content of doped layer is 6 × 1015/cm3To 2 × 1017/cm3。
7. mos field effect transistor as claimed in claim 1, it is characterised in that further include
One second top doped region, has this first conductivity type, between this insertion doped layer and this first top doped region.
8. mos field effect transistor as claimed in claim 1, it is characterised in that further include:
One first doped region, has this first conductivity type, is positioned in this substrate around this drain region, makes this first top
Doped region and this drain region are positioned at this first doped region；
One second doped region, has this first conductivity type, is positioned in this substrate around this source area；
One the 3rd doped region, has this second conductivity type, is positioned among this first conductivity type second doped region；
One the 4th doped region, has this first conductivity type, is positioned in this first conductivity type first doped region, with this first
Top doped region is adjacent；
Two dense doped regions, have this first conductivity type, lay respectively in the 4th doped region and the 3rd doped region,
And make this source area and this drain region lay respectively at wherein；And
One the 5th doped region, has this second conductivity type, and the 5th doped region adjoins this drain region.
9. mos field effect transistor as claimed in claim 1, it is characterised in that further include
One isolation structure, is positioned on this top doped region, wherein this this isolation structure of grid structure covering part of part.
10. mos field effect transistor as claimed in claim 1, it is characterised in that further include:
One first metal interconnecting, is electrically connected to this drain region；And
One second metal interconnecting, is electrically connected to this source area, wherein this first metal interconnecting with in this second metal
Having at least one opening between line, this opening is positioned at the top of this first top doped region.
The manufacture method of 11. 1 kinds of mos field effect transistor, it is characterised in that including:
A grid structure is formed on a substrate；
A drain region with one first conductivity type is formed in this substrate of one first side of this grid structure；
The source region with this first conductivity type, this source electrode is formed in this substrate of one second side of this grid structure
District is surrounded on around this drain region；
This substrate between this source area and this drain region is formed the one first top doping with one second conductivity type
District；And
Formed on this first top doped region between this grid structure and this drain region and there is the one of this second conductivity type
Inserting doped layer, wherein this insertion doped layer partly overlaps with this first top doped region.
The manufacture method of 12. mos field effect transistor as claimed in claim 11, its feature
Being, the forming method of this insertion doped layer includes:
After forming this drain region and this source area, this substrate is carried out an ion implantation technology, with in not by this
This substrate that grid structure is covered is formed this insertion doped layer.
The manufacture method of 13. mos field effect transistor as claimed in claim 12, its feature
Being, the degree of depth that is ion implanted of this ion implantation technology is 200nm～500nm, and it is ion implanted concentration and is
6×1015/cm3To 2 × 1017/cm3。
The manufacture method of 14. mos field effect transistor as claimed in claim 11, its feature
Be, further include formation one isolation structure in this first top doped region on, wherein part this grid structure covering part should
Isolation structure.
The manufacture method of 15. mos field effect transistor as claimed in claim 14, its feature
Being, the forming method of this insertion doped layer includes:
Forming the mask layer of a patterning on this substrate, the mask layer of this patterning exposes this drain region and this grid
This isolation structure between structure；
With the mask layer of this patterning as mask, carry out an ion implantation technology, to form this insertion doped layer；And
Remove the mask layer of this patterning.
The manufacture method of 16. mos field effect transistor as claimed in claim 15, its feature
Being, the degree of depth that is ion implanted of this ion implantation technology is 200nm～500nm, and it is 6 × 10 that concentration is ion implanted15/cm3
To 2 × 1017/cm3。
The manufacture method of 17. mos field effect transistor as claimed in claim 11, its feature
It is, after forming this first top doped region, further includes shape between this insertion doped layer and this first top doped region
Become to have one second top doped region of this first conductivity type.
The manufacture method of 18. mos field effect transistor as claimed in claim 11, its feature
It is, further includes:
This substrate around this drain region is formed one first doped region with this first conductivity type, makes this first top
Doped region and this drain region are positioned at this first doped region；
This substrate around this source area is formed one second doped region with this first conductivity type；
One the 3rd doped region with this second conductivity type is formed among this second doped region；
Formed in this first doped region and there is one the 4th doped region of this first conductivity type, the 4th doped region with this
One top doped region is adjacent；And
A dense doped region with this first conductivity type is formed respectively in the 4th doped region and the 3rd doped region,
This source area and this drain region is made to lay respectively at wherein.
The manufacture method of 19. mos field effect transistor as claimed in claim 18, its feature
Be, formed in this substrate and there is an epitaxial layer of this first conductivity type, make this first doped region and this second mix
Miscellaneous district is located therein.
The manufacture method of 20. mos field effect transistor as claimed in claim 11, its feature
It is, after forming this insertion doped layer, further includes:
Forming one first metal interconnecting on this substrate, it is electrically connected to this drain region；And
Forming one second metal interconnecting on this substrate, it is electrically connected to this source area, wherein connects in this first metal
Having at least one opening between line and this second metal interconnecting, this opening is positioned at the top of this first top doped region.
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| CN109560119A (en) * | 2017-09-25 | 2019-04-02 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN109599439A (en) * | 2017-12-28 | 2019-04-09 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor field effect transistor |
| CN113540223A (en) * | 2020-04-22 | 2021-10-22 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
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| US5569937A (en) * | 1995-08-28 | 1996-10-29 | Motorola | High breakdown voltage silicon carbide transistor |
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| US20090273026A1 (en) * | 2002-10-03 | 2009-11-05 | Wilson Peter H | Trench-gate ldmos structures |
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| CN109560119A (en) * | 2017-09-25 | 2019-04-02 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN109560119B (en) * | 2017-09-25 | 2021-11-16 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN109599439A (en) * | 2017-12-28 | 2019-04-09 | 新唐科技股份有限公司 | Transverse diffusion metal oxide semiconductor field effect transistor |
| CN113540223A (en) * | 2020-04-22 | 2021-10-22 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
| CN113540223B (en) * | 2020-04-22 | 2023-11-10 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
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| TWI567977B (en) | 2017-01-21 |
| TW201701467A (en) | 2017-01-01 |
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