TWI531067B - Semiconductor device and method of fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

The UHV component must have a high breakdown voltage and a low on-state resistance (Ron) during operation to reduce power loss. In order to provide a higher current and maintain a sufficiently large breakdown voltage, an array structure has been developed. In the layout of AC-DC products, the array structure can reduce the layout area and improve the performance of components.

Embodiments of the present invention provide a semiconductor device and a method of fabricating the same, which can reduce the turn-on resistance and increase the breakdown voltage of the device.

Embodiments of the present invention provide a semiconductor device including a drain region, a source region, a channel region, a gate, and a composite doping region. The drain region has a first conductivity type and is located in the substrate. The source region has a first conductivity type, located in the substrate, surrounding the drain Around the area. The channel region is located in a portion of the substrate between the source region and the drain region. The gate covers the channel region and a portion of the substrate. The composite doped region is located in the substrate between the channel region and the drain region. The composite doped region includes a top doped region and a compensated doped region. The top doped region has a second conductivity type, which is located in the substrate between the channel region and the drain region, and the doping concentration of the top doping region decreases from the proximity channel region to the concentration near the drain region. The compensation doped region has a first conductivity type and is located in the top doped region to compensate for the top doped region.

Another embodiment of the present invention provides a method of fabricating a semiconductor device, comprising forming a top doped region having a second conductivity type. A compensation doping region having a first conductivity type is formed, and the compensation doping region is located in the top doping region. A drain region is formed on a first side of the top doped region, and the drain region has a first conductivity type. A source region is formed on a second side of the top doped region, the source region has a first conductivity type and surrounds the drain region, and a portion between the source region and the drain region has a channel region in the substrate. The doping concentration of the top doped region decreases from near the channel region to near the drain region.

The embodiment of the invention further provides a gold oxide half field effect transistor, which comprises a drain region, a source region, a gate, a gate dielectric layer, a compensation doping region and a top doping region. The drain region has a first conductivity type and is located in the substrate. The source region, having a first conductivity type, is located in the substrate and surrounds the periphery of the drain region. The gate is located above the substrate between the source region and the drain region. The gate dielectric layer is located between the gate and the substrate. The compensation doped region has a first conductivity type and is located in a substrate between the source region and the drain region. The top doped region, having a second conductivity type, is located below the compensation doped region, has a doping concentration gradient, and decreases in concentration from near the source to near the drain region.

The embodiment of the invention further provides a method for manufacturing a semiconductor component, which comprises An N-type doped layer is formed in the substrate. A P-type top doped region is formed in the N-type doped layer between the predetermined formation of the drain region and the channel region. An N-type doping is implanted in the top doped region to form a compensated doped region in the top doped region. An N-type drain region is formed in the N-type doped layer. A source region is formed on one side of the channel region, and the source region has an N-type conductivity type.

The embodiment of the invention further provides a method for fabricating a semiconductor device, comprising forming a first patterned mask layer on a substrate, the first patterned mask layer having a plurality of first openings. The first ion implantation process is performed with the first patterned mask layer as a mask to form a top doped region. The first patterned mask layer is removed. A second patterned mask layer is formed on the substrate, and the second patterned mask layer has a second opening to expose the top doped region. The second patterned implantation process is performed by using the second patterned mask layer as a mask to form a compensation doping region in the top doping region. The second patterned mask layer is removed. A drain region is formed on the first side of the compensation doped region, and the drain region has a first conductivity type. A source region is formed on the second side of the compensation doping region, and the source region has a first conductivity type and surrounds the drain region. The compensation doped region has a first conductivity type. The top doped region has a second conductivity type with a doping concentration gradient that decreases in concentration from near the source region to near the drain region.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Base

10a‧‧‧Semiconductor substrate

10b‧‧‧ epitaxial layer

12‧‧‧First doped area

14, 14', 75‧ ‧ compensating doped area

15, 74‧‧‧ top doped area

16‧‧‧ gate

17, 77‧‧‧Composite doped area

18‧‧‧gate dielectric layer

19‧‧‧Channel area

20‧‧‧Bungee Area

20a‧‧‧Starting

20b‧‧‧Connecting Department

20c‧‧‧ bottom

22‧‧‧ source area

24‧‧‧Isolation structure

26‧‧‧ fifth doping area

28‧‧‧Four doped area

30‧‧‧Second doped area

32‧‧‧ Third doped area

34, 36‧‧‧Densely doped area

42‧‧‧ sixth doping area

44‧‧‧ seventh doped area

46‧‧‧ eighth doped area

50‧‧‧Mat oxide layer

52, 56, 62, 82‧‧‧ patterned mask layer

54, 58, 63, 84, 88‧‧‧ openings

60, 94‧‧‧ overlapping areas

64, 90‧‧‧Doped area

100a, 100b, 100c, 100d, 200a, 200b, 200c‧‧‧ gold oxide half field effect transistor

I, II, III, IV‧‧‧ current path

FIG. 1A is a diagram of a gold-oxygen half field effect power according to a first embodiment of the present invention. Upper view of the crystal.

1B is a partial top view of a gold-oxygen half field effect transistor according to a first embodiment of the present invention, which omits the gate and isolation structure.

1C is a cross-sectional view showing a gold oxide half field effect transistor of an exemplary embodiment of the I-I tangential line of FIG. 1A.

1D is a cross-sectional view showing a gold oxide half field effect transistor of another exemplary embodiment of the I-I tangential line of FIG. 1A.

2A is a top view of a gold oxide half field effect transistor according to another embodiment of the invention.

2B is a top view of a gold oxide half field effect transistor according to another embodiment of the invention.

3A to 3E are cross-sectional views showing the manufacturing flow of the I-I tangent line in Fig. 1A.

4A is a top view of a metal oxide half field effect transistor according to a second embodiment of the present invention.

4B is a partial top view of a MOS field effect transistor in accordance with a second embodiment of the present invention, omitting the gate and isolation structure.

4C is a cross-sectional view showing a gold oxide half field effect transistor of an exemplary embodiment of II-II tangent in FIG. 4A.

FIG. 5A is a top view of a gold oxide half field effect transistor according to another embodiment of the invention.

FIG. 5B is a top view of a metal oxide half field effect transistor according to another embodiment of the invention. FIG.

6A to 6E are cross-sectional views showing the manufacturing flow of the II-II tangential line in Fig. 4A.

1A is a top view of a gold oxide half field effect transistor according to a first embodiment of the present invention. 1B is a partial top view of a gold-oxygen half field effect transistor according to a first embodiment of the present invention, which omits the gate and isolation structure. 1C is a cross-sectional view showing a gold oxide half field effect transistor of an exemplary embodiment of the I-I tangential line of FIG. 1A.

In the following embodiments, the first conductivity type may be P-type or N-type; the second conductivity type may be N-type or P-type as opposed to the first conductivity type. In this embodiment, the first conductivity type is N-type; the second conductivity type is P-type as an example, but the invention is not limited thereto.

Referring to FIG. 1A, FIG. 1B and FIG. 1C, a gold-oxygen half field effect transistor 100a according to an embodiment of the invention includes a gate 16, a gate dielectric layer 18, a source region 22, a drain region 20, and a composite doping region 17 . In another embodiment, the gold oxide half field effect transistor 100a may further include a first doping region 12, a second doping region 30, a third doping region 32, a fourth doping region 28, and a heavily doped region. 34, 36.

Substrate 10 can be a semiconductor substrate, such as a germanium substrate. The substrate 10 may have a P-type doping or an N-type doping. The P-type dopant can be a Group IIIA ion, such as a boron ion. The N-type dopant may be a VA group ion such as an arsenic ion or a phosphorus ion. In another embodiment of the present invention, the substrate 10 may also include a semiconductor substrate 10a. And an epitaxial layer 10b located above it. In this embodiment, the semiconductor substrate 10a may be a P-type substrate, and the epitaxial layer 10b may be an N-type epitaxial layer (N-epi).

The first doped region 12 (eg, the first N-type well region) has a first conductivity type and is located in the substrate 10. The composite doped region 17, the fourth doped region (eg, the second N-type well region) 28, the heavily doped region 36, and the drain region 20 may be located in the first doped region 12. The fourth doped region 28 has a first conductivity type adjacent to the composite doped region 17. The doping concentration of the fourth doping region 28 is higher than that of the first doping region 12. The heavily doped region 36 has a first conductivity type and is located within the fourth doped region 28. The doping concentration of the heavily doped region 36 may be higher than that of the fourth doping region 28 to reduce the series resistance and increase the breakdown voltage.

The drain region 20 has a first conductivity type and is located in the heavily doped region 36. The doping concentration of the drain region 20 is higher than that of the heavily doped region 36. In this embodiment, the shape of the drain region 20 projected onto the surface of the substrate 10 is, for example, at least one U-shape (as shown in FIGS. 1A and 1B). In another embodiment, the shape of the drain region 20 projected onto the surface of the substrate 10 may be formed by two U-shaped or more U-shapes, or other shapes (not shown). In this embodiment, the drain region 20 can be divided into a starting portion 20a, a connecting portion 20b, and a bottom portion 20c. In the present embodiment, the corners of the starting portion 20a and the bottom portion 20c are both represented by an arc, however, the embodiment of the present invention is not limited thereto. The starting portion 20a may be a half circle, or may be other curved shapes, for example, a quarter circle, an eighth circle, and the like, and will not be described herein. In another embodiment, the starting portion 20a may also be a rectangle.

The second doped region (which may be, for example, HVNW) 30 has a first conductivity type and is located in the substrate 10. A third doped region (eg, a P-type well region) 32, a heavily doped region 34, and a source region 22 are located in the second doped region 30. The third doping region 32 has a second conductivity The type is located in the second doping region 30. The heavily doped region 34 has a first conductivity type and is located in the third doping region 32 to reduce the series resistance and increase the breakdown voltage.

Gate 16 is located on substrate 10 between source region 22 and drain region 20. More specifically, in one embodiment, the gate 16 extends from the source region 22 toward the drain region 20, covering the channel region 19, the substrate 10, the first doped region 12, and a portion of the composite doped region. 17. In another embodiment, the gate 16 is from the source region 22, covering the heavily doped region 34, the third doped region 32, the second doped region 30, the substrate 10, the first doped region 12, and a partial composite Doped region 17. The gate 16 is a stacked layer of a conductive material such as a metal, a polysilicon, a doped polysilicon, a polycrystalline metal, or a combination thereof. In one embodiment, the gate 16 and the composite doped region 17 are separated by an isolation structure (or referred to as a drift isolation structure) 24. By covering the structure of the partial isolation structure 24 through the gate 16, the position of the maximum electric field strength in the electric field formed between the drain region 20 and the source region 22 can be shifted below the isolation structure 24 instead of falling on the gate dielectric. Below layer 18, the thinner gate dielectric layer 18 is prevented from being broken by an excessive electric field. The isolation structure 24 is, for example, a partial thermal oxidation isolation structure made of an insulating material such as hafnium oxide. The gate dielectric layer 18 is between the gate 16 and the substrate 10. The material of the gate dielectric layer 18 is, for example, hafnium oxide or other dielectric material.

The source region 22 has a first conductivity type and is located in the heavily doped region 34. The doping concentration of the source region 22 is higher than that of the heavily doped region 34. The source region 22 surrounds the drain region 20 (as shown in Figures 1A and 1B). More specifically, the source region 22 surrounds the periphery of the composite doping region 17. There is a channel region 19 below the gate 16 between the source region 22 and the drain region 20.

The composite doped region 17 is located in the first doped region 12 between the channel region 19 and the drain region 20. In the present embodiment, the composite doping region 17 includes a top doping region 15 and a compensation doping region 14.

The top doped region 15 has a second conductivity type, located in the first doped region 12 between the channel region 19 and the drain region 20, adjacent to the fourth doped region 28. In the present embodiment, the top doping region 15 is a linear doping region having a doping concentration gradient, and the concentration decreases from the approaching channel region 19 to the vicinity of the drain region 20, or can be said to be from the proximity source region 22 The concentration decreases to 20 near the bungee zone. That is, the doping concentration gradient of the top doping region 15 is linear. That is, the top doped region 15 is gradually reduced in depth from the channel region 19 to the drain region 20, and the outline of the bottom portion of the top doped region 15 is substantially linear.

The compensation doped region 14 has a first conductivity type and is located in the top doping region 15. More specifically, the compensation doping region 14 is located in the top doping region 15 between the channel region 19 and the drain region 20, and the gate electrode 16 covers a portion of the compensation doping region 14 and a portion of the top doping region. Above area 15. In the present embodiment, the compensation doping region 14 may be a bulk region having a uniform doping concentration. Since the top doping region 15 and the compensation doping region 14 have opposite conductivity type doping, the doping of the compensation doping region 14 can compensate for the doping of the top doping region 15. After doping, the concentration of the surface of the composite doped region 17 is substantially uniform from the dopant region near the channel region 19 to the vicinity of the drain region 20. In an embodiment, the doping of the compensation doping region 14 can completely compensate the doping of the partial top doping region 15 and the compensating doping region 14 in the composite doping region 17 can be partially doped. After the compensation is performed 15, the other top doped regions 15 where the uncompensated (ie, not overlapped with the compensated doped regions 14) still have the second conductivity type and have a doping concentration gradient, the self-adjacent pass The concentration decreases from 19 to near the bungee zone. In this embodiment, the doping concentration gradient is also degraded from near channel region 19 to near drain region 20 before compensation of top doped region 15 to uncompensated doped region 14.

In an exemplary embodiment, the doping of the compensation doping region 14 is, for example, phosphorus or arsenic, and the doping concentration is, for example, 1.0× ^{10 16} to 1.0× ^{10 17} /cm ³ , and the depth is, for example, 0.1 to 0.5 μm; The doping of 15 is, for example, boron or boron difluoride, and the doping concentration near the predetermined channel region 19 is 1.0× ^{10 16} to 2.5× ^{10 17} /cm ³ , and the depth may be 1.5 to 3.5 μm; The doping concentration at the drain region 20 may be ⁸ × ^{10 15} to 2.0× ^{10 17} /cm ³ and the depth may be 0.6 to 2.2 μm.

Referring to FIG. 1B, the compensation doping region 14 can be divided into at least three regions according to its positional relationship with the drain region 20. In one embodiment, the shape of the drain region 20 and the source region 22 projected onto the surface of the substrate 10 is at least U-shaped; the compensation doping region 14 surrounds the U-shaped region of the drain region 20 and extends to Its U-shaped periphery. As shown in FIG. 1B, in an embodiment, the compensation doping region 14 may include at least four regions, namely a top turn region 14a, a rectangular region 14b, a bottom inner turn region 14c, and a bottom outer turn region 14d. The top turn region 14a surrounds the start portion 20a of the drain region 20. The rectangular area 14b is located around the connecting portion 20b of the drain region 20. The bottom inner turning zone 14c is located within the area enclosed by the bottom 20c of the drain region 20. The bottom outer turning portion 14d is located outside the area surrounded by the bottom portion 20c of the drain region 20. Each of the regions (14a, 14b, 14c, 14d) of the compensation doped region 14 has a concentration. The concentration of each of the regions (14a, 14b, 14c, 14d) of the compensation doped region 14 may be the same or different. Similarly, the top doping region 15 may include at least four regions corresponding to the top turn region 14a and the moment, respectively. Each of the region 14b, the bottom inner turning portion 14c, and the bottom outer turning portion 14d. Each region of the top doped region 15 has a doping concentration gradient, and the concentration and depth of each region gradually decrease from near the channel region 19 to near the drain region 20. The contour of the bottom of the top doped region 15 is substantially linear. In addition, the doping concentration gradient of the top doping region 15 is different in each region.

In addition, the third doping region 32 of the above-mentioned metal oxide half field effect transistor 100a further includes a sixth doping region 42 having a second conductivity type, which serves as a junction of the substrate 10. In addition, the seventh doping region 44 and the eighth doping region 46 may be further included in the substrate 10 (in FIGS. 1A, 1B, 2A, and 2B, the seventh doping region 44 and the eighth doping region 46 are omitted. ). The seventh doping region 44 has a second conductivity type and is located around the second doping region 30. The eighth doped region 46 has a second conductivity type and is located in the seventh doping region 44.

Referring to FIG. 1A, FIG. 1B and FIG. 1C, the composite doping region 17 of the gold-oxygen half field effect transistor 100a of the first embodiment of the present invention includes a compensation doping region 14 and a top doping region 15. The conductivity type of the compensation doping region 14 is the same as that of the source region 22 and the drain region 20, and is located in the top doping region 15 having a substantially uniform concentration from the approaching channel region 19 to the vicinity of the drain region 20. The conductivity type of the top doping region 15 is different from the conductivity type of the source region 22 and the drain region 20, and is located in the first doping region 12. Each region of the top doped region 15 has a doping concentration gradient that decreases from near the channel region 19 to near the drain region 20. Furthermore, the depth of the profile of the top doped region 15 decreases smoothly linearly from near the channel region 19 to near the drain region 20.

Referring to FIG. 1C, the gold-oxygen half field effect transistor 100a of the first embodiment of the present invention can be made under the gate 16 when a suitable bias voltage is applied to the gate 16. The channel on the surface of the third doping region 32 forms an inversion layer (channel region), and two current paths, that is, a current path I and a current path II, may be formed. More specifically, in the first current path I, electrons may pass from the source region 22, through the heavily doped region 34, the channel region 19, the second doped region 30, the substrate 10 (in this embodiment, for example, The epitaxial layer 10b) in the substrate 10 and the first doped region 12 are further flowed into the compensation doping region 14; the electrons flowing into the compensation doping region 14 are passed through the fourth doping region 28 and the heavily doped region 36. It flows into the drain region 20 to form a current path I in which the paths of electrons and current are opposite paths. In other embodiments, without the epitaxial layer 10b, the first doped region 12 and the second doped region 30 can be designed to be close to each other (not shown), even near the surface. The semiconductor substrate 10a can be bonded together, and since the semiconductor substrate 10a is doped with a lighter concentration, after the electrons flow to the second doping region 30, they can flow into the first doping region 12 along the surface below the gate, and then flow in. The doped region 14 is compensated; and the electrons flowing into the compensation doped region 14 flow into the drain region 20 via the fourth doped region 28 and the heavily doped region 36. The second current path II is electrons from the source region 22, via the heavily doped region 34, the channel region 19, the second doped region 30, and the substrate 10 (in this embodiment, for example, the protrusion in the substrate 10) The crystal layer 10b) flows into the first doping region 12, flows into the fourth doping region 28 along the contour of the top doping region 15 in the first doping region 12, and flows into the drain electrode through the heavily doped region 36. Zone 20 forms a current path II. Since the gold-oxygen half field effect transistor 100a of the first embodiment of the present invention can form two current paths during operation, the on-resistance can be lowered. Furthermore, the gold-oxygen half field effect transistor 100a of the first embodiment of the present invention can form three reduced surface field (RESURF) structures. In Figure 1C, the three reduced surface electric field structures formed include compensation doping The junction of the region 14 and the top doping region 15, the junction of the top doping region 15 and the first doping region 12, and the junction of the epitaxial layer 10b and the semiconductor substrate 10a. In other embodiments, in addition to compensating the junction of the doped region 14 and the top doped region 15 and the junction of the top doped region 15 and the first doped region 12, the third RESURF structure may be the first doping. The junction of the region 12 and the semiconductor substrate 10a. In addition, the depth of the compensation doped region 14 is very shallow, and when the device is operated, it can be completely depleted, so the breakdown voltage does not drop too much. In addition, the regions of the top doped region 15 are smoothly linearly decreasing from near the channel region 19 to near the drain region 20 to adjust the electric field distribution to increase the breakdown voltage. Therefore, the gold-oxygen half field effect transistor 100a of the first embodiment of the present invention can utilize the composite doping region 17 to lower the on-resistance and increase the consistency of the breakdown voltage.

1D is a cross-sectional view showing a gold oxide half field effect transistor of another exemplary embodiment of the I-I tangential line of FIG. 1A or FIG. 1B.

The bottom of the compensation doped region 14 of FIG. 1C above is substantially parallel to the surface of the substrate 10. However, embodiments of the invention are not limited thereto. In another embodiment, referring to FIG. 1D, the compensation doping region 14' of the gold-oxygen half field effect transistor 100b of the present embodiment is a linear doping region, and the doping concentration gradient of the linear doping region is linear. The compensation doped region 14' is gradually reduced in depth from near the channel region 19 to near the drain region 20, and the contour of the bottom portion of the compensation doped region 14' is substantially linear. The doping of the doped region 14 ′ can compensate for the doping of the top doped region 15 , and the doping concentration of the top doped region 15 can be compensated after the top doped region 15 in the composite doped region 17 is compensated. The concentration decreases near the channel region 19 to near the drain region 20. In this embodiment, the doping concentration of the top doping region 15 is also close to the channel region 19 until the undoped doping region 14' is compensated. 20 bungee areas The concentration is decreasing.

2A is a partial top view of a gold oxide half field effect transistor according to another embodiment of the invention. 2B is a partial top view of a gold oxide half field effect transistor according to another embodiment of the invention. .

Referring to FIG. 2A and FIG. 2B , in another embodiment, the MOS field-effect transistor 100c may further include a fifth doping region 26 having a second conductivity type, adjacent to the drain region 20 and the fifth doping region 26 . It can be located within the area enclosed by the bungee region 20 (as shown in Figure 2A). Referring to FIG. 2B, in yet another embodiment, the MOS field-effect transistor 100d can have a fifth doped region 26 of a second conductivity type that can be located around the drain region 20 within the heavily doped region 36.

3A-3E are cross-sectional views showing a manufacturing process of a metal oxide half field effect transistor according to a first embodiment of the present invention.

Referring to FIG. 3A, the substrate 10 is, for example, a semiconductor substrate 10a and an epitaxial layer 10b is formed on the semiconductor substrate 10a. The semiconductor substrate 10a may be a P-type substrate, and the epitaxial layer 10b may be an N-type epitaxial layer (N-epi). A first doping region 12, a second doping region 30, and a seventh doping region 44 are formed in the substrate 10. The first doping region 12, the second doping region 30, and the seventh doping region 44 may respectively form an ion implantation mask on the substrate 10, and implant the dopant into the epitaxial layer 10b by ion implantation. And then through the tempering process to form. The order in which the first doping region 12, the second doping region 30, and the seventh doping region 44 are formed may be adjusted according to actual needs, and is not particularly limited. The doping amount of the first doping region 12 is, for example, 5× ^{10 11} to 2×10 ¹³ /cm ² . The doping amount of the second doping region 30 is, for example, 1×10 ¹² to 5×10 ¹³ /cm ² . A pad oxide layer 50 may be formed on the substrate 10 prior to performing each of the ion implantation processes described above. The method of forming the pad oxide layer 50 is, for example, a thermal oxidation method.

Thereafter, referring to FIG. 3B, a third doping region 32 is formed in the second doping region 30, and a fourth doping region 28 is formed in the first doping region 12. The third doping region 32 or the fourth doping region 28 may also form an ion implantation mask first, and implant the dopant into the second doping region 30 or the first doping region 12 by ion implantation. After that, it is formed through a tempering process. The doping amount of the third doping region 32 is, for example, 5x10 ¹² to 1x10 ¹⁴ /cm ² , and the doping amount of the fourth doping region 28 is, for example, 5.5 x 10 ¹² /cm ² .

Thereafter, a mask layer 52 is formed on the pad oxide layer 50. The mask layer 52 has a plurality of openings 54. An isolation structure 24 is predetermined on the substrate 10 below the opening 54 (Fig. 3E). Thereafter, a patterned mask layer 56 is formed on the substrate 10. The patterned mask layer 56 has a plurality of openings 58 at positions corresponding to the top turn region 14a, the rectangular region 14b, the bottom inner turn region 14c, and the bottom outer turn region 14d of FIG. 1B, respectively, exposed above the first doped region 12 Part of the pad oxide layer 50. The size of the opening 58 corresponding to the top turn zone 14a, the rectangular zone 14b, the bottom inner turn zone 14c, and the bottom outer turn zone 14d of FIG. 1B is from the predetermined channel region 19 to the predetermined formation of the drain region 20 (FIG. 3E). Decrease (Figure 3B is from left to right). The spacing between the openings 58 (i.e., the patterned mask layer 56) is gradually reduced from the channel region 19 that is intended to be formed to the predetermined formation of the drain region 20 (Fig. 3E) (Fig. 3B from left to right). The patterned mask layer 56 can be a hard mask or a photoresist layer. The material of the hard mask layer is, for example, tantalum nitride, which is formed by, for example, depositing a mask material layer by chemical vapor deposition, and then patterning it by lithography and etching. If a photoresist material is used as the mask layer, it can be straight It is patterned by lithography.

Thereafter, the patterned mask layer 56 is used as an ion implantation mask to perform an ion implantation process, and a dopant having a second conductivity type can be implanted in the first doping region 12 to be in the first doping. A plurality of doped regions 64 having a second conductivity type are formed in the impurity regions 12. The second conductivity type dopant implanted in this ion implantation process is, for example, boron or boron difluoride ion. The two adjacent doped regions 64 are formed to overlap each other under the corresponding patterned mask layer 56 to form an overlap region 60. The size of the overlap region 60 is related to the spacing between adjacent two openings 58 (i.e., the patterned mask layer 56).

Then, referring to FIG. 3C, the patterned mask layer 56 is removed. Then temper. The tempering temperature is, for example, 900 degrees Celsius to 1150 degrees Celsius. When tempering is performed, the overlap region 60 is uniformly diffused, and the top doped region 15 having the second conductivity type is formed together with the non-overlapping region. The concentration of the top doping region 15 is gradually decreased from the channel region 19 to be formed to the predetermined formation of the drain region 20 (Fig. 3E) (the figure is left to right). In an embodiment, the doping concentration gradient of the top doped region 15 is linear. That is, the doping concentration from the predetermined channel region 19 to the predetermined formation of the drain region 20 (Fig. 3E) (from left to right in the drawing) is linearly decreasing. The top doping region 15 is gradually reduced in depth from the channel region 19 which is to be formed to the predetermined formation of the drain region 20 (FIG. 3E) (from left to right in the drawing), and the contour of the bottom portion of the top doping region 15 is smooth, substantially Linear.

By controlling the size and spacing of the previously patterned mask layer 56 at the position corresponding to the top turn zone 14a, the rectangular zone 14b, the bottom inner turn zone 14c, and the bottom outer turn zone 14d of FIG. 1B, a single light can be transmitted through the single light. The hood and the single ion implantation process form different dopant concentration gradients in multiple regions, so Simplify the process without increasing process costs.

Thereafter, referring to FIG. 3D, a patterned mask layer 62 is formed on the substrate 10. A patterned mask layer 62 overlies the mask layer 52. In particular, the patterned mask layer 62 has an opening 63 that exposes the pad oxide layer 50 over the top doped region 15. The patterned mask layer 62 can be a hard mask or a photoresist layer. The material of the hard mask layer is, for example, tantalum nitride, which is formed by, for example, depositing a mask material layer by chemical vapor deposition, and then patterning it by lithography and etching. If a photoresist material is used as the mask layer, it can be directly patterned by lithography.

Thereafter, the patterned mask layer 62 is used as an ion implantation mask to perform an ion implantation process, and a dopant having a first conductivity type is implanted in the first doping region 12 to be in the top doping region. A compensation doping region 14 is formed in 15. The dopant implanted in the ion implantation process has a first conductivity type, such as arsenic or phosphorus. In an embodiment, the compensation doped region 14 has a uniform concentration and approximately the same depth near the predetermined formation of the channel region 19 to near the predetermined formation of the drain region 20. Doping concentration of the compensation region in one embodiment, isolation structures in a predetermined (drift oxide layer) 14 of, for example, at ^{1.0x10 16 ~ 1.0x10 17 / cm 3} , for example, a depth of 0.1 0.5μm ~; top doped region The doping concentration at 15 near the channel region 19 is 1.0x10 ¹⁶ ~ 2.5x10 ¹⁷ /cm ³ and the depth is 1.5 to 3.5 μm; and the doping concentration near the drain region 20 is 8x10 ¹⁵ ~ 2.0x10 ¹⁷ / Cm ³ with a depth of 0.6 to 2.2 μm. In one embodiment, the top doped region 15 (FIG. 3C) has a second conductivity type from the predetermined channel region 19 to the predetermined formation of the drain region 20 (FIG. 3E) prior to forming the compensation doped region 14. The doping concentration (from left to right) is linearly decreasing. After the compensation doping region 14 is formed, in the top doping region 15, the region overlapping the compensation doping region 14 is completely compensated by the compensation doping region 14 having different conductivity types to have the first conductivity type; The region overlapping the compensation doped region 14 is maintained to have a second conductivity type, and is doped from the channel region 19 which is formed to form a predetermined formation of the drain region 20 (Fig. 3E) (the figure is left to right). The impurity concentration is linearly decreasing.

Thereafter, referring to FIG. 3E, the patterned mask layer 62 is removed and an isolation structure 24 is formed on the substrate 10. The method of forming the isolation structure 24 can utilize a local thermal oxidation process to form a local thermal oxide layer in the exposed opening 54 of the mask layer 52. The mask layer 52 and the pad oxide layer 50 (not labeled in Figure 3E) are then removed. However, the method for forming the isolation structure 24 of the embodiment of the present invention is not limited thereto.

Thereafter, a heavily doped region 36 is formed in the fourth doped region 28, and a heavily doped region 34 is formed in the third doped region 32. The method for forming the heavily doped regions 34 and 36 can also form an ion implantation mask, and the dopants are implanted into the fourth doping region 28 and the third doping region 32 by ion implantation, respectively. The tempering process is formed.

Thereafter, a gate dielectric layer 18 and a gate 16 are formed on the substrate 10. The gate dielectric layer 18 can be formed from a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. A low dielectric constant material refers to a dielectric material having a dielectric constant of less than 4, such as cerium oxide or cerium oxynitride. The high dielectric constant material refers to a dielectric material having a dielectric constant higher than 4, such as HfAlO, HfO ₂ , Al ₂ O ₃ or Si ₃ N ₄ . The thickness of the gate dielectric layer 18 varies depending on the choice of dielectric material. For example, if the gate dielectric layer 18 is yttria, the thickness can be from 12 nm to 200 nm. The gate 16 is a conductive material such as a metal, polysilicon, doped polysilicon, polycrystalline metal or a combination thereof. The gate dielectric layer 18 and the gate electrode 16 can be formed by first forming a gate dielectric material layer and a gate conductor, and then patterning by a lithography and etching process. Thereafter, a source region 22 and a drain region 20 are formed in the heavily doped regions 34, 36, respectively. In one embodiment, the doping amount of the drain region 20 and the source region 22 is, for example, 5× ^{10 14} to ⁸ × ^{10 15} /cm ² .

In the above-described embodiment, the mask layer 52 defining the isolation structure may be formed on the pad oxide layer 50 prior to forming the patterned mask layer 56 of the compensation doping region 14. However, the embodiments of the present invention are not limited thereto. In another example, the mask layer 56 used to define the patterned doped regions 14 may be formed on the pad oxide layer 50, after the compensation doped regions 14 are formed, and the patterned mask layer removed. After 56, a mask layer 52 for defining an isolation structure is formed on the pad oxide layer 50.

Moreover, in another embodiment, the compensation doped region 14 of Figure 3E can also be replaced with a compensation doped region 14', as shown in Figure 1D. The method of forming the compensated doped region 14' can change the patterned mask layer 62 of Figure 3D to a patterned mask layer 56 similar to that of Figure 3B. That is, the patterned mask layer 62 can be modified to have a plurality of openings (not shown) that expose portions of the pad oxide layer 50 over the first doped regions 12 of the regions. The size of the opening (not shown) of each zone is gradually decreased from the predetermined channel region 19 to the predetermined formation of the drain region 20 (from left to right as in Fig. 3B). The spacing between the openings of each zone (i.e., the patterned mask layer 62) is gradually reduced from the channel region 19 that is intended to be formed to the predetermined formation of the drain region 20 (from left to right as in Figure 3B). Thereafter, an ion implantation is performed to form a compensation doped region 14' from the source 22 (or from the channel region 19) to the drain region 20, and the bottom portion is substantially linear.

The method for forming the linear doping region (ie, the top doping region) of the present invention can be transmitted through The change in the pattern of the reticle, with a single ion implantation process, allows different regions to have different doping concentration gradients. The pattern of the reticle can be divided into a plurality of regions according to the shape and position of the drain region and the source region. Therefore, the linear doping region (ie, the top doping region) of the embodiment of the present invention does not require an additional mask. And an additional ion implantation process to make.

4A is a top view of a metal oxide half field effect transistor according to a second embodiment of the present invention. 4B is a partial top view of a MOS field effect transistor in accordance with a second embodiment of the present invention, omitting the gate and isolation structure. 4C is a cross-sectional view of a metal oxide half field effect transistor according to a second embodiment of the present invention. 5A and FIG. 5B are respectively partial top views of a gold-oxygen half field effect transistor according to another embodiment of the present invention. For the sake of clarity, the gates are also omitted in FIGS. 5A and 5B. Isolation structure. 6A to 6E are cross-sectional views showing the manufacturing flow of the II-II tangential line in Fig. 4A.

4A, FIG. 4B and FIG. 4C, a gold oxide half field effect transistor 200a according to still another embodiment of the present invention includes a gate 16, a gate dielectric layer 18, a source region 22, a drain region 20, and a composite doping region. 77. In another embodiment, the gold oxide half field effect transistor 200a may further include a first doping region 12, a second doping region 30, a third doping region 32, a fourth doping region 28, and a heavily doped region. 34, 36.

In this embodiment, the substrate 10, the gate 16, the gate dielectric layer 18, the source region 22, the drain region 20, the first doping region 12, the second doping region 30, and the third doping region 32, The fourth doping region 28 and the heavily doped regions 34, 36 can be as described in the first embodiment, and are not described herein again. In addition, in FIGS. 4A, 4B, 5A, and 5B, the seventh doping is also omitted. Region 44 and eighth doped region 46.

A composite doped region 77 is located in the substrate 10 between the channel region 19 and the drain region 20. In the present embodiment, the composite doping region 77 includes a top doping region 74 and a compensation doping region 75.

In the present embodiment, the top doping region 74 may have a second conductivity type. The top doped region 74 is located in the first doped region 12 between the channel region 19 and the drain region 20, adjacent to the fourth doped region 28, and the gate 16 covers a portion of the top doped region 74 and Part of the compensation doped region 75.

The compensation doped region 75 can have a first conductivity type located within the top doped region 74. In this embodiment, the compensation doping region 75 can be a linear doping region having a doping concentration gradient. The doping concentration gradient of the compensation doping region 75 is linearly increasing. That is, the depth of the compensation doping region 75 from the approaching channel region 19 to the vicinity of the drain region 20 is gradually increased, and the contour of the bottom portion of the compensation doping region 75 is substantially linear and the depth of the profile is from the approaching channel region 19 to the approach. The bungee region 20 is smoothly linearly increasing. In an embodiment, in the case of the uncompensated doped region 75, the top doped region 74 may be a bulk region having a uniform concentration. When the doped compensation doped region 75 is used, the conductivity type of the two is different. The doping of the compensation doping region 75 can compensate for the doping of the top doping region 74, and after compensation, the region (top doping region) has a second conductivity type and has a doping concentration gradient from the proximity channel region. The concentration decreased from 19 to nearly 20 in the bungee zone.

In one embodiment, the doped region 74, for example, the top doped boron or boron difluoride, the implantation energy and dopant concentration of 80 ~ 120KeV example ^{1.5x10 16 ~ 3x10 16 / cm 3} ; compensation doped region The doping of 75 is, for example, phosphorus or arsenic, the implantation energy is 80-120 KeV, and the doping concentration near the channel region 19 is 1.3× ^{10 16} ~3.7× ^{10 16} /cm ³ , and the depth may be 0.1-0.5 μm; The doping concentration near the drain region 20 is 3.5× ^{10 16} to 5.0×10 ¹⁶ /cm ³ and the depth may be 0.3 to 1.0 μm.

Referring to FIG. 4B and FIG. 4C, in an embodiment, the shape of the drain region 20 and the source region 22 projected onto the surface of the substrate 10 is at least one U-shape; the top doped region 74 surrounds the U-shaped region of the drain region 20. Within the enclosed area and extending to the U-shaped periphery. The compensation doped region 75 is located in the top doped region 74. As shown in FIG. 4B, in an embodiment, the compensation doping region 75 may include at least four regions, that is, a top turn region 75a, a rectangular region 75b, a bottom inner turn region 75c, and a bottom outer turn region 75d. The top turn zone 75a surrounds the beginning 20a of the drain region 20. The rectangular area 75b is located around the connecting portion 20b of the drain region 20. The bottom inner turning zone 75c is located within the area surrounded by the bottom 20c of the drain region 20. The bottom outer turning region 75d is located outside the area surrounded by the bottom portion 20c of the drain region 20. Each of the regions (75a, 75b, 75c, 75d) of the compensation doping region 75 has a doping concentration gradient, and the doping concentration gradients of the compensation doping regions 75 in the respective regions (75a, 75b, 75c, 75d) are different. The top doped region 74 may include at least four regions corresponding to the top turn region 75a, the rectangular region 75b, the bottom inner turn region 75c, and the bottom outer turn region 75d, respectively. Each region of the top doped region 74 has a concentration, respectively. The concentration of each of the regions (75a, 75b, 75c, 75d) of the top doping region 74 may be the same or different.

Referring to FIG. 4C, the gold-oxygen half field effect transistor 200a of the second embodiment of the present invention can make the channel on the surface of the third doping region 32 under the gate 16 reverse when a proper bias voltage is applied to the gate 16. The transition layer (channel region) and two current paths, namely current path III and current path IV, can be formed. More specifically, at the current In path III, electrons from the source region 22, via the heavily doped region 34, the channel region 19, the second doped region 30, the substrate 10 (which in this embodiment may be, for example, the epitaxial layer 10b in the substrate 10) and The first doped region 12 flows into the compensation doping region 75; and the electrons flowing into the compensation doping region 75 flow into the drain region 20 via the fourth doping region 28 and the heavily doped region 36 to form a current path III. . In the current path III, after the electrons flow to the substrate 10 (which may be, for example, the epitaxial layer 10b in the substrate 10), it may also flow directly into the compensation doping region 75, and then through the fourth doping region. 28 and the heavily doped region 36 flows into the drain region 20. The current path IV is electrons from the source region 22, via the heavily doped region 34, the channel region 19, the second doped region 30, and the substrate 10 (in this embodiment, for example, the epitaxial layer 10b in the substrate 10) And the first doped region 12, flowing into the first doped region 12 under the top doped region 74; the electrons flowing into the first doped region 12 under the top doped region 74, and then via the fourth doped region 28 and The heavily doped region 36 flows into the drain region 20 to form a current path IV. Since the gold-oxygen half field effect transistor 200a of the second embodiment of the present invention can form two channel paths, the opening resistance can be lowered. In addition, the metal oxide half field effect transistor 200a of the second embodiment of the present invention may form three RESURF structures including a compensation doping region 75 and a top doping region 74 junction, a top doping region 74 and a first doping region 12 The junction, and the epitaxial layer 10b and the semiconductor substrate 10a are connected to each other, in other embodiments, in addition to compensating the junction of the doped region 75 and the top doped region 74 and the top doped region 74 and the first doped region 12 Outside the junction, the third RESURF structure can be the junction of the first doped region 12 and the semiconductor substrate 10a. In addition, the depth of the compensation doped region 75 is shallow and can be completely depleted when the component is operated. Compensating the doped region 75, smoothly increasing linearly from near the channel region 19 to near the drain region 20, can adjust the electric field distribution to enhance Crash voltage.

Referring to FIG. 5A, in another embodiment, the MOS field-effect transistor 200b may further include a fifth doping region 26 having a second conductivity type adjacent to the drain region 20, and the fifth doping region 26 is at the drain Within the area enclosed by zone 20 (as shown in Figure 5A). In yet another embodiment, referring to FIG. 5B, the MOS field-effect transistor 200c may further include a fifth doping region 26 having a second conductivity type, which may be located around the drain region 20 in the heavily doped region 36. .

6A-6E are cross-sectional views showing a manufacturing process of a metal oxide half field effect transistor according to a second embodiment of the present invention.

Referring to FIG. 6A, a first doping region 12, a second doping region 30, a seventh doping region 44, and a pad oxide layer 50 may be formed in the substrate 10 in accordance with the method of the first embodiment.

Then, referring to FIG. 6B, in the first doping region 12 and the second doping region 30, the fourth doping region 28 and the third doping region 32 are formed and patterned according to the method of the first embodiment. The mask layer 52. Next, a patterned mask layer 82 is formed on the substrate 10. A patterned mask layer 82 overlies the patterned mask layer 52. In particular, the patterned mask layer 82 has an opening 84 that exposes a portion of the pad oxide layer 50 above the first doped region 12. The patterned mask layer 82 can be a hard mask layer or a photoresist layer. The material of the hard mask layer is, for example, tantalum nitride, which is formed by, for example, depositing a mask material layer by chemical vapor deposition, and then patterning it by lithography and etching. If a photoresist material is used as the mask layer, it can be directly patterned by lithography.

Thereafter, the patterned mask layer 82 is used as an ion implantation mask to perform an ion implantation process, and the dopant is implanted in the first doping region 12 to form a top doping region 74. The dopant implanted in the ion implantation process has a second conductivity type, such as boron or boron difluoride ions. In one embodiment, the top doped region 74 has a uniform concentration and approximately the same depth near the predetermined channel region 19 to near the drain region 20 (FIG. 6E).

Thereafter, referring to FIG. 6C, the patterned mask layer 82 is removed. Thereafter, a patterned mask layer 86 is formed on the substrate 10. The patterned mask layer 86 has a plurality of openings 88 at positions corresponding to the predetermined top turn region 75a, the rectangular region 75b, the bottom inner turn region 75c, and the bottom outer turn region 75d of FIG. 4B, respectively exposing the first doping. A portion of the pad oxide layer 50 above the region 12. The size of the opening 88 corresponding to the top turn zone 75a, the rectangular zone 75b, the bottom inner turn zone 75c, and the bottom outer turn zone 75d of FIG. 4B is from the predetermined channel region 19 to the predetermined formation of the drain region 20 (FIG. 6E). (Fig. 6C is from left to right) increasing. The spacing between the openings 88 (i.e., the patterned mask layer 86) is gradually increased from the channel region 19 that is formed to form the gate region 20 (Fig. 6E) (Fig. 6C is left to right). The patterned mask layer 86 can be a hard mask layer or a photoresist layer. The material of the hard mask layer is, for example, tantalum nitride, which is formed by, for example, depositing a mask material layer by chemical vapor deposition, and then patterning it by lithography and etching. If a photoresist material is used as the mask layer, it can be directly patterned by lithography.

Thereafter, the patterned mask layer 86 is used as an ion implantation mask to perform an ion implantation process, and a dopant having a first conductivity type is implanted in the top doping region 74 to A plurality of doped regions 90 having a first conductivity type are formed in the top doping region 74. The first conductivity type dopant implanted in the ion implantation process is, for example, arsenic or phosphorus. The two adjacent doped regions 90 formed overlap each other under the corresponding patterned mask layer 86 to form an overlap region 94. The size of the overlap region 94 is related to the spacing between adjacent two openings 88 (i.e., the patterned mask layer 86).

Then, referring to FIG. 6D, the patterned mask layer 86 is removed. Then temper. The tempering temperature is, for example, 900 degrees Celsius to 1150 degrees Celsius. When tempering is performed, the overlap region 94 is uniformly diffused, and the compensation doped region 75 having the first conductivity type is formed together with the non-overlapping region. The concentration of the compensation doping region 75 is gradually increased from the channel region 19 to be formed to the predetermined formation of the drain region 20 (Fig. 6E) (the figure is left to right). In an embodiment, the doping concentration gradient of the compensation doping region 75 is linear. That is, the doping concentration from the predetermined channel region 19 to the predetermined formation of the drain region 20 (Fig. 6E) (from left to right in the drawing) is linearly increasing. The compensation doping region 75 is gradually increased in depth from the channel region 19 which is to be formed to the predetermined formation of the drain region 20 (FIG. 6E) (from left to right in the drawing), and the contour of the bottom portion of the compensation doping region 75 is smooth, It is roughly linear. The compensation doped region 75 can compensate for a portion of the top doped region 74. The compensation doping region 75 and the top doping region 74 constitute a composite doping region 77. The composite doped region 77 is located in the substrate 10 (more specifically, the first doped region 12) between the channel region 19 to be formed and the gate region 20 to be formed. The top doped region 74 in the composite doped region 77, prior to forming the compensation doped region 75 (FIG. 6B), has a second conductivity type from near the predetermined channel region 19 to near the drain region 20 (FIG. 6E) ) has a uniform concentration and approximately the same depth. After forming the compensation doping region 75 (FIG. 6D), the top doping region 74 in the composite doping region 77, Where the compensation doping region 75 overlaps, the compensation doping region 75 having a different conductivity type is compensated to have the first conductivity type from the channel region 19 which is to be formed to the predetermined formation of the drain region 20 (Fig. 6E) (Fig. 6E) The doping concentration of the pattern from left to right is linearly increasing; and if it is not overlapped with the compensation doping region 75, it maintains the second conductivity type, and from the channel region 19 which is formed to be close to the drain The concentration at zone 20 (Fig. 6E) is decreasing.

In addition, by the size and spacing of the opening 88 of the patterned mask 86, a different dopant concentration gradient corresponding to FIG. 4B can be formed in the top doping region 74 through a single mask and a single ion implantation process. The top turn zone 75a, the rectangular zone 75b, the bottom inner turn zone 75c, and the bottom outer turn zone 75d can greatly simplify the process without increasing the process cost.

In one embodiment, the implant energy of the top doped region 74 below the predetermined isolation structure (or drift isolation structure) 24 (FIG. 6E) is 80-120 KeV and the doping concentration is 1.5 x 10 ¹⁶ ~ 3.0 x 10 ¹⁶ /cm ³ ; compensation doping region 75 implant energy is 80 ~ 120KeV and the doping concentration near the channel region 19 is 1.3x10 ¹⁶ ~ 3.7x10 ¹⁶ / cm ³ , the depth can be 0.1 ~ 0.5μm; The doping concentration near the drain region 20 is 3.5× ^{10 16} to 5.0×10 ¹⁶ /cm ³ and the depth may be 0.3 to 1.0 μm.

Thereafter, referring to FIG. 6E, an isolation structure 24 is formed on the substrate 10 in accordance with the method of the first embodiment described above. The mask layer 52 and the pad oxide layer 50 are then removed. Thereafter, a heavily doped region 36 is formed in the fourth doped region 28, and a heavily doped region 34 is formed in the third doped region 32. Next, a gate dielectric layer 18 and a gate 16 are formed on the substrate 10. Next, a source region 22 and a drain region 20 are formed in the heavily doped regions 34, 36, respectively.

In the above-described embodiments, a patterned mask layer 52 for defining an isolation structure may be formed on the pad oxide layer 50 prior to forming the patterned cap layer 82 of the top doped region 74. However, the embodiments of the present invention are not limited thereto. In another example, the patterned mask layer 82 used to define the top doped region 74 can be formed first on the pad oxide layer 50 after the top doped region 74 is formed and the patterned mask layer removed. After 82, a patterned mask layer 52 is formed over the pad oxide layer 50 to define the isolation structure.

The method for forming the linear doping region (ie, the compensation doping region 75) of the embodiment of the present invention can change different patterns of the doping concentration by using a single ion implantation process through the change of the pattern of the reticle. The pattern of the reticle can be divided into a plurality of regions according to the shape and position of the drain region and the source region. Therefore, the linear doping region (ie, the compensation doping region 75) of the embodiment of the present invention does not need to use additional light. A cover and an additional ion implantation process are available.

According to the method disclosed by TCAD (Technology Computer Aided Design), in which the TCAD used is a product provided by Synopsys technology, the gold-oxygen half-field electric power with the compensation doping region of the first embodiment of the present invention is simulated. The breakdown voltage values of the crystals, and the gold-oxygen half-field effect transistors having the top doping regions but not the compensation doping regions in different regions, are shown in Table 1. Here, the manner disclosed by TCAD is incorporated into the present reference. In the conditions used in the simulation, the doping of the top doped region of the composite doped region is boron, and the ion implantation dose is 1.0×10 ¹³ ~1.8×10 ¹³ /cm ² and the energy is 350-400 KeV. The dopant doped in the doped region is arsenic, and the ion implantation dose is 1.8×10 ¹² ~2.2×10 ¹² /cm ² , and the energy is 130-150 KeV.

The results from Table 1 show that the gold-oxygen half-field effect transistor with the compensation doping region of the embodiment of the present invention has a source terminal and a 汲 terminal, compared to a gold-oxygen half-field effect transistor having no compensation doping region. And the breakdown voltage of the rectangular region (flat region) between the source and the drain is very close, that is, the metal oxide half field effect transistor with the compensation doping region in the embodiment of the present invention can solve the current concentration of the drain and the source terminal. The problem also has a very uniform breakdown voltage.

Table 2 is a graph showing the on-resistance value and the starting voltage of a gold-oxygen half-field effect transistor having a compensation doping region and a compensation doping region according to the first embodiment of the present invention in accordance with the method disclosed in the TCAD.

The results from Table 2 show that compared to the gold oxide half field without compensating the doping region In the effect transistor, the opening resistance value Ron of the gold-oxygen half field effect transistor having the compensation doping region of the embodiment of the invention is significantly decreased, and the starting voltage is substantially similar.

Table 3 is a graph showing the breakdown voltage values of different regions of the gold-oxygen half field effect transistor having a compensation doping region according to the second embodiment of the present invention in accordance with the method disclosed in the TCAD. A top doped region dopant is boron dose in ion implantation doping of the channel region 19 near the dose is ^{5.0 × 10 12 ~ 6.0 × 10} 12 / cm 2, at a dopant near the drain region 20 of the It is 3.5 × 10 ¹² ~ 4.5 × 10 ¹² /cm ² and the energy is 80 to 120 KeV. The doping of the compensation doped region is phosphorus, and the dose of ion implantation is close to the channel region 19 at a doping dose of 2.6×10 ¹¹ to 7.4×10 ¹¹ /cm ² , and the doping at the vicinity of the drain region 20 The dose is 1.8×10 ¹² ~2.5×10 ¹² /cm ² and the energy is 80-120 KeV.

From the results of Table 3, it is shown that the breakdown voltage of the flat region or the source central region of the second embodiment is close to the breakdown voltage of the first embodiment, and the demand for high voltage operation can be attained.

In summary, the gold-oxygen half-field effect transistor having a composite doping region in the embodiment of the present invention can solve the problem of current concentration of the drain and source terminals, so that each region of the device has a uniform breakdown voltage and reduces the opening resistance of the device. Moreover, only one The photomask can be formed into a linear doping region having a concentration gradient through a single ion implantation process by using the size of the mask opening and the spacing adjustment (such as the top doping region in the first embodiment or the second embodiment) Compensation doping zone) Therefore, the process is very simple and does not increase the process cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base

10a‧‧‧Semiconductor substrate

10b‧‧‧ epitaxial layer

12‧‧‧First doped area

14‧‧‧Compensation doped area

15‧‧‧Top doped area

16‧‧‧ gate

17‧‧‧Composite doped area

18‧‧‧gate dielectric layer

19‧‧‧Channel area

20‧‧‧Bungee Area

22‧‧‧ source area

24‧‧‧Isolation structure

28‧‧‧Four doped area

30‧‧‧Second doped area

32‧‧‧ Third doped area

34, 36‧‧‧Densely doped area

42‧‧‧ sixth doping area

44‧‧‧ seventh doped area

46‧‧‧ eighth doped area

100a‧‧‧Gold oxygen half-field effect transistor

I, II‧‧‧ current path

Claims (18)

A semiconductor device comprising: a drain region having a first conductivity type in a substrate; a source region having the first conductivity type, located in the substrate, surrounding the drain region; a channel a portion of the substrate between the source region and the drain region; a gate covering the channel region and a portion of the substrate; and a composite doped region located in the channel region and the drain In the substrate between the regions, the composite doped region comprises: a top doped region having a second conductivity type in the substrate between the channel region and the drain region, the top doped region The doping concentration decreases from near the channel region to near the drain region; and a compensation doping region having the first conductivity type is located in the top doped region to compensate for the top doped region. The semiconductor device of claim 1, wherein: the top doped region is a first linear doped region, and the concentration decreases from near the channel region to the drain region; and the compensation doping The impurity region is a block region having a uniform doping concentration. The semiconductor device of claim 1, wherein: the top doped region is a first linear doped region, and the concentration decreases from near the channel region to the drain region; and the compensation doping The impurity region is a second linear doped region, and the concentration decreases from near the channel region to near the drain region. The semiconductor device of claim 1, wherein: the doping concentration gradient of the top doped region decreases from a proximity to the channel region to a concentration close to the drain region; The compensation doped region is a linear doped region having an increasing concentration from near the channel region to near the drain region. The semiconductor device of claim 1, further comprising: a first doped region having the first conductivity type, located in the substrate around the drain region, wherein the composite doped region and the germanium a pole region is located in the first doping region; a second doping region having the first conductivity type, located in the substrate around the source region; and a third doping region having the second conductivity type Located in the second doped region; a fourth doped region having the first conductivity type, located in the first doped region adjacent to the composite doped region; and a second heavily doped region having The first conductivity type is respectively located in the fourth doping region and the third doping region, and the drain region and the source region are respectively located therein. The semiconductor device of claim 1, further comprising a fifth doped region having the second conductivity type, the fifth doped region adjoining the drain region. The semiconductor device according to claim 1, wherein when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type It is N type. A method of fabricating a semiconductor device, comprising: forming a top doped region having a second conductivity type; forming a compensation doped region having a first conductivity type, wherein the compensation doping region is located in the top doped region, Forming a drain region on a first side of the top doped region, the drain region having the first conductivity type; and forming a source region on a second side of the top doped region, the source region Having the first conductivity type and surrounding the drain region, the portion between the source region and the drain region There is a channel region in the substrate, wherein the doping concentration of the top doping region decreases from near the channel region to near the drain region. The method of fabricating a semiconductor device according to claim 8, wherein the method of forming the top doped region and the compensation doped region comprises: forming a first patterned mask layer, the first patterned The mask layer has at least one first opening; the first patterned mask layer is used as a mask to perform a first ion implantation process to form the top doping region; and the first patterned mask is removed Forming a second patterned mask layer, the second patterned mask layer having at least one second opening exposing the top doped region; the second patterned mask layer being a mask Screening, performing a second ion implantation process to form the compensation doped region in the top doped region; and removing the second patterned mask layer. The method of manufacturing the semiconductor device of claim 9, wherein the first patterned mask layer has a plurality of first openings, and the first openings are sized from near the channel region to the proximity The drain region is gradually reduced, and the spacing between the first openings is gradually reduced from near the channel region to near the drain region. The method of fabricating a semiconductor device according to claim 10, further comprising a tempering process to smooth the outline of the top doped region. The method of fabricating a semiconductor device according to claim 9, wherein the first patterned mask layer has the first opening, and the top doped region formed after the first ion implantation process is performed. Has a uniform doping concentration. A method of manufacturing a semiconductor device according to claim 12, Wherein the second patterned mask layer has a plurality of second openings, and the second openings are increased in size from near the channel region to near the drain region, and between the second openings The spacing increases from near the channel region to near the drain region. The method for fabricating a semiconductor device according to claim 13 further includes a tempering process to smooth the contour of the compensation doping region. The method for fabricating a semiconductor device according to claim 8, further comprising: forming a first doped region having the first conductivity type around the drain region, wherein the top doped region, the compensation doping The doping region and the drain region are located in the first doping region; a second doping region having the first conductivity type is formed around the source region; and the second doping region is formed in the second doping region a third doped region of the second conductivity type; forming a fourth doped region having the first conductivity type, the fourth doped region and the top doped region and the compensation The doped regions are adjacent to each other; and one of the first doped regions and the third doped region is formed with a concentrated doped region of the first conductivity type, wherein the drain region and the source region respectively correspond to In the concentrated doped region. A gold-oxygen half-field effect transistor, comprising: a drain region having a first conductivity type, located in a substrate; a source region having the first conductivity type, located in the substrate, surrounding the drain region Surrounding; a gate over the substrate between the source region and the drain region; a gate dielectric layer between the gate and the substrate; and a compensation doped region having the first a conductivity type in the substrate between the source region and the drain region; A doped region having a second conductivity type, located below the compensation doped region, has a doping concentration gradient, and the concentration decreases from near the source to near the drain region. A method of fabricating a semiconductor device, comprising: forming an N-type doped layer in a substrate; forming a P-type top doping in the N-type doped layer between a gate region and a channel region that is predetermined to be formed a N-doped region is formed in the top doped region to form a compensation doped region in the top doped region; and the N-type drain region is formed in the N-doped layer; One side of the channel region forms a source region, and the source region has the N-type conductivity type. A method of fabricating a semiconductor device, comprising: forming a first patterned mask layer on a substrate, the first patterned mask layer having a plurality of first openings; and the first patterned mask layer a masking process, performing a first ion implantation process to form a top doped region; removing the first patterned mask layer; forming a second patterned mask layer on the substrate, the first The second patterned mask layer has a second opening to expose the top doped region; the second patterned mask layer is used as a mask to perform a second ion implantation process in the top doping region Forming a compensation doping region; removing the second patterned mask layer; forming a drain region on the first side of the compensation doping region, the drain region having a first conductivity type; a second region of the doped region forms a source region, and the source region has the first region a conductive type surrounding and surrounding the drain region; wherein the compensation doped region has the first conductivity type; and the top doped region has a second conductivity type having a doping concentration gradient from the source The concentration from the area to the bungee area is decreasing.