TWI463666B - Semiconductor device and methods for forming the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a super junction structure and a method of fabricating the same.

A conventional vertical diffusion metal-oxide-semiconductor field effect transistor (VDMOSFET) has a PN junction formed by an N-type doped drift region and an upper P-type doped base region. Surface structure. The P-N junction structure is primarily used to withstand the voltage applied to conventional vertical diffusion metal oxide semiconductor field effect transistors. To improve the withstand voltage of the vertically-diffused metal oxide semiconductor field effect transistor, it is necessary to reduce the doping concentration of the N-type doped drift region and increase the thickness of the N-type doping drift region. Improving the withstand voltage of the P-N junction structure results in an increase in on-resistance (Ron) of a conventional vertically-diffused metal oxide semiconductor field effect transistor. That is, the on-resistance of a conventional vertical diffusion metal oxide semiconductor field effect transistor is limited by the doping concentration and thickness of the N-type doped drift region. In order to improve the doping concentration of the N-type doped drift region, a vertical diffusion metal oxide semiconductor field effect transistor having a super junction structure is developed, thereby improving the on-resistance of the vertically-diffused metal oxide semiconductor field effect transistor.

Typically manufactured in conventional superjunction structures through multiple epitaxy (COOlMOS ^TM). Multiple epitaxial techniques require multiple cycles of processing, including epitaxial growth processes, P-type dopant ion implantation processes, and thermal diffusion processes. Therefore, the multiple epitaxial technology has the disadvantages of many manufacturing steps and high manufacturing cost. In addition, it is also difficult to reduce the size of the vertically-diffused metal oxide semiconductor field effect transistor.

Therefore, it is necessary to find a new manufacturing method of a semiconductor device having a super junction structure which can alleviate or eliminate the above problems.

The present invention provides a method of fabricating a semiconductor device comprising providing a semiconductor substrate having a first conductivity type. An epitaxial layer having a first conductivity type is formed on the semiconductor substrate. A plurality of first trenches are formed in the epitaxial layer. A first doped region having a first conductivity type is formed in the epitaxial layer and surrounds each of the first trenches. A second doped region having a first conductivity type is formed in each of the first doping regions and adjacent to each of the first trenches. Each of the first trenches is filled with a first insulating material. A plurality of second trenches alternately arranged with the first trench are formed in the epitaxial layer. A third doped region having a second conductivity type is formed in the epitaxial layer and surrounds each of the second trenches. Each second trench is filled with a second insulating material. Each of the first doped regions includes a first dopant and each of the second doped regions includes a second dopant, and a diffusion coefficient of the first dopant is greater than a diffusion coefficient of the second dopant.

The present invention provides a semiconductor device including a semiconductor substrate having a first conductivity type. An epitaxial layer having a first conductivity type is disposed on the semiconductor substrate. A plurality of first trenches filled in the first insulating material are disposed in the epitaxial layer. A first doped region having a first conductivity type is disposed within the epitaxial layer and surrounding each of the first trenches. A second doped region having a first conductivity type is disposed in each of the first doping regions and adjacent to each of the first trenches. Filling a plurality of second trenches filled with a second insulating material, and alternately arranged with the first trenches in the epitaxial layer Inside. A third doped region having a second conductivity type is disposed within the epitaxial layer and surrounding each of the second trenches. Each of the first doped regions includes a first dopant and each of the second doped regions includes a second dopant, and a diffusion coefficient of the first dopant is greater than a diffusion coefficient of the second dopant.

The fabrication of an embodiment of the invention is described below. The description is intended to provide an overall concept of the invention and is not intended to limit the scope of the invention. The scope of the invention is defined by the scope of the appended claims. In the drawings and the text, the same or similar components are given the same or similar reference numerals.

The present invention is not limited to the specific embodiments and the contents described in the drawings, but is limited to the scope of the patent application. The drawings are for illustrative purposes only and are not intended to limit the invention. In the drawings, the size of some of the elements are exaggerated for the purpose of illustration and are not drawn to scale, and their relative dimensions do not correspond to the actual dimensions of the invention.

FIG. 7 is a cross-sectional view showing a semiconductor device 500 in accordance with an embodiment of the present invention. The semiconductor device 500 may include a metal-oxide-semiconductor field effect transistor (MOSFET) having a super junction structure, such as a super junction vertical diffusion metal oxide semiconductor field effect transistor (super junction VDMOSFET). ). The semiconductor device 500 may include a semiconductor substrate 200 having a first conductivity type and an epitaxial layer 202 formed thereon and having a first conductivity type. In this embodiment, the first conductivity type may be a P type or an N type. Furthermore, the doping concentration of the semiconductor substrate 200 is greater than the doping concentration of the epitaxial layer 202. For example, the first conductivity type For the N-type, the semiconductor substrate 200 can be an N-type heavily doped (N+) semiconductor substrate 200, and the epitaxial layer 202 can be an N-type lightly doped (N-) epitaxial layer 202. Epitaxial layer 202 can include active region 300 and its surrounding termination region 302. Active region 300 is used to place semiconductor devices thereon/in, while termination region 302 acts as an isolation feature between the semiconductor devices.

The active region 300 of the epitaxial layer 202 can include a plurality of first trenches 204 and a plurality of second trenches 218 alternately disposed therein such that each second trench 218 is adjacent to at least one of the first trenches 204 One or each first trench 204 is adjacent to at least one of the second trenches 218. To simplify the drawing, only one second trench 218 and two first trenches 204 adjacent thereto are shown here. The first trench 204 may extend through the epitaxial layer 202 into the semiconductor substrate 200 such that the lower surface 205 of the first trench 204 may be located within the semiconductor substrate 200. Likewise, the second trench 218 can extend through the epitaxial layer 202 into the semiconductor substrate 200 such that the lower surface 209 of the second trench 218 can be located within the semiconductor substrate 200. The advantage that the first trench 204 and the second trench 218 extend into the semiconductor substrate 200 is that when the inner surfaces (ie, the sidewalls and the bottom) of the first trench 204 and the second trench 218 are doped, the ion reverse can be reduced. Ion recoil effect. For super-junction vertical-diffused MOSFETs, reducing the ion kickback effect when doping trenches can help reduce on-resistance and increase breakdown voltage (VB).

The first insulating liner 206 is conformally formed on the inner surfaces (side walls 207 and lower surface 205) of the first trench 204. In an embodiment, the first insulating liner 206 can be an oxide layer that can be used to release the stress of the epitaxial layer 202. In addition, the first insulating liner 206 can be used as a pre-ion implant oxide layer for Subsequent ion implantation processes to reduce channel effects.

A first insulating material 212 is filled in each of the first trenches 204. The upper surface 213 of the first insulating material 212 can be substantially aligned with the upper surface 203 of the epitaxial layer 202. In an embodiment, the first insulating material 212 may comprise an oxide or an undoped polysilicon.

A first doped region 210 having a first conductivity type (eg, N-type) is formed in and around each of the epitaxial layers 202, wherein the first doped region 210 can include a first dopant. A second doping region 310 having a first conductivity type (eg, N-type) is formed in the first doping region 210 and adjacent to each of the first trenches 204 such that the second doping region 310 surrounds the corresponding portion A trench 204, wherein the second doped region 310 can include a second dopant. The diffusion coefficient of the first dopant is greater than the diffusion coefficient of the second dopant. For example, the first dopant is phosphorus and the second dopant is arsenic. The doping concentration of the first doping region 210 may be greater than the epitaxial layer 202 and less than the doping concentration of the semiconductor substrate 200.

The depth of the first doped region 210 (eg, the distance between the upper surface 203 of the epitaxial layer 202 and the lower surface 209 of the first doped region 210) may be substantially greater than the depth of the second doped region 310 (eg, epitaxial The distance between the upper surface 203 of the layer 202 and the lower surface 211 of the second doped region 310), and the depth of the second doped region 310 may be substantially greater than the depth of the first trench 204 (eg, the epitaxial layer 202 The distance between the upper surface 203 and the lower surface 205 of the first trench 204). Therefore, the lower surface 211 of the second doping region 310 may be located in the first doping region 210, and the lower surface 205 of the first trench 204 may be located in the first doping region 210 and the second doping region 310.

Likewise, the second insulating liner 220 is conformally formed on the inner surfaces (the sidewalls 221 and the lower surface 219) of the second trench 218. In an embodiment The second insulating liner 220 may be an oxide layer to release the stress of the epitaxial layer 202. In addition, the second insulating liner 220 can be used as a pre-ion implant oxide layer for subsequent ion implantation processes to reduce channel effects.

The second insulating material 230 is disposed in the second trench 218. The upper surface of the second insulating material 230 may be substantially aligned with the upper surface 203 of the epitaxial layer 202. In an embodiment, the second insulating material 230 may include an oxide or an undoped polysilicon.

A third doped region 222 having a second conductivity type relative to the first conductivity type is formed within the epitaxial layer 202 and surrounds the second trench 218. For example, the second conductivity type may be a P type, and the third doping region 222 may be a P type doping region. The third doped region 222 can include a third dopant (eg, boron, indium, boron fluoride (BF2), or a combination thereof). In addition, the doping concentration of the third doping region 222 may be greater than the epitaxial layer 202 and less than the doping concentration of the semiconductor substrate 200.

The depth of the third doped region 222 (eg, the distance between the upper surface 203 of the epitaxial layer 202 and the lower surface 229 of the third doped region 222) may be substantially greater than the depth of the second trench 218 (eg, an epitaxial layer) The distance between the upper surface 203 of the 202 and the lower surface 219 of the second trench 218). Accordingly, the lower surface 219 of the second trench 218 can be located within the third doped region 222.

The super junction structure 250 may be formed through the first doping region 210, the second doping region 310, and the third doping region 222, wherein each of the first doping regions 210 is adjacent to at least the third doping region 222 One.

The plurality of gate structures 228 can be correspondingly disposed on the plurality of first trenches 204. Each gate structure 228 can include a gate oxide layer 224 and an upper gate layer 226. In one embodiment, each of the gate structures 228 respectively covers one of the plurality of first trenches 204 and adjacent to the covered first trenches A portion of the epitaxial layer 202 of 204. Additionally, the second trench 218 is exposed through the gate structure 228. In an embodiment, the gate oxide layer 224 can include an oxide, a nitride, an oxynitride, a carbon oxide, or a combination thereof. In an embodiment, the gate layer 226 can be a polysilicon layer.

A pair of well regions 232 having a second conductivity type are formed in the active region 300 of the epitaxial layer 202 on either side of the second trench 218 such that the pair of well regions 232 are located between adjacent two gate structures 228. Furthermore, the pair of well regions 232 are located above the third doped region 222.

A pair of source regions 234 having a first conductivity type (e.g., a pair of N-type heavily doped regions) are correspondingly formed within the pair of well regions 232. The pair of source regions 234 are adjacent to one side of the corresponding gate structure 228, respectively. In addition, the interface position between the first doping region 210 and the third doping region 222 may be changed according to the needs of the characteristics of the semiconductor device. Further, the N-type semiconductor substrate 200 can function as a drain of a vertically-diffused metal oxide semiconductor field effect transistor.

An interlayer dielectric (ILD) layer 236 having contact holes 238 may be formed over epitaxial layer 202 and overlying gate structure 228. It is worth noting that the number of contact holes 238 can be one or more depending on the design of the semiconductor device. As shown in FIG. 7, a portion of each source region 234 and a portion of each well region 232 adjacent thereto are exposed from contact holes 238. A pair of contact doping regions 240 may be correspondingly formed in the pair of well regions 232. The pick-up doped region 240 can have a second conductivity type, and each contact doped region 240 is adjacent to a corresponding source region 234. A conductive layer can be formed on the inner dielectric layer 236 and filled in the contact holes 238 to form a contact plug 242. The contact plug 242 can serve as a source electrode of the semiconductor device 500.

1 to 7 are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. As shown in Fig. 1, a semiconductor substrate 200 having a first conductivity type is provided. Next, an epitaxial layer 202 having a first conductivity type is formed on the semiconductor substrate 200 through an epitaxial growth process. In this embodiment, the first conductivity type may be a P type or an N type. Furthermore, the doping concentration of the semiconductor substrate 200 may be greater than the doping concentration of the epitaxial layer 202. For example, the semiconductor substrate 200 can be an N-type heavily doped (N+) semiconductor substrate 200, and the epitaxial layer 202 can be an N-type lightly doped (N-) epitaxial layer 202. As shown in FIG. 1, epitaxial layer 202 can include active region 300 and its surrounding termination region 302.

Please refer to FIG. 2, which illustrates the fabrication of the first trench 204. A hard mask layer (not shown) is formed on the epitaxial layer 202 by a low pressure chemical vapor deposition (LPCVD) process. Next, a lithography and etching process is performed to form a mask pattern (not shown) covering the active region 300 of the epitaxial layer 202 to define a plurality of first trenches. Next, the epitaxial layer 202 not covered by the mask pattern is subjected to an etching process to form a plurality of first trenches 204 corresponding to the active region 300. In an embodiment, the first trench 204 may extend through the epitaxial layer 202 into the semiconductor substrate 200 such that the lower surface 205 of the first trench 204 may be located within the semiconductor substrate 200.

Next, after the mask pattern is removed, a process (for example, thermal oxide growth method) is performed, and the first insulating liner 206 is conformally formed on the sidewall 207 and the lower surface 205 of each of the first trenches 204.

Referring to FIG. 3, a doping process 208 (eg, a tilt ion implantation process) is performed from opposite sidewalls 207 of each first trench 204 to dope the epitaxial layer 202. First, the epitaxial layer 202 is doped with a relatively high diffusion system. The first dopants are formed to form a first doping region 210 around each of the first trenches 204. Thereafter, the doping process 208 is continued through the second dopant having a relatively low diffusion coefficient to form a second doping region 310 in each of the first doping regions 210 adjacent to each of the first trenches 204. The first dopant and the second dopant have a first conductivity type (eg, N-type). The doping process 208 forming the first doped region 210 and the second doped region 310 may be a similar or different process. In an embodiment, the doping process 208 forming the first doped region 210 and the second doped region 310 has different parameters (including doping angle, energy, dose, temperature, or a combination thereof). The "diffusion coefficient" herein means the diffusivity of the first dopant or the second dopant in the epitaxial layer 202 or the semiconductor substrate 200. In an embodiment, the first dopant may include phosphorus, and the second dopant may include arsenic, but is not limited thereto.

It should be noted that in the doping process 208, the first dopant having a relatively high diffusion coefficient may be further from the inner surface of each of the first trenches 204 than the second dopant having a relatively low diffusion coefficient. Deep into the epitaxial layer 202. As shown in FIG. 3 , each of the first doping regions 210 formed in the epitaxial layer 202 and surrounding each of the first trenches 204 may include a first dopant formed in the first doping region 210 . And each of the second doped regions 310 adjacent to each of the first trenches 204 may surround the corresponding first trenches 204 and may include a second dopant. The doping concentration of each of the first doping regions 210 is greater than the epitaxial layer 202 and less than the doping concentration of the semiconductor substrate 200.

The depth of the first doped region 210 (eg, the distance between the upper surface 203 of the epitaxial layer 202 and the lower surface 209 of the first doped region 210) may be substantially greater than the depth of the second doped region 310 (eg, epitaxial a distance between the upper surface 203 of the layer 202 and the lower surface 211 of the second doping region 310), and the second doping region 310 The depth may be substantially greater than the depth of the first trench 204 (eg, the distance between the upper surface 203 of the epitaxial layer 202 and the lower surface 205 of the first trench 204). Therefore, the lower surface 211 of the second doping region 310 may be located in the first doping region 210, and the lower surface 205 of the first trench 204 may be located in the first doping region 210 and the second doping region 310.

In an embodiment, the tilt angle θ1 of the doping process 208 is primarily dependent on the width and depth of the first trench 204. For example, the tilt angle θ1 of the doping process 208 may range from 1° to 10°. In an embodiment, after the doping process 208 is performed, a diffusion process (eg, a rapid thermal annealing (RTA) process) may be performed in the first doping region 210 and the second doping region 310 to The dopants therein are activated. The process temperature of the diffusion process may range from 800 ° C to 1500 ° C such that the first dopant may be uniformly distributed in the first doping region 210 and the second dopant may be uniformly distributed in the second doping region 310 .

Referring to FIG. 4, the first insulating material 212 is formed on the epitaxial layer through a deposition process (for example, a low pressure chemical vapor deposition process) or a coating process (for example, a spin-on glass (SOG) method). Each of the first trenches 204 is filled and filled. Next, a planarization process (eg, a chemical mechanical polishing (CMP) process) is performed to remove excess first insulating material 212 on the upper surface 203 of the epitaxial layer 202 such that the upper surface 213 of the first insulating material 212 The upper surface 203 of the epitaxial layer 202 is substantially aligned.

Referring again to FIG. 4, the fabrication of the second trench 218 is illustrated. Similarly, a hard mask layer (not shown) is formed on the epitaxial layer 202. Next, a lithography and etching process is performed to form an active region 300 covering the epitaxial layer 202. A mask pattern (not shown) is used to define a plurality of second trenches. Next, the epitaxial layer 202 not covered by the mask pattern is etched to form a plurality of second trenches 218 alternately arranged with the plurality of first trenches 204 such that each second trench 218 is adjacent to each other The at least one first trench 204 or each of the first trenches 204 is adjacent to the at least one second trench 218. Moreover, the plurality of second trenches 218 can extend through the epitaxial layer 202 into the semiconductor substrate 200 such that the lower surface 219 of the second trench 218 can be located within the semiconductor substrate 200. The first trench 204 and the second trench 218 extending into the semiconductor substrate 200 prevent an early breakdown of the semiconductor device. To simplify the drawing, only one second trench 218 between adjacent two first trenches 204 is shown here.

In an embodiment, each of the first trenches 204 has the same width and depth as each of the second trenches 218. In addition, the width and depth of the second trench 218 can be changed according to the needs of the characteristics of the semiconductor device, respectively.

Next, after the mask pattern is removed, a process (for example, thermal oxide growth method) is performed, and the second insulating liner 220 is conformally formed on the sidewall 221 and the lower surface 219 of the second trench 218.

Referring to FIG. 5, a doping process 216 (eg, a tilt ion implantation process) is performed from the opposite sidewalls 221 of each of the second trenches 218, and the epitaxial layer 202 is doped with respect to the first conductivity type. The third dopant of the second conductivity type forms a third doping region 222. As shown in FIG. 5, the third doped region 222 substantially surrounds the second trench 218. The depth of the third doped region 222 (eg, the distance between the upper surface 203 of the epitaxial layer 202 and the lower surface 213 of the third doped region 222) may be substantially greater than the depth of the second trench 218 (eg, an epitaxial layer) Between the upper surface 203 of the 202 and the lower surface 219 of the second trench 218 distance). Accordingly, the lower surface 219 of the second trench 218 can be located within the third doped region 222.

Likewise, the tilt angle θ2 of the doping process 216 is primarily dependent on the width and depth of the second trench 218. For example, the tilt angle θ2 of the doping process 216 may range from 1° to 10°. In one embodiment, after the doping process 216 is performed, a diffusion process (eg, a rapid thermal annealing process) may be performed in the third doped region 222 to activate dopants therein. The process temperature of the diffusion process may range from 800 ° C to 1500 ° C such that the third dopant may be uniformly distributed within the third doped region 222 .

In an embodiment, the third dopant may include boron, boron fluoride (BF2), indium, or a combination thereof. In addition, the doping concentration of the third doping region 222 may be greater than the epitaxial layer 202 and less than the doping concentration of the semiconductor substrate 200. It should be noted that the dose of the third dopant can be changed to match the total dose of the first dopant and the second dopant, thereby achieving the Lei between the first trench 204 and the second trench 218. The charge in the crystal layer 202 and the semiconductor substrate 200 is balanced.

Referring to FIG. 6, a second insulating material 230 is filled in each of the second trenches 218 by a process similar or identical to filling each of the first trenches 204. Next, a planarization process (eg, a chemical mechanical polishing process) is performed to remove excess second insulating material 230 on the upper surface 203 of the epitaxial layer 202. In addition, the upper surface of the second insulating material 230 is substantially aligned with the upper surface 203 of the epitaxial layer 202 after the planarization process. After performing the above process, a super junction structure 250 including a first doping region 210, a second doping region 310, and a third doping region 222 is formed, wherein each of the first doping regions 210 or the second doping The region 310 is adjacent to at least one of the third doping regions 222.

The plurality of gate structures 228 are correspondingly formed in the plurality of first trenches 204 on. Each gate structure 228 can include a gate oxide layer 224 and an upper gate layer 226. In one embodiment, the gate oxide layer 224 can be formed by a thermal oxidation process or other conventional deposition processes such as chemical vapor deposition processes or atomic layer deposition (ALD). Furthermore, the gate layer 226 can be formed by a conventional deposition process such as a physical vapor deposition (PVD), a chemical vapor deposition process, an atomic layer deposition process, a sputtering process, or a coating process. In one embodiment, each of the gate structures 228 respectively covers a first trench 204 and a portion of the epitaxial layer 202 adjacent to the covered first trench 204 such that the second via the gate structure 228 is exposed. Trench 218.

Next, using the gate structure 228 as a mask layer, a doping process (eg, an ion implantation process) is performed in the epitaxial layer 202 to actively act on the epitaxial layer 202 on both sides of each of the second trenches 218. A pair of well regions 232 having a second conductivity type are formed within region 300 such that the pair of well regions 232 are respectively located between adjacent two gate structures 228. Furthermore, the pair of well regions 232 are located above the third doped region 222.

Next, using the gate structure 228 as a mask layer, an additional doping process (eg, an ion implantation process) is performed to form a pair of source regions 234 having the first conductivity type correspondingly in the pair of well regions 232 ( For example, a pair of N-type heavily doped regions). The pair of source regions 234 are adjacent to one side of the corresponding gate structure 228, respectively. In addition, the interface position between the first doping region 210 and the third doping region 222 may be changed according to the needs of the characteristics of the semiconductor device.

A doping process is performed in a portion of the epitaxial layer 202 to form a pair of contact doped regions 240 having a second conductivity type. As shown in FIG. 6, the butt doping region 240 is formed in the pair of well regions 232, and each contact Doped region 240 is adjacent to corresponding source region 234.

Referring to FIG. 7, an inner dielectric layer 236 may be formed on the epitaxial layer 202 and cover the plurality of gate structures 228, such as by a chemical vapor deposition process. Next, a patterned photoresist layer (not shown) is formed on the inner dielectric layer 236 to define contact holes. Next, an anisotropic etching process is performed to remove a portion of the inner dielectric layer 236, and then a contact hole 238 is formed over each of the second trenches 218.

Next, a conductive layer is formed on the inner dielectric layer 236 and fills each contact hole 238 through a deposition process (eg, a sputtering process) to form a contact plug 242 in each contact hole 238. After the above process is performed, a semiconductor device 500 having a super junction structure 250 (e.g., a vertically diffused metal oxide semiconductor field effect transistor) is formed. In the method of fabricating the semiconductor device 500, an N-type vertical diffusion metal oxide semiconductor field effect transistor is used as the present embodiment. Alternatively, the first and second conductivity types described above may be exchanged to form a P-type vertical diffusion metal oxide semiconductor field effect transistor.

By controlling the doping concentration of the N-type doped region and the P-type doped region, the super junction structure 250 can achieve an effect of improving charge balance as compared with the prior art. The doping concentration of the N-type epitaxial layer may vary depending on the design of the semiconductor device. In addition, an additional epitaxial growth process is not required in the manufacturing method of the super junction structure 250, and therefore, the manufacturing cost can be reduced. The semiconductor device fabricated in the super junction structure 250 can have a smaller size than conventional techniques.

In the above embodiment, the conduction is reduced by forming the first doping region 210 and the second doping region 310 containing dopants and having different diffusion coefficients and activating the dopant by an annealing process (for example, a rapid thermal annealing process). Resistance (Ron), And increase the breakdown voltage (VB). In addition, the charge balance in the epitaxial layer 202 can be improved by the first doped region 210 formed by doping the epitaxial layer 202 with the first dopant (as described in FIGS. 1 to 7). Increase the breakdown voltage (VB). Furthermore, since the second doping region 310 is formed by doping the epitaxial layer 202 with the second dopant (as described in FIGS. 1 to 7), the second doping region 310 has a small conduction. The resistor (Ron) thus helps to direct current through the semiconductor device 500. For example, referring to FIG. 7, the second doping region 310 can help direct current (not shown) from the contact plug 242 to the source region 234 and the well region 232, substantially along the epitaxial layer 202. The sidewall of the first trench 204 in the semiconductor substrate 200 flows and flows through the epitaxial layer 202 and the semiconductor substrate 200. Therefore, more current can be driven to flow through the semiconductor device 500 to generate a high saturation current.

While the invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and any of ordinary skill in the art can be used in various modifications and equivalents. Therefore, equivalent changes and modifications made in the scope of the invention and the description of the invention are still within the scope of the invention.

200‧‧‧Semiconductor substrate

202‧‧‧ epitaxial layer

203, 213‧‧‧ upper surface

204‧‧‧First trench

205, 209, 211, 219, 229‧‧‧ lower surface

206‧‧‧First insulating lining

207, 221‧‧‧ side wall

208, 216‧‧‧ doping process

210‧‧‧First doped area

212‧‧‧First insulation material

218‧‧‧Second trench

220‧‧‧Second insulation lining

222‧‧‧ Third doped area

224‧‧ ‧ gate oxide layer

226‧‧ ‧ gate layer

228‧‧ ‧ gate structure

230‧‧‧Second insulation

232‧‧‧ Well Area

234‧‧‧ source area

236‧‧‧ Inner dielectric layer

238‧‧‧Contact hole

240‧‧‧Contact Doping Area

242‧‧‧Contact plug

250‧‧‧Super junction structure

300‧‧‧active area

302‧‧‧ Terminal Area

310‧‧‧Second doped area

500‧‧‧Semiconductor device

Θ1, θ2‧‧‧ tilt angle

1 to 7 are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

200‧‧‧Semiconductor substrate

202‧‧‧ epitaxial layer

203‧‧‧ upper surface

204‧‧‧First trench

205, 209, 211, 219, 229‧‧‧ lower surface

206‧‧‧First insulating lining

207, 221‧‧‧ side wall

210‧‧‧First doped area

212‧‧‧First insulation material

218‧‧‧Second trench

220‧‧‧Second insulation lining

222‧‧‧ Third doped area

224‧‧ ‧ gate oxide layer

226‧‧ ‧ gate layer

228‧‧ ‧ gate structure

230‧‧‧Second insulation

232‧‧‧ Well Area

234‧‧‧ source area

236‧‧‧ Inner dielectric layer

238‧‧‧Contact hole

240‧‧‧Contact Doping Area

242‧‧‧Contact plug

250‧‧‧Super junction structure

300‧‧‧active area

302‧‧‧ Terminal Area

310‧‧‧Second doped area

500‧‧‧Semiconductor device

Claims (17)

A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming an epitaxial layer having the first conductivity type on the semiconductor substrate; forming a plurality of first trenches in the epitaxial layer Forming a first doped region having the first conductivity type in the epitaxial layer and surrounding each of the first trenches; forming a first conductivity type in each of the first doping regions a second doped region adjacent to each of the first trenches; each of the first trenches is filled with a first insulating material; and a plurality of second regions alternately arranged with the first trenches are formed in the epitaxial layer a trench; a third doped region having a second conductivity type formed in the epitaxial layer and surrounding each second trench; and each second trench filled with a second insulating material; wherein each A first doped region includes a first dopant and each of the second doped regions includes a second dopant, and a diffusion coefficient of the first dopant is greater than a diffusion coefficient of the second dopant. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type It is N type. The method of fabricating a semiconductor device according to claim 1, wherein a doping concentration of the semiconductor substrate is greater than a doping concentration of the epitaxial layer. The method for fabricating a semiconductor device according to claim 1, further comprising: performing a first diffusion process in each of the first doping regions; and performing a second diffusion in each of the third doping regions Process. The method of fabricating a semiconductor device according to claim 1, wherein the lower surfaces of the first trenches and the second trenches are located in the semiconductor substrate. The method of fabricating a semiconductor device according to claim 1, wherein each of the first insulating material and each of the second insulating materials comprises an oxide or a non-doped polysilicon. The method of fabricating a semiconductor device according to claim 1, wherein each of the first doped regions is adjacent to at least one of the third doped regions. The method for fabricating a semiconductor device according to claim 1, further comprising: forming a plurality of gate structures correspondingly on the first trenches, wherein each gate structure comprises a gate oxide layer and an upper portion a gate layer; a pair of well regions having the second conductivity type formed on both sides of each of the second trenches in the epitaxial layer; and correspondingly formed in the pair of well regions A pair of source regions. The method of fabricating a semiconductor device according to claim 1, wherein the first dopant is phosphorus and the second dopant is arsenic. A semiconductor device comprising: a semiconductor substrate having a first conductivity type; An epitaxial layer having the first conductivity type disposed on the semiconductor substrate; a plurality of first trenches filled with a first insulating material disposed in the epitaxial layer; and a first doped region having the a first conductivity type disposed in the epitaxial layer and surrounding each of the first trenches; a second doped region having the first conductivity type disposed in each of the first doping regions and adjacent to each a first trench; a plurality of second trenches filled with a second insulating material, and the first trenches are alternately arranged in the epitaxial layer; and a third doped region having a second conductive region And disposed in the epitaxial layer and surrounding each of the second trenches; wherein each of the first doped regions includes a first dopant and each of the second doped regions includes a second dopant, and The diffusion coefficient of the first dopant is greater than the diffusion coefficient of the second dopant. The semiconductor device of claim 10, wherein the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type . The semiconductor device of claim 10, wherein the semiconductor substrate has a doping concentration greater than a doping concentration of the epitaxial layer. The semiconductor device of claim 10, wherein the lower surfaces of the first trenches and the second trenches are located in the semiconductor substrate. The semiconductor device of claim 10, wherein each of the first insulating material and each of the second insulating materials comprises an oxide or a non-doped Heteropolycrystalline germanium. The semiconductor device of claim 10, wherein each of the first doped regions is adjacent to at least one of the third doped regions. The semiconductor device of claim 10, further comprising: a plurality of gate structures correspondingly disposed on the first trenches, wherein each gate structure comprises a gate oxide layer and a gate above a pair of well regions having the second conductivity type disposed on both sides of each of the second trenches in the epitaxial layer; and a pair of source regions having the first conductivity type, correspondingly Set in the pair of well areas. The semiconductor device of claim 10, wherein the first dopant is phosphorus and the second dopant is arsenic.