TW201635536A - 半導體元件及其製作方法 - Google Patents
半導體元件及其製作方法 Download PDFInfo
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- TW201635536A TW201635536A TW104109776A TW104109776A TW201635536A TW 201635536 A TW201635536 A TW 201635536A TW 104109776 A TW104109776 A TW 104109776A TW 104109776 A TW104109776 A TW 104109776A TW 201635536 A TW201635536 A TW 201635536A
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- hard mask
- interlayer dielectric
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims description 49
- 239000010410 layer Substances 0.000 claims abstract description 185
- 239000011229 interlayer Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 14
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 13
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 7
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 31
- 239000002184 metal Substances 0.000 description 31
- 238000005530 etching Methods 0.000 description 16
- 238000001459 lithography Methods 0.000 description 11
- 239000007769 metal material Substances 0.000 description 10
- 229910000951 Aluminide Inorganic materials 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910021324 titanium aluminide Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910010041 TiAlC Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
本發明揭露一種半導體元件,其包含一基底,一閘極結構設於基底上,一第一層間介電層環繞閘極結構,一第一硬遮罩設於閘極結構上以及一第二硬遮罩設於閘極結構上,其中第一硬遮罩設於第二硬遮罩兩側且第一硬遮罩包含氮化矽。
Description
本發明是關於一種半導體元件及其製作方法,尤指一種在進行自行對準接觸插塞(self-aligned contacts,SAC))製程時於閘極結構上形成兩層硬遮罩的半導體元件及其製作方法。
在習知半導體產業中,多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor,MOS)電晶體中,作為標準的閘極填充材料選擇。然而,隨著MOS電晶體尺寸持續地微縮,傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低,及其難以避免的空乏效應(depletion effect)等問題,使得等效的閘極介電層厚度增加、閘極電容值下降,進而導致元件驅動能力的衰退等困境。因此,半導體業界更嘗試以新的閘極填充材料,例如利用功函數(work function)金屬來取代傳統的多晶矽閘極,用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
在現今金屬閘極電晶體製作過程中,特別是在進行自行對準接觸插塞(self-aligned contacts,SAC))製程時通常會進行兩次微影
暨蝕刻分別形成連接閘極結構與源極/汲極區域的接觸插塞。由於閘極結構上的硬遮罩通常僅為單一材料所構成,一般在去除部分硬遮罩以形成接觸插塞過程中容易使後續連接閘極結構的接觸插塞接觸到連接源極/汲極區域的接觸插塞並造成短路。因此如何改良現行金屬閘極製程以解決此問題即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底,該基底上具有一閘極結構以及一第一層間介電層環繞閘極結構,然後去除部分閘極結構,形成一第一遮罩層於第一層間介電層及閘極結構上,去除第一層間介電層上之第一遮罩層及閘極結構上之部分第一遮罩層以形成一第一硬遮罩於閘極結構上,形成一第二遮罩層於第一層間介電層、第一硬遮罩及閘極結構上。之後再平坦化部分第二遮罩層以形成一第二硬遮罩於閘極結構上,其中第一硬遮罩、第二硬遮罩及第一層間介電層之上表面齊平。
本發明又一實施例揭露一種半導體元件,其包含一基底,一閘極結構設於基底上,一第一層間介電層環繞閘極結構,一第一硬遮罩設於閘極結構上以及一第二硬遮罩設於閘極結構上,其中第一硬遮罩設於第二硬遮罩兩側且第一硬遮罩包含氮化矽。
本發明另一實施例揭露一種半導體元件,包含一基底,一閘極結構設於基底上,一第一層間介電層環繞閘極結構,一第一硬遮罩設於閘極結構上以及一第二硬遮罩設於閘極結構上,其中第一硬遮罩設於第二硬遮罩兩側且第一硬遮罩及第二硬遮罩均直接接觸
閘極結構。
12‧‧‧基底
14‧‧‧鰭狀結構
18‧‧‧閘極結構
24‧‧‧側壁子
26‧‧‧源極/汲極區域
30‧‧‧接觸洞蝕刻停止層
32‧‧‧層間介電層
34‧‧‧功函數金屬層
36‧‧‧低阻抗金屬層
38‧‧‧閘極電極
40‧‧‧第一遮罩層
42‧‧‧第二遮罩層
44‧‧‧第一硬遮罩
46‧‧‧第二硬遮罩
48‧‧‧層間介電層
50‧‧‧接觸插塞
第1圖至第3圖為本發明第一實施例製作一半導體元件之方法示意圖。
第4圖至第6圖為本發明第二實施例製作一半導體元件之方法示意圖。
第7圖至第10圖為本發明第三實施例製作一半導體元件之方法示意圖。
第11圖至第14圖為本發明第四實施例製作一半導體元件之方法示意圖。
請參照第1圖至第3圖,第1圖至第3圖為本發明第一實施例製作一半導體元件之方法示意圖。如第1圖所示,首先提供一基底12,例如一矽基底或矽覆絕緣(SOI)基板,其上定義有一電晶體區,例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示),其中鰭狀結構14之底部係被絕緣層,例如氧化矽所包覆而形成淺溝隔離,且部分的鰭狀結構14上設有一閘極結構18。
上述鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上,再經過一蝕刻製程,將圖案化遮罩之圖案轉移至基底12中。接著,對應三閘極電晶體元件及雙閘極鰭狀電晶
體元件結構特性的不同,而可選擇性去除或留下圖案化遮罩,並利用沈積、化學機械研磨(chemical mechanical polishing,CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之絕緣層。除此之外,鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上,並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層,此半導體層即可作為相對應的鰭狀結構14。同樣的,另可以選擇性去除或留下圖案化硬遮罩層,並透過沈積、CMP及回蝕刻製程形成一絕緣層以包覆住鰭狀結構14之底部。另外,當基底12為矽覆絕緣(SOI)基板時,則可利用圖案化遮罩來蝕刻基底上之一半導體層,並停止於此半導體層下方的一底氧化層以形成鰭狀結構,故可省略前述製作絕緣層的步驟。
閘極結構18之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先閘極介電層(high-k first)製程以及後閘極製程之後閘極介電層(high-k last)製程等方式製作完成。以本實施例之先閘極介電層製程為例,可先於鰭狀結構14與絕緣層上形成一較佳包含高介電常數介電層與多晶矽材料所構成的虛置閘極(圖未示),然後於虛置閘極側壁形成側壁子24。接著於側壁子24兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域26與磊晶層(圖未示)、形成一接觸洞蝕刻停止層30覆蓋虛置閘極,並形成一由四乙氧基矽烷(Tetraethyl orthosilicate,TEOS)所組成的層間介電層32於接觸洞蝕刻停止層30上。
之後可進行一金屬閘極置換(replacement metal gate)製程,先平坦化部分之層間介電層32及接觸洞蝕刻停止層30,並再將虛置閘極轉換為一金屬閘極。金屬閘極置換製程可包括先進行一
選擇性之乾蝕刻或濕蝕刻製程,例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除虛置閘極中的多晶矽材料以於層間介電層32中形成一凹槽。之後形成一至少包含U型功函數金屬層34與低阻抗金屬層36的導電層於該凹槽內,並再搭配進行一平坦化製程使U型功函數金屬層34與低阻抗金屬層36的表面與層間介電層32表面齊平,以形成閘極結構18之閘極電極38。
在本實施例中,功函數金屬層34較佳用以調整形成金屬閘極之功函數,使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體,功函數金屬層34可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料,如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等,但不以此為限;若電晶體為P型電晶體,功函數金屬層34可選用功函數為4.8eV~5.2eV的金屬材料,如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等,但不以此為限。功函數金屬層34與低阻抗金屬層36之間可包含另一阻障層(圖未示),其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層44則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide,CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝,在此不另加贅述。
形成閘極結構18後可選擇性先去除部分閘極電極38,例如部分功函數金屬層34與低阻抗金屬層36以於側壁子24間蝕刻出一凹槽,然後依序形成一第一遮罩層40與一第二遮罩層42於層間
介電層32、接觸洞蝕刻停止層30、側壁子24及閘極電極38上。
如第2圖所示,接著以CMP製程平坦化部分第二遮罩層42及部分第一遮罩層40,以形成一第一硬遮罩44與一第二硬遮罩46於閘極電極38上,其中第一硬遮罩44、第二硬遮罩46、側壁子24、接觸洞蝕刻停止層30及層間介電層32之上表面為齊平。
在本實施例中,第一硬遮罩44及第二硬遮罩46較佳包含不同材料,例如本實施例之第一硬遮罩44包含氮化矽而第二硬遮罩46包含氧化矽,但不侷限於此。另外以結構來看,本實施例之第一硬遮罩44較佳為U型且設於閘極電極38上並相接觸,而第二硬遮罩46則設於第一硬遮罩44上且不接觸閘極電極38。
接著如第3圖所示,形成另一層間介電層48於第一硬遮罩44、第二硬遮罩46、側壁子24、接觸洞蝕刻停止層30以及層間介電層32上,然後進行一接觸插塞製程以形成複數個接觸插塞50分別電連接閘極電極38與源極/汲極區域26。在本實施例中,接觸插塞50的製作可先利用一微影暨蝕刻製程去除部分閘極電極38正上方的部分層間介電層48與部分或全部的第二硬遮罩46以暴露出第一硬遮罩44表面,隨後再進行另一道蝕刻製程去除部分第一硬遮罩44,使剩下的第一硬遮罩44如側壁子一般,僅覆蓋在凹槽側壁而暴露出閘極電極38頂表面,以形成一接觸洞。接著重複進行上述微影暨蝕刻步驟再分別形成兩個接觸洞暴露源極/汲極區域26,然後同時填入金屬材料於各接觸洞中並再以CMP製程去除部分金屬材料甚至部分層間介電層48以形成電連接閘極電極38與源極/汲極區域26的接觸插塞50。至此即完成本發明第一實施例之半導體元件
的製作。
請參照第4圖至第6圖,第4圖至第6圖為本發明第二實施例製作一半導體元件之方法示意圖。如第4圖所示,依據前述第一實施例中形成由U型功函數金屬層34與低阻抗金屬層36所構成的閘極電極38後可先去除部分閘極電極38與部分側壁子24以於層間介電層32中形成一凹槽,然後依序形成一第一遮罩層40與一第二遮罩層42於層間介電層32、接觸洞蝕刻停止層30、側壁子24及閘極電極38上。
如第5圖所示,接著以CMP製程平坦化部分第二遮罩層42及部分第一遮罩層40以形成一第一硬遮罩44與一第二硬遮罩46於側壁子24及閘極電極38上,其中第一硬遮罩44、第二硬遮罩46、接觸洞蝕刻停止層30及層間介電層32之上表面為齊平。
在本實施例中,第一硬遮罩44及第二硬遮罩46較佳包含不同材料,例如本實施例之第一硬遮罩44包含氮化矽而第二硬遮罩46包含氧化矽,但不侷限於此。另外以結構來看,本實施例之第一硬遮罩44較佳為U型且同時跨坐在閘極電極38與側壁子24上,而第二硬遮罩46則設於第一硬遮罩44上且不接觸閘極電極38。
接著如第6圖所示,形成另一層間介電層48於第一硬遮罩44、第二硬遮罩46、側壁子24、接觸洞蝕刻停止層30以及層間介電層32上,然後進行一接觸插塞製程以形成複數個接觸插塞50分別電連接閘極電極38與源極/汲極區域26。在本實施例中,接觸插塞50的製作可先利用一微影暨蝕刻製程去除部分閘極電極38正
上方的部分層間介電層48與部分第二硬遮罩46以暴露出第一硬遮罩44表面,隨後再進行另一道蝕刻製程去除部分第一硬遮罩44暴露出閘極電極38表面以形成一接觸洞。接著重複進行上述微影暨蝕刻步驟再分別形成兩個接觸洞暴露源極/汲極區域26,然後同時填入金屬材料於各接觸洞中並再以CMP製程去除部分金屬材料甚至部分層間介電層48以形成電連接閘極電極38與源極/汲極區域26的接觸插塞50。至此即完成本發明第二實施例之半導體元件的製作。
請參照第7圖至第10圖,第7圖至第10圖為本發明第三實施例製作一半導體元件之方法示意圖。如第7圖所示,依據前述第一實施例中形成由U型功函數金屬層34與低阻抗金屬層36所構成的閘極電極38後可先以蝕刻去除部分閘極電極38以於側壁子24間形成一凹槽,然後共形地形成一第一遮罩層40於層間介電層32、接觸洞蝕刻停止層30、側壁子24及閘極電極38上。
接著如第8圖所示,去除層間介電層32、接觸洞蝕刻停止層30及側壁子24上的第一遮罩層40以及閘極電極38上的部分第一遮罩層40,使剩下的第一遮罩層40如側壁子一般僅覆蓋在凹槽側壁,以形成一第一硬遮罩44於閘極電極38上,並再形成一第二遮罩層42於層間介電層32、接觸洞蝕刻停止層30、側壁子24、第一硬遮罩44及閘極電極38上。
如第9圖所示,然後以CMP製程平坦化部分第二遮罩層42以形成一第二硬遮罩46於第一硬遮罩44之間的閘極電極38上,使第一硬遮罩44、第二硬遮罩46、側壁子24、接觸洞蝕刻停止層30及層間介電層32上表面齊平。
在本實施例中,第一硬遮罩44及第二硬遮罩46較佳包含不同材料,例如本實施例之第一硬遮罩44包含氮化矽而第二硬遮罩46包含氧化矽,但不侷限於此。另外以結構來看,本實施例的第一硬遮罩44與第二硬遮罩46均同時設置於閘極電極38上並直接接觸閘極電極38,且第二硬遮罩46較佳設置於第一硬遮罩44之間。
接著如第10圖所示,形成另一層間介電層48於第一硬遮罩44、第二硬遮罩46、側壁子24、接觸洞蝕刻停止層30以及層間介電層32上,然後進行一接觸插塞製程以形成複數個接觸插塞50分別電連接閘極電極38與源極/汲極區域26。在本實施例中,接觸插塞50的製作可先利用一微影暨蝕刻製程去除部分閘極電極38正上方的部分層間介電層48與部分或全部的第二硬遮罩46以暴露出閘極電極38表面以形成一接觸洞。相較於前述第一實施例與第二實施例中需採用兩段式蝕刻來分別去除部分由不同材料所構成的第二硬遮罩46與第一硬遮罩44以形成接觸洞,本實施例之第一硬遮罩44並非U型且未設於第二硬遮罩46下方,因此僅需以一道微影暨蝕刻製程便可形成接觸插塞50所需的接觸洞。接著重複進行上述微影暨蝕刻步驟再分別形成兩個接觸洞暴露源極/汲極區域26,然後同時填入金屬材料於各接觸洞中並再以CMP製程去除部分金屬材料甚至部分層間介電層48以形成電連接閘極電極38與源極/汲極區域26的接觸插塞50。至此即完成本發明第三實施例之半導體元件的製作。
請參照第11圖至第14圖,第11圖至第14圖為本發明第四實施例製作一半導體元件之方法示意圖。如第11圖所示,依據前
述第一實施例中形成由U型功函數金屬層34與低阻抗金屬層36所構成的閘極電極38後可先去除部分閘極電極38與部分側壁子24以於層間介電層32中形成一凹槽,然後共形地形成一第一遮罩層40於層間介電層32、接觸洞蝕刻停止層30、側壁子24及閘極電極38上。
接著如第12圖所示,去除層間介電層32與接觸洞蝕刻停止層30上的第一遮罩層40及閘極電極38上的部分第一遮罩層40,使剩下的第一遮罩層40如側壁子一般僅覆蓋在凹槽側壁,以形成第一硬遮罩44於側壁子24上,並形成一第二遮罩層42於層間介電層32、接觸洞蝕刻停止層30、第一硬遮罩44及閘極電極38上。
如第13圖所示,然後以CMP製程平坦化部分第二遮罩層42以形成一第二硬遮罩46於閘極電極38上,使第一硬遮罩44、第二硬遮罩46、接觸洞蝕刻停止層30及層間介電層32之上表面為齊平。
在本實施例中,第一硬遮罩44及第二硬遮罩46較佳包含不同材料,例如本實施例之第一硬遮罩44包含氮化矽而第二硬遮罩46包含氧化矽,但不侷限於此。另外以結構來看,本實施例的第一硬遮罩44與第二硬遮罩46均同時設置於閘極電極38與側壁子24上並接觸閘極電極38,或從更細部來看,第一硬遮罩44設置於側壁子24上而第二硬遮罩46則設於閘極電極38上,且第二硬遮罩46較佳設置於第一硬遮罩44之間。
接著如第14圖所示,形成另一層間介電層48於第一硬遮
罩44、第二硬遮罩46、側壁子24、接觸洞蝕刻停止層30以及層間介電層32上,然後進行一接觸插塞製程以形成複數個接觸插塞50分別電連接閘極電極38與源極/汲極區域26。在本實施例中,接觸插塞50的製作可先利用一微影暨蝕刻製程去除部分閘極電極38正上方的部分層間介電層48與部分第二硬遮罩46以暴露出閘極電極38表面以形成一接觸洞。如同第三實施例,本實施例的第一硬遮罩44並非U型且未設於第二硬遮罩46下方,因此僅需以一道微影暨蝕刻製程便可形成接觸插塞50所需的接觸洞。接著重複進行上述微影暨蝕刻步驟再分別形成兩個接觸洞暴露源極/汲極區域26,然後同時填入金屬材料於各接觸洞中並再以CMP製程去除部分金屬材料甚至部分層間介電層48以形成電連接閘極電極38與源極/汲極區域26的接觸插塞50。至此即完成本發明第四實施例之半導體元件的製作。
綜上所述,本發明主要於閘極電極上形成兩層硬遮罩,其中第一硬遮罩設於第二硬遮罩兩側且第一硬遮罩較佳由氮化矽所構成而第二硬遮罩則較佳由氧化矽所構成。依據前述實施例,本發明之第一硬遮罩與第二硬遮罩的組合共有四種態樣,其中第一硬遮罩可為U型或I型,或側壁子可經由蝕刻使第一硬遮罩直接跨坐於側壁子上。由於本發明是採用雙層硬遮罩的設計且較佳將由氮化矽所設於第一硬遮罩環繞由氧化矽所構成的第二硬遮罩,本發明可於後續製作接觸插塞時避免連接閘極結構的接觸插塞直接接觸到連接源極/汲極區域的接觸插塞並造成短路。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧鰭狀結構
18‧‧‧閘極結構
24‧‧‧側壁子
26‧‧‧源極/汲極區域
30‧‧‧接觸洞蝕刻停止層
32‧‧‧層間介電層
34‧‧‧功函數金屬層
36‧‧‧低阻抗金屬層
38‧‧‧閘極電極
44‧‧‧第一硬遮罩
46‧‧‧第二硬遮罩
48‧‧‧層間介電層
50‧‧‧接觸插塞
Claims (20)
- 一種製作半導體元件的方法,包含:提供一基底,該基底上具有一閘極結構以及一第一層間介電層環繞該閘極結構;去除部分該閘極結構;形成一第一遮罩層於該第一層間介電層及該閘極結構上;去除該第一層間介電層上之該第一遮罩層及該閘極結構上之部分該第一遮罩層以形成一第一硬遮罩於該閘極結構上;形成一第二遮罩層於該第一層間介電層、該第一硬遮罩及該閘極結構上;以及平坦化部分該第二遮罩層以形成一第二硬遮罩於該閘極結構上,其中該第一硬遮罩、該第二硬遮罩及該第一層間介電層之上表面齊平。
- 如申請專利範圍第1項所述之方法,其中該閘極結構包含一閘極電極以及一側壁子鄰近該閘極電極,該方法另包含:去除該閘極結構之部分該閘極電極;形成該第一遮罩層於該第一層間介電層、該側壁子及該閘極電極上;去除該第一層間介電層及該側壁子上之該第一遮罩層及該閘極電極上之部分該第一遮罩層以形成該第一硬遮罩於該閘極電極上;形成該第二遮罩層於該第一層間介電層、該第一硬遮罩及該閘極電極上;以及平坦化部分該第二遮罩層以形成該第二硬遮罩於該閘極電極 上,其中該第一硬遮罩、該第二硬遮罩、該側壁子及該第一層間介電層之上表面為齊平。
- 如申請專利範圍第2項所述之方法,另包含:形成一第二層間介電層於該第一硬遮罩、該第二硬遮罩、該側壁子及該第一層間介電層上;去除部分該第二層間介電層及該第一硬遮罩以暴露該閘極結構;以及形成一接觸插塞電連接該閘極結構。
- 如申請專利範圍第1項所述之方法,其中該閘極結構包含一閘極電極以及一側壁子鄰近該閘極電極,該方法另包含:去除該閘極結構之部分該閘極電極及部分該側壁子;形成該第一遮罩層於該第一層間介電層、該側壁子及該閘極電極上;去除該第一層間介電層上之該第一遮罩層及該閘極電極上之部分該第一遮罩層以形成該第一硬遮罩於該側壁子上;形成該第二遮罩層於該第一層間介電層、該第一硬遮罩、及該閘極電極上;以及平坦化部分該第二遮罩層以形成該第二硬遮罩於該閘極電極上,其中該第一硬遮罩、該第二硬遮罩及該第一層間介電層之上表面為齊平。
- 如申請專利範圍第4項所述之方法,另包含:形成一第二層間介電層於該第一硬遮罩、該第二硬遮罩及該第一層間介電層上; 去除部分該第二層間介電層及該第一硬遮罩以暴露該閘極結構;以及形成一接觸插塞電連接該閘極結構。
- 如申請專利範圍第1項所述之方法,其中該第一硬遮罩及該第二硬遮罩包含不同材料。
- 如申請專利範圍第1項所述之方法,其中該第一硬遮罩包含氮化矽且該第二硬遮罩包含氧化矽。
- 一種半導體元件,包含:一基底,該基底上設有一閘極結構以及一第一層間介電層環繞該閘極結構;一第一硬遮罩設於該閘極結構上;以及一第二硬遮罩設於該閘極結構上,其中該第一硬遮罩設於該第二硬遮罩兩側且該第一硬遮罩包含氮化矽。
- 如申請專利範圍第8項所述之半導體元件,其中該閘極結構包含一閘極電極以及一側壁子鄰近該閘極電極,該半導體元件另包含:該第一硬遮罩設於該閘極電極上;以及該第二硬遮罩設於該第一硬遮罩上。
- 如申請專利範圍第9項所述之半導體元件,其中該第一硬遮罩為U型。
- 如申請專利範圍第8項所述之半導體元件,其中該閘極結構包含一閘極電極以及一側壁子鄰近該閘極電極,該半導體元件另包含: 該第一硬遮罩設於該閘極電極及該側壁子上;以及該第二硬遮罩設於該第一硬遮罩上。
- 如申請專利範圍第11項所述之半導體元件,其中該第一硬遮罩為U型。
- 如申請專利範圍第8項所述之半導體元件,其中該閘極結構包含一閘極電極以及一側壁子鄰近該閘極電極,該半導體元件另包含:該第一硬遮罩設於該閘極電極上;以及該第二硬遮罩設於該閘極電極上並直接接觸該閘極電極。
- 如申請專利範圍第8項所述之半導體元件,其中該閘極結構包含一閘極電極以及一側壁子鄰近該閘極電極,該半導體元件另包含:該第一硬遮罩設於該側壁子上;以及該第二硬遮罩設於該閘極電極上並直接接觸該閘極電極。
- 如申請專利範圍第8項所述之半導體元件,其中該第一硬遮罩包含氮化矽且該第二硬遮罩包含氧化矽。
- 如申請專利範圍第8項所述之半導體元件,另包含:一第二層間介電層設於該第一層間介電層、該第一硬遮罩及該第二硬遮罩上;以及一接觸插塞貫穿該第二層間介電層及第二硬遮罩並直接接觸該閘極結構。
- 如申請專利範圍第8項所述之半導體元件,另包含:一第二層間介電層設於該第一層間介電層、該第一硬遮罩及該第 二硬遮罩上;以及一接觸插塞貫穿該第二層間介電層、該第一硬遮罩及該第二硬遮罩並直接接觸該閘極結構。
- 一種半導體元件,包含:一基底,該基底上設有一閘極結構以及一第一層間介電層環繞該閘極結構;一第一硬遮罩設於該閘極結構上;以及一第二硬遮罩設於該閘極結構上,其中該第一硬遮罩設於該第二硬遮罩兩側且該第一硬遮罩及該第二硬遮罩均直接接觸該閘極結構。
- 如申請專利範圍第18項所述之半導體元件,其中該第一硬遮罩包含氮化矽且該第二硬遮罩包含氧化矽。
- 如申請專利範圍第18項所述之半導體元件,另包含:一第二層間介電層設於該第一層間介電層、該第一硬遮罩及該第二硬遮罩上;以及一接觸插塞貫穿該第二層間介電層及該第二硬遮罩並直接接觸該閘極結構。
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CN201510210463.5A CN106206270B (zh) | 2015-03-26 | 2015-04-29 | 半导体器件及其制作方法 |
CN202010439678.5A CN111653483B (zh) | 2015-03-26 | 2015-04-29 | 半导体器件及其制作方法 |
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US20160315007A1 (en) | 2016-10-27 |
US9607892B2 (en) | 2017-03-28 |
US9466564B1 (en) | 2016-10-11 |
CN106206270B (zh) | 2020-06-23 |
CN111653483A (zh) | 2020-09-11 |
TWI642188B (zh) | 2018-11-21 |
CN111653483B (zh) | 2023-04-11 |
CN106206270A (zh) | 2016-12-07 |
US20160284641A1 (en) | 2016-09-29 |
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