TW201528477A - E-fuse structure of semiconductor device - Google Patents

E-fuse structure of semiconductor device Download PDF

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TW201528477A
TW201528477A TW103135016A TW103135016A TW201528477A TW 201528477 A TW201528477 A TW 201528477A TW 103135016 A TW103135016 A TW 103135016A TW 103135016 A TW103135016 A TW 103135016A TW 201528477 A TW201528477 A TW 201528477A
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fuse link
fuse
metal
plug
dummy
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TW103135016A
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TWI691054B (en
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Hyun-Min Choi
Shigenobu Maeda
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Samsung Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.

Description

半導體元件的電熔絲結構 Electrical fuse structure of semiconductor component 【對相關申請案之交叉參考】[Cross-reference to related applications]

2013年10月11日申請之美國專利申請案第61/889,911號以及2014年2月26日申請且題為「半導體元件的電熔絲結構(E-Fuse Structure of Semiconductor Device)」的韓國專利申請案第10-2014-0022774號的全文以引用方式併入本文中。 Korean Patent Application entitled "E-Fuse Structure of Semiconductor Device", filed on October 11, 2013, and filed on Feb. 26, 2014, and entitled "E-Fuse Structure of Semiconductor Device" The entire contents of the Japanese Patent Publication No. 10-2014-0022774 are herein incorporated by reference.

本文中所描述之一或多個實施例是關於半導體元件的電熔絲結構。 One or more embodiments described herein are related to an electrical fuse structure of a semiconductor component.

熔絲在半導體晶片製造及設計中已用於各種用途。舉例而言,在記憶體元件中,熔絲已用以在修復程序期間用冗餘記憶胞替換缺陷記憶胞。此替換有助於增加製造良率。熔絲亦已用以在晶片識別程序期間記錄晶片的製造歷史。熔絲亦已用以在晶片定製程序之製造後操作中使晶片的特性最佳化。 Fuses have been used in a variety of applications in semiconductor wafer fabrication and design. For example, in a memory component, a fuse has been used to replace a defective memory cell with a redundant memory cell during a repair procedure. This replacement helps increase manufacturing yield. Fuses have also been used to record the manufacturing history of wafers during the wafer identification process. Fuses have also been used to optimize wafer characteristics during post-manufacturing operations of wafer customization programs.

熔絲可被分類為鐳射熔絲或電熔絲。在鐳射熔絲中,將 鐳射束用以切斷電連接。在電熔絲中,將電流用於此用途。 The fuse can be classified as a laser fuse or an electric fuse. In the laser fuse, will The laser beam is used to cut off the electrical connection. In an electrical fuse, current is used for this purpose.

根據一個實施例,半導體元件之電熔絲結構包含:連接陰極與陽極的第一金屬材料之熔絲鏈;覆蓋所述熔絲鏈之頂部表面的罩蓋介電質;以及穿透所述罩蓋介電質並接觸所述熔絲鏈的虛設金屬插塞(dummy metal plug),所述虛設金屬插塞包含金屬層與所述熔絲鏈之間的障壁金屬層,其中所述障壁金屬層包含不同於所述第一金屬材料的第二金屬材料。第一金屬材料可具有大於第二金屬材料之電導率的電導率。 According to one embodiment, an electrical fuse structure of a semiconductor component includes: a fuse link of a first metal material connecting a cathode and an anode; a cap dielectric covering a top surface of the fuse link; and penetrating the cover a dummy metal plug covering the dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer A second metal material different from the first metal material is included. The first metallic material may have a conductivity greater than the electrical conductivity of the second metallic material.

第一金屬材料可包含鎢、鋁、銅或銅合金中的至少一者,且第二金屬材料可包含Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合中的至少一者。 The first metal material may include at least one of tungsten, aluminum, copper, or a copper alloy, and the second metal material may include at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof .

電熔絲結構為攜載程式化電流的熔絲鏈,且熔絲鏈在程式化狀態下具有介於陽極與虛設金屬插塞之間的空隙。空隙與虛設金屬插塞之間的距離可小於空隙與陽極之間的距離。虛設金屬插塞之下部寬度可小於所述熔絲鏈的上部寬度。 The electrical fuse structure is a fuse chain carrying a stylized current, and the fuse link has a gap between the anode and the dummy metal plug in a stylized state. The distance between the void and the dummy metal plug may be less than the distance between the void and the anode. The width of the lower portion of the dummy metal plug may be smaller than the upper width of the fuse link.

虛設金屬插塞之下部寬度可大於熔絲鏈的上部寬度,且虛設金屬插塞可接觸熔絲鏈的頂部表面及側表面。障壁金屬層可覆蓋金屬層的底部及側表面。在金屬層的底部表面上的障壁金屬層可較在金屬層之所述側表面中之一者或兩者上的障壁金屬層厚。 The width of the lower portion of the dummy metal plug may be greater than the upper width of the fuse link, and the dummy metal plug may contact the top surface and the side surface of the fuse link. The barrier metal layer covers the bottom and side surfaces of the metal layer. The barrier metal layer on the bottom surface of the metal layer may be thicker than the barrier metal layer on one or both of the side surfaces of the metal layer.

虛設金屬插塞之底部表面可在熔絲鏈之頂部表面與底部表面之間。金屬層可包含具有第一寬度的接觸部分,及具有大 於第一寬度之第二寬度的互連部分。熔絲鏈可具有實質上等於或小於陽極及陰極之寬度的寬度。 The bottom surface of the dummy metal plug can be between the top surface and the bottom surface of the fuse link. The metal layer may include a contact portion having a first width and has a large An interconnect portion of a second width of the first width. The fuse link can have a width substantially equal to or less than the width of the anode and cathode.

電熔絲結構可包含在虛設金屬插塞之頂部表面上的虛設金屬圖案,且虛設金屬圖案可具有大於熔絲鏈之厚度的厚度。多個虛設熔絲鏈可處於熔絲鏈之各別側處,且虛設金屬圖案可具有小於虛設熔絲鏈之間的距離之寬度。多個虛設金屬插塞可在陽極與陰極之間。 The electrical fuse structure can include a dummy metal pattern on the top surface of the dummy metal plug, and the dummy metal pattern can have a thickness greater than the thickness of the fuse link. A plurality of dummy fuse links may be at respective sides of the fuse link, and the dummy metal patterns may have a width that is less than a distance between the dummy fuse links. A plurality of dummy metal plugs can be between the anode and the cathode.

虛設金屬插塞可沿著實質上垂直於熔絲鏈之縱向軸線的方向延伸。陽極及陰極可處於不同層面,且熔絲鏈與虛設金屬插塞可在陽極與陰極之間。陽極及陰極可相對於下伏層之頂部表面處於第一層面,熔絲鏈可相對於下伏層之頂部表面處於第二層面,且第二層面可高於第一層面。 The dummy metal plug can extend in a direction substantially perpendicular to the longitudinal axis of the fuse link. The anode and cathode can be at different levels, and the fuse link and the dummy metal plug can be between the anode and the cathode. The anode and cathode may be at a first level relative to a top surface of the underlying layer, the fuse link may be at a second level relative to a top surface of the underlying layer, and the second level may be higher than the first level.

電熔絲結構可包含在半導體基板上之電晶體,且電晶體可包含閘電極,所述閘電極包含第一金屬材料,且電晶體實質上處於與熔絲鏈相同的層面。 The electrical fuse structure can comprise a transistor on the semiconductor substrate, and the transistor can comprise a gate electrode comprising a first metal material and the transistor is substantially at the same level as the fuse link.

電熔絲結構可包含與半導體基板隔開之多個金屬線,且金屬線可包含第一金屬材料並處於與熔絲鏈實質上相同的層面。熔絲鏈可攜載程式化電流,且虛設金屬插塞在程式化電流之供應期間可改變熔絲鏈中的溫度梯度。熔絲鏈可包含與虛設金屬插塞接觸之第一區及與罩蓋介電質接觸的第二區,且在程式化電流之供應期間熔絲鏈之溫度在第二區處可具有最大值。 The electrical fuse structure can include a plurality of metal lines spaced apart from the semiconductor substrate, and the metal lines can comprise the first metal material and be at substantially the same level as the fuse link. The fuse link can carry a programmed current, and the dummy metal plug can change the temperature gradient in the fuse link during the supply of the programmed current. The fuse link may include a first region in contact with the dummy metal plug and a second region in contact with the cap dielectric, and the temperature of the fuse link may have a maximum value at the second region during supply of the stylized current .

熔絲鏈可包含與虛設金屬插塞接觸之第一區及與罩蓋介電質接觸的第二區,電熔絲結構可攜載程式化電流,且在程式化電流之供應期間,由熔絲鏈之第一區處之電遷移引起的第一電 驅動力可不同於由熔絲鏈之第二區處的電遷移引起的第二電驅動力。 The fuse link can include a first region in contact with the dummy metal plug and a second region in contact with the dielectric of the cover, the electrical fuse structure can carry a stylized current, and during the supply of the stabilizing current, the fuse The first electricity caused by electromigration at the first zone of the wire chain The driving force may be different from the second electric driving force caused by electromigration at the second region of the fuse link.

根據另一實施例,半導體元件之電熔絲結構包含:連接陰極與陽極的第一金屬材料之熔絲鏈;覆蓋陽極、陰極及熔絲鏈的層間絕緣層;在熔絲鏈之頂部表面與層間絕緣層之間的罩蓋介電質,罩蓋介電質包含不同於層間絕緣層的絕緣材料;以及穿透層間絕緣層與罩蓋介電質且接觸熔絲鏈的虛設金屬插塞,虛設金屬插塞包含介於金屬層與熔絲鏈之間的障壁金屬層,其中障壁金屬層包含不同於第一金屬材料的第二金屬材料。第一金屬材料可具有大於第二金屬材料之電導率的電導率。 In accordance with another embodiment, an electrical fuse structure of a semiconductor component includes: a fuse link of a first metal material connecting a cathode and an anode; an interlayer insulating layer covering the anode, the cathode, and the fuse link; and a top surface of the fuse link a cap dielectric between the interlayer insulating layers, the cap dielectric includes an insulating material different from the interlayer insulating layer; and a dummy metal plug penetrating the interlayer insulating layer and the cap dielectric and contacting the fuse link, The dummy metal plug includes a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer comprises a second metal material different from the first metal material. The first metallic material may have a conductivity greater than the electrical conductivity of the second metallic material.

第一金屬材料可包含鎢、鋁、銅或銅合金中的至少一者,且第二金屬材料可包含Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合中的至少一者。障壁金屬層可覆蓋金屬層的底部表面及側表面。在金屬層的底部表面上的障壁金屬層可較在金屬層之側表面上的障壁金屬層厚。 The first metal material may include at least one of tungsten, aluminum, copper, or a copper alloy, and the second metal material may include at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof . The barrier metal layer may cover the bottom surface and the side surface of the metal layer. The barrier metal layer on the bottom surface of the metal layer may be thicker than the barrier metal layer on the side surface of the metal layer.

熔絲鏈可攜載程式化電流,且熔絲鏈在程式化狀態下可具有介於陽極與虛設金屬插塞之間的空隙。空隙與虛設金屬插塞之間的距離可小於空隙與陽極之間的距離。 The fuse link can carry a programmed current, and the fuse link can have a gap between the anode and the dummy metal plug in the stylized state. The distance between the void and the dummy metal plug may be less than the distance between the void and the anode.

根據另一實施例,半導體元件之電熔絲結構包含:熔絲鏈,以將陽極連接至陰極且基於程式化電流來程式化;及與熔絲鏈接觸的虛設金屬插塞,其中熔絲鏈包含第一金屬材料,虛設金屬插塞包含不同於第一金屬材料的第二金屬材料,且虛設金屬插塞在程式化電流至熔絲鏈之供應期間改變電及熱驅動力,且其中電及熱驅動力基於熔絲鏈中的電遷移及熱遷移。 In accordance with another embodiment, an electrical fuse structure of a semiconductor component includes: a fuse link to connect the anode to the cathode and to be programmed based on a programmed current; and a dummy metal plug in contact with the fuse link, wherein the fuse link Including a first metal material, the dummy metal plug includes a second metal material different from the first metal material, and the dummy metal plug changes electrical and thermal driving force during the supply of the stabilizing current to the fuse chain, and wherein The thermal driving force is based on electromigration and thermal migration in the fuse link.

虛設金屬插塞可包含介於金屬層與熔絲鏈之間的障壁金屬層,且障壁金屬層可包含第二金屬材料。第一金屬材料可具有大於第二金屬材料之電導率的電導率。總驅動力在程式化電流至熔絲鏈之供應期間可具有在陽極與虛設金屬插塞之間的最大值,且總驅動力可基於電及熱驅動力的總和。 The dummy metal plug may include a barrier metal layer between the metal layer and the fuse link, and the barrier metal layer may include a second metal material. The first metallic material may have a conductivity greater than the electrical conductivity of the second metallic material. The total driving force may have a maximum between the anode and the dummy metal plug during the supply of the stabilizing current to the fuse link, and the total driving force may be based on the sum of the electrical and thermal driving forces.

電熔絲結構可包含:覆蓋陽極、陰極及熔絲鏈的層間絕緣層;及介於熔絲鏈之頂部表面與層間絕緣層之間的罩蓋介電質,罩蓋介電質包含不同於層間絕緣層的絕緣材料,其中熔絲鏈包含與虛設金屬插塞接觸的第一區及與罩蓋介電質接觸的第二區。 The electric fuse structure may include: an interlayer insulating layer covering the anode, the cathode and the fuse link; and a cap dielectric between the top surface of the fuse link and the interlayer insulating layer, and the cap dielectric contains a different An insulating material for an interlayer insulating layer, wherein the fuse link includes a first region in contact with the dummy metal plug and a second region in contact with the cap dielectric.

由熔絲鏈之第一區處的電遷移引起之第一電驅動力可小於由熔絲鏈之第二區處的電遷移引起的第二電驅動力。熔絲鏈的溫度在程式化電流至熔絲鏈之供應期間在第二區處可具有最大值。 The first electrical driving force caused by electromigration at the first region of the fuse link may be less than the second electrical driving force caused by electromigration at the second region of the fuse link. The temperature of the fuse link may have a maximum at the second zone during the supply of the programmed current to the fuse link.

根據另一實施例,半導體元件之電熔絲結構包含:連接陰極與陽極的第一金屬材料之熔絲鏈;覆蓋熔絲鏈之頂部表面的罩蓋介電質;以及穿透罩蓋介電質並接觸熔絲鏈的虛設金屬插塞,其中熔絲鏈將攜載程式化電流,且其中虛設金屬插塞將在熔絲鏈攜載程式化電流時改變熔絲鏈中的溫度梯度。 In accordance with another embodiment, an electrical fuse structure of a semiconductor component includes: a fuse link of a first metal material connecting a cathode and an anode; a cap dielectric covering a top surface of the fuse link; and a dielectric through the cover A dummy metal plug that is in contact with the fuse link, wherein the fuse link will carry a programmed current, and wherein the dummy metal plug will change the temperature gradient in the fuse link when the fuse chain carries the programmed current.

虛設金屬插塞可包含介於金屬層與熔絲鏈之間的障壁金屬層,且障壁金屬層可包含不同於第一金屬材料的第二金屬材料。熔絲鏈可包含與虛設金屬插塞接觸之第一區及與罩蓋介電質接觸的第二區,且熔絲鏈之溫度在熔絲鏈攜載程式化電流時在第二區處可具有最大值。熔絲鏈在程式化狀態下可具有介於陽極與 虛設金屬插塞之間的空隙。空隙與虛設金屬插塞之間的距離可小於空隙與陽極之間的距離。 The dummy metal plug may include a barrier metal layer between the metal layer and the fuse link, and the barrier metal layer may include a second metal material different from the first metal material. The fuse link may include a first region in contact with the dummy metal plug and a second region in contact with the cap dielectric, and the temperature of the fuse link may be at the second region when the fuse chain carries the stylized current Has the maximum value. The fuse link can have an anode and a The gap between the dummy metal plugs. The distance between the void and the dummy metal plug may be less than the distance between the void and the anode.

10‧‧‧下伏層 10‧‧‧Under layer

20‧‧‧金屬層 20‧‧‧metal layer

20a‧‧‧陽極 20a‧‧‧Anode

20c‧‧‧陰極 20c‧‧‧ cathode

20d‧‧‧虛設熔絲鏈 20d‧‧‧Fuse fuse chain

20f‧‧‧熔絲鏈 20f‧‧‧fuse chain

30‧‧‧罩蓋介電質 30‧‧‧ Cover dielectric

40‧‧‧層間絕緣層 40‧‧‧Interlayer insulation

50‧‧‧虛設金屬插塞 50‧‧‧Virtual metal plug

50a‧‧‧第一虛設金屬插塞 50a‧‧‧First dummy metal plug

50b‧‧‧第二虛設金屬插塞 50b‧‧‧second dummy metal plug

51‧‧‧障壁金屬層 51‧‧‧Baffle metal layer

53‧‧‧金屬層 53‧‧‧metal layer

53a‧‧‧接觸部分 53a‧‧‧Contact section

53b‧‧‧互連部分 53b‧‧‧Interconnect

60a‧‧‧第一接觸插塞 60a‧‧‧first contact plug

60b‧‧‧第二接觸插塞 60b‧‧‧second contact plug

65a‧‧‧第一連接圖案 65a‧‧‧first connection pattern

65b‧‧‧第二連接圖案 65b‧‧‧Second connection pattern

70‧‧‧第二層間絕緣層 70‧‧‧Second interlayer insulation

71‧‧‧通孔 71‧‧‧through hole

73‧‧‧溝槽 73‧‧‧ trench

80‧‧‧虛設金屬圖案 80‧‧‧Dummy metal pattern

80a‧‧‧第一虛設金屬圖案 80a‧‧‧First dummy metal pattern

80b‧‧‧第二虛設金屬圖案 80b‧‧‧second dummy metal pattern

81‧‧‧第二障壁金屬層 81‧‧‧Second barrier metal layer

83‧‧‧第二金屬層 83‧‧‧Second metal layer

90a‧‧‧第一導電圖案 90a‧‧‧First conductive pattern

90b‧‧‧第二導電圖案 90b‧‧‧Second conductive pattern

100‧‧‧下伏層 100‧‧‧Under layer

110‧‧‧陽極圖案 110‧‧‧Anode pattern

110a‧‧‧陽極圖案 110a‧‧‧Anode pattern

110b‧‧‧陰極圖案 110b‧‧‧ cathode pattern

120‧‧‧第一層間絕緣層 120‧‧‧First interlayer insulation

125‧‧‧第一接觸插塞 125‧‧‧First contact plug

125a‧‧‧第一接觸插塞 125a‧‧‧first contact plug

125b‧‧‧第二接觸插塞 125b‧‧‧second contact plug

130‧‧‧熔絲鏈 130‧‧‧Fuse chain

135‧‧‧罩蓋介電質 135‧‧‧ Cover dielectric

140‧‧‧第二層間絕緣層 140‧‧‧Second interlayer insulation

150‧‧‧虛設金屬插塞 150‧‧‧Virtual metal plug

151‧‧‧障壁金屬層 151‧‧‧ barrier metal layer

153‧‧‧金屬層 153‧‧‧metal layer

155‧‧‧第二接觸插塞 155‧‧‧Second contact plug

160‧‧‧陰極圖案 160‧‧‧Cathode pattern

200‧‧‧下伏層 200‧‧‧Under layer

210‧‧‧陰極圖案 210‧‧‧ cathode pattern

210a‧‧‧第一部分 210a‧‧‧Part 1

210b‧‧‧第二部分 210b‧‧‧Part II

215‧‧‧第一接觸插塞 215‧‧‧First contact plug

220‧‧‧熔絲鏈 220‧‧‧Fuse chain

220d‧‧‧虛設熔絲鏈 220d‧‧‧Fuse fuse chain

225‧‧‧第二接觸插塞 225‧‧‧Second contact plug

230‧‧‧陽極圖案 230‧‧‧Anode pattern

230a‧‧‧第一部分 230a‧‧‧Part I

230b‧‧‧第二部分 230b‧‧‧Part II

235‧‧‧虛設金屬插塞 235‧‧‧Virtual metal plug

240‧‧‧虛設金屬圖案 240‧‧‧Dummy metal pattern

300‧‧‧半導體基板 300‧‧‧Semiconductor substrate

301‧‧‧元件隔離層 301‧‧‧ Component isolation layer

310‧‧‧第一層間絕緣層 310‧‧‧First interlayer insulation

310f‧‧‧熔絲鏈 310f‧‧‧Fuse chain

310g‧‧‧閘電極 310g‧‧‧ gate electrode

315‧‧‧罩蓋介電質 315‧‧‧ Cover dielectric

320‧‧‧第一層間絕緣層 320‧‧‧First interlayer insulation

321‧‧‧胞接觸插塞 321‧‧‧cell contact plug

321a‧‧‧第一接觸插塞 321a‧‧‧first contact plug

321b‧‧‧第二接觸插塞 321b‧‧‧second contact plug

321d‧‧‧虛設金屬插塞 321d‧‧‧Virtual metal plug

325‧‧‧第一互連線 325‧‧‧First interconnect

325a‧‧‧第一導電圖案 325a‧‧‧First conductive pattern

325b‧‧‧第二導電圖案 325b‧‧‧Second conductive pattern

325d‧‧‧虛設金屬圖案 325d‧‧‧dummy metal pattern

325f‧‧‧熔絲鏈 325f‧‧‧fuse chain

327‧‧‧罩蓋介電質 327‧‧‧ Cover dielectric

330‧‧‧第二層間絕緣層 330‧‧‧Second interlayer insulation

331a‧‧‧第一接觸插塞 331a‧‧‧first contact plug

331b‧‧‧第二接觸插塞 331b‧‧‧second contact plug

331d‧‧‧虛設金屬插塞 331d‧‧‧Virtual metal plug

335‧‧‧第二互連線 335‧‧‧Second interconnect

335a‧‧‧第一導電圖案 335a‧‧‧First conductive pattern

335b‧‧‧第二導電圖案 335b‧‧‧Second conductive pattern

335d‧‧‧虛設金屬圖案 335d‧‧‧dummy metal pattern

340‧‧‧第三層間絕緣層 340‧‧‧3rd interlayer insulation

345‧‧‧第三互連線 345‧‧‧ third interconnect

345f‧‧‧熔絲鏈 345f‧‧‧fuse chain

347‧‧‧罩蓋介電質 347‧‧‧ Cover dielectric

351a‧‧‧第一接觸插塞 351a‧‧‧first contact plug

351b‧‧‧第二接觸插塞 351b‧‧‧second contact plug

351d‧‧‧虛設金屬插塞 351d‧‧‧Virtual metal plug

353a‧‧‧第一導電圖案 353a‧‧‧First conductive pattern

353b‧‧‧第二導電圖案 353b‧‧‧Second conductive pattern

353d‧‧‧虛設金屬圖案 353d‧‧‧Dummy metal pattern

1100‧‧‧記憶體系統 1100‧‧‧ memory system

1110‧‧‧控制器 1110‧‧‧ Controller

1120‧‧‧輸入/輸出元件 1120‧‧‧Input/output components

1130‧‧‧記憶體 1130‧‧‧ memory

1140‧‧‧介面 1140‧‧ interface

1150‧‧‧匯流排 1150‧‧ ‧ busbar

1200‧‧‧記憶卡 1200‧‧‧ memory card

1210‧‧‧半導體記憶體元件 1210‧‧‧Semiconductor memory components

1220‧‧‧記憶體控制器 1220‧‧‧ memory controller

1221‧‧‧靜態隨機存取記憶體(SRAM) 1221‧‧‧Static Random Access Memory (SRAM)

1222‧‧‧處理單元 1222‧‧‧Processing unit

1223‧‧‧主機介面 1223‧‧‧Host interface

1224‧‧‧錯誤校正區塊 1224‧‧‧Error correction block

1225‧‧‧記憶體介面 1225‧‧‧ memory interface

1300‧‧‧資訊處理系統 1300‧‧‧Information Processing System

1310‧‧‧記憶體系統 1310‧‧‧Memory System

1311‧‧‧半導體元件 1311‧‧‧Semiconductor components

1312‧‧‧記憶體控制器 1312‧‧‧ memory controller

1320‧‧‧數據機 1320‧‧‧Data machine

1330‧‧‧中央處理單元(CPU) 1330‧‧‧Central Processing Unit (CPU)

1340‧‧‧RAM 1340‧‧‧RAM

1350‧‧‧使用者介面 1350‧‧‧User interface

1360‧‧‧系統匯流排 1360‧‧‧System Bus

A‧‧‧曲線 A‧‧‧ curve

AP‧‧‧陽極 AP‧‧‧Anode

B‧‧‧曲線 B‧‧‧ Curve

C‧‧‧曲線 C‧‧‧ Curve

CP‧‧‧陰極 CP‧‧‧ cathode

D‧‧‧間隔 D‧‧‧ interval

d‧‧‧熔絲鏈FL中的位置 D‧‧‧ Location in the fuse link FL

EM‧‧‧電遷移 EM‧‧‧Electric migration

EM1‧‧‧第一電驅動力 EM1‧‧‧First electric driving force

EM2‧‧‧第二電驅動力 EM2‧‧‧second electric driving force

FEM‧‧‧電驅動力 F EM ‧‧‧Electric driving force

FL‧‧‧熔絲鏈 FL‧‧‧Fuse Chain

R1‧‧‧第一區 R1‧‧‧ first district

R2‧‧‧第二區 R2‧‧‧Second District

R3‧‧‧第三區 R3‧‧‧ Third District

t1‧‧‧厚度 T1‧‧‧ thickness

t2‧‧‧第一厚度 T2‧‧‧first thickness

t3‧‧‧第二厚度 T3‧‧‧second thickness

TM1‧‧‧第一熱遷移 TM1‧‧‧First Thermal Migration

TM2‧‧‧第二熱遷移 TM2‧‧‧Second Thermal Migration

V‧‧‧空隙 V‧‧‧ gap

W1‧‧‧寬度/上部寬度 W1‧‧‧Width/Upper Width

W2‧‧‧寬度/第一下部寬度 W2‧‧‧Width / first lower width

W3‧‧‧寬度 W3‧‧‧Width

△FTM‧‧‧熱驅動力之差 △F TM ‧‧‧The difference between the thermal driving forces

△FEM‧‧‧電驅動力的差 △F EM ‧‧‧The difference in electric driving force

藉由參看附加圖式詳細地描述例示性實施例,特徵對於熟習此項技術者將變得顯而易見,其中:圖1說明電熔絲結構之一個實施例的程式化程序中的電遷移效應。 Features of the skilled artisan will become apparent to those skilled in the art from a <RTIgt; </RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

圖2說明電熔絲結構之一個實施例的程式化程序中的熱遷移。 Figure 2 illustrates thermal migration in a stylized program of one embodiment of an electrical fuse structure.

圖3說明電熔絲結構之一實施例的程式化程序中的熱遷移及電遷移。 Figure 3 illustrates thermal migration and electromigration in a stylized program of one embodiment of an electrical fuse structure.

圖4A說明電熔絲結構之第一實施例,且圖4B說明沿著圖4A中之截面線I-I'及II-II'獲得的視圖。 4A illustrates a first embodiment of an electrical fuse structure, and FIG. 4B illustrates a view taken along section lines II' and II-II' of FIG. 4A.

圖5說明電熔絲結構之第一實施例的程式化程序中的電遷移。 Figure 5 illustrates electromigration in a stylized program of a first embodiment of an electrical fuse structure.

圖6說明電熔絲結構之第一實施例的程式化程序中的熱遷移。 Figure 6 illustrates thermal migration in a stylized program of a first embodiment of an electrical fuse structure.

圖7說明電熔絲結構之第一實施例的程式化程序中的熱遷移及電遷移。 Figure 7 illustrates thermal migration and electromigration in a stylized program of a first embodiment of an electrical fuse structure.

圖8A至圖8C說明電熔絲結構之第一實施例的修改的截面圖。 8A to 8C illustrate a modified cross-sectional view of a first embodiment of an electric fuse structure.

圖9A及圖10A說明電熔絲結構之第二實施例,圖9B及圖10B分別說明沿著圖9A及圖10A中之截面線I-I'及II-II'獲得的視 圖,且圖9C及圖10C說明電熔絲結構之第二實施例的修改。 9A and 10A illustrate a second embodiment of an electrical fuse structure, and FIGS. 9B and 10B illustrate views taken along section lines I-I' and II-II' of FIGS. 9A and 10A, respectively. Figures, and Figures 9C and 10C illustrate a modification of the second embodiment of the electrical fuse structure.

圖11A及圖12A說明電熔絲結構之第二實施例的程式化程序中的熱遷移,且圖11B及圖12B說明電熔絲結構之第二實施例的程式化程序中的熱遷移及電遷移。 11A and 12A illustrate thermal migration in a stylized program of a second embodiment of an electrical fuse structure, and FIGS. 11B and 12B illustrate thermal migration and power in a programmatic program of a second embodiment of an electrical fuse structure. migrate.

圖13A及圖14A說明電熔絲結構之第三實施例,圖13B及圖14B分別說明沿著圖13A及圖14A中之截面線I-I'及II-II'獲得的視圖。 13A and 14A illustrate a third embodiment of the electric fuse structure, and Figs. 13B and 14B respectively illustrate views taken along section lines I-I' and II-II' in Figs. 13A and 14A.

圖15A說明電熔絲結構之第四實施例,且圖15B說明沿著圖15A中之截面線I-I'及II-II'獲得的視圖。 Fig. 15A illustrates a fourth embodiment of the electric fuse structure, and Fig. 15B illustrates a view taken along section lines I-I' and II-II' in Fig. 15A.

圖16A說明電熔絲結構之第五實施例,且圖16B說明沿著圖16A中之截面線I-I'及II-II'獲得的視圖。 Fig. 16A illustrates a fifth embodiment of the electric fuse structure, and Fig. 16B illustrates a view taken along section lines I-I' and II-II' in Fig. 16A.

圖17A說明電熔絲結構之第六實施例,且圖17B說明沿著圖17A中之截面線I-I'及II-II'獲得的視圖。 Fig. 17A illustrates a sixth embodiment of the electric fuse structure, and Fig. 17B illustrates a view taken along section lines I-I' and II-II' in Fig. 17A.

圖18A說明電熔絲結構之第七實施例,且圖18B說明沿著圖18A中之截面線I-I'及II-II'獲得的視圖。 Fig. 18A illustrates a seventh embodiment of the electric fuse structure, and Fig. 18B illustrates a view taken along section lines I-I' and II-II' in Fig. 18A.

圖19說明電熔絲結構之第七實施例的修改。 Figure 19 illustrates a modification of the seventh embodiment of the electrical fuse structure.

圖20A、圖20B、圖21A及圖21B說明電熔絲結構之第七實施例的修改。 20A, 20B, 21A and 21B illustrate a modification of the seventh embodiment of the electric fuse structure.

圖22及圖23說明電熔絲結構之第八實施例。 22 and 23 illustrate an eighth embodiment of an electrical fuse structure.

圖24A及圖24B說明電熔絲結構之第九實施例。 24A and 24B illustrate a ninth embodiment of an electrical fuse structure.

圖25A至圖25C說明半導體元件的實施例,所述半導體元件中之每一者包含根據前述實施例中之一或多者的電熔絲結構。 25A-25C illustrate an embodiment of a semiconductor component, each of which includes an electrical fuse structure in accordance with one or more of the foregoing embodiments.

圖26說明包含根據前述實施例中之一或多者之半導體元件的記憶體系統。 Figure 26 illustrates a memory system incorporating a semiconductor component in accordance with one or more of the foregoing embodiments.

圖27說明包含根據前述實施例中之一或多者之半導體元件的記憶卡。 Figure 27 illustrates a memory card incorporating a semiconductor component in accordance with one or more of the foregoing embodiments.

圖28說明包含根據前述實施例中之一或多者之半導體元件的資訊處理系統。 Figure 28 illustrates an information processing system including semiconductor components in accordance with one or more of the foregoing embodiments.

下文中參看隨附圖式更充分地描述實例實施例;然而,實例實施例可以不同形式來體現,且不應解釋為限於本文中所闡述的實施例。確切而言,此等實施例經提供,使得本發明將為透徹且完整的,且將把例示性實施充分地傳達至熟習此項技術者。 The example embodiments are described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments may be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and the exemplary embodiments will be fully conveyed to those skilled in the art.

在圖式諸圖中,層及區的尺寸可為了說明清楚而經誇示。亦應理解,當層或器件被稱作「在另一層或基板上」時,所述層或器件可直接在另一層或基板上,或亦可存在介入層。另外,應理解,當將層稱作在另一層「下方」時,所述層可直接在另一層下方,且亦可存在一或多個介入層。此外,亦應理解,當將層稱作在兩個層「之間」時,所述層可為兩個層之間的唯一層,或亦可存在一或多個介入層。相同參考數字始終指代相同器件。 In the drawings, the dimensions of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or device is referred to as "on another layer or substrate", the layer or device can be directly on the other layer or substrate, or an intervening layer can also be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, the layer may be directly under the other layer, and one or more intervening layers may also be present. In addition, it should also be understood that when a layer is referred to as being "between" two layers, the layer can be a single layer between the two layers, or one or more intervening layers can also be present. The same reference numbers always refer to the same device.

又,應理解,當器件被稱作「連接」或「耦接」至另一器件時,所述器件可直接連接或耦接至另一器件,或可存在介入器件。相比之下,當器件被稱作「直接連接」或「直接耦接」至另一器件時,不存在任何介入器件。相同數字始終指示相同器件。如本文中所使用,術語「及/或」包含相關聯的所列項目中之一或多者的任一及所有組合。用以描述器件或層之間的關係的其他詞語應以相似方式解釋(例如,「在......之間」相對於「直接在...... 之間」、「鄰近」相對於「直接鄰近」、「在......上」相對於「直接在......上」)。 Also, it will be understood that when a device is referred to as "connected" or "coupled" to another device, the device can be directly connected or coupled to another device, or an intervening device can be present. In contrast, when a device is referred to as being "directly connected" or "directly coupled" to another device, there are no intervening devices. The same number always indicates the same device. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between devices or layers should be interpreted in a similar manner (for example, "between" and "directly in" "Between" and "proximity" are relative to "directly adjacent", "on" and "directly on").

又,應理解,當器件被稱作「連接」或「耦接」至另一器件時,所述器件可直接連接或耦接至另一器件,或可存在介入器件。相比之下,當器件被稱作「直接連接」或「直接耦接」至另一器件時,不存在任何介入器件。如本文中所使用,術語「及/或」包含相關聯的所列項目中之一或多者的任一及所有組合。用以描述器件或層之間的關係的其他詞語應以相似方式解釋(例如,「在......之間」相對於「直接在......之間」、「鄰近」相對於「直接鄰近」、「在......上」相對於「直接在......上」)。 Also, it will be understood that when a device is referred to as "connected" or "coupled" to another device, the device can be directly connected or coupled to another device, or an intervening device can be present. In contrast, when a device is referred to as being "directly connected" or "directly coupled" to another device, there are no intervening devices. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between devices or layers should be interpreted in a similar manner (for example, "between" and "directly between" and "adjacent" Relative to "direct proximity", "on" versus "directly on").

本文中參看橫截面說明來描述本發明概念之實例實施例,所述橫截面說明為實例實施例的理想化實施例(及中間結構)的示意性說明。因此,應預期到由於(例如)製造技術及/或公差而引起的相對於說明之形狀的變化。因此,本發明概念的實例實施例不應解釋為限於本文中所說明之區的特定形狀,而是將包含由(例如)製造產生的形狀偏差。舉例而言,被說明為矩形之植入區可具有圓形或彎曲特徵及/或在植入區之邊緣處的植入濃度梯度,而非自植入區至非植入區之二元改變。同樣,藉由植入形成之埋入區可在埋入區與植入藉以發生之表面之間的區中導致某植入。因此,諸圖中所說明之區本質上為示意性的,且其形狀不意欲說明元件之區的實際形狀且不意欲限制實例實施例的範疇。 Example embodiments of the inventive concepts are described herein with reference to the cross-section illustrations, which are illustrative of the preferred embodiments (and intermediate structures) of the example embodiments. Accordingly, variations from the shapes of the descriptions as a result of, for example, manufacturing techniques and/or tolerances are contemplated. Thus, example embodiments of the inventive concepts should not be construed as being limited to the specific shapes of the regions illustrated herein. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or an implant concentration gradient at the edge of the implanted region rather than a binary change from the implanted region to the non-implanted region. . Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface from which the implantation takes place. The area illustrated in the figures is therefore illustrative in nature and is not intended to limit the scope of the embodiments.

如本發明實體所瞭解的,根據本文中所描述之各種實施例的元件及形成元件之方法可體現於諸如積體電路的微型電子元件中,其中根據本文中所描述之各種實施例的多個元件整合於同 一微型電子元件中。因此,可在微型電子元件中在不需要為正交的兩個不同方向上複製本文中所說明之橫截面圖。因此,體現根據本文中所描述之各種實施例之元件的微型電子元件之平面圖可包含呈陣列及/或二維圖案的多個元件,所述陣列及/或二維圖案是基於微型電子元件的功能性。 As understood by the entities of the present invention, elements in accordance with various embodiments described herein and methods of forming the elements can be embodied in a miniature electronic component, such as an integrated circuit, in accordance with various embodiments described herein. Component integration In a miniature electronic component. Thus, the cross-sectional views described herein can be replicated in two different directions in a miniature electronic component that do not need to be orthogonal. Accordingly, a plan view of a miniature electronic component embodying elements in accordance with various embodiments described herein can comprise a plurality of elements in an array and/or a two-dimensional pattern, the array and/or two-dimensional pattern being based on microelectronic elements Feature.

視微型電子元件之功能性而定,根據本文中所描述之各種實施例的元件可分散於其他元件間。此外,根據本文中所描述之各種實施例的微型電子元件可在可正交於所述兩個不同方向的第三方向上複製,以提供三維積體電路。 Depending on the functionality of the miniature electronic components, elements in accordance with various embodiments described herein may be inter-distributed between other components. Moreover, miniature electronic components in accordance with various embodiments described herein can be replicated in a third direction that can be orthogonal to the two different directions to provide a three-dimensional integrated circuit.

因此,本文中所說明的橫截面圖提供對根據本文中所描述之各種實施例之多個元件的支援,所述多個元件在平面圖中沿著兩個不同方向及/或在透視圖中在三個不同方向上延伸。舉例而言,當在元件/結構之橫截面圖中說明單一主動區時,元件/結構可包含多個主動區及其上的電晶體結構(或在對於所述狀況適當時的記憶胞結構、閘結構等),如藉由元件/結構之平面圖將說明。 Accordingly, the cross-sectional views illustrated herein provide support for a plurality of elements in accordance with various embodiments described herein, in a plan view along two different directions and/or in a perspective view. Extend in three different directions. For example, when a single active region is illustrated in a cross-sectional view of a component/structure, the component/structure may comprise a plurality of active regions and a transistor structure thereon (or a memory cell structure when appropriate for the condition, Gate structure, etc., as illustrated by the plan view of the component/structure.

圖1說明電熔絲結構之一個實施例的程式化程序中的電遷移效應。圖2說明圖,所述圖說明電熔絲結構之一個實施例的程式化程序中之熱遷移效應。 Figure 1 illustrates the electromigration effects in a stylized program of one embodiment of an electrical fuse structure. Figure 2 illustrates a diagram illustrating the thermal transfer effects in a stylized program of one embodiment of an electrical fuse structure.

參看圖1及圖2,電熔絲結構包含連接陰極CP與陽極AP的熔絲鏈FL。程式化此電熔絲結構之程序可包含形成陰極CP與陽極AP之間的電壓差,以便將程式化電流提供至熔絲鏈FL。 Referring to Figures 1 and 2, the electrical fuse structure includes a fuse link FL connecting the cathode CP to the anode AP. The procedure for stylizing the electrical fuse structure can include forming a voltage difference between the cathode CP and the anode AP to provide a programmed current to the fuse link FL.

舉例而言,在電熔絲結構之程式化程序期間,負電壓可施加至陰極CP,且正電壓可施加至陽極AP。因此,電子自陰極CP通過熔絲鏈FL朝向陽極AP流動。隨著電子流動通過熔絲鏈 FL,電子可與熔絲鏈FL的原子碰撞,從而導致稱作電遷移EM的現象。如圖1中所展示,由電遷移引起之驅動力(例如,電驅動力FEM)可為完全恆定的而不考慮在熔絲鏈FL中的位置。 For example, during the stylization procedure of the electrical fuse structure, a negative voltage can be applied to the cathode CP and a positive voltage can be applied to the anode AP. Therefore, electrons flow from the cathode CP toward the anode AP through the fuse link FL. As electrons flow through the fuse link FL, electrons can collide with atoms of the fuse link FL, resulting in a phenomenon called electromigration EM. As shown in FIG. 1, the driving force (eg, electric driving force F EM ) caused by electromigration may be completely constant regardless of the position in the fuse link FL.

當程式化電流供應至由金屬性材料(例如,鎢、鋁及銅)形成的熔絲鏈FL時,熔絲鏈FL之溫度可藉由焦耳加熱而增加。如圖2中所展示,焦耳加熱可產生熔絲鏈FL的非均一溫度分佈。舉例而言,熔絲鏈FL之溫度在中心部分處可最高。此非均一溫度分佈可引起熔絲鏈FL的熱遷移。舉例而言,熔絲鏈FL之原子可自中心部分朝向陽極AP遷移(下文中稱作第一熱遷移TM1)或朝向陰極CP遷移(下文中稱作第二熱遷移TM2)。 When the stylized current is supplied to the fuse link FL formed of a metallic material (for example, tungsten, aluminum, and copper), the temperature of the fuse link FL can be increased by Joule heating. As shown in Figure 2, Joule heating can produce a non-uniform temperature distribution of the fuse link FL. For example, the temperature of the fuse link FL can be highest at the central portion. This non-uniform temperature distribution can cause thermal migration of the fuse link FL. For example, atoms of the fuse link FL may migrate from the central portion toward the anode AP (hereinafter referred to as first thermal migration TM1) or toward the cathode CP (hereinafter referred to as second thermal migration TM2).

圖3說明電熔絲結構之實施例的程式化程序中的熱遷移及電遷移效應。在圖3中,曲線A表示由電遷移引起之驅動力的實例,所述驅動力可在電熔絲結構經程式化時發生。曲線B表示由熱遷移引起之驅動力,所述熱遷移可在電熔絲結構經程式化時發生。曲線C呈現由熱及電遷移引起之兩個驅動力的總驅動力或合力。 Figure 3 illustrates the thermal migration and electromigration effects in a stylized program of an embodiment of an electrical fuse structure. In Fig. 3, a curve A shows an example of a driving force caused by electromigration, which can occur when the electric fuse structure is programmed. Curve B represents the driving force caused by thermal migration, which can occur when the electrical fuse structure is programmed. Curve C presents the total driving force or resultant force of the two driving forces caused by thermal and electromigration.

參看圖3,由電遷移引起的驅動力(例如,電驅動力FEM)可恆定而無關於熔絲鏈FL中的部分。相比之下,由非均一溫度分佈引起的驅動力(例如,熱驅動力FTM)可自熔絲鏈FL的中心部分在相反方向上施加。 Referring to FIG. 3, the driving force (for example, the electric driving force F EM ) caused by electromigration can be constant regardless of the portion in the fuse link FL. In contrast, the driving force (for example, the thermal driving force F TM ) caused by the non-uniform temperature distribution can be applied in the opposite direction from the central portion of the fuse link FL.

在陽極AP與熔絲鏈FL之中心部分之間,電遷移EM與第一熱遷移TM1可在同一方向上發生。結果,施加於熔絲鏈FL上的總驅動力FEM+TM可基於電驅動力與熱驅動力的總和。相比之下,電遷移EM及第二熱遷移TM2可在陰極CP與熔絲鏈FL之中 心部分之間在相反方向上發生。結果,施加於熔絲鏈FL上的總驅動力FEM+TM可基於熱驅動力與電驅動力之間的差。 Between the anode AP and the central portion of the fuse link FL, the electromigration EM and the first thermal migration TM1 may occur in the same direction. As a result, the total driving force F EM+TM applied to the fuse link FL can be based on the sum of the electric driving force and the thermal driving force. In contrast, electromigration EM and second thermal migration TM2 can occur in opposite directions between the cathode CP and the central portion of the fuse link FL. As a result, the total driving force F EM+TM applied to the fuse link FL can be based on the difference between the thermal driving force and the electric driving force.

在熔絲鏈FL中,熱及電驅動力可因此導致非均一原子流動速率或非零通量發散(flux divergence),如圖3中所展示。另外,可取決於通量發散的量值而發生原子之耗盡或累積。舉例而言,若在熔絲鏈FL的特定區中流出通量大於流入通量,則原子可被耗盡以形成空隙。相比之下,若在熔絲鏈FL的特定區中流入通量大於流出通量,則原子可被累積以建立小丘構造(hillock formation)。空隙可增加熔絲鏈FL的電阻,藉此使電熔絲結構程式化。 In the fuse link FL, thermal and electrical driving forces may thus result in a non-uniform atomic flow rate or a non-zero flux divergence, as shown in FIG. In addition, depletion or accumulation of atoms may occur depending on the magnitude of the flux divergence. For example, if the outflow flux is greater than the inflow flux in a particular region of the fuse link FL, the atoms can be depleted to form a void. In contrast, if the influx flux is greater than the outflow flux in a particular region of the fuse link FL, the atoms can be accumulated to establish a hillock formation. The voids increase the resistance of the fuse link FL, thereby stylizing the electrical fuse structure.

根據以上方法,熔絲鏈FL中的通量發散愈大,則形成空隙愈快。下文中,將描述用於增加熔絲鏈FL中之通量發散的各種結構及方法。 According to the above method, the larger the flux divergence in the fuse link FL, the faster the void is formed. Hereinafter, various structures and methods for increasing flux divergence in the fuse link FL will be described.

圖4A說明電熔絲結構之第一實施例,且圖4B說明沿著圖4A中之截面線I-I'及II-II'獲得的視圖。參看圖4A及圖4B,電熔絲結構之第一實施例包含下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及罩蓋介電質30上的層間絕緣層40。金屬層20可形成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。另外,電熔絲結構可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50。 4A illustrates a first embodiment of an electrical fuse structure, and FIG. 4B illustrates a view taken along section lines II' and II-II' of FIG. 4A. Referring to Figures 4A and 4B, a first embodiment of an electrical fuse structure includes a metal layer 20 on the underlying layer 10, a cap dielectric 30 overlying the top surface of the metal layer 20, and a cap dielectric 30. Interlayer insulating layer 40. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a. Additionally, the electrical fuse structure can include a dummy metal plug 50 that is in contact with a portion of the fuse link 20f.

下伏層10可為絕緣薄膜。舉例而言,下伏層10可為以下兩者中的一者:元件隔離層,其可形成於半導體基板上以定義主動區,或層間絕緣層40,其形成於電晶體上以支撐金屬線。 The underlying layer 10 can be an insulating film. For example, the underlying layer 10 can be one of: an element isolation layer that can be formed on a semiconductor substrate to define an active region, or an interlayer insulating layer 40 formed on the transistor to support the metal line .

金屬層20可為薄膜。在一個實施例中,金屬層20可由 第一金屬材料形成。舉例而言,金屬層20可由以下各者中的至少一者製成:鎢(W)、鋁(Al)、銅(Cu)或銅合金。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 Metal layer 20 can be a thin film. In one embodiment, the metal layer 20 can be The first metal material is formed. For example, the metal layer 20 can be made of at least one of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

可藉由將金屬層20沈積於下伏層10上且圖案化金屬層20而形成陽極20a、陰極20c及熔絲鏈20f。替代地,陽極20a、陰極20c及熔絲鏈20f可藉由鑲嵌(damascene)製程形成,所述鑲嵌製程包含在絕緣層中形成溝槽,且用金屬性材料填充溝槽。在一個實施例中,熔絲鏈20f可沿著特定方向延伸,陽極20a可連接至熔絲鏈20f的末端部分,且陰極20c可連接至熔絲鏈20f的相對末端部分。陽極20a及陰極20c可具有大於熔絲鏈20f之寬度的寬度。如諸圖中所展示,可對稱地形成陽極20a及陰極20c。然而,在替代性實施例中,可非對稱地形成陽極20a及陰極20c。 The anode 20a, the cathode 20c, and the fuse link 20f can be formed by depositing the metal layer 20 on the underlying layer 10 and patterning the metal layer 20. Alternatively, the anode 20a, the cathode 20c, and the fuse link 20f may be formed by a damascene process including forming a trench in the insulating layer and filling the trench with a metallic material. In one embodiment, the fuse link 20f may extend in a particular direction, the anode 20a may be coupled to an end portion of the fuse link 20f, and the cathode 20c may be coupled to an opposite end portion of the fuse link 20f. The anode 20a and the cathode 20c may have a width greater than the width of the fuse link 20f. As shown in the figures, the anode 20a and the cathode 20c can be formed symmetrically. However, in an alternative embodiment, anode 20a and cathode 20c may be formed asymmetrically.

在一個實施例中,熔絲鏈20f可包含第一區R1、第二區R2及第三區R3。在第一區R1中,虛設金屬插塞50及熔絲鏈20f彼此接觸。在第二區R2中,罩蓋介電質30及熔絲鏈20f在陽極20a與虛設金屬插塞50之間彼此接觸。在第三區R3中,罩蓋介電質30及熔絲鏈20f在陰極20c與虛設金屬插塞50之間彼此接觸。 In one embodiment, the fuse link 20f can include a first zone R1, a second zone R2, and a third zone R3. In the first region R1, the dummy metal plug 50 and the fuse link 20f are in contact with each other. In the second region R2, the cap dielectric 30 and the fuse link 20f are in contact with each other between the anode 20a and the dummy metal plug 50. In the third region R3, the cap dielectric 30 and the fuse link 20f are in contact with each other between the cathode 20c and the dummy metal plug 50.

罩蓋介電質30可在層間絕緣層40與熔絲鏈20f的頂部表面之間。罩蓋介電質30可由不同於下伏層10及層間絕緣層40的絕緣材料形成。罩蓋介電質層30亦可(例如)以均一厚度保形地覆蓋熔絲鏈20f的頂部表面,但此情形並非在所有實施例中有必要。罩蓋介電質30可由(例如)SiO2、SiON、Si3N4、SiCN、 SiC或SiCN形成。層間絕緣層40可由氧化矽、氮化矽、氮氧化矽或低k材料形成。 The cap dielectric 30 can be between the interlayer insulating layer 40 and the top surface of the fuse link 20f. The cap dielectric 30 may be formed of an insulating material different from the underlying layer 10 and the interlayer insulating layer 40. The cap dielectric layer 30 may also conformally cover the top surface of the fuse link 20f, for example, in a uniform thickness, although this is not necessary in all embodiments. The cap dielectric 30 can be formed of, for example, SiO 2 , SiON, Si 3 N 4 , SiCN, SiC, or SiCN. The interlayer insulating layer 40 may be formed of tantalum oxide, tantalum nitride, hafnium oxynitride or a low-k material.

虛設金屬插塞50可藉由以下程序形成,所述程序包含形成虛設接觸孔以透過罩蓋介電質30及層間絕緣層40暴露熔絲鏈20f的一部分,且接著用金屬性材料填充虛設接觸孔。在一個實施例中,虛設金屬插塞50可形成於熔絲鏈20f的中心部分上,且可與熔絲鏈20f的頂部表面接觸。虛設金屬插塞50的下部寬度可大於熔絲鏈20f的上部寬度,且虛設金屬插塞50的上部寬度可大於虛設金屬插塞50的下部寬度。 The dummy metal plug 50 can be formed by a process including forming a dummy contact hole to expose a portion of the fuse link 20f through the cap dielectric 30 and the interlayer insulating layer 40, and then filling the dummy contact with a metallic material hole. In one embodiment, the dummy metal plug 50 may be formed on a central portion of the fuse link 20f and may be in contact with the top surface of the fuse link 20f. The lower width of the dummy metal plug 50 may be greater than the upper width of the fuse link 20f, and the upper width of the dummy metal plug 50 may be greater than the lower width of the dummy metal plug 50.

在一個實施例中,虛設金屬插塞50可包含金屬層53,與插入於金屬層53與熔絲鏈20f之間的障壁金屬層51。障壁金屬層51可經提供以覆蓋金屬層53的底部及側表面。在一個實施例中,障壁金屬層51在金屬層53之側表面及底部表面上可具有均一厚度。障壁金屬層51可由一種材料形成,所述材料能夠防止構成金屬層53之金屬材料擴散至與其相鄰的層間絕緣層40中。 In one embodiment, the dummy metal plug 50 may include a metal layer 53 and a barrier metal layer 51 interposed between the metal layer 53 and the fuse link 20f. A barrier metal layer 51 may be provided to cover the bottom and side surfaces of the metal layer 53. In one embodiment, the barrier metal layer 51 may have a uniform thickness on the side and bottom surfaces of the metal layer 53. The barrier metal layer 51 may be formed of a material capable of preventing the metal material constituting the metal layer 53 from diffusing into the interlayer insulating layer 40 adjacent thereto.

在一個實施例中,障壁金屬層51可由第二金屬材料形成,所述第二金屬材料可不同於熔絲鏈20f的第一金屬材料,且其具有小於第一金屬材料之電導率的電導率。形成障壁金屬層51之材料的實例包含Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合中的至少一者。 In one embodiment, the barrier metal layer 51 may be formed of a second metal material that may be different from the first metal material of the fuse link 20f and that has a conductivity that is less than the conductivity of the first metal material. . Examples of the material forming the barrier metal layer 51 include at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.

在一個實施例中,金屬層53可由第三金屬材料形成,所述金屬材料可不同於障壁金屬層51的第二金屬材料。金屬層53之第三金屬材料可與熔絲鏈20f的第一金屬材料相同或不同。舉例而言,金屬層53可由以下各者中的至少一者製成:鎢(W)、 鋁(Al)、銅(Cu)或銅合金。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 In one embodiment, the metal layer 53 may be formed of a third metal material that may be different from the second metal material of the barrier metal layer 51. The third metal material of the metal layer 53 may be the same as or different from the first metal material of the fuse link 20f. For example, the metal layer 53 may be made of at least one of: tungsten (W), Aluminum (Al), copper (Cu) or copper alloy. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

圖5說明電熔絲結構之第一實施例的程式化程序中可發生的電遷移。圖6說明電熔絲結構之第一實施例的程式化程序中可發生的熱遷移。圖7說明電熔絲結構之第一實施例的程式化程序中可發生的熱及電遷移。 Figure 5 illustrates the electromigration that can occur in the stylized program of the first embodiment of the electrical fuse structure. Figure 6 illustrates the thermal transfer that can occur in the stylized program of the first embodiment of the electrical fuse structure. Figure 7 illustrates the heat and electromigration that can occur in the stylized procedure of the first embodiment of the electrical fuse structure.

參看圖5,電熔絲結構之程式化程序可使用程式化電流來執行。可藉由在陰極20c與陽極20a之間形成電壓差來產生程式化電流。在一個實施例中,在程式化程序期間,負電壓可施加至陰極20c,正電壓可施加至陽極20a,且虛設金屬插塞50可處於電浮動狀態。陰極20c與陽極20a之間的電壓差產生程式化電流,所述程式化電流使得電子自陰極20c通過熔絲鏈20f朝向陽極20a流動。 Referring to Figure 5, the stylized program of the electrical fuse structure can be implemented using a programmed current. The stylized current can be generated by forming a voltage difference between the cathode 20c and the anode 20a. In one embodiment, during the stylization process, a negative voltage may be applied to the cathode 20c, a positive voltage may be applied to the anode 20a, and the dummy metal plug 50 may be in an electrically floating state. The voltage difference between the cathode 20c and the anode 20a produces a stylized current that causes electrons to flow from the cathode 20c through the fuse link 20f toward the anode 20a.

在此電子流期間,電子可與構成熔絲鏈20f的原子碰撞,藉此引起電遷移。電遷移可主要沿著金屬層之表面發生。電遷移引起之驅動力可視與熔絲鏈20f接觸之材料而改變。換言之,如上文所描述,熔絲鏈20f可包含以下各者:第一區R1,其中虛設金屬插塞50與熔絲鏈20f彼此接觸;第二區R2,其中罩蓋介電質30與熔絲鏈20f在陽極20a與虛設金屬插塞50之間彼此接觸;及第三區R3,其中罩蓋介電質30與熔絲鏈20f在陰極20c與虛設金屬插塞50之間彼此接觸。 During this electron flow, electrons can collide with atoms constituting the fuse link 20f, thereby causing electromigration. Electromigration can occur primarily along the surface of the metal layer. The driving force caused by electromigration may vary depending on the material in contact with the fuse link 20f. In other words, as described above, the fuse link 20f may include the following: a first region R1 in which the dummy metal plug 50 and the fuse link 20f are in contact with each other; and a second region R2 in which the cap dielectric 30 is melted The wire chain 20f is in contact with each other between the anode 20a and the dummy metal plug 50; and the third region R3 in which the cap dielectric 30 and the fuse link 20f are in contact with each other between the cathode 20c and the dummy metal plug 50.

由電遷移引起之驅動力在第一區R1與第二區R2之間且在第一區R1與第三區R3之間可不同。舉例而言,金屬層及介電 質層彼此接觸所在的第二區R2與第三區R3上之第一電驅動力EM1可小於第一區R1上的第二電驅動力EM2,在第一區R1處,不同金屬性材料彼此接觸。 The driving force caused by electromigration may be different between the first region R1 and the second region R2 and between the first region R1 and the third region R3. For example, metal layers and dielectrics The first electric driving force EM1 on the second region R2 and the third region R3 where the physical layers are in contact with each other may be smaller than the second electric driving force EM2 on the first region R1, and at the first region R1, different metallic materials are mutually contact.

參看圖6,在電熔絲結構經程式化時可發生焦耳熱。焦耳熱可產生熔絲鏈20f之溫度的非零梯度。在一個實施例中,最大量之焦耳熱可產生於熔絲鏈20f的中心部分處。然而,第一區R1之溫度可降低,此是因為此熱之相當大的部分可經由虛設金屬插塞50與熔絲鏈20f彼此接觸所在的部分耗散。舉例而言,虛設金屬插塞50與熔絲鏈20f之間的實體接觸可導致熔絲鏈20f之溫度梯度的改變。舉例而言,在程式化期間,熔絲鏈20f之溫度可由於虛設金屬插塞50之存在而在兩個分離部分處具有最大值。舉例而言,熔絲鏈20f之溫度可在第二區R2與第三區R3中為最大值,第二區R2與第三區R3位於虛設金屬插塞50的各別側處。 Referring to Figure 6, Joule heat can occur when the electrical fuse structure is programmed. Joule heat can produce a non-zero gradient of the temperature of the fuse link 20f. In one embodiment, a maximum amount of Joule heat may be generated at a central portion of the fuse link 20f. However, the temperature of the first zone R1 can be lowered because a considerable portion of this heat can be dissipated via the portion where the dummy metal plug 50 and the fuse link 20f are in contact with each other. For example, physical contact between the dummy metal plug 50 and the fuse link 20f can result in a change in the temperature gradient of the fuse link 20f. For example, during stylization, the temperature of the fuse link 20f may have a maximum at the two separate portions due to the presence of the dummy metal plug 50. For example, the temperature of the fuse link 20f may be a maximum in the second region R2 and the third region R3, and the second region R2 and the third region R3 are located at respective sides of the dummy metal plug 50.

在圖7中,曲線A展示由電遷移引起之驅動力,所述電遷移可在電熔絲結構經程式化時發生。曲線B展示由熱遷移引起之驅動力,所述熱遷移可在電熔絲結構經程式化時發生。曲線C展示由熱及電遷移引起之兩個驅動力的總驅動力或合力。 In Figure 7, curve A shows the driving force caused by electromigration, which can occur when the electrical fuse structure is programmed. Curve B shows the driving force caused by thermal migration that can occur when the electrical fuse structure is programmed. Curve C shows the total driving force or resultant force of the two driving forces caused by heat and electromigration.

在一個實施例中,因為虛設金屬插塞50之存在,熔絲鏈20f之溫度可在兩個分離部分處具有最大值。結果,熔絲鏈20f的在虛設金屬插塞50下方的部分可具有低於熔絲鏈20f之其他部分之溫度的溫度。另外,歸因於虛設金屬插塞50之存在,熔絲鏈20f的在虛設金屬插塞50下方之部分中的電驅動力可降低。 In one embodiment, the temperature of the fuse link 20f may have a maximum at the two separated portions because of the presence of the dummy metal plug 50. As a result, the portion of the fuse link 20f below the dummy metal plug 50 may have a temperature lower than the temperature of other portions of the fuse link 20f. In addition, due to the presence of the dummy metal plug 50, the electric driving force of the fuse link 20f in the portion below the dummy metal plug 50 can be lowered.

總驅動力可在熔絲鏈20f之第一區R1中或附近急劇改變。舉例而言,相較於在參看圖3描述之電熔絲結構中,在具有 虛設金屬插塞50的電熔絲結構中總驅動力FEM+TM之改變速率可更大。舉例而言,因為通量發散在與虛設金屬插塞50接觸的第一區R1處增加,所以電熔絲結構在相同條件下(例如在相同電壓下)可經更快速地程式化。此情形使得有可能以減小之程式化電壓程式化電熔絲結構。 The total driving force can be drastically changed in or near the first region R1 of the fuse link 20f. For example, the rate of change of the total driving force F EM+TM in the electrical fuse structure having the dummy metal plug 50 can be greater than in the electrical fuse structure described with reference to FIG. For example, because the flux divergence increases at the first region R1 that is in contact with the dummy metal plug 50, the electrical fuse structure can be programmed more quickly under the same conditions (eg, at the same voltage). This situation makes it possible to program the electrical fuse structure with a reduced stylized voltage.

如圖7中所展示,總驅動力FEM+TM在相鄰於陽極20a且在虛設金屬插塞50之一側的熔絲鏈20f的一部分處可具有最大值。因為流出通量急劇增加,所以在熔絲鏈20f的相鄰於虛設金屬插塞50的第二區R2處可發生耗盡或空隙。因此,在程式化程序之後,電熔絲結構可具有在陽極20a與虛設金屬插塞50之間的空隙V。空隙V與虛設金屬插塞50之間的距離可小於空隙V與陽極20a之間的距離。 As shown in FIG. 7, the total driving force F EM+TM may have a maximum value at a portion of the fuse link 20f adjacent to the anode 20a and on one side of the dummy metal plug 50. Since the outflow flux increases sharply, depletion or voids may occur at the second region R2 of the fuse link 20f adjacent to the dummy metal plug 50. Thus, after the stylization process, the electrical fuse structure can have a gap V between the anode 20a and the dummy metal plug 50. The distance between the void V and the dummy metal plug 50 may be smaller than the distance between the void V and the anode 20a.

圖8A至圖8C說明電熔絲結構之第一實施例的修改。參看圖8A至圖8C,如參看圖4B所描述,電熔絲結構包含陰極20c、陽極20a、熔絲鏈20f及虛設金屬插塞50。熔絲鏈20f包含以下各者:第一區R1,其中虛設金屬插塞50及熔絲鏈20f彼此接觸;第二區R2,其中罩蓋介電質30及熔絲鏈20f在陽極20a與虛設金屬插塞50之間彼此接觸;及第三區R3,其中罩蓋介電質30與熔絲鏈20f在陰極20c與虛設金屬插塞50之間彼此接觸。 8A to 8C illustrate a modification of the first embodiment of the electric fuse structure. Referring to Figures 8A-8C, as described with reference to Figure 4B, the electrical fuse structure includes a cathode 20c, an anode 20a, a fuse link 20f, and a dummy metal plug 50. The fuse link 20f includes the following: a first region R1 in which the dummy metal plug 50 and the fuse link 20f are in contact with each other; and a second region R2 in which the cap dielectric 30 and the fuse link 20f are in the anode 20a and dummy The metal plugs 50 are in contact with each other; and the third region R3 in which the cap dielectric 30 and the fuse link 20f are in contact with each other between the cathode 20c and the dummy metal plug 50.

參看圖8A至圖8C,虛設金屬插塞50可包含如上文所描述之障壁金屬層51及金屬層53,且可具有低於熔絲鏈20f之頂部表面的底部表面。虛設金屬插塞50之底部表面可與下伏層10的頂部表面隔開。換言之,相較於在第二區R2及第三區R3上,熔絲鏈20f之厚度在第一區R1上可較小。另外,如圖8A及圖8B 中所展示,虛設金屬插塞50可具有低於熔絲鏈20f之上部寬度的下部寬度。在一個實施例中,如圖8B中所展示,在金屬層53之底部表面上的障壁金屬層51之厚度相較於在金屬層53之側表面上的障壁金屬層51之厚度可更大。 Referring to FIGS. 8A through 8C, the dummy metal plug 50 may include the barrier metal layer 51 and the metal layer 53 as described above, and may have a bottom surface lower than the top surface of the fuse link 20f. The bottom surface of the dummy metal plug 50 may be spaced apart from the top surface of the underlying layer 10. In other words, the thickness of the fuse link 20f may be smaller in the first region R1 than in the second region R2 and the third region R3. In addition, as shown in Figures 8A and 8B As shown, the dummy metal plug 50 can have a lower width that is lower than the width of the upper portion of the fuse link 20f. In one embodiment, as shown in FIG. 8B, the thickness of the barrier metal layer 51 on the bottom surface of the metal layer 53 may be greater than the thickness of the barrier metal layer 51 on the side surface of the metal layer 53.

在一個實施例中,如圖8C中所展示,虛設金屬插塞50可具有圓形下部拐角。又,虛設金屬插塞50之下部寬度可大於熔絲鏈20f的上部寬度。因此,虛設金屬插塞50可覆蓋熔絲鏈20f的頂部表面,及側表面的一部分。換言之,障壁金屬層51可與熔絲鏈20f之頂部表面及側表面直接接觸。 In one embodiment, as shown in Figure 8C, the dummy metal plug 50 can have a rounded lower corner. Also, the width of the lower portion of the dummy metal plug 50 may be greater than the upper width of the fuse link 20f. Therefore, the dummy metal plug 50 may cover the top surface of the fuse link 20f and a portion of the side surface. In other words, the barrier metal layer 51 can be in direct contact with the top surface and the side surface of the fuse link 20f.

圖9A及圖10A說明電熔絲結構之第二實施例,圖9B及圖10B說明分別沿著圖9A及圖10A中之截面線I-I'及II-II'獲得的視圖,且圖9C及圖10C說明電熔絲結構之第二實施例的修改。 9A and FIG. 10A illustrate a second embodiment of the electric fuse structure, and FIGS. 9B and 10B illustrate views taken along section lines I-I' and II-II' of FIGS. 9A and 10A, respectively, and FIG. 9C. And Figure 10C illustrates a modification of the second embodiment of the electrical fuse structure.

在第二實施例中,電熔絲結構包含虛設金屬插塞50的至少一層及連接至熔絲鏈20f之虛設金屬圖案80。虛設金屬圖案80之體積可經調整以控制電熔絲結構的熔融效能。 In the second embodiment, the electrical fuse structure includes at least one layer of the dummy metal plug 50 and a dummy metal pattern 80 connected to the fuse link 20f. The volume of the dummy metal pattern 80 can be adjusted to control the melting efficiency of the electrical fuse structure.

參看圖9A、圖9B、圖10A及圖10B,電熔絲結構之第二實施例包含在下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。金屬層20可形成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。此外,電熔絲結構可包含虛設金屬插塞50,及連接至熔絲鏈20f之一部分的虛設金屬圖案80。第一接觸插塞60a及第一導電圖案90a可連接至陽極20a。第二接觸插塞60b及第二導電圖案90b可連接至陰極20c。 Referring to FIGS. 9A, 9B, 10A and 10B, a second embodiment of the electrical fuse structure includes a metal layer 20 on the underlying layer 10, a capping dielectric 30 covering the top surface of the metal layer 20, and The interlayer insulating layer 40 on the dielectric 30 is covered. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a. Additionally, the electrical fuse structure can include a dummy metal plug 50, and a dummy metal pattern 80 that is coupled to a portion of the fuse link 20f. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20c.

在一個實施例中,熔絲鏈20f可沿著特定方向延伸,陽 極20a可連接至熔絲鏈20f的末端部分,且陰極20c可連接至熔絲鏈20f的相對末端部分。陽極20a及陰極20c可具有大於熔絲鏈20f之寬度的寬度。在一個實施例中,金屬層20可由第一金屬材料形成。舉例而言,金屬層20可由以下各者中的至少一者製成:鎢(W)、鋁(Al)、銅(Cu)或銅合金。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 In one embodiment, the fuse link 20f can extend in a particular direction, The pole 20a can be connected to the end portion of the fuse link 20f, and the cathode 20c can be connected to the opposite end portion of the fuse link 20f. The anode 20a and the cathode 20c may have a width greater than the width of the fuse link 20f. In one embodiment, the metal layer 20 can be formed from a first metallic material. For example, the metal layer 20 can be made of at least one of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

罩蓋介電質30及第一層間絕緣層40可依序形成於下伏層10上,在所述下伏層10上,提供陽極20a、陰極20c及熔絲鏈20f。罩蓋介電質30可由不同於下伏層10及第一層間絕緣層40的絕緣材料形成。罩蓋介電質可保形地覆蓋熔絲鏈20f之頂部表面,且可由(例如)SiO2、SiON、Si3N4、SiCN、SiC或SiCN形成。 The cap dielectric 30 and the first interlayer insulating layer 40 may be sequentially formed on the underlying layer 10, and on the underlying layer 10, an anode 20a, a cathode 20c, and a fuse link 20f are provided. The cap dielectric 30 may be formed of an insulating material different from the underlying layer 10 and the first interlayer insulating layer 40. The cap dielectric may conformally cover the top surface of the fuse link 20f and may be formed of, for example, SiO 2 , SiON, Si 3 N 4 , SiCN, SiC, or SiCN.

虛設金屬插塞50之形成可包含:形成穿透罩蓋介電質30及第一層間絕緣層40的虛設接觸孔,及暴露熔絲鏈20f的一部分。接著,可用金屬性材料填充虛設接觸孔。形成第一接觸插塞60a可包含:形成穿透罩蓋介電質30及第一層間絕緣層40的第一接觸孔並暴露陽極20a的一部分,及接著用金屬性材料填充第一接觸孔。 The formation of the dummy metal plug 50 may include forming a dummy contact hole penetrating the cap dielectric 30 and the first interlayer insulating layer 40, and exposing a portion of the fuse link 20f. Next, the dummy contact holes may be filled with a metallic material. Forming the first contact plug 60a may include: forming a first contact hole penetrating the cap dielectric 30 and the first interlayer insulating layer 40 and exposing a portion of the anode 20a, and then filling the first contact hole with a metallic material .

形成第二接觸插塞60a可包含:形成穿透罩蓋介電質30及第一層間絕緣層40的第二接觸孔並暴露陰極20c的一部分,及接著用金屬性材料填充第二接觸孔。在一個實施例中,虛設金屬插塞50可與第一接觸插塞60a及第二接觸插塞60b同時形成。另 外,虛設金屬插塞50可包含與第一接觸插塞60a及第二接觸插塞60b中之至少一者相同的金屬性材料。 Forming the second contact plug 60a may include: forming a second contact hole penetrating the cap dielectric 70 and the first interlayer insulating layer 40 and exposing a portion of the cathode 20c, and then filling the second contact hole with a metallic material . In one embodiment, the dummy metal plug 50 can be formed simultaneously with the first contact plug 60a and the second contact plug 60b. another In addition, the dummy metal plug 50 may include the same metallic material as at least one of the first contact plug 60a and the second contact plug 60b.

在一個實施例中,虛設金屬插塞50以及第一金屬接觸插塞60a及第二金屬接觸插塞60b中的每一者可包含第一障壁金屬層51及第一金屬層53。第一障壁金屬層51可經形成以在虛設接觸孔之側表面及底部表面上具有均一厚度。在一個實施例中,第一障壁金屬層51可由第二金屬材料形成,所述第二金屬材料可不同於熔絲鏈20f的第一金屬材料,且第一障壁金屬層51可具有小於第一金屬材料之電導率的電導率。舉例而言,第一障壁金屬層51可由Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合形成。 In one embodiment, the dummy metal plug 50 and each of the first metal contact plug 60a and the second metal contact plug 60b may include a first barrier metal layer 51 and a first metal layer 53. The first barrier metal layer 51 may be formed to have a uniform thickness on the side surface and the bottom surface of the dummy contact hole. In one embodiment, the first barrier metal layer 51 may be formed of a second metal material, the second metal material may be different from the first metal material of the fuse link 20f, and the first barrier metal layer 51 may have less than the first The conductivity of the electrical conductivity of a metallic material. For example, the first barrier metal layer 51 may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.

第一金屬層53可由第三金屬材料形成,所述金屬材料可不同於第一障壁金屬層51的第二金屬材料。第一金屬層53之第三金屬材料可與熔絲鏈20f的第一金屬材料相同或不同。舉例而言,第一金屬層53可由以下各者中的至少一者製成:鎢(W)、鋁(Al)、銅(Cu)或銅合金。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 The first metal layer 53 may be formed of a third metal material that may be different from the second metal material of the first barrier metal layer 51. The third metal material of the first metal layer 53 may be the same as or different from the first metal material of the fuse link 20f. For example, the first metal layer 53 may be made of at least one of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

第二層間絕緣層70可形成於具備虛設金屬插塞50以及第一接觸插塞60a及第二接觸插塞60b的第一層間絕緣層40上。第一導電圖案90a及第二導電圖案90b以及虛設金屬圖案80可形成於第二層間絕緣層70中。虛設金屬圖案80可連接至虛設金屬插塞50。第一導電圖案90a及第二導電圖案90b可分別連接至第一接觸插塞60a及第二接觸插塞60b。 The second interlayer insulating layer 70 may be formed on the first interlayer insulating layer 40 including the dummy metal plug 50 and the first contact plug 60a and the second contact plug 60b. The first conductive pattern 90a and the second conductive pattern 90b and the dummy metal pattern 80 may be formed in the second interlayer insulating layer 70. The dummy metal pattern 80 can be connected to the dummy metal plug 50. The first conductive pattern 90a and the second conductive pattern 90b may be connected to the first contact plug 60a and the second contact plug 60b, respectively.

虛設金屬圖案80可包含第二金屬層83,與插入於第二金屬層83與虛設金屬插塞50之間的第二障壁金屬層81。形成虛設金屬圖案80可包含:在第二層間絕緣層70中形成溝槽以暴露虛設金屬插塞50的頂部表面,且接著依序形成第二障壁金屬層81及第二金屬層83以填充溝槽。第二障壁金屬層81可由(例如)Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合形成。 The dummy metal pattern 80 may include a second metal layer 83 and a second barrier metal layer 81 interposed between the second metal layer 83 and the dummy metal plug 50. Forming the dummy metal pattern 80 may include: forming a trench in the second interlayer insulating layer 70 to expose a top surface of the dummy metal plug 50, and then sequentially forming a second barrier metal layer 81 and a second metal layer 83 to fill the trench groove. The second barrier metal layer 81 may be formed of, for example, Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.

第二金屬層83可由不同於構成虛設金屬插塞50之第一金屬層51之金屬材料的金屬材料形成。第一導電圖案90a及第二導電圖案90b可與虛設金屬圖案80同時形成。舉例而言,第一導電圖案90a及第二導電圖案90b可由與虛設金屬圖案80相同的金屬材料形成。 The second metal layer 83 may be formed of a metal material different from the metal material constituting the first metal layer 51 of the dummy metal plug 50. The first conductive pattern 90a and the second conductive pattern 90b may be formed simultaneously with the dummy metal pattern 80. For example, the first conductive pattern 90a and the second conductive pattern 90b may be formed of the same metal material as the dummy metal pattern 80.

根據圖9A及圖9B中的實施例,虛設金屬插塞50之寬度W2可小於熔絲鏈20f的寬度W1。虛設金屬圖案80之寬度W3可大於熔絲鏈20f的寬度W1。此外,虛設金屬圖案80可具有小於熔絲鏈20f之厚度t1的第一厚度t2。 According to the embodiment of FIGS. 9A and 9B, the width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20f. The width W3 of the dummy metal pattern 80 may be greater than the width W1 of the fuse link 20f. Further, the dummy metal pattern 80 may have a first thickness t2 that is smaller than the thickness t1 of the fuse link 20f.

根據圖10A及圖10B中的實施例,虛設金屬插塞50之寬度W2可小於熔絲鏈20f的寬度W1。虛設金屬圖案80之寬度W3可大於熔絲鏈20f的寬度W1。此外,虛設金屬圖案80可具有大於熔絲鏈20f之厚度t1的第二厚度t3。 According to the embodiment of FIGS. 10A and 10B, the width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20f. The width W3 of the dummy metal pattern 80 may be greater than the width W1 of the fuse link 20f. Further, the dummy metal pattern 80 may have a second thickness t3 that is greater than the thickness t1 of the fuse link 20f.

根據第二實施例,圖9A及圖9B中之虛設金屬圖案80可具有不同於圖10A及圖10B中之虛設金屬圖案80之體積的體積。舉例而言,圖9A及圖9B中虛設金屬圖案80的體積可小於圖10A及圖10B中之虛設金屬圖案80之體積。 According to the second embodiment, the dummy metal pattern 80 in FIGS. 9A and 9B may have a volume different from the volume of the dummy metal pattern 80 in FIGS. 10A and 10B. For example, the volume of the dummy metal pattern 80 in FIGS. 9A and 9B may be smaller than the volume of the dummy metal pattern 80 in FIGS. 10A and 10B.

根據圖9C及圖10C中的實施例,電熔絲結構可包含在 下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的第一層間絕緣層40及第二層間絕緣層70。金屬層20可形成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。在一個實施例中,陽極20a及陰極20c可具有大於熔絲鏈20f之寬度的寬度。金屬層20可由(例如)第一金屬材料(例如,鎢(W)、鋁(Al)、銅(Cu)或銅合金的至少一者)形成。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 According to the embodiment of Figures 9C and 10C, the electrical fuse structure can be included in The metal layer 20 on the underlying layer 10, the cap dielectric 30 covering the top surface of the metal layer 20, and the first interlayer insulating layer 40 and the second interlayer insulating layer 70 on the cap dielectric 30. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a. In one embodiment, anode 20a and cathode 20c may have a width greater than the width of fuse link 20f. The metal layer 20 may be formed of, for example, a first metal material such as at least one of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

根據此實施例,電熔絲結構可包含與虛設熔絲鏈20f之一部分接觸的虛設金屬插塞50。虛設金屬插塞50可包含障壁金屬層51、接觸部分53a及互連部分53b。障壁金屬層51可由導電材料形成,所述材料能夠防止構成接觸部分53a及互連部分53b之金屬材料擴散至其相鄰的第一層間絕緣層40及第二層間絕緣層70中。障壁金屬層51可由不同於第一金屬材料且具有小於第一金屬材料之導電率的第二金屬材料形成。舉例而言,障壁金屬層51可由Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合形成。 According to this embodiment, the electrical fuse structure can include a dummy metal plug 50 that is in partial contact with one of the dummy fuse links 20f. The dummy metal plug 50 may include a barrier metal layer 51, a contact portion 53a, and an interconnection portion 53b. The barrier metal layer 51 may be formed of a conductive material capable of preventing the metal material constituting the contact portion 53a and the interconnection portion 53b from diffusing into the adjacent first interlayer insulating layer 40 and second interlayer insulating layer 70. The barrier metal layer 51 may be formed of a second metal material different from the first metal material and having a conductivity lower than that of the first metal material. For example, the barrier metal layer 51 may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.

在一個實施例中,接觸部分53a可通過第一層間絕緣層40連接至熔絲鏈20f。互連部分53b可安置於第二層間絕緣層70中,且可連接至接觸部分53a。互連部分53b可具有大於接觸部分53a之寬度的寬度。接觸部分53a及互連部分53b可由第三金屬材料形成,所述第三金屬材料可不同於第二金屬材料。舉例而言,接觸部分53a及互連部分53b可由鎢(W)、鋁(Al)、銅(Cu)或銅合金製成。銅合金之實例包含銅基材料,在所述銅基材料中 以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 In one embodiment, the contact portion 53a may be connected to the fuse link 20f through the first interlayer insulating layer 40. The interconnection portion 53b may be disposed in the second interlayer insulating layer 70 and may be connected to the contact portion 53a. The interconnecting portion 53b may have a width greater than the width of the contact portion 53a. The contact portion 53a and the interconnection portion 53b may be formed of a third metal material, which may be different from the second metal material. For example, the contact portion 53a and the interconnection portion 53b may be made of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of copper alloys include copper-based materials in which the copper-based materials are At least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al or Zr is contained in a small amount or in a predetermined amount.

在展示於圖9C中之一個實施例中,虛設金屬插塞50之下部寬度W2可小於熔絲鏈20f的寬度W1。虛設金屬插塞50之上部寬度W3可大於熔絲鏈20f的寬度W1。此外,在虛設金屬插塞50中,互連部分53b可具有小於熔絲鏈20f之厚度t1的第一厚度t2。 In one embodiment, shown in FIG. 9C, the width W2 of the lower portion of the dummy metal plug 50 may be less than the width W1 of the fuse link 20f. The width W3 of the upper portion of the dummy metal plug 50 may be greater than the width W1 of the fuse link 20f. Further, in the dummy metal plug 50, the interconnection portion 53b may have a first thickness t2 smaller than the thickness t1 of the fuse link 20f.

替代地,如圖10C中所展示,虛設金屬插塞50之下部寬度W2可小於熔絲鏈20f的寬度W1。虛設金屬插塞50之上部寬度W3可大於熔絲鏈20f的寬度W1。又,虛設金屬插塞50之互連部分53b可具有大於熔絲鏈20f之厚度t1的第二厚度t3。舉例而言,圖9C中虛設金屬插塞50之互連部分53b的體積可小於圖10C中虛設金屬插塞50的互連部分53b。 Alternatively, as shown in FIG. 10C, the lower width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20f. The width W3 of the upper portion of the dummy metal plug 50 may be greater than the width W1 of the fuse link 20f. Also, the interconnection portion 53b of the dummy metal plug 50 may have a second thickness t3 larger than the thickness t1 of the fuse link 20f. For example, the volume of the interconnect portion 53b of the dummy metal plug 50 in FIG. 9C may be smaller than the interconnect portion 53b of the dummy metal plug 50 in FIG. 10C.

形成虛設金屬插塞50可包含:依序形成第一層間絕緣層40及第二層間絕緣層70,形成通過第一層間絕緣層40及第二層間絕緣層70的通孔,圖案化第二層間絕緣層70以形成連接至通孔的溝槽,及在通孔及溝槽中依序形成障壁金屬層及金屬層。在一個實施例中,可在形成虛設金屬插塞50期間形成第一連接圖案65a及第二連接圖案65b。第一連接圖案65a可連接至陽極20a,且第二連接圖案65b可連接至陰極20c。 Forming the dummy metal plug 50 may include: sequentially forming the first interlayer insulating layer 40 and the second interlayer insulating layer 70, forming through holes through the first interlayer insulating layer 40 and the second interlayer insulating layer 70, and patterning The two interlayer insulating layer 70 forms a trench connected to the via hole, and sequentially forms a barrier metal layer and a metal layer in the via hole and the trench. In one embodiment, the first connection pattern 65a and the second connection pattern 65b may be formed during formation of the dummy metal plug 50. The first connection pattern 65a may be connected to the anode 20a, and the second connection pattern 65b may be connected to the cathode 20c.

類似於虛設金屬插塞50,第一連接圖案65a及第二連接圖案65b中的每一者可包含通路部分、互連部分,及覆蓋其底部表面及側表面的障壁金屬層。 Similar to the dummy metal plug 50, each of the first connection pattern 65a and the second connection pattern 65b may include a via portion, an interconnect portion, and a barrier metal layer covering the bottom surface and the side surface thereof.

圖11A及圖12A說明在電熔絲結構之第二實施例的程 式化程序中熱遷移可如何取決於虛設金屬圖案之體積的實例。 11A and 12A illustrate the process of the second embodiment of the electrical fuse structure How the thermal migration in the programming procedure depends on the example of the volume of the dummy metal pattern.

根據第二實施例,在程式化程序期間,負電壓可施加至陰極20c,正電壓可施加至陽極20a,且虛設金屬插塞50可處於電浮動狀態。因為陰極20c與陽極20a之間的電壓差及隨之發生的程式化電流,電子自陰極20c通過熔絲鏈20f朝向陽極20a流動。 According to the second embodiment, during the stylization procedure, a negative voltage can be applied to the cathode 20c, a positive voltage can be applied to the anode 20a, and the dummy metal plug 50 can be in an electrically floating state. Because of the voltage difference between the cathode 20c and the anode 20a and the accompanying stylized current, electrons flow from the cathode 20c toward the anode 20a through the fuse link 20f.

根據第二實施例,如圖11A及圖12A中所展示,在程式化期間,可藉由調整虛設金屬插塞50之體積來控制熔絲鏈20f之溫度梯度。在圖11A中,虛設金屬插塞50之互連部分53b可具有小於熔絲鏈20f之厚度t1的第一厚度t2。在圖12A中,虛設金屬插塞50之互連部分53b可具有大於熔絲鏈20f之厚度t1的第二厚度t3。舉例而言,圖12A中虛設金屬插塞50的互連部分53b之體積可大於展示於圖11A中虛設金屬插塞50的互連部分53b。 According to the second embodiment, as shown in FIGS. 11A and 12A, during the stylization, the temperature gradient of the fuse link 20f can be controlled by adjusting the volume of the dummy metal plug 50. In FIG. 11A, the interconnection portion 53b of the dummy metal plug 50 may have a first thickness t2 that is smaller than the thickness t1 of the fuse link 20f. In FIG. 12A, the interconnection portion 53b of the dummy metal plug 50 may have a second thickness t3 larger than the thickness t1 of the fuse link 20f. For example, the volume of the interconnect portion 53b of the dummy metal plug 50 in FIG. 12A may be larger than the interconnect portion 53b of the dummy metal plug 50 shown in FIG. 11A.

隨著虛設金屬插塞50之體積增加,熔絲鏈20f之第一區R1可被更有效地冷卻。舉例而言,與相鄰區相比較,熔絲鏈20f之第一區R1的溫度可被更有效地降低。相較於在圖11A中之電熔絲結構中,在圖12A中之電熔絲結構中第一區R1之溫度減小可較大。結果,相較於圖11A中之電熔絲結構,在圖12A之電熔絲結構中熔絲鏈20f之溫度分佈的非均一性可較高。 As the volume of the dummy metal plug 50 increases, the first region R1 of the fuse link 20f can be cooled more efficiently. For example, the temperature of the first region R1 of the fuse link 20f can be more effectively reduced as compared to the adjacent region. In comparison with the electric fuse structure in Fig. 11A, the temperature decrease of the first region R1 in the electric fuse structure of Fig. 12A can be large. As a result, the non-uniformity of the temperature distribution of the fuse link 20f in the electric fuse structure of Fig. 12A can be higher than that of the electric fuse structure of Fig. 11A.

圖11B及圖12B說明電熔絲結構之第二實施例的程式化程序中的熱遷移及電遷移效應。在圖11B及圖12B中,曲線A表示由電遷移引起之驅動力,所述電遷移可在電熔絲結構經程式化時發生。曲線B表示由熱遷移引起之驅動力,所述熱遷移可在電熔絲結構經程式化時發生。在圖11B及圖12B中,曲線C表示由熱及電遷移引起之兩個驅動力的總驅動力或合力。 11B and 12B illustrate the thermal migration and electromigration effects in the stylized program of the second embodiment of the electrical fuse structure. In FIGS. 11B and 12B, a curve A indicates a driving force caused by electromigration, which may occur when the electric fuse structure is programmed. Curve B represents the driving force caused by thermal migration, which can occur when the electrical fuse structure is programmed. In FIGS. 11B and 12B, a curve C indicates the total driving force or resultant force of the two driving forces caused by heat and electromigration.

參看圖11B,在熔絲鏈20f之第一區R1中,電驅動力之差△FEM可大於熱驅動力的差△FTM。舉例而言,熔絲鏈20f之第一區R1中的總驅動力可主要取決於電驅動力的差△FEM。 Referring to Fig. 11B, in the first region R1 of the fuse link 20f, the difference ΔF EM of the electric driving force may be greater than the difference ΔF TM of the thermal driving force. For example, the total driving force in the first region R1 of the fuse link 20f may depend mainly on the difference ΔFEM of the electric driving force.

參看圖12B,在熔絲鏈20f之第一區R1中,熱驅動力之差△FTM可大於電驅動力的差△FEM。舉例而言,熔絲鏈20f之第一區R1中的總驅動力可主要取決於熱驅動力的差△FTMReferring to Fig. 12B, in the first region R1 of the fuse link 20f, the difference ΔF TM of the thermal driving force may be greater than the difference ΔF EM of the electric driving force. For example, the total driving force of the first region R1 20f of the fuse link may be dependent on the thermal driving force of the main difference △ F TM.

根據本實施例,熱驅動力愈強,則熔絲鏈20f中之第一區R1中的總驅動力愈強。此情形可允許在給定電壓條件下更快速程式化電熔絲結構或減小程式化電熔絲結構所要求的電壓。 According to the present embodiment, the stronger the thermal driving force, the stronger the total driving force in the first region R1 in the fuse link 20f. This situation may allow for faster programming of the electrical fuse structure or reduction of the voltage required for the stylized electrical fuse structure under given voltage conditions.

圖13A及圖14A說明電熔絲結構之第三實施例,且圖13B及圖14B說明分別沿著圖13A及圖14A中之截面線I-I'及II-II'獲得的視圖。 13A and 14A illustrate a third embodiment of the electric fuse structure, and Figs. 13B and 14B illustrate views taken along section lines I-I' and II-II' of Figs. 13A and 14A, respectively.

參看圖13A、圖13B、圖14A及圖14B,電熔絲結構包含在下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。在一個實施例中,金屬層20可由第一金屬材料形成,且可構成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。另外,電熔絲結構可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50,及提供於虛設金屬插塞50上的虛設金屬圖案80。第一接觸插塞60a及第一導電圖案90a可連接至陽極20a,且第二接觸插塞60b及第二導電圖案90b可連接至陰極20c。 Referring to Figures 13A, 13B, 14A and 14B, the electrical fuse structure comprises a metal layer 20 on the underlying layer 10, a capping dielectric 30 covering the top surface of the metal layer 20, and a cap dielectric. Interlayer insulating layer 40 on 30. In one embodiment, the metal layer 20 may be formed of a first metal material and may constitute a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a. Additionally, the electrical fuse structure can include a dummy metal plug 50 that is in contact with a portion of the fuse link 20f, and a dummy metal pattern 80 that is provided on the dummy metal plug 50. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a, and the second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20c.

類似於展示於圖9C及圖10C中的虛設金屬插塞50,虛設金屬插塞50及虛設金屬圖案80可使用鑲嵌製程同時形成。舉例而言,障壁金屬層81可不形成於虛設金屬插塞50之金屬層53 與虛設金屬圖案80的金屬層83之間。 Similar to the dummy metal plug 50 shown in FIGS. 9C and 10C, the dummy metal plug 50 and the dummy metal pattern 80 can be simultaneously formed using a damascene process. For example, the barrier metal layer 81 may not be formed on the metal layer 53 of the dummy metal plug 50. Between the metal layer 83 of the dummy metal pattern 80.

根據第三實施例,虛設金屬插塞50與熔絲鏈20f之間的接觸區域可經改變以控制電熔絲結構之程式化程序中熔絲鏈的溫度梯度。舉例而言,如圖13A及圖13B中所展示,虛設金屬插塞50可具有小於熔絲鏈20f之上部寬度W1的第一下部寬度W2。虛設金屬圖案80之下部寬度可大於熔絲鏈20f的上部寬度W1。替代地,如圖14A及圖14B中所展示,虛設金屬插塞50可具有大於熔絲鏈20f之上部寬度W1的第二下部寬度W3。虛設金屬圖案80之下部寬度可大於熔絲鏈20f的上部寬度W1。根據第三實施例,在圖13A及圖13B中之電熔絲結構與圖14A及圖14B中之電熔絲結構之間,程式化程序中熔絲鏈20f的溫度梯度可不同。 According to the third embodiment, the contact area between the dummy metal plug 50 and the fuse link 20f can be changed to control the temperature gradient of the fuse link in the stylized program of the electric fuse structure. For example, as shown in Figures 13A and 13B, the dummy metal plug 50 can have a first lower width W2 that is less than the width W1 of the upper portion of the fuse link 20f. The width of the lower portion of the dummy metal pattern 80 may be greater than the upper width W1 of the fuse link 20f. Alternatively, as shown in FIGS. 14A and 14B, the dummy metal plug 50 may have a second lower width W3 that is greater than the upper width W1 of the fuse link 20f. The width of the lower portion of the dummy metal pattern 80 may be greater than the upper width W1 of the fuse link 20f. According to the third embodiment, the temperature gradient of the fuse link 20f in the stylization program may be different between the electric fuse structure in Figs. 13A and 13B and the electric fuse structure in Figs. 14A and 14B.

圖15A說明電熔絲結構之第四實施例,且圖15B說明沿著圖15A中之截面線I-I'及II-II'獲得的視圖。參看圖15A及圖15B,電熔絲結構可包含在下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。金屬層20可用以形成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。 Fig. 15A illustrates a fourth embodiment of the electric fuse structure, and Fig. 15B illustrates a view taken along section lines I-I' and II-II' in Fig. 15A. Referring to Figures 15A and 15B, the electrical fuse structure can include a metal layer 20 on the underlying layer 10, a capping dielectric 30 overlying the top surface of the metal layer 20, and interlayer dielectric on the cap dielectric 30. Layer 40. The metal layer 20 can be used to form the cathode 20c, the anode 20a, and the fuse link 20f connecting the cathode 20c and the anode 20a.

另外,電熔絲結構可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50,及在虛設金屬插塞50上的虛設金屬圖案80。第一接觸插塞60a及第一導電圖案90a可連接至陽極20a。第二接觸插塞60b及第二導電圖案90b可連接至陰極20c。類似於圖9C及圖10C中的虛設金屬插塞50,虛設金屬插塞50及虛設金屬圖案80可同時形成。舉例而言,障壁金屬層81可不形成於虛設金屬插塞50之金屬層53與虛設金屬圖案80的金屬層83之間。 Additionally, the electrical fuse structure can include a dummy metal plug 50 that is in contact with a portion of the fuse link 20f, and a dummy metal pattern 80 on the dummy metal plug 50. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20c. Similar to the dummy metal plug 50 in FIGS. 9C and 10C, the dummy metal plug 50 and the dummy metal pattern 80 can be simultaneously formed. For example, the barrier metal layer 81 may not be formed between the metal layer 53 of the dummy metal plug 50 and the metal layer 83 of the dummy metal pattern 80.

在本實施例中,虛設金屬插塞50及虛設金屬圖案80的位置可相對於陽極20a及陰極20c而改變。舉例而言,在圖15A中,虛設金屬插塞50與陽極20a之間的距離可大於虛設金屬插塞50與陰極20c之間的距離。虛設金屬插塞50之位置可經改變以控制空隙的位置,空隙將在電熔絲結構的程式化程序中形成。 In the present embodiment, the positions of the dummy metal plugs 50 and the dummy metal patterns 80 may be changed with respect to the anode 20a and the cathode 20c. For example, in FIG. 15A, the distance between the dummy metal plug 50 and the anode 20a may be greater than the distance between the dummy metal plug 50 and the cathode 20c. The position of the dummy metal plug 50 can be varied to control the position of the void which will be formed in the stylized program of the electrical fuse structure.

圖16A說明電熔絲結構之第五實施例,且圖16B說明沿著圖16A中之截面線I-I'及II-II'獲得的視圖。參看圖16A及圖16B,電熔絲結構可包含在下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。在一個實施例中,金屬層20可由第一金屬材料形成,且可形成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。 Fig. 16A illustrates a fifth embodiment of the electric fuse structure, and Fig. 16B illustrates a view taken along section lines I-I' and II-II' in Fig. 16A. 16A and 16B, the electrical fuse structure can include a metal layer 20 on the underlying layer 10, a capping dielectric 30 overlying the top surface of the metal layer 20, and interlayer dielectric on the cap dielectric 30. Layer 40. In one embodiment, the metal layer 20 may be formed of a first metal material and may form a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a.

電熔絲結構亦可包含與熔絲鏈20f之一部分接觸的第一虛設金屬插塞50a及第二虛設金屬插塞50b。第一虛設金屬圖案80a及第二虛設金屬圖案80b可分別提供於第一虛設金屬插塞50a及第二虛設金屬插塞50b上。第一虛設金屬插塞50a及第二虛設金屬插塞50b可在陽極20a與陰極20c之間,且彼此隔開。第一虛設金屬插塞50a及第二虛設金屬插塞50b中之每一者可包含障壁金屬層51及金屬層53。障壁金屬層51可由不同於第一金屬材料且具有小於第一金屬材料之導電率的第二金屬材料形成。第一接觸插塞60a及第一導電圖案90a可連接至陽極20a。第二接觸插塞60b及第二導電圖案90b可連接至陰極20c。 The electrical fuse structure may also include a first dummy metal plug 50a and a second dummy metal plug 50b that are in contact with a portion of the fuse link 20f. The first dummy metal pattern 80a and the second dummy metal pattern 80b may be respectively provided on the first dummy metal plug 50a and the second dummy metal plug 50b. The first dummy metal plug 50a and the second dummy metal plug 50b may be between the anode 20a and the cathode 20c and spaced apart from each other. Each of the first dummy metal plug 50a and the second dummy metal plug 50b may include a barrier metal layer 51 and a metal layer 53. The barrier metal layer 51 may be formed of a second metal material different from the first metal material and having a conductivity lower than that of the first metal material. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20c.

在其他實施例中,類似於圖9C及圖10C中的虛設金屬插塞50,第一虛設金屬插塞50a及第一虛設金屬圖案80a可同時 形成。類似地,第二虛設金屬插塞50b及第二虛設金屬圖案80b可同時形成。 In other embodiments, similar to the dummy metal plug 50 in FIG. 9C and FIG. 10C, the first dummy metal plug 50a and the first dummy metal pattern 80a can simultaneously form. Similarly, the second dummy metal plug 50b and the second dummy metal pattern 80b may be simultaneously formed.

圖17A說明電熔絲結構之第六實施例,且圖17B說明沿著圖17A中之截面線I-I'及II-II'獲得的視圖。參看圖17A及圖17B,電熔絲結構可包含在下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。金屬層20可形成陰極20c、陽極20a及連接陰極20c與陽極20a的熔絲鏈20f,以及安置於熔絲鏈20f之各別側處的虛設熔絲鏈20d。虛設熔絲鏈20d可具有(例如)與熔絲鏈20f實質上相同的線寬度,且可平行於熔絲鏈20f延伸。虛設熔絲鏈20d可與陽極20a、陰極20c及熔絲鏈20c隔開。 Fig. 17A illustrates a sixth embodiment of the electric fuse structure, and Fig. 17B illustrates a view taken along section lines I-I' and II-II' in Fig. 17A. Referring to Figures 17A and 17B, the electrical fuse structure can include a metal layer 20 on the underlying layer 10, a capping dielectric 30 overlying the top surface of the metal layer 20, and interlayer dielectric on the cap dielectric 30. Layer 40. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a, and a dummy fuse link 20d disposed at each side of the fuse link 20f. The dummy fuse link 20d may have, for example, substantially the same line width as the fuse link 20f, and may extend parallel to the fuse link 20f. The dummy fuse link 20d is separable from the anode 20a, the cathode 20c, and the fuse link 20c.

電熔絲結構可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50,及在虛設金屬插塞50上的虛設金屬圖案80。虛設金屬圖案80之寬度可小於與虛設金屬圖案80相鄰之一對虛設熔絲鏈20d之間的間隔D。類似於圖9C及圖10C中的虛設金屬插塞50,虛設金屬插塞50及虛設金屬圖案80可同時形成。舉例而言,障壁金屬層81可不形成於虛設金屬插塞50之金屬層53與虛設金屬圖案80的金屬層83之間。 The electrical fuse structure can include a dummy metal plug 50 that is in contact with a portion of the fuse link 20f, and a dummy metal pattern 80 on the dummy metal plug 50. The width of the dummy metal pattern 80 may be smaller than the interval D between one of the adjacent dummy fuse chains 20d adjacent to the dummy metal pattern 80. Similar to the dummy metal plug 50 in FIGS. 9C and 10C, the dummy metal plug 50 and the dummy metal pattern 80 can be simultaneously formed. For example, the barrier metal layer 81 may not be formed between the metal layer 53 of the dummy metal plug 50 and the metal layer 83 of the dummy metal pattern 80.

圖18A說明電熔絲結構之第七實施例,且圖18B說明沿著圖18A之線I-I'及II-II'獲得的截面圖。電熔絲結構之第七實施例包含形成於下伏層10中之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。金屬層20可由(例如)第一金屬材料形成,且可構成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。 Fig. 18A illustrates a seventh embodiment of the electric fuse structure, and Fig. 18B illustrates a cross-sectional view taken along lines I-I' and II-II' of Fig. 18A. A seventh embodiment of an electrical fuse structure includes a metal layer 20 formed in the underlying layer 10, a cap dielectric 30 overlying the top surface of the metal layer 20, and an interlayer insulating layer over the cap dielectric 30 40. The metal layer 20 may be formed of, for example, a first metal material, and may constitute a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a.

另外,電熔絲結構可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50,及在虛設金屬插塞50上的虛設金屬圖案80。虛設金屬插塞50可沿著實質上垂直於熔絲鏈20f之縱向軸線的方向延伸。如上文所描述,虛設金屬插塞50可包含障壁金屬層51及金屬層53。障壁金屬層51可由不同於第一金屬材料的第二金屬材料形成,且金屬層53可由不同於第二金屬材料的第三金屬材料形成。 Additionally, the electrical fuse structure can include a dummy metal plug 50 that is in contact with a portion of the fuse link 20f, and a dummy metal pattern 80 on the dummy metal plug 50. The dummy metal plug 50 can extend in a direction substantially perpendicular to the longitudinal axis of the fuse link 20f. As described above, the dummy metal plug 50 may include the barrier metal layer 51 and the metal layer 53. The barrier metal layer 51 may be formed of a second metal material different from the first metal material, and the metal layer 53 may be formed of a third metal material different from the second metal material.

另外,第一接觸插塞60a及第一導電圖案90a可連接至陽極20a。第二接觸插塞60b及第二導電圖案90b可連接至陰極20c。在本實施例中,第一接觸插塞60a及第二接觸插塞60b可平行於虛設金屬插塞50延伸。 In addition, the first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20c. In the present embodiment, the first contact plug 60a and the second contact plug 60b may extend parallel to the dummy metal plug 50.

另外,在本實施例中,第一導電圖案90a及第二導電圖案90b可藉由以下操作而形成:在具備第一接觸插塞60a及第二接觸插塞60b以及虛設金屬插塞50的第一層間絕緣層40上形成第二層間絕緣層70,在第二層間絕緣層70中形成通孔71及溝槽73,以及在通孔71及溝槽73中依序形成第二障壁金屬層及第二金屬層。虛設金屬插塞50之頂部表面可(例如)藉由第二層間絕緣層70覆蓋。 In addition, in the present embodiment, the first conductive pattern 90a and the second conductive pattern 90b can be formed by the following operations: the first contact plug 60a and the second contact plug 60b and the dummy metal plug 50 are provided. A second interlayer insulating layer 70 is formed on the interlayer insulating layer 40, a via hole 71 and a trench 73 are formed in the second interlayer insulating layer 70, and a second barrier metal layer is sequentially formed in the via 71 and the trench 73. And a second metal layer. The top surface of the dummy metal plug 50 can be covered, for example, by a second interlayer insulating layer 70.

圖19說明電熔絲結構之第七實施例的修改。參看圖19,電熔絲結構可包含在下伏層10上之金屬層20、覆蓋金屬層20之頂部表面的罩蓋介電質30,及在罩蓋介電質30上的層間絕緣層40。金屬層20可由(例如)第一金屬材料形成,且可構成陰極20c、陽極20a,及連接陰極20c與陽極20a的熔絲鏈20f。陽極20a及陰極20c的寬度可大於熔絲鏈20f之寬度。電熔絲結構亦 可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50,及在虛設金屬插塞50上的虛設金屬圖案80。 Figure 19 illustrates a modification of the seventh embodiment of the electrical fuse structure. Referring to FIG. 19, the electrical fuse structure can include a metal layer 20 on the underlying layer 10, a cap dielectric 30 overlying the top surface of the metal layer 20, and an interlayer insulating layer 40 over the cap dielectric 30. The metal layer 20 may be formed of, for example, a first metal material, and may constitute a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20a. The width of the anode 20a and the cathode 20c may be greater than the width of the fuse link 20f. Electric fuse structure A dummy metal plug 50 that is in contact with a portion of the fuse link 20f, and a dummy metal pattern 80 on the dummy metal plug 50 may be included.

在本實施例中,多個第一接觸插塞60a可連接至陽極20a。第一導電圖案90a可共同地連接至多個第一接觸插塞60a。類似地,多個第二接觸插塞60b可連接至陰極20c,且第二導電圖案90b可共同連接至多個第二接觸插塞60b。 In the present embodiment, a plurality of first contact plugs 60a may be connected to the anode 20a. The first conductive patterns 90a may be commonly connected to the plurality of first contact plugs 60a. Similarly, a plurality of second contact plugs 60b can be connected to the cathode 20c, and the second conductive patterns 90b can be commonly connected to the plurality of second contact plugs 60b.

圖20A、圖20B、圖21A及圖21B說明電熔絲結構之第七實施例的額外修改。參看圖20A、圖20B、圖21A及圖21B,此電熔絲結構可包含陽極20a、陰極20c,及連接陰極20c與陽極20a的熔絲鏈20f。陽極20a、陰極20c及熔絲鏈20f可具有實質上相同的均一線寬度。 20A, 20B, 21A and 21B illustrate additional modifications of the seventh embodiment of the electrical fuse structure. Referring to Figures 20A, 20B, 21A and 21B, the electrical fuse structure may include an anode 20a, a cathode 20c, and a fuse link 20f connecting the cathode 20c and the anode 20a. The anode 20a, the cathode 20c, and the fuse link 20f may have substantially the same uniform line width.

另外,電熔絲結構可包含與熔絲鏈20f之一部分接觸的虛設金屬插塞50。虛設金屬插塞50可沿著實質上垂直於熔絲鏈20f之縱向軸線的方向延伸。虛設金屬插塞50可包含障壁金屬層51及金屬層53。障壁金屬層51可由不同於第一金屬材料的第二金屬材料形成,且金屬層53可由不同於第二金屬材料的第三金屬材料形成。 Additionally, the electrical fuse structure can include a dummy metal plug 50 that is in contact with a portion of the fuse link 20f. The dummy metal plug 50 can extend in a direction substantially perpendicular to the longitudinal axis of the fuse link 20f. The dummy metal plug 50 may include a barrier metal layer 51 and a metal layer 53. The barrier metal layer 51 may be formed of a second metal material different from the first metal material, and the metal layer 53 may be formed of a third metal material different from the second metal material.

根據圖20A及圖20B中的實施例,多個第一接觸插塞60a可連接至陽極20a之頂部表面,且多個第二接觸插塞60b可連接至陰極20c的頂部表面。第一接觸插塞60a及第二接觸插塞60b中的每一者可具有(例如)桿形狀,從而具有垂直於熔絲鏈20f之軸線的縱向軸線。第一接觸插塞60a及第二接觸插塞60b可由與虛設金屬插塞50相同的材料形成。 According to the embodiment of Figures 20A and 20B, a plurality of first contact plugs 60a can be coupled to the top surface of the anode 20a, and a plurality of second contact plugs 60b can be coupled to the top surface of the cathode 20c. Each of the first contact plug 60a and the second contact plug 60b can have, for example, a rod shape to have a longitudinal axis that is perpendicular to the axis of the fuse link 20f. The first contact plug 60a and the second contact plug 60b may be formed of the same material as the dummy metal plug 50.

第一導電圖案90a可共同地連接至第一接觸插塞60a。 第二導電圖案90b可共同地連接至第二接觸插塞60b。第一導電圖案90a可藉由以下操作形成:在第二層間絕緣層70中形成多個通孔71及連接至通孔71的溝槽73,及接著在通孔71及溝槽73中依序形成障壁金屬層及金屬層。通孔71可形成於各別第一接觸插塞60a上,且可(例如)在彼此交叉之第一方向及第二方向上彼此隔開。第二導電圖案90b可以與第一導電圖案90a相同的方式形成。 The first conductive patterns 90a may be commonly connected to the first contact plugs 60a. The second conductive patterns 90b may be commonly connected to the second contact plugs 60b. The first conductive pattern 90a can be formed by forming a plurality of vias 71 and trenches 73 connected to the vias 71 in the second interlayer insulating layer 70, and then sequentially in the vias 71 and the trenches 73. A barrier metal layer and a metal layer are formed. The through holes 71 may be formed on the respective first contact plugs 60a and may be spaced apart from each other, for example, in a first direction and a second direction that intersect each other. The second conductive pattern 90b may be formed in the same manner as the first conductive pattern 90a.

根據圖21A及圖21B中的實施例,多個第一接觸插塞60a可連接至陽極20a,且多個第二接觸插塞60b可連接至陰極20c。第一導電圖案90a可共同地連接至多個第一接觸插塞60a。第二導電圖案90b可共同地連接至多個第二接觸插塞60b。在本實施例中,第一接觸插塞60a及第二接觸插塞60b可實質上平行於虛設金屬插塞50。舉例而言,第一接觸插塞60a及第二接觸插塞60b可沿著實質上垂直於熔絲鏈20f之縱向軸線的方向延伸。 According to the embodiment of Figures 21A and 21B, a plurality of first contact plugs 60a can be coupled to the anode 20a, and a plurality of second contact plugs 60b can be coupled to the cathode 20c. The first conductive patterns 90a may be commonly connected to the plurality of first contact plugs 60a. The second conductive patterns 90b may be commonly connected to the plurality of second contact plugs 60b. In the present embodiment, the first contact plug 60a and the second contact plug 60b may be substantially parallel to the dummy metal plug 50. For example, the first contact plug 60a and the second contact plug 60b can extend in a direction substantially perpendicular to the longitudinal axis of the fuse link 20f.

第一導電圖案90a及第二導電圖案90b可藉由以下操作形成:在第二層間絕緣層70中形成多個通孔71及連接至通孔71的溝槽73,及接著在通孔71及溝槽73中依序形成障壁金屬層及金屬層。第一導電圖案90a之通孔71可經形成以暴露相鄰於彼此的第一接觸插塞60a。第二導電圖案90b之通孔71可經形成以暴露相鄰於彼此的第二接觸插塞60b。 The first conductive pattern 90a and the second conductive pattern 90b can be formed by forming a plurality of vias 71 and trenches 73 connected to the vias 71 in the second interlayer insulating layer 70, and then in the vias 71 and A barrier metal layer and a metal layer are sequentially formed in the trench 73. The through holes 71 of the first conductive patterns 90a may be formed to expose the first contact plugs 60a adjacent to each other. The through holes 71 of the second conductive patterns 90b may be formed to expose the second contact plugs 60b adjacent to each other.

圖22及圖23說明電熔絲結構的第八實施例,所述電熔絲結構包含陽極圖案110a、陰極圖案110b、熔絲鏈130、連接陽極圖案110a與熔絲鏈130的第一接觸插塞125a、連接陰極圖案110b與熔絲鏈130的第二接觸插塞125b,及與熔絲鏈130之一部 分接觸的虛設金屬插塞150。在此實施例中,熔絲鏈130可與陽極圖案110a及陰極圖案110b處於不同的層面。 22 and FIG. 23 illustrate an eighth embodiment of an electrical fuse structure including an anode pattern 110a, a cathode pattern 110b, a fuse link 130, and a first contact plug connecting the anode pattern 110a and the fuse link 130. a plug 125a, a second contact plug 125b connecting the cathode pattern 110b and the fuse link 130, and a portion of the fuse link 130 A dummy metal plug 150 that is contacted. In this embodiment, the fuse link 130 may be at a different level than the anode pattern 110a and the cathode pattern 110b.

陽極圖案110a及陰極圖案110b可(例如)藉由鑲嵌製程形成於下伏層100中,且可彼此隔開。第一接觸插塞125a可通過第一層間絕緣層120連接至陽極圖案110a。第二接觸插塞125b可通過第一層間絕緣層120連接至陰極圖案110b。 The anode pattern 110a and the cathode pattern 110b may be formed in the underlying layer 100, for example, by a damascene process, and may be spaced apart from each other. The first contact plug 125a may be connected to the anode pattern 110a through the first interlayer insulating layer 120. The second contact plug 125b may be connected to the cathode pattern 110b through the first interlayer insulating layer 120.

熔絲鏈130可藉由圖案化由第一金屬材料製成的金屬層而形成,且可提供於第一層間絕緣層120上。熔絲鏈130可連接至第一接觸插塞125a及第二接觸插塞125b。第二層間絕緣層140可在具備熔絲鏈130的第一層間絕緣層120上。罩蓋介電質135可插入於第二層間絕緣層140與熔絲鏈130之間。 The fuse link 130 may be formed by patterning a metal layer made of a first metal material, and may be provided on the first interlayer insulating layer 120. The fuse link 130 can be connected to the first contact plug 125a and the second contact plug 125b. The second interlayer insulating layer 140 may be on the first interlayer insulating layer 120 having the fuse link 130. The cap dielectric 135 can be interposed between the second interlayer insulating layer 140 and the fuse link 130.

虛設金屬插塞150可穿透第二層間絕緣層140及罩蓋介電質135,且可接觸熔絲鏈130的一部分。虛設金屬插塞150可包含障壁金屬層151及金屬層153。障壁金屬層151可由不同於構成熔絲鏈130之第一金屬材料的第二金屬材料形成。金屬層130可由不同於第二金屬材料的第三金屬材料形成。 The dummy metal plug 150 may penetrate the second interlayer insulating layer 140 and the cap dielectric 135 and may contact a portion of the fuse link 130. The dummy metal plug 150 may include a barrier metal layer 151 and a metal layer 153. The barrier metal layer 151 may be formed of a second metal material different from the first metal material constituting the fuse link 130. The metal layer 130 may be formed of a third metal material different from the second metal material.

參看圖23,陽極圖案110可提供於下伏層100上,熔絲鏈130可提供於相對於下伏層100的第一層面處,且陰極圖案160可提供於相對於下伏層100的第二層面處。第二層面可高於第一層面。 Referring to FIG. 23, an anode pattern 110 may be provided on the underlying layer 100, a fuse link 130 may be provided at a first level relative to the underlying layer 100, and a cathode pattern 160 may be provided in relation to the underlying layer 100. At the second level. The second level can be higher than the first level.

舉例而言,第一層間絕緣層120可在具備陽極圖案110之下伏層100上。第一接觸插塞125可通過第一層間絕緣層120連接至陽極圖案110。熔絲鏈130可提供於第一接觸插塞125上。熔絲鏈130可由第一金屬材料形成。第一接觸插塞125可連接至 熔絲鏈130的末端部分。熔絲鏈130可(例如)藉由鑲嵌製程形成於第一層間絕緣層120中。 For example, the first interlayer insulating layer 120 may be provided on the underlying layer 100 of the anode pattern 110. The first contact plug 125 may be connected to the anode pattern 110 through the first interlayer insulating layer 120. A fuse link 130 can be provided on the first contact plug 125. The fuse link 130 may be formed of a first metal material. The first contact plug 125 can be connected to The end portion of the fuse link 130. The fuse link 130 can be formed in the first interlayer insulating layer 120, for example, by a damascene process.

罩蓋介電質135及第二層間絕緣層140可依序形成於熔絲鏈130上。第二接觸插塞155可連接至熔絲鏈130的另一末端部分。虛設金屬插塞150可提供於第二層間絕緣層140的一部分中,虛設金屬插塞150與第二接觸插塞155隔開。虛設金屬插塞150可與第二接觸插塞155同時形成。虛設金屬插塞150及第二接觸插塞155中的每一者可包含障壁金屬層151及金屬層153。 The cap dielectric 135 and the second interlayer insulating layer 140 may be sequentially formed on the fuse link 130. The second contact plug 155 can be connected to the other end portion of the fuse link 130. A dummy metal plug 150 may be provided in a portion of the second interlayer insulating layer 140, and the dummy metal plug 150 is spaced apart from the second contact plug 155. The dummy metal plug 150 may be formed simultaneously with the second contact plug 155. Each of the dummy metal plug 150 and the second contact plug 155 may include a barrier metal layer 151 and a metal layer 153.

障壁金屬層151可由不同於第一金屬材料的第二金屬材料形成。金屬層153可由不同於第二金屬材料的第三金屬材料形成。此外,陰極圖案160可提供於第二層間絕緣層140中,且可連接至第二接觸插塞155。虛設金屬插塞150可包含接觸部分及互連部分。 The barrier metal layer 151 may be formed of a second metal material different from the first metal material. The metal layer 153 may be formed of a third metal material different from the second metal material. Further, the cathode pattern 160 may be provided in the second interlayer insulating layer 140 and may be connected to the second contact plug 155. The dummy metal plug 150 may include a contact portion and an interconnection portion.

圖24A及圖24B說明具有三維結構之電熔絲結構的第九實施例。電熔絲結構可包含陰極圖案210、熔絲鏈220及陽極圖案230。陰極圖案210可在下伏層200上,熔絲鏈220可處於相對於下伏層200之頂部表面的第一層面,且陽極圖案230可提供於相對於下伏層200之頂部表面的第二層面。第二層面可高於第一層面。此外,虛設熔絲鏈220d可提供於與熔絲鏈220相同的層面。 24A and 24B illustrate a ninth embodiment of an electric fuse structure having a three-dimensional structure. The electrical fuse structure can include a cathode pattern 210, a fuse link 220, and an anode pattern 230. The cathode pattern 210 can be on the underlying layer 200, the fuse link 220 can be in a first level relative to the top surface of the underlying layer 200, and the anode pattern 230 can be provided on a second level relative to the top surface of the underlying layer 200. . The second level can be higher than the first level. Further, the dummy fuse link 220d may be provided on the same level as the fuse link 220.

在此實施例中,為了在程式化操作期間有效地收集熱,陰極圖案210可包含在第一(例如,x軸)方向上延伸的第一部分210a,及在第二(例如,y軸)方向上延伸的第二部分210b。第一接觸插塞215可將陰極圖案210連接至熔絲鏈220。 In this embodiment, to efficiently collect heat during the stylization operation, the cathode pattern 210 can include a first portion 210a that extends in a first (eg, x-axis) direction, and a second (eg, y-axis) direction. The second portion 210b extends upward. The first contact plug 215 can connect the cathode pattern 210 to the fuse link 220.

類似於陰極圖案210,陽極圖案230可包含沿著第一(例 如,x軸)方向延伸的第一部分230a,及沿著第二(例如,y軸)方向延伸的第二部分230b。第二接觸插塞225可將熔絲鏈220連接至陽極圖案230。自平面圖看出,第一接觸插塞215及第二接觸插塞225可不彼此重疊。 Similar to the cathode pattern 210, the anode pattern 230 can be included along the first (eg, For example, the first portion 230a extending in the x-axis direction and the second portion 230b extending in the second (eg, y-axis) direction. The second contact plug 225 can connect the fuse link 220 to the anode pattern 230. As seen from the plan view, the first contact plug 215 and the second contact plug 225 may not overlap each other.

陰極圖案210、熔絲鏈220及陽極圖案230可由第一金屬材料形成,所述第一金屬材料包含(例如)鎢(W)、鋁(Al)、銅(Cu)或銅合金中的至少一者。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 The cathode pattern 210, the fuse link 220, and the anode pattern 230 may be formed of a first metal material including, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. By. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

電熔絲結構可包含虛設金屬插塞235及虛設金屬圖案240。虛設金屬插塞235可接觸陽極圖案230的一部分。根據圖24A中的實施例,虛設金屬插塞235可連接至陽極圖案230的第一部分230a,且自平面圖看來,可鄰近於第二接觸插塞225而安置。相比之下,在圖24B中,自平面圖之觀點,虛設金屬插塞235可與第二接觸插塞225隔開。 The electrical fuse structure can include a dummy metal plug 235 and a dummy metal pattern 240. The dummy metal plug 235 may contact a portion of the anode pattern 230. According to the embodiment of FIG. 24A, the dummy metal plug 235 can be coupled to the first portion 230a of the anode pattern 230 and can be disposed adjacent to the second contact plug 225 from a plan view. In contrast, in FIG. 24B, the dummy metal plug 235 can be spaced apart from the second contact plug 225 from the viewpoint of the plan view.

虛設金屬插塞235可包含障壁金屬層及金屬層。障壁金屬層可由不同於陽極圖案230之第一金屬材料的第二金屬材料形成。金屬層可由不同於障壁金屬層的第三金屬材料形成。第二金屬材料可具有低於第一金屬材料之電導率的電導率。此外,虛設金屬圖案240可連接至虛設金屬插塞235的頂部表面。 The dummy metal plug 235 may include a barrier metal layer and a metal layer. The barrier metal layer may be formed of a second metal material different from the first metal material of the anode pattern 230. The metal layer may be formed of a third metal material different from the barrier metal layer. The second metallic material can have a conductivity that is lower than the electrical conductivity of the first metallic material. Further, the dummy metal pattern 240 may be connected to the top surface of the dummy metal plug 235.

使用圖24A及圖24B中之三維電熔絲結構使得有可能在程式化程序期間更有效地收集熱,藉此改良程式化程序的效能。在程式化程序期間,負電壓可施加至陰極圖案210,正電壓可施加至陽極圖案230,且虛設金屬插塞235及虛設金屬圖案240可處於 電浮動狀態。 The use of the three-dimensional electrical fuse structure of Figures 24A and 24B makes it possible to collect heat more efficiently during the stylization procedure, thereby improving the performance of the stylized program. During the stylization process, a negative voltage can be applied to the cathode pattern 210, a positive voltage can be applied to the anode pattern 230, and the dummy metal plug 235 and the dummy metal pattern 240 can be in Electrically floating state.

陰極圖案210與陽極圖案230之間的電壓差產生程式化電流。結果,電子自陰極圖案210通過熔絲鏈220朝向陽極圖案230流動。電流可改變虛設金屬插塞235下方的陽極圖案230處的電及熱驅動力。因此,空隙可形成於相鄰於虛設金屬插塞235的陽極圖案230的一部分處。 The voltage difference between the cathode pattern 210 and the anode pattern 230 produces a stylized current. As a result, electrons flow from the cathode pattern 210 toward the anode pattern 230 through the fuse link 220. The current can change the electrical and thermal driving forces at the anode pattern 230 beneath the dummy metal plug 235. Therefore, a void may be formed at a portion of the anode pattern 230 adjacent to the dummy metal plug 235.

圖25A至圖25C說明半導體元件的實施例,所述半導體元件中之每一者包含根據前述實施例中之任一者的至少一電熔絲結構。參看圖25A至圖25C,半導體基板300包含記憶胞區A及熔絲區B。MOS電晶體形成於半導體基板300的記憶胞區A上,且電熔絲結構形成於半導體基板300的熔絲區B上。 25A-25C illustrate an embodiment of a semiconductor component, each of which includes at least one electrical fuse structure in accordance with any of the preceding embodiments. Referring to FIGS. 25A to 25C, the semiconductor substrate 300 includes a memory cell region A and a fuse region B. The MOS transistor is formed on the memory cell region A of the semiconductor substrate 300, and the electric fuse structure is formed on the fuse region B of the semiconductor substrate 300.

元件隔離層301可形成於半導體基板300上以定義主動區,且閘電極310g可經形成以跨過主動區。雜質區可形成於半導體基板300的在閘電極310g的各別側處的部分中。第一層間絕緣層320可在具備MOS電晶體及電熔絲結構之半導體基板300上。胞接觸插塞321可經由第一層間絕緣層310電連接至MOS電晶體。 The element isolation layer 301 may be formed on the semiconductor substrate 300 to define an active region, and the gate electrode 310g may be formed to cross the active region. The impurity regions may be formed in portions of the semiconductor substrate 300 at respective sides of the gate electrode 310g. The first interlayer insulating layer 320 may be on the semiconductor substrate 300 having the MOS transistor and the electric fuse structure. The cell contact plug 321 may be electrically connected to the MOS transistor via the first interlayer insulating layer 310.

第一互連線325可提供於記憶胞區A之第一層間絕緣層320上。第一互連線325中的每一者可電連接至胞接觸插塞321中的至少一者。第二層間絕緣層330可安置於第一層間絕緣層上。第二互連線335可安置於第二層間絕緣層330中。第二互連線335可具有大於第一互連線325之線寬度的線寬度。 The first interconnect 325 may be provided on the first interlayer insulating layer 320 of the memory cell region A. Each of the first interconnects 325 can be electrically connected to at least one of the cell contact plugs 321 . The second interlayer insulating layer 330 may be disposed on the first interlayer insulating layer. The second interconnect 335 may be disposed in the second interlayer insulating layer 330. The second interconnect 335 may have a line width greater than a line width of the first interconnect 325.

此外,第三層間絕緣層340可提供於第二層間絕緣層330上。第三互連線345可安置於第三層間絕緣層340中。第三互連線345可具有大於第二互連線335之線寬度的線寬度。 Further, a third interlayer insulating layer 340 may be provided on the second interlayer insulating layer 330. The third interconnect line 345 may be disposed in the third interlayer insulating layer 340. The third interconnect 345 may have a line width greater than a line width of the second interconnect 335.

根據圖25A中的實施例,熔絲鏈310f可形成於熔絲區B的元件隔離層301上,且熔絲鏈310f之頂部表面可藉由罩蓋介電質315覆蓋。熔絲鏈310f可與記憶胞區A之閘電極310g同時形成,且可由第一金屬材料形成。第一金屬材料可由以下各者中的至少一者形成:鎢(W)、鋁(Al)、銅(Cu)或銅合金。銅合金之實例包含銅基材料,在所述銅基材料中以小量或預定量含有C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr中的至少一者。 According to the embodiment of FIG. 25A, the fuse link 310f may be formed on the element isolation layer 301 of the fuse region B, and the top surface of the fuse link 310f may be covered by the cap dielectric 315. The fuse link 310f may be formed simultaneously with the gate electrode 310g of the memory cell region A, and may be formed of a first metal material. The first metal material may be formed of at least one of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of the copper alloy include a copper-based material in which C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt are contained in a small amount or a predetermined amount. At least one of Mg, Al or Zr.

在熔絲區B中,第一接觸插塞321a及第二接觸插塞321b以及虛設金屬插塞321d可經由第一層間絕緣層320連接至熔絲鏈310f。虛設金屬插塞321d可包含障壁金屬層及金屬層。障壁金屬層可由不同於第一金屬材料的第二金屬材料形成。金屬層可由第三金屬材料形成。虛設金屬插塞321d可與記憶胞區A的接觸插塞321同時形成。 In the fuse region B, the first contact plug 321a and the second contact plug 321b and the dummy metal plug 321d may be connected to the fuse link 310f via the first interlayer insulating layer 320. The dummy metal plug 321d may include a barrier metal layer and a metal layer. The barrier metal layer may be formed of a second metal material different from the first metal material. The metal layer may be formed of a third metal material. The dummy metal plug 321d can be formed simultaneously with the contact plug 321 of the memory cell area A.

第一導電圖案325a及第二導電圖案325b以及虛設金屬圖案325d可提供於熔絲區B的第一層間絕緣層320上。第一導電圖案325a可電連接至第一接觸插塞321a,且第二導電圖案325b可電連接至第二接觸插塞321b。虛設金屬圖案325d可接觸虛設金屬插塞321d的頂部表面。第一導電圖案325a及第二導電圖案325b以及虛設金屬圖案325d可與記憶胞區A的第一互連線325同時形成。 The first conductive pattern 325a and the second conductive pattern 325b and the dummy metal pattern 325d may be provided on the first interlayer insulating layer 320 of the fuse region B. The first conductive pattern 325a may be electrically connected to the first contact plug 321a, and the second conductive pattern 325b may be electrically connected to the second contact plug 321b. The dummy metal pattern 325d may contact the top surface of the dummy metal plug 321d. The first conductive pattern 325a and the second conductive pattern 325b and the dummy metal pattern 325d may be formed simultaneously with the first interconnect line 325 of the memory cell region A.

根據圖25B中的實施例,熔絲區B的電熔絲結構可與記憶胞區A的第一互連線325同時形成。電熔絲結構之熔絲鏈325f可形成於第一層間絕緣層320上,且與半導體基板300的頂部表 面隔開。第一互連線325及熔絲鏈325f可由第一金屬材料形成,且熔絲鏈325f的頂部表面可由罩蓋介電質327覆蓋。 According to the embodiment of FIG. 25B, the electrical fuse structure of the fuse region B can be formed simultaneously with the first interconnect 325 of the memory cell region A. The fuse link 325f of the electric fuse structure may be formed on the first interlayer insulating layer 320, and the top table of the semiconductor substrate 300 Separated by faces. The first interconnect 325 and the fuse link 325f may be formed of a first metal material, and a top surface of the fuse link 325f may be covered by a cap dielectric 327.

在熔絲區B中,第一接觸插塞331a及第二接觸插塞331b以及虛設金屬插塞331d可經由第二層間絕緣層330及罩蓋介電質327連接至熔絲鏈310f。虛設金屬插塞331d可包含障壁金屬層及金屬層。障壁金屬層由不同於第一金屬材料的第二金屬材料形成。金屬層由第三金屬材料形成。 In the fuse region B, the first contact plug 331a and the second contact plug 331b and the dummy metal plug 331d may be connected to the fuse link 310f via the second interlayer insulating layer 330 and the cap dielectric 327. The dummy metal plug 331d may include a barrier metal layer and a metal layer. The barrier metal layer is formed of a second metal material different from the first metal material. The metal layer is formed of a third metal material.

第一導電圖案335a及第二導電圖案335b以及虛設金屬圖案335d可提供於熔絲區B的第二層間絕緣層330上。第一導電圖案335a可電連接至第一接觸插塞331a,且第二導電圖案335b可電連接至第二接觸插塞331b。 The first conductive pattern 335a and the second conductive pattern 335b and the dummy metal pattern 335d may be provided on the second interlayer insulating layer 330 of the fuse region B. The first conductive pattern 335a may be electrically connected to the first contact plug 331a, and the second conductive pattern 335b may be electrically connected to the second contact plug 331b.

根據圖25C中的實施例,熔絲區B的電熔絲結構可與記憶胞區A的第三互連線345同時形成。電熔絲結構可包含與半導體基板300之頂部表面隔開的熔絲鏈345f。第三互連線345及熔絲鏈345f可由第一金屬材料形成,且熔絲鏈345f的頂部表面可由罩蓋介電質347覆蓋。 According to the embodiment of FIG. 25C, the electrical fuse structure of the fuse region B can be formed simultaneously with the third interconnect line 345 of the memory cell region A. The electrical fuse structure can include a fuse link 345f spaced from the top surface of the semiconductor substrate 300. The third interconnect 345 and the fuse link 345f may be formed of a first metal material, and a top surface of the fuse link 345f may be covered by a cap dielectric 347.

在熔絲區B中,第一接觸插塞351a及第二接觸插塞351b以及虛設金屬插塞351d可經由第三層間絕緣層340及罩蓋介電質347連接至熔絲鏈345f。虛設金屬插塞351d可包含以下兩者:障壁金屬層,其由不同於第一金屬材料之第二金屬材料形成;及金屬層,其由第三金屬材料形成。 In the fuse region B, the first contact plug 351a and the second contact plug 351b and the dummy metal plug 351d may be connected to the fuse link 345f via the third interlayer insulating layer 340 and the cap dielectric 347. The dummy metal plug 351d may include both: a barrier metal layer formed of a second metal material different from the first metal material; and a metal layer formed of a third metal material.

第一導電圖案353a及第二導電圖案353b以及虛設金屬圖案353d可提供於熔絲區B的第三層間絕緣層340上。第一導電圖案353a可電連接至第一接觸插塞351a,且第二導電圖案353b 可電連接至第二接觸插塞351b。 The first conductive pattern 353a and the second conductive pattern 353b and the dummy metal pattern 353d may be provided on the third interlayer insulating layer 340 of the fuse region B. The first conductive pattern 353a may be electrically connected to the first contact plug 351a, and the second conductive pattern 353b It can be electrically connected to the second contact plug 351b.

圖26說明包含根據前述實施例中之任一者之半導體元件的記憶體系統1100的實施例。參看圖26,記憶體系統1100可應用至(例如)PDA(個人數位助理)、攜帶型電腦、網頁平板電腦、無線電話、行動電話、數位音樂播放器、記憶卡及/或可在無線通信環境中傳輸及/或接收資料的所有元件。 FIG. 26 illustrates an embodiment of a memory system 1100 incorporating a semiconductor component in accordance with any of the preceding embodiments. Referring to Figure 26, the memory system 1100 can be applied to, for example, a PDA (Personal Digital Assistant), a portable computer, a web tablet, a wireless telephone, a mobile phone, a digital music player, a memory card, and/or can be in a wireless communication environment. All components that transmit and/or receive data.

記憶體系統1100包含控制器1110、輸入/輸出元件1120(例如,小鍵盤及/或顯示元件)、記憶體1130、介面1140及匯流排1150。記憶體1130及介面1140可經由匯流排1150彼此通信。 The memory system 1100 includes a controller 1110, input/output components 1120 (eg, keypads and/or display elements), memory 1130, interface 1140, and busbars 1150. The memory 1130 and the interface 1140 can communicate with each other via the bus bar 1150.

控制器1110可包含微處理器、數位信號處理器、微控制器及/或類似於微處理器、數位信號處理器及微控制器的其他處理元件。記憶體1130可用以儲存由控制器1110執行的指令。輸入/輸出元件1120可自系統外部1100接收資料及/或信號,及/或傳輸資料及/或信號到系統1100外部。舉例而言,輸入/輸出元件1120可包含鍵盤、小鍵盤及/或顯示器。 Controller 1110 can include a microprocessor, a digital signal processor, a microcontroller, and/or other processing elements similar to microprocessors, digital signal processors, and microcontrollers. Memory 1130 can be used to store instructions that are executed by controller 1110. Input/output component 1120 can receive data and/or signals from system external 1100 and/or transmit data and/or signals external to system 1100. For example, input/output component 1120 can include a keyboard, a keypad, and/or a display.

記憶體1130可包含根據前述實施例中之任一者的半導體元件。記憶體1130可更包含不同種類之記憶體,例如,諸如隨機存取記憶體的揮發性記憶體元件,及/或其他種類的記憶體。介面1140可將資料傳輸至通信網路及/或可自通信網路接收資料。 The memory 1130 may comprise a semiconductor component according to any of the preceding embodiments. The memory 1130 may further comprise different kinds of memory, such as volatile memory elements such as random access memory, and/or other kinds of memory. The interface 1140 can transmit data to and/or receive data from the communication network.

圖27說明包含根據前述實施例中之任一者之半導體元件的記憶卡1200的實施例。參看圖27,記憶卡1200可具有大型或其他預定容量儲存能力,且可包含根據前述實施例中之任一者的半導體記憶體元件1210。記憶卡1200可包含可控制主機與半導體記憶體元件1210之間的資料交換之記憶體控制器1220。 Figure 27 illustrates an embodiment of a memory card 1200 incorporating a semiconductor component in accordance with any of the preceding embodiments. Referring to Figure 27, memory card 1200 can have a large or other predetermined capacity storage capability and can include semiconductor memory component 1210 in accordance with any of the preceding embodiments. The memory card 1200 can include a memory controller 1220 that can control the exchange of data between the host and the semiconductor memory component 1210.

靜態隨機存取記憶體(SRAM)1221可用作(例如)處理單元1222的操作記憶體。主機介面1223可包含可連接至記憶卡1200的主機之資料交換協定。錯誤校正區塊1224可偵測及/或校正自多位元半導體記憶體元件1210讀出的資料中之錯誤。 Static Random Access Memory (SRAM) 1221 can be used, for example, as an operational memory for processing unit 1222. The host interface 1223 can include a data exchange protocol that can be connected to a host of the memory card 1200. Error correction block 1224 can detect and/or correct errors in the material read from multi-bit semiconductor memory component 1210.

記憶體介面1225可與半導體記憶體元件1210介接。處理單元1222可執行控制操作從而交換記憶體控制器1220的資料。記憶卡1200可包含(例如)用於儲存程式碼、指令或用於與主機介接之其他資訊的ROM。 The memory interface 1225 can interface with the semiconductor memory component 1210. Processing unit 1222 can perform control operations to exchange data for memory controller 1220. Memory card 1200 can include, for example, a ROM for storing code, instructions, or other information for interfacing with a host.

圖28說明包含根據前述實施例中之任一者之半導體元件的資訊處理系統1300的實施例。參看圖28,資訊處理系統1300包含具有半導體元件之記憶體系統1310。 FIG. 28 illustrates an embodiment of an information processing system 1300 incorporating semiconductor components in accordance with any of the preceding embodiments. Referring to Figure 28, information processing system 1300 includes a memory system 1310 having semiconductor components.

記憶體系統1310可安裝至資訊處理系統,所述資訊處理系統(例如)可為行動元件及/或桌上型電腦。資訊處理系統1300可包含數據機1320、中央處理單元(CPU)1330、RAM 1340,及電連接至系統匯流排1360的使用者介面1350。記憶體系統1310可以類似於圖20之方式組態,且可包含半導體元件1311及記憶體控制器1312。 The memory system 1310 can be mounted to an information processing system, which can be, for example, a mobile device and/or a desktop computer. The information processing system 1300 can include a data machine 1320, a central processing unit (CPU) 1330, a RAM 1340, and a user interface 1350 that is electrically coupled to the system bus 1360. The memory system 1310 can be configured similarly to that of FIG. 20 and can include a semiconductor component 1311 and a memory controller 1312.

記憶體系統1310可為(例如)固態碟機SSD,且可儲存待由CPU 1330處理或已由CPU 1330處理的資料,及/或自外部源輸入的資料。資訊處理系統1300可將大量或預定量資料可靠地儲存於記憶體系統1310中。記憶體系統1310可節省用於錯誤校正的資源,且亦可提供高速度資料交換功能。在一個實施例中,資訊處理系統1300可包含應用晶片集、攝影機影像處理器(CIS),及/或輸入/輸出元件。 The memory system 1310 can be, for example, a solid state drive SSD, and can store data to be processed by the CPU 1330 or processed by the CPU 1330, and/or data input from an external source. The information processing system 1300 can reliably store a large amount or a predetermined amount of data in the memory system 1310. The memory system 1310 can save resources for error correction and can also provide high speed data exchange functions. In one embodiment, information processing system 1300 can include an application wafer set, a camera image processor (CIS), and/or input/output elements.

根據前述實施例中之一或多者,電熔絲結構包含附接至熔絲鏈的虛設金屬插塞。熔絲鏈可由第一金屬材料形成,且虛設金屬插塞可包含第二金屬材料。因此,在電熔絲結構之程式化程序期間,由電遷移引起的熔絲鏈之溫度梯度以及驅動力可經控制以增加施加至熔絲鏈的總驅動力。結果,可用減小之操作電壓程式化電熔絲結構。 In accordance with one or more of the foregoing embodiments, the electrical fuse structure includes a dummy metal plug attached to the fuse link. The fuse link may be formed of a first metal material, and the dummy metal plug may comprise a second metal material. Thus, during the stylization procedure of the electrical fuse structure, the temperature gradient of the fuse link and the driving force caused by electromigration can be controlled to increase the total driving force applied to the fuse link. As a result, the electrical fuse structure can be programmed with a reduced operating voltage.

根據前述實施例中之一或多者,可藉由調整虛設金屬插塞之體積或接觸區域及/或虛設金屬插塞的數目來控制施加至熔絲鏈之總驅動力。此外,虛設金屬插塞之位置可經調整以控制將在電熔絲結構的程式化程序中形成的空隙的位置。 According to one or more of the foregoing embodiments, the total driving force applied to the fuse link can be controlled by adjusting the volume or contact area of the dummy metal plug and/or the number of dummy metal plugs. Additionally, the location of the dummy metal plug can be adjusted to control the location of the void to be formed in the stylized program of the electrical fuse structure.

本文中已揭露實例實施例,且儘管使用特定術語,但僅以一般且描述性含義且並非為了限制目的來使用且解釋所述特定術語。在一些情況下,如對於熟習此項技術者將顯而易見,在本申請案之申請時,結合特定實施例描述之特徵、特性及/或器件可被單個使用或組合結合其他實施例描述之特徵、特性及/或器件來使用,除非另有指示。因此,熟習此項技術者將理解,可進行形式及細節之各種改變而不偏離如在以下申請專利範圍中闡述的本發明之精神及範疇。 The example embodiments are disclosed herein, and the specific terms are used and are to be construed in a In some instances, as will be apparent to those skilled in the art, the features, characteristics, and/or devices described in connection with the specific embodiments may be used individually or in combination with features described in other embodiments. Features and / or devices are used unless otherwise indicated. It will be appreciated by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

20a‧‧‧陽極 20a‧‧‧Anode

20c‧‧‧陰極 20c‧‧‧ cathode

20f‧‧‧熔絲鏈 20f‧‧‧fuse chain

50‧‧‧虛設金屬插塞 50‧‧‧Virtual metal plug

R1‧‧‧第一區 R1‧‧‧ first district

R2‧‧‧第二區 R2‧‧‧Second District

R3‧‧‧第三區 R3‧‧‧ Third District

Claims (20)

一種半導體元件之電熔絲結構,其包括:連接陰極與陽極的第一金屬材料之熔絲鏈;覆蓋所述熔絲鏈之頂部表面的罩蓋介電質;以及穿透所述罩蓋介電質並接觸所述熔絲鏈的虛設金屬插塞,所述虛設金屬插塞包含介於金屬層與所述熔絲鏈之間的障壁金屬層,其中所述障壁金屬層包含不同於所述第一金屬材料的第二金屬材料。 An electric fuse structure of a semiconductor component, comprising: a fuse link of a first metal material connecting a cathode and an anode; a cover dielectric covering a top surface of the fuse link; and penetrating the cover a dummy metal plug electrically contacting the fuse link, the dummy metal plug comprising a barrier metal layer interposed between the metal layer and the fuse link, wherein the barrier metal layer comprises a different a second metallic material of the first metallic material. 如申請專利範圍第1項所述之電熔絲結構,其中所述第一金屬材料具有大於所述第二金屬材料之電導率的電導率。 The electric fuse structure of claim 1, wherein the first metal material has a conductivity greater than a conductivity of the second metal material. 如申請專利範圍第1項所述之電熔絲結構,其中:所述第一金屬材料包含鎢、鋁、銅或銅合金中的至少一者,且所述第二金屬材料包含Ta、TaN、TaSiN、Ti、TiN、TiSiN、W、WN或其組合中的至少一者。 The electric fuse structure according to claim 1, wherein the first metal material comprises at least one of tungsten, aluminum, copper or a copper alloy, and the second metal material comprises Ta, TaN, At least one of TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof. 如申請專利範圍第1項所述之電熔絲結構,其中:所述熔絲鏈用於攜載程式化電流,且所述熔絲鏈在程式化狀態下具有介於所述陽極與所述虛設金屬插塞之間的空隙。 The electric fuse structure of claim 1, wherein: the fuse link is for carrying a stylized current, and the fuse link has a stroma between the anode and the The gap between the dummy metal plugs. 如申請專利範圍第4項所述之電熔絲結構,其中所述空隙與所述虛設金屬插塞之間的距離小於所述空隙與所述陽極之間的距離。 The electrical fuse structure of claim 4, wherein a distance between the void and the dummy metal plug is less than a distance between the void and the anode. 如申請專利範圍第1項所述之電熔絲結構,其中所述虛設金屬插塞的下部寬度小於所述熔絲鏈的上部寬度。 The electric fuse structure of claim 1, wherein a lower width of the dummy metal plug is smaller than an upper width of the fuse link. 如申請專利範圍第1項所述之電熔絲結構,其中:所述虛設金屬插塞之下部寬度大於所述熔絲鏈的上部寬度,且所述虛設金屬插塞接觸所述熔絲鏈的頂部表面及側表面。 The electric fuse structure of claim 1, wherein: a width of a lower portion of the dummy metal plug is greater than an upper width of the fuse link, and the dummy metal plug contacts the fuse link Top surface and side surface. 如申請專利範圍第1項所述之電熔絲結構,其中所述障壁金屬層覆蓋所述金屬層的底部表面及側表面。 The electric fuse structure of claim 1, wherein the barrier metal layer covers a bottom surface and a side surface of the metal layer. 如申請專利範圍第8項所述之電熔絲結構,其中在所述金屬層的所述底部表面上的所述障壁金屬層較在所述金屬層之所述側表面中之一者或兩者上的所述障壁金屬層厚。 The electric fuse structure of claim 8, wherein the barrier metal layer on the bottom surface of the metal layer is one or both of the side surfaces of the metal layer The barrier metal layer on the person is thick. 如申請專利範圍第1項所述之電熔絲結構,其中所述虛設金屬插塞的底部表面在所述熔絲鏈的頂部表面與底部表面之間。 The electric fuse structure of claim 1, wherein a bottom surface of the dummy metal plug is between a top surface and a bottom surface of the fuse link. 如申請專利範圍第1項所述之電熔絲結構,其中所述金屬層包含具有第一寬度的接觸部分,及具有大於所述第一寬度之第二寬度的互連部分。 The electrical fuse structure of claim 1, wherein the metal layer comprises a contact portion having a first width and an interconnect portion having a second width greater than the first width. 如申請專利範圍第1項所述之電熔絲結構,其更包括:在所述虛設金屬插塞之頂部表面上的虛設金屬圖案,其中所述虛設金屬圖案具有大於所述熔絲鏈之厚度的厚度。 The electrical fuse structure of claim 1, further comprising: a dummy metal pattern on a top surface of the dummy metal plug, wherein the dummy metal pattern has a thickness greater than the thickness of the fuse link thickness of. 如申請專利範圍第1項所述之電熔絲結構,其中:所述陽極及所述陰極處於不同層面,且所述熔絲鏈與所述虛設金屬插塞在所述陽極與所述陰極之間。 The electric fuse structure of claim 1, wherein: the anode and the cathode are at different levels, and the fuse link and the dummy metal plug are at the anode and the cathode between. 如申請專利範圍第1項所述之電熔絲結構,其中:所述陽極及所述陰極相對於下伏層之頂部表面處於第一層 面,所述熔絲鏈相對於所述下伏層之所述頂部表面處於第二層面,且所述第二層面高於所述第一層面。 The electric fuse structure of claim 1, wherein: the anode and the cathode are in a first layer with respect to a top surface of the underlying layer The fuse link is at a second level with respect to the top surface of the underlying layer, and the second level is higher than the first level. 一種半導體元件之電熔絲結構,其包括:連接陰極與陽極的第一金屬材料之熔絲鏈;覆蓋所述陽極、所述陰極及所述熔絲鏈的層間絕緣層;介於所述熔絲鏈之頂部表面與所述層間絕緣層之間的罩蓋介電質,所述罩蓋介電質包含不同於所述層間絕緣層的絕緣材料;以及穿透所述層間絕緣層與所述罩蓋介電質且接觸所述熔絲鏈的虛設金屬插塞,所述虛設金屬插塞包含介於金屬層與所述熔絲鏈之間的障壁金屬層,其中所述障壁金屬層包含不同於所述第一金屬材料的第二金屬材料。 An electric fuse structure of a semiconductor component, comprising: a fuse link of a first metal material connecting a cathode and an anode; an interlayer insulating layer covering the anode, the cathode and the fuse link; a cap dielectric between the top surface of the wire and the interlayer insulating layer, the cap dielectric comprising an insulating material different from the interlayer insulating layer; and penetrating the interlayer insulating layer and the a dummy metal plug covering the dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer comprises different And a second metal material of the first metal material. 如申請專利範圍第15項所述之電熔絲結構,其中所述第一金屬材料具有大於所述第二金屬材料之電導率的電導率。 The electric fuse structure of claim 15, wherein the first metal material has a conductivity greater than a conductivity of the second metal material. 一種半導體元件之電熔絲結構,其包括:連接陰極與陽極的第一金屬材料之熔絲鏈;覆蓋所述熔絲鏈之頂部表面的罩蓋介電質;以及穿透所述罩蓋介電質並接觸所述熔絲鏈的虛設金屬插塞,其中所述熔絲鏈用於攜載程式化電流,且其中所述虛設金屬插塞用於在所述熔絲鏈攜載所述程式化電流時改變所述熔絲鏈中的溫度梯度。 An electric fuse structure of a semiconductor component, comprising: a fuse link of a first metal material connecting a cathode and an anode; a cover dielectric covering a top surface of the fuse link; and penetrating the cover a dummy metal plug electrically contacting the fuse link, wherein the fuse link is for carrying a programmed current, and wherein the dummy metal plug is for carrying the program in the fuse link The temperature gradient in the fuse link is changed when the current is changed. 如申請專利範圍第17項所述之電熔絲結構,其中: 所述虛設金屬插塞包含介於金屬層與所述熔絲鏈之間的障壁金屬層,且所述障壁金屬層包含不同於所述第一金屬材料的第二金屬材料。 The electric fuse structure as described in claim 17 of the patent application, wherein: The dummy metal plug includes a barrier metal layer between the metal layer and the fuse link, and the barrier metal layer includes a second metal material different from the first metal material. 如申請專利範圍第17項所述之電熔絲結構,其中:所述熔絲鏈包含與所述虛設金屬插塞接觸的第一區,及與所述罩蓋介電質接觸的第二區,且所述熔絲鏈的溫度在所述熔絲鏈攜載所述程式化電流時在所述第二區處具有最大值。 The electric fuse structure of claim 17, wherein: the fuse link includes a first region in contact with the dummy metal plug, and a second region in contact with the dielectric of the cover And the temperature of the fuse link has a maximum at the second region when the fuse chain carries the stylized current. 如申請專利範圍第17項所述之電熔絲結構,其中所述熔絲鏈在程式化狀態下具有介於所述陽極與所述虛設金屬插塞之間的空隙。 The electric fuse structure of claim 17, wherein the fuse link has a gap between the anode and the dummy metal plug in a stylized state.
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