CN108305867B - Electric fuse structure of semiconductor device - Google Patents

Electric fuse structure of semiconductor device Download PDF

Info

Publication number
CN108305867B
CN108305867B CN201810309622.0A CN201810309622A CN108305867B CN 108305867 B CN108305867 B CN 108305867B CN 201810309622 A CN201810309622 A CN 201810309622A CN 108305867 B CN108305867 B CN 108305867B
Authority
CN
China
Prior art keywords
fuse
fuse link
dummy
electrical
dummy metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810309622.0A
Other languages
Chinese (zh)
Other versions
CN108305867A (en
Inventor
崔贤民
前田茂伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN108305867A publication Critical patent/CN108305867A/en
Application granted granted Critical
Publication of CN108305867B publication Critical patent/CN108305867B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

An electrical fuse structure of a semiconductor device is provided. The electrical fuse structure may include: a fuse link of a first metal material connecting the cathode and the anode; a cover dielectric covering a top surface of the fuse link; and a dummy metal plug penetrating the cover dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer includes a second metal material different from the first metal material, wherein a width of the fuse link is substantially equal to or less than a width of the anode and a width of the cathode.

Description

Electric fuse structure of semiconductor device
The present application is a divisional application of No. 201410528528.6 entitled "electric fuse structure of semiconductor device" filed on 10/9/2014 by the chinese intellectual property office.
Technical Field
One or more embodiments described herein relate to an electrical fuse structure of a semiconductor device.
Background
Fuses have been used for various purposes in semiconductor chip manufacturing and design. For example, in memory devices, fuses have been used to replace defective memory cells with redundant memory cells during a repair process. Such replacement helps to improve manufacturing yield. Fuses have been used during the chip identification process to record the manufacturing history of the chip. Fuses have been used in post-fabrication operations of chip customization processes to optimize the characteristics of the chip.
Fuses may be classified as laser fuses or electric fuses. In the laser fuse, electrical connection is cut using a laser beam. In an electrical fuse, a current is used for this purpose.
Disclosure of Invention
According to one embodiment, an electrical fuse structure of a semiconductor device includes: a fuse of a first metallic material connecting the cathode and the anode; a cover dielectric covering a top surface of the fuse link; and a dummy metal plug penetrating the cover dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer includes a second metal material different from the first metal material. Wherein the width of the fuse link is substantially equal to or less than the width of the anode and the width of the cathode.
The electrical fuse structure further includes: a dummy metal pattern on a top surface of the dummy metal plug; and dummy fuses at respective sides of the fuses, wherein a thickness of the dummy metal pattern is greater than a thickness of the fuses, and a width of the dummy metal pattern is less than a distance between the dummy fuses.
A plurality of dummy metal plugs may be positioned between the anode and the cathode. The dummy metal plug may extend in a direction substantially perpendicular to a longitudinal axis of the fuse link.
The fuse link will conduct a programming current, and the dummy metal plug may alter a temperature gradient in the fuse link while the fuse link conducts the programming current.
The fuse link may include a first area in contact with the dummy metal plug and a second area in contact with the capping dielectric, and a temperature of the fuse link may have a maximum value at the second area when the fuse link conducts the programming current.
The fuse link includes a first region in contact with the dummy metal plug and a second region in contact with the capping dielectric, the electrical fuse structure is to conduct a programming current, and a first electrical actuation force caused by electromigration at the first region of the fuse link is different from a second electrical actuation force caused by electromigration at the second region of the fuse link during supply of the programming current.
According to another embodiment, an electrical fuse structure of a semiconductor device includes: a fuse of a first metallic material connecting the cathode and the anode; an interlayer insulating layer covering the anode, the cathode and the fuse; a cover dielectric between the top surface of the fuse link and the interlayer insulating layer, the cover dielectric comprising a different insulating material than the interlayer insulating layer; and a dummy metal plug penetrating the interlayer insulating layer and the cover dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer includes a second metal material different from the first metal material. The barrier metal layer covers the bottom surface and the side surfaces of the metal layer.
The first metallic material may include at least one of tungsten, aluminum, copper, and copper alloy, and the second metallic material may include at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, and combinations thereof. The barrier metal layer may be thicker on a bottom surface of the metal layer than on a side surface of the metal layer.
The fuse link will conduct a programming current and in a programmed state, the fuse link may have a void between the anode and the dummy metal plug. A distance between the void and the dummy metal plug may be smaller than a distance between the void and the anode.
According to another embodiment, an electrical fuse structure of a semiconductor device includes: a fuse connecting the anode to the cathode and to be programmed based on a programming current; and a dummy metal plug in contact with the fuse link, wherein the fuse link includes a first metal material, the dummy metal plug includes a second metal material different from the first metal material, the dummy metal plug changes an electrical driving force and a thermal driving force when the fuse link conducts a programming current, wherein the electrical driving force and the thermal driving force are based on electro-migration and thermo-migration in the fuse link.
The dummy metal plug may include a barrier metal layer between the metal layer and the fuse link, and the barrier metal layer may include a second metal material. The first metal material may have a conductivity greater than a conductivity of the second metal material. The total driving force may have a maximum value between the anode and the dummy metal plug when the fuse link conducts the programming current. The total driving force may be based on the sum of the electrical driving force and the thermal driving force.
The electrical fuse structure may further include: an interlayer insulating layer covering the anode, the cathode and the fuse; and a cover dielectric between the top surface of the fuse link and the interlayer insulating layer, the cover dielectric including an insulating material different from that of the interlayer insulating layer, wherein the fuse link includes a first region in contact with the dummy metal plug and a second region in contact with the cover dielectric.
The first electrical actuation force caused by electromigration at the first region of the fuse link may be less than the second electrical actuation force caused by electromigration at the second region of the fuse link. The temperature of the fuse link may have a maximum value at the second region when the fuse link conducts the programming current.
Drawings
Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
FIG. 1 illustrates an electromigration effect in a programming process of one embodiment of an electrical fuse structure;
FIG. 2 illustrates thermal migration during a programming process of one embodiment of an electrical fuse structure;
FIG. 3 illustrates electromigration and electromigration in a programming process of an embodiment of an electrical fuse structure;
FIG. 4A shows a first embodiment of an electrical fuse structure, and FIG. 4B shows a view along section lines I-I 'and II-II' in FIG. 4A;
FIG. 5 illustrates thermal migration in a programming process of a first embodiment of an electrical fuse structure;
FIG. 6 illustrates electromigration in a programming process of a first embodiment of an electrical fuse structure;
FIG. 7 illustrates electromigration and electromigration in a programming process of a first embodiment of an electrical fuse structure;
fig. 8A to 8C show cross-sectional views of modifications of the first embodiment of the electric fuse structure;
fig. 9A and 10A show a second embodiment of an electrical fuse structure, fig. 9B and 10B show views along a section line I-I 'and a section line II-II' in fig. 9A and 10A, respectively, and fig. 9C and 10C show modifications of the second embodiment of the electrical fuse structure;
fig. 11A and 12A illustrate thermal migration in a programming process of the second embodiment of the electrical fuse structure, and fig. 11B and 12B illustrate thermal migration and electromigration in a programming process of the second embodiment of the electrical fuse structure;
FIGS. 13A and 14A show a third embodiment of an electric fuse structure, and FIGS. 13B and 14B show views along the section lines I-I 'and II-II' in FIGS. 13A and 14A, respectively;
FIG. 15A shows a fourth embodiment of an electrical fuse structure, and FIG. 15B shows a view along section lines I-I 'and II-II' in FIG. 15A;
FIG. 16A shows a fifth embodiment of an electrical fuse structure, and FIG. 16B shows a view along the section lines I-I 'and II-II' in FIG. 16A;
FIG. 17A shows a sixth embodiment of an electrical fuse structure, and FIG. 17B shows a view along the section lines I-I 'and II-II' in FIG. 17A;
FIG. 18A shows a seventh embodiment of an electrical fuse structure, and FIG. 18B shows a view along the section lines I-I 'and II-II' in FIG. 18A;
fig. 19 shows a modification of the seventh embodiment of the electric fuse structure;
fig. 20A, 20B, 21A and 21B show modifications of a seventh embodiment of an electric fuse structure;
fig. 22 and 23 show an eighth embodiment of an electrical fuse structure;
fig. 24A and 24B show a ninth embodiment of an electric fuse structure;
fig. 25A to 25C illustrate embodiments of semiconductor devices, each including an electrical fuse structure according to one or more of the foregoing embodiments;
fig. 26 illustrates a memory system including a semiconductor device according to one or more of the foregoing embodiments;
fig. 27 illustrates a memory card including a semiconductor device according to one or more of the foregoing embodiments;
fig. 28 illustrates an information processing system including a semiconductor device according to one or more of the foregoing embodiments.
Detailed Description
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; they may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the exemplary embodiments to those skilled in the art.
In the drawings, the size of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under, and one or more intervening layers may also be present. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers (e.g., "between … …" and "directly between … …", "adjacent" and "directly adjacent", "on … …" and "directly on … …") should be interpreted in a similar manner.
Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in a degree of implantation occurring in the region between the buried region and the surface through which implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
As understood by the inventive body, devices and methods of forming devices according to various embodiments described herein may be implemented in microelectronic devices, such as integrated circuits, in which multiple devices according to various embodiments described herein are integrated in the same microelectronic apparatus. Thus, the cross-sectional views shown herein may be repeated in two different directions that need not be orthogonal in a microelectronic device. Thus, a plan view of a microelectronic device embodied as a device according to various embodiments described herein may include multiple devices in an array and/or in a two-dimensional pattern based on the functionality of the microelectronic device.
Devices according to various embodiments described herein may be inserted among other devices depending on the functionality of the microelectronic device. Furthermore, microelectronic devices according to various embodiments described herein may be repeated in a third direction, which may be orthogonal to the two different directions, to provide a three-dimensional integrated circuit.
Thus, the cross-sectional views shown herein provide support for multiple devices that extend in two different directions in plan view and/or in three different directions in perspective view according to various embodiments described herein. For example, as illustrated by a plan view of a device/structure, when a single active region is illustrated in a cross-sectional view of the device/structure, the device/structure may include multiple active regions and transistor structures (or memory cell structures, gate structures, etc. where appropriate) located over the active regions.
FIG. 1 illustrates an electromigration effect in a programming process of one embodiment of an electrical fuse structure. FIG. 2 illustrates a diagram showing a thermomigration effect in a programming process of one embodiment of an electrical fuse structure.
Referring to fig. 1 and 2, the electric fuse structure includes a fuse link FL connecting the cathode CP with the anode AP. The process of programming such an electrical fuse structure may include forming a voltage difference between the cathode CP and the anode AP to provide a programming current to the fuse link FL.
For example, during a programming process of the electrical fuse structure, a negative voltage may be applied to the cathode CP, and a positive voltage may be applied to the anode AP. Therefore, electrons flow from the cathode CP toward the anode AP through the fuse FL. When electrons flow through the fuse link FL, the electrons may collide with atoms of the fuse link FL, resulting in a phenomenon known as electromigration EM. As shown in fig. 1, the driving force (e.g., electrical driving force, F) in the fuse link FL due to electromigrationEM) May be completely constant regardless of location.
When a programming current is supplied to the fuse link FL formed of a metal material (e.g., tungsten, aluminum, or copper), the temperature of the fuse link FL may increase due to joule heating. As shown in fig. 2, joule heating may generate an uneven temperature distribution of the fuse link FL. For example, the temperature of the fuse link FL may be highest at the center portion. Such uneven temperature distribution may cause thermal migration in the fuse link FL. For example, atoms of the fuse link FL may migrate from the central portion toward the anode AP (hereinafter, referred to as first thermomigration TM1) or toward the cathode CP (hereinafter, referred to as second thermomigration TM 2).
FIG. 3 illustrates a thermomigration effect and an electromigration effect in a programming process of an embodiment of an electrical fuse structure. In fig. 3, a curve a represents an example of a driving force caused by electromigration that may occur when programming an electrical fuse structure. Curve B represents the driving force due to thermomigration that may occur when programming an electrical fuse structure. Curve C represents the total driving force or the resultant of the two driving forces resulting from thermomigration and electromigration.
Referring to FIG. 3, the driving force resulting from electromigration (e.g., electrical driving force F)EM) Can be fusedIs constant in volume FL regardless of location. In contrast, the driving force resulting from the uneven temperature distribution (e.g., thermal driving force F)TM) May be applied in opposite directions from the central portion of the fuse link FL.
Electromigration EM and first thermomigration TM1 may occur in the same direction between anode AP and the central portion of fuse link FL. As a result, the total driving force F applied to the fuse link FLEM+TMWould be based on the sum of the electrical driving force and the thermal driving force. In contrast, electromigration EM and second thermomigration TM2 may occur in opposite directions between cathode CP and the central portion of fuse link FL. As a result, the total driving force F applied to the fuse link FLEM+TMWould be based on the difference between the thermal driving force and the electrical driving force.
In the fuse link FL, the thermal and electrical driving forces may therefore result in a non-uniform atom flow rate or a non-zero flux divergence (flux divergence), as shown in fig. 3. In addition, depletion or aggregation of atoms may occur depending on the magnitude of the flux divergence. For example, if the outflow flux is larger than the inflow flux at a specific region of the fuse link FL, atoms may be consumed to form voids (void). In contrast, if the inflow flux at a specific region of the fuse link FL is larger than the outflow flux, atoms may aggregate to establish hillock formation (hillock formation). The void may increase the resistance of the fuse link FL to program the electrical fuse structure.
According to the above method, the larger the flux divergence in the fuse link FL, the faster the void is formed. Hereinafter, various structures and methods for increasing the flux divergence in the fuse link FL will be described.
Fig. 4A shows a first embodiment of an electrical fuse structure, and fig. 4B shows a diagram taken along the section lines I-I 'and II-II' in fig. 4A. Referring to fig. 4A and 4B, the first embodiment of the electrical fuse structure includes a metal layer 20 on an underlying layer 10, a capping dielectric (capping dielectric)30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse 20f connecting the cathode 20c and the anode 20 a. Further, the electrical fuse structure may include a dummy metal plug 50 in contact with a portion of the fuse link 20 f.
The underlying layer 10 may be an insulating film. For example, the underlying layer 10 may be one of a device isolation layer, which may be formed on a semiconductor substrate to define an active region, and an interlayer insulating layer 40, which is formed on a transistor to support a metal line.
The metal layer 20 may be a thin film. In one embodiment, the metal layer 20 may be formed of a first metal material. For example, the metal layer 20 may be made of at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy. Examples of the copper alloy include a copper-based material In which at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr is contained In a small amount or a predetermined amount.
The anode 20a, cathode 20c, and fuse link 20f may be formed by depositing a metal layer 20 on the underlying layer 10 and patterning the metal layer 20. Alternatively, the anode 20a, the cathode 20c, and the fuse link 20f may be formed by a damascene process including forming a trench in an insulating layer and filling the trench with a metal material. In one embodiment, the fuse link 20f may extend in a specific direction, the anode 20a may be connected to an end of the fuse link 20f, and the cathode 20c may be connected to an opposite end of the fuse link 20 f. The width of the anode 20a and the cathode 20c may be larger than the width of the fuse link 20 f. As shown in the drawing, the anode 20a and the cathode 20c may be symmetrically formed. However, in alternative embodiments, the anode 20a and the cathode 20c may be formed asymmetrically.
In one embodiment, the fuse link 20f may include a first region R1, a second region R2, and a third region R3. In the first region R1, the dummy metal plug 50 and the fuse link 20f contact each other. In the second region R2, the cover dielectric 30 and the fuse link 20f contact each other between the anode 20a and the dummy metal plug 50. In the third region R3, the cover dielectric 30 and the fuse link 20f contact each other between the cathode 20c and the dummy metal plug 50.
The capping dielectric 30 may be located between the interlayer insulating layer 40 and the top surface of the fuse link 20 f. The capping dielectric 30 may be formed from and between the underlying layer 10 and the layerThe insulating layer 40 is formed of a different insulating material. The capping dielectric 30 may also conformally cover the top surface of the fuse link 20f, for example, with a uniform thickness, but this is not required in all embodiments. Capping dielectric 30 may be made of, for example, SiO2、SiON、Si3N4SiCN, SiC or SiCN. The interlayer insulating layer 40 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.
The dummy metal plug 50 may be formed by a process including the steps of: a dummy contact hole is formed through the capping dielectric 30 and the interlayer insulating layer 40 to expose a portion of the fuse link 20f, and then the dummy contact hole is filled with a metal material. In one embodiment, the dummy metal plug 50 may be formed on a central portion of the fuse link 20f and may be in contact with a top surface of the fuse link 20 f. The lower width of the dummy metal plug 50 may be greater than the upper width of the fuse body 20f, and the upper width of the dummy metal plug 50 may be greater than the lower width of the dummy metal plug 50.
In one embodiment, the dummy metal plug 50 may include a metal layer 53 and a barrier metal layer 51 disposed between the metal layer 53 and the fuse link 20 f. The barrier metal layer 51 may be disposed to cover a bottom surface and a side surface of the metal layer 53. In one embodiment, the barrier metal layer 51 may have a uniform thickness on the side and bottom surfaces of the metal layer 53. The barrier metal layer 51 may be formed of a material capable of preventing a metal material constituting the metal layer 53 from diffusing into the interlayer insulating layer 40 adjacent thereto.
In one embodiment, the barrier metal layer 51 may be formed of a second metal material, which may be different from the first metal material for the fuse link 20f and has a conductivity smaller than that of the first metal material. Examples of the material forming the barrier metal layer 51 include at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, and combinations thereof.
In one embodiment, the metal layer 53 may be formed of a third metal material that may be different from the second metal material for the barrier metal layer 51. The third metallic material for the metallic layer 53 may be the same as or different from the first metallic material for the fuse link 20 f. For example, the metal layer 53 may be made of at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy. Examples of the copper alloy include a copper-based material In which at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr is contained In a small amount or a predetermined amount.
Fig. 5 illustrates thermal migration that may occur during a programming process of the first embodiment of the electrical fuse structure. Fig. 6 illustrates electromigration that may occur in the programming process of the first embodiment of the electrical fuse structure. Fig. 7 illustrates electromigration and electromigration that may occur in the programming process of the first embodiment of the electrical fuse structure.
Referring to fig. 6, a programming process of the electrical fuse structure may be performed using a programming current. The programming current may be generated by creating a voltage difference between the cathode 20c and the anode 20 a. In one embodiment, during the programming process, a negative voltage may be applied to the cathode 20c, a positive voltage may be applied to the anode 20a, and the dummy metal plug 50 may be in an electrically floating state. The voltage difference between the cathode 20c and the anode 20a creates a programming current that causes electrons to flow from the cathode 20c toward the anode 20a through the fuse link 20 f.
During this electron flow, the electrons may collide with atoms constituting the fuse link 20f, resulting in electromigration. Electromigration may occur primarily along the surface of the metal layer. The driving force resulting from electromigration may vary depending on the material in contact with the fuse link 20 f. In other words, as described above, the fuse link 20f may include the first region R1 where the dummy metal plug 50 and the fuse link 20f contact each other, the second region R2 where the cover dielectric 30 and the fuse link 20f contact each other between the anode 20a and the dummy metal plug 50, and the third region R3 where the cover dielectric 30 and the fuse link 20f contact each other between the cathode 20c and the dummy metal plug 50.
The driving force caused by electromigration may differ between the first region R1 and the second region R2 and between the first region R1 and the third region R3. For example, the first electrical actuation force EM1 on the second and third regions R2 and R3 where the metal layer and the capping dielectric contact each other may be larger than the second electrical actuation force EM2 on the first region R1 where the different metal materials contact each other.
Referring to fig. 5, joule heating may occur when programming the electrical fuse structure. Joule heating can produce a non-zero gradient temperature of the fuse link 20 f. In one embodiment, the maximum amount of joule heat may be generated at the central portion of the fuse link 20 f. However, since a considerable portion of such heat may be consumed by the portion where the dummy metal plug 50 and the fuse link 20f contact each other, the temperature of the first region R1 may be lowered. For example, physical contact between the dummy metal plug 50 and the fuse link 20f may cause a change in the temperature gradient of the fuse link 20 f. For example, during programming, the temperature of the fuse link 20f may be maximized at two separate portions due to the presence of the dummy metal plug 50. For example, the temperature of the fuse body 20f may have a maximum value in the second and third regions R2 and R3 respectively located on the sides of the dummy metal plug 50.
In fig. 7, curve a shows the driving force due to electromigration that may occur when programming an electrical fuse structure. Curve B shows the driving force due to thermomigration that may occur when programming an electrical fuse structure. Curve C shows the total driving force or resultant of the two driving forces resulting from thermomigration and electromigration.
In one embodiment, the temperature of the fuse link 20f may be maximized at two separate portions due to the presence of the dummy metal plug 50. As a result, the portion of the fuse link 20f located under the dummy metal plug 50 may have a lower temperature than other portions of the fuse link 20 f. In addition, due to the presence of the dummy metal plug 50, the electrical driving force in the portion of the fuse link 20f located below the dummy metal plug 50 can be reduced.
The total driving force may sharply change in or near the first region R1 of the fuse link 20 f. For example, the total driving force FEM+TMMay be larger in the electrical fuse structure having the dummy metal plug 50 than in the electrical fuse structure described with reference to fig. 3. For example, since the flux divergence is increased at the first region R1 in contact with the dummy metal plug 50, the electrical fuse structure can be programmed more quickly under the same condition (e.g., at the same voltage). This enables the programming voltage to be reducedThe fuse structure is programmed.
As shown in fig. 7, the total driving force FEM+TMIt may have a maximum value at a portion of the fuse link 20f adjacent to the anode 20a and at a side of the dummy metal plug 50. Since the outflow flux is abruptly increased, a depletion (depletion) or a void may occur at the second region R2 of the fuse link 20f adjacent to the dummy metal plug 50. Accordingly, the electrical fuse structure may have a void V between the anode 20a and the dummy metal plug 50 after the programming process. The distance between the void V and the dummy metal plug 50 may be smaller than the distance between the void V and the anode 20 a.
Fig. 8A to 8C show modifications of the first embodiment of the electric fuse structure. Referring to fig. 8A to 8C, the electrical fuse structure includes a cathode 20C, an anode 20a, a fuse link 20f, and a dummy metal plug 50, as described with reference to fig. 4B. The fuse link 20f includes a first region R1 where the dummy metal plug 50 and the fuse link 20f contact each other, a second region R2 where the cover dielectric 30 and the fuse link 20f contact each other between the anode 20a and the dummy metal plug 50, and a third region R3 where the cover dielectric 30 and the fuse link 20f contact each other between the cathode 20c and the dummy metal plug 50.
Referring to fig. 8A to 8C, the dummy metal plug 50 may include the barrier metal layer 51 and the metal layer 53 as described above, and may have a bottom surface lower than the top surface of the fuse link 20 f. The bottom surface of the dummy metal plug 50 may be separated from the top surface of the underlying layer 10. In other words, the thickness of the fuse link 20f on the first region R1 may be smaller than the thickness on the second region R2 and the third region R3. In addition, as shown in fig. 8A and 8B, the dummy metal plug 50 may have a lower width smaller than an upper width of the fuse link 20 f. In one embodiment, as shown in fig. 8B, the barrier metal layer 51 may have a greater thickness on the bottom surface of the metal layer 53 than on the side surface of the metal layer 53.
In one embodiment as shown in fig. 8C, the dummy metal plugs 50 may have rounded lower corners. In addition, the lower width of the dummy metal plug 50 may be greater than the upper width of the fuse link 20 f. Accordingly, the dummy metal plug 50 may cover a portion of the side surface and the top surface of the fuse link 20 f. In other words, the blocking insulating layer 51 may be in direct contact with the top surface and the side surface of the fuse link 20 f.
Fig. 9A and 10A show a second embodiment of an electrical fuse structure, fig. 9B and 10B show views taken along a section line I-I 'and a section line II-II' in fig. 9A and 10A, respectively, and fig. 9C and 10C show modifications of the second embodiment of the electrical fuse structure.
In the second embodiment, the electrical fuse structure includes at least one layer of the dummy metal pattern 80 and the dummy metal plug 50 connected to the fuse link 20 f. The volume of the dummy metal pattern 80 may be adjusted to control the blowing performance of the electrical fuse structure.
Referring to fig. 9A, 9B, 10A, and 10B, the second embodiment of the electrical fuse structure includes a metal layer 20 on an underlying layer 10, a capping dielectric 30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse 20f connecting the cathode 20c and the anode 20 a. Further, the electrical fuse structure may include a dummy metal plug 50 and a dummy metal pattern 80 connected to a portion of the fuse link 20 f. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20 a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20 c.
In one embodiment, the fuse link 20f may extend in a particular direction, the anode 20a may be connected to an end of the fuse link 20f, and the cathode 20c may be connected to an opposite end of the fuse link 20 f. The width of the anode 20a and the cathode 20c may be larger than the width of the fuse link 20 f. In one embodiment, the metal layer 20 may be formed of a first metal material. For example, the metal layer 20 may be made of at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy. Examples of the copper alloy include copper-based materials containing at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr In a small amount or a predetermined amount.
The capping dielectric 30 and the first interlayer insulating layer 40 may be sequentially formed on the underlying layer 10 on which the anode 20a, the cathode 20c and the fuse link 20f are disposed. The capping dielectric 30 may be of a different insulating material than the underlying layer 10 and the first interlayer insulating layer 40And (4) forming. The capping dielectric may conformally cap the top surface of the fuse link 20f and may be, for example, formed of SiO2、SiON、Si3N4SiC or SiCN.
The forming of the dummy metal plug 50 may include forming a dummy contact hole penetrating the cover dielectric 30 and the first interlayer insulating layer 40 and exposing a portion of the fuse link 20 f. The dummy contact hole may then be filled with a metal material. The forming of the first contact plug 60a may include forming a first contact hole penetrating the cover dielectric 30 and the first interlayer insulating layer 40 and exposing a portion of the anode electrode 20a, and then filling the first contact hole with a metal material.
The forming of the second contact plug 60 may include forming a second contact hole penetrating the cover dielectric 30 and the first interlayer insulating layer 40 and exposing a portion of the cathode 20c, and then filling the second contact hole with a metal material. In one embodiment, the dummy metal plug 50 may be formed simultaneously with the first and second contact plugs 60a and 60 b. In addition, the dummy metal plug 50 may include the same metal material as at least one of the first and second contact plugs 60a and 60 b.
In one embodiment, each of the dummy metal plug 50, the first contact plug 60a, and the second contact plug 60b may include a first barrier metal layer 51 and a first metal layer 53. The first barrier metal layer 51 may be formed to have a uniform thickness on the side and bottom surfaces of the dummy contact hole. In one embodiment, the first barrier metal layer 51 may be formed of a second metal material that may be different from the first metal material for the fuse link 20f, and the first barrier metal layer 51 may have a conductivity less than that of the first metal material. For example, the first barrier metal layer 51 may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.
The first metal layer 53 may be formed of a third metal material that may be different from the second metal material for the first barrier metal layer 51. The third metallic material for the first metallic layer 53 may be the same as or different from the first metallic material for the fuse link 20 f. For example, the first metal layer 53 may be made of at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy. Examples of the copper alloy include copper-based materials containing at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr In a small amount or a predetermined amount.
The second interlayer insulating layer 70 may be formed on the first interlayer insulating layer 40 provided with the dummy metal plug 50, the first contact plug 60a, and the second contact plug 60 b. The first conductive pattern 90a, the second conductive pattern 90b, and the dummy metal pattern 80 may be formed in the second interlayer insulating layer 70. The dummy metal pattern 80 may be connected to the dummy metal plug 50. The first and second conductive patterns 90a and 90b may be connected to the first and second contact plugs 60a and 60b, respectively.
The dummy metal pattern 80 may include a second metal layer 83 and a second barrier metal layer 81 disposed between the second metal layer 83 and the dummy metal plug 50. The formation of the dummy metal pattern 80 may include forming a trench in the second interlayer insulating layer 70 to expose the top surface of the dummy metal plug 50, and then sequentially forming a second barrier metal layer 81 and a second metal layer 83 to fill the trench. The second barrier metal layer 81 may be formed of, for example, Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.
The second metal layer 83 may be formed of a metal material different from that of the first metal layer 51 constituting the dummy metal plug 50. The first and second conductive patterns 90a and 90b may be formed simultaneously with the dummy metal pattern 80. For example, the first and second conductive patterns 90a and 90b may be formed of the same metal material as the dummy metal pattern 80.
According to the embodiment in fig. 9A and 9B, the width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20 f. The width W3 of the dummy metal pattern 80 may be greater than the width W1 of the fuse link 20 f. Further, the dummy metal pattern 80 may have a first thickness t2 smaller than the thickness t1 of the fuse link 20 f.
According to the embodiment in fig. 10A and 10B, the width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20 f. The width W3 of the dummy metal pattern 80 may be greater than the width W1 of the fuse link 20 f. Further, the dummy metal pattern 80 may have a second thickness t3 greater than the thickness t1 of the fuse link 20 f.
According to the second embodiment, the volume of the dummy metal pattern 80 in fig. 9A and 9B may be different from the volume of the dummy metal pattern 80 in fig. 10A and 10B. For example, the volume of the dummy metal pattern 80 in fig. 9A and 9B may be smaller than the volume of the dummy metal pattern 80 in fig. 10A and 10B.
According to the embodiment in fig. 9C and 10C, the electrical fuse structure may include a metal layer 20 on the underlying layer 10, a cover dielectric 30 covering a top surface of the metal layer 20, a first interlayer insulating layer 40 and a second interlayer insulating layer 70 on the cover dielectric 30. The metal layer 20 may form a cathode 20c, an anode 20a, and a fuse 20f connecting the cathode 20c and the anode 20 a. In one embodiment, the width of the anode 20a and the cathode 20c may be greater than the width of the fuse link 20 f. The metal layer 20 may be formed of, for example, a first metal material (e.g., at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy). Examples of the copper alloy include copper-based materials containing at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr In a small amount or a predetermined amount.
According to this embodiment, the electrical fuse structure may include the dummy metal plug 50 in contact with a portion of the fuse link 20 f. The dummy metal plug 50 may include a barrier metal layer 51, a contact portion 53a, and an interconnection portion 53 b. The barrier metal layer 51 may be formed of a conductive material capable of preventing the metal materials constituting the contact portion 53a and the interconnection portion 53b from diffusing into the adjacent first and second interlayer insulating layers 40 and 70. The barrier metal layer 51 may be formed of a second metal material different from the first metal material and having a conductivity smaller than that of the first metal material. For example, the barrier metal layer 51 may be formed of, for example, Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof.
In one embodiment, the contact portion 53a may be connected to the fuse link 20f through the first interlayer insulating layer 40. The interconnection portion 53b may be disposed in the second interlayer insulating layer 70 and may be connected to the contact portion 53 a. The width of the interconnection portion 53b may be greater than the width of the contact portion 53 a. The contact portion 53a and the interconnection portion 53b may be formed of a third metal material different from the second metal material. For example, the contact portion 53a and the interconnection portion 53b may be made of tungsten (W), aluminum (Al), copper (Cu), or a copper alloy. Examples of the copper alloy include copper-based materials containing at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr In a small amount or a predetermined amount.
In one embodiment shown in fig. 9C, the lower width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20 f. The upper width W3 of the dummy metal plug 50 may be greater than the width W1 of the fuse link 20 f. Further, in the dummy metal plug 50, the interconnection portion 53b may have a first thickness t2 smaller than the thickness t1 of the fuse link 20 f.
Alternatively, as shown in fig. 10C, the lower width W2 of the dummy metal plug 50 may be smaller than the width W1 of the fuse link 20 f. The upper width W3 of the dummy metal plug 50 may be greater than the width W1 of the fuse link 20 f. In addition, the interconnection portion 53b of the dummy metal plug 50 may have a second thickness t3 greater than the thickness t1 of the fuse link 20 f. For example, the volume of the interconnection portion 53b of the dummy metal plug 50 in fig. 9C may be smaller than the volume of the interconnection portion 53b of the dummy metal plug 50 in fig. 10C.
The formation of the dummy metal plug 50 may include sequentially forming a first interlayer insulating layer 40 and a second interlayer insulating layer 70, forming a via hole through the first interlayer insulating layer 40 and the second interlayer insulating layer 70, patterning the second interlayer insulating layer 70 to form a trench connected to the via hole, and sequentially forming a barrier metal layer and a metal layer in the via hole and the trench. In one embodiment, the first and second connection patterns 65a and 65b may be formed in the process of forming the dummy metal plug 50. The first connection pattern 65a may be connected to the anode 20a, and the second connection pattern 65b may be connected to the cathode 20 c.
Similar to the dummy metal plug 50, each of the first and second connection patterns 65a and 65b may include a through portion, an interconnection portion, and a barrier metal layer covering a bottom surface and a side surface of the interconnection portion.
Fig. 11A and 12A illustrate an example of how heat migration depends on the volume of a dummy metal pattern in a programming process of the second embodiment of the electrical fuse structure.
According to the second embodiment, during programming, a negative voltage may be applied to the cathode 20c, a positive voltage may be applied to the anode 20a, and the dummy metal plug 50 may be in an electrically floating state. Due to the voltage difference between the cathode 20c and the anode 20a and the consequent programming current, electrons flow from the cathode 20c towards the anode 20a through the fuse link 20 f.
According to the second embodiment, as shown in fig. 11A and 12A, during programming, the temperature gradient of the fuse link 20f can be controlled by adjusting the volume of the dummy metal plug 50. In fig. 11A, the interconnection portion 53b of the dummy metal plug 50 may have a first thickness t2 smaller than a thickness t1 of the fuse link 20 f. In fig. 12A, the interconnection portion 53b of the dummy metal plug 50 may have a second thickness t3 greater than the thickness t1 of the fuse link 20 f. For example, the volume of the interconnection portion 53b of the dummy metal plug 50 in fig. 12A may be larger than the volume of the interconnection portion 53b of the dummy metal plug 50 shown in fig. 11A.
As the volume of the dummy metal plug 50 increases, the first region R1 of the fuse link 20f may be more effectively cooled. For example, the temperature of the first region R1 of the fuse link 20f may be reduced more effectively than the adjacent regions. The decrease in the temperature of the first region R1 in the electrical fuse structure in fig. 12A may be larger than the decrease in the temperature of the first region R1 in the electrical fuse structure in fig. 11A. As a result, the unevenness of the temperature distribution of the fuse link 20f in the electrical fuse structure of fig. 12A can be higher than the unevenness of the temperature distribution of the fuse link 20f in the electrical fuse structure of fig. 11A.
Fig. 11B and 12B illustrate a thermomigration and an electromigration effect in a programming process of the second embodiment of the electrical fuse structure. In fig. 11B and 12B, curve a represents a driving force due to electromigration that may occur when programming an electrical fuse structure. Curve B represents the driving force due to thermomigration that may occur when programming an electrical fuse structure. In fig. 11B and 12B, curve C represents the total driving force or resultant of the two driving forces resulting from thermomigration and electromigration.
Referring to fig. 11B, in the first region of the fuse link 20fIn R1, the difference Δ F between the electric driving forcesEMMay be greater than the difference Δ F in thermal driving forceTM. For example, the total driving force in the first region R1 of the fuse link 20F may be primarily dependent on the difference in electrical driving force Δ FEM。
Referring to fig. 12B, in the first region R1 of the fuse link 20F, the difference Δ F in thermal driving forceTMCan be larger than the difference delta F of the electric driving forceEM. For example, the total driving force in the first region R1 of the fuse link 20F may be primarily dependent on the difference Δ F in thermal driving forceTM。
According to the present embodiment, the stronger the thermal driving force, the stronger the total driving force in the first region R1 of the fuse link 20 f. This may allow for faster programming of the eFUSE structure for a given voltage condition, or reduce the voltage required to program the eFUSE structure.
Fig. 13A and 14A show a third embodiment of an electric fuse structure, and fig. 13B and 14B show diagrams taken along a section line I-I 'and a section line II-II' in fig. 13A and 14A, respectively.
Referring to fig. 13A, 13B, 14A, and 14B, the electrical fuse structure includes a metal layer 20 on an underlying layer 10, a capping dielectric 30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. In one embodiment, the metal layer 20 may be formed of a first metal material, and may constitute a cathode 20c, an anode 20a, and a fuse 20f connecting the cathode 20c and the anode 20 a. In addition, the electrical fuse structure may include a dummy metal plug 50 contacting a portion of the fuse link 20f and a dummy metal pattern 80 disposed on the dummy metal plug 50. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a, and the second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20 c.
Similar to dummy metal plug 50 shown in fig. 9C and 10C, dummy metal plug 50 and dummy metal pattern 80 may be simultaneously formed using a damascene process. For example, the barrier metal layer 81 may not be formed between the metal layer 53 of the dummy metal plug 50 and the metal layer 83 of the dummy metal pattern 80.
According to the third embodiment, the contact area between the dummy metal plug 50 and the fuse link 20f may be changed to control the temperature gradient of the fuse link in the programming process of the electrical fuse structure. For example, as shown in fig. 13A and 13B, the dummy metal plug 50 may have a first lower width W2 that is less than the upper width W1 of the fuse link 20 f. The lower width of the dummy metal pattern 80 may be greater than the upper width W1 of the fuse link 20 f. Alternatively, as shown in fig. 14A and 14B, the dummy metal plug 50 may have a second lower width W3 that is greater than the upper width W1 of the fuse link 20 f. The lower width of the dummy metal pattern 80 may be greater than the upper width W1 of the fuse link 20 f. According to the third embodiment, the temperature gradient of the fuse link 20f in the programming process may be different between the electrical fuse structure in fig. 13A and 13B and the electrical fuse structure in fig. 14A and 14B.
Fig. 15A shows a fourth embodiment of an electric fuse structure, and fig. 15B shows a diagram taken along the section lines I-I 'and II-II' in fig. 15A. Referring to fig. 15A and 15B, the electrical fuse structure may include a metal layer 20 on an underlying layer 10, a capping dielectric 30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. The metal layer 20 may be used to form a cathode 20c, an anode 20a, and a fuse 20f connecting the cathode 20c and the anode 20 a.
In addition, the electrical fuse structure may include a dummy metal plug 50 contacting a portion of the fuse link 20f and a dummy metal pattern 80 on the dummy metal plug 50. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20a, and the second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20 c. Similar to the dummy metal plug 50 in fig. 9C and 10C, the dummy metal plug 50 and the dummy metal pattern 80 may be simultaneously formed. For example, the barrier metal layer 81 may not be formed between the metal layer 53 of the dummy metal plug 50 and the metal layer 83 of the dummy metal pattern 80.
In the present embodiment, the positions of the dummy metal plugs 50 and the dummy metal patterns 80 may be changed with respect to the anode 20a and the cathode 20 c. For example, in fig. 15A, the distance between the dummy metal plug 50 and the anode 20a may be greater than the distance between the dummy metal plug 50 and the cathode 20 c. The position of the dummy metal plug 50 may be changed to control the position of a void to be formed in a programming process of the electrical fuse structure.
Fig. 16A shows a fifth embodiment of an electric fuse structure, and fig. 16B shows a diagram taken along the section lines I-I 'and II-II' in fig. 16A. Referring to fig. 16A and 16B, the electrical fuse structure may include a metal layer 20 on an underlying layer 10, a capping dielectric 30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. In one embodiment, the metal layer 20 may be formed of a first metal material, and may form a cathode 20c, an anode 20a, and a fuse 20f connecting the cathode 20c and the anode 20 a.
The electrical fuse structure may further include a first dummy metal plug 50a and a second dummy metal plug 50b contacting a portion of the fuse link 20 f. The first dummy metal pattern 80a and the second dummy metal pattern 80b may be disposed on the first dummy metal plug 50a and the second dummy metal plug 50b, respectively. The first dummy metal plug 50a and the second dummy metal plug 50b may be positioned between the anode 20a and the cathode 20c and may be separated from each other. Each of the first dummy metal plug 50a and the second dummy metal plug 50b may include a barrier metal layer 51 and a metal layer 53. The barrier metal layer 51 may be formed of a second metal material different from the first metal material and having a conductivity smaller than that of the first metal material. The first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20 a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20 c.
In other embodiments, the first dummy metal plug 50a and the first dummy metal pattern 80a may be simultaneously formed, similar to the dummy metal plug 50 in fig. 9C and 10C. Similarly, the second dummy metal plug 50b and the second dummy metal pattern 80b may be simultaneously formed.
Fig. 17A shows a sixth embodiment of an electric fuse structure, and fig. 17B shows a diagram taken along the section lines I-I 'and II-II' in fig. 17A. Referring to fig. 17A and 17B, the electrical fuse structure may include a metal layer 20 on an underlying layer 10, a capping dielectric 30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. The metal layer 20 may form a cathode 20c, an anode 20a, a fuse link 20f connecting the cathode 20c and the anode 20a, and a dummy fuse link 20d disposed at a corresponding side of the fuse link 20 f. The dummy fuse link 20d may have, for example, substantially the same line width as the fuse link 20f, and may extend parallel to the fuse link 20 f. The dummy fuse 20d may be separated from the anode 20a, the cathode 20c, and the fuse 20 f.
The electrical fuse structure may include a dummy metal plug 50 contacting a portion of the fuse link 20f and a dummy metal pattern 80 on the dummy metal plug 50. The width of the dummy metal pattern 80 may be smaller than the spacing D between a pair of dummy fuses 20D adjacent to the dummy metal pattern 80. Similar to the dummy metal plug 50 in fig. 9C and 10C, the dummy metal plug 50 and the dummy metal pattern 80 may be simultaneously formed. For example, the barrier metal layer 81 may not be formed between the metal layer 53 of the dummy metal plug 50 and the metal layer 83 of the dummy metal pattern 80.
Fig. 18A shows a seventh embodiment of an electric fuse structure, and fig. 18B shows a cross-sectional view taken along lines I-I 'and II-II' of fig. 18A. The seventh embodiment of the electrical fuse structure includes the metal layer 20 formed in the underlying layer 10, the cover dielectric 30 covering the top surface of the metal layer 20, and the interlayer insulating layer 40 on the cover dielectric 30. The metal layer 20 may be formed of, for example, a first metal material, and may constitute a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20 a.
In addition, the electrical fuse structure may include a dummy metal plug 50 contacting a portion of the fuse link 20f and a dummy metal pattern 80 on the dummy metal plug 50. The dummy metal plugs 50 may extend in a direction substantially perpendicular to a longitudinal axis of the fuse link 20 f. As described above, the dummy metal plug 50 may include the barrier metal layer 51 and the metal layer 53. The barrier metal layer 51 may be formed of a second metal material different from the first metal material, and the metal layer 53 may be formed of a third metal material different from the second metal material.
In addition, the first contact plug 60a and the first conductive pattern 90a may be connected to the anode 20 a. The second contact plug 60b and the second conductive pattern 90b may be connected to the cathode 20 c. In the present embodiment, the first and second contact plugs 60a and 60b may extend parallel to the dummy metal plug 60.
In addition, in the present embodiment, the first and second conductive patterns 90a and 90b may be formed by forming the second interlayer insulating layer 70 on the first interlayer insulating layer 40 provided with the first and second contact plugs 60a and 60b and the dummy metal plug 50, forming the via hole 71 and the trench 73 in the second interlayer insulating layer 70, and sequentially forming the second barrier metal layer and the second metal layer in the via hole 71 and the trench 73. The top surface of the dummy metal plug 50 may be covered with, for example, a second interlayer insulating layer 70.
Fig. 19 shows a modification of the seventh embodiment of the electric fuse structure. Referring to fig. 19, the electrical fuse structure may include a metal layer 20 in an underlying layer 10, a capping dielectric 30 covering a top surface of the metal layer 20, and an interlayer insulating layer 40 on the capping dielectric 30. The metal layer 20 may be formed of, for example, a first metal material, and may constitute a cathode 20c, an anode 20a, and a fuse link 20f connecting the cathode 20c and the anode 20 a. The width of the anode 20a and the cathode 20c may be greater than the width of the fuse link 20 f. The electrical fuse structure may further include a dummy metal plug 50 contacting a portion of the fuse link 20f and a dummy metal pattern 80 on the dummy metal plug 50.
In the present embodiment, a plurality of first contact plugs 60a may be connected to the anode 20 a. The first conductive patterns 90a may be commonly connected to the plurality of first contact plugs 60 a. Similarly, a plurality of second contact plugs 60b may be connected to the cathode 20c, and the second conductive pattern 90b may be commonly connected to the plurality of second contact plugs 60 b.
Fig. 20A, 20B, 21A and 21B show further modifications of the seventh embodiment of the electric fuse structure. Referring to fig. 20A, 20B, 21A and 21B, such an electrical fuse structure may include an anode 20A, a cathode 20c, and a fuse link 20f connecting the cathode 20c and the anode 20A. The anode 20a, the cathode 20c, and the fuse link 20f may have substantially the same uniform line width.
In addition, the electrical fuse structure may include a dummy metal plug 50 in contact with a portion of the fuse link 20 f. The dummy metal plugs 50 may extend in a direction substantially perpendicular to a longitudinal axis of the fuse link 20 f. The dummy metal plug 50 may include a barrier metal layer 51 and a metal layer 53. The barrier metal layer 51 may be formed of a second metal material different from the first metal material, and the metal layer 53 may be formed of a third metal material different from the second metal material.
According to the embodiment in fig. 20A and 20B, a plurality of first contact plugs 60A may be connected to the top surface of the anode 20A, and a plurality of second contact plugs 60B may be connected to the top surface of the cathode 20 c. Each of the first and second contact plugs 60a and 60b may have, for example, a strip shape, wherein a longitudinal axis of the strip shape is perpendicular to a longitudinal axis of the fuse link 20 f. The first and second contact plugs 60a and 60b may be formed of the same material as the dummy metal plug 50.
The first conductive patterns 90a may be commonly connected to the first contact plugs 60 a. The second conductive patterns 90b may be commonly connected to the second contact plugs 60 b. The first conductive pattern 90a may be formed by forming a plurality of via holes 71 and trenches 73 connected to the via holes 71 in the second interlayer insulating layer 70, and then sequentially forming a barrier metal layer and a metal layer in the via holes 71 and the trenches 73. The through-holes 71 may be formed on the respective first contact plugs 60a, and may be spaced apart from each other in first and second directions crossing each other. The second conductive pattern 90b may be formed in the same manner as the first conductive pattern 90 a.
According to the embodiment in fig. 21A and 21B, a plurality of first contact plugs 60a may be connected to the anode 20a, and a plurality of second contact plugs 60B may be connected to the cathode 20 c. The first conductive patterns 90a may be commonly connected to the plurality of first contact plugs 60 a. The second conductive pattern 90b may be commonly connected to the plurality of second contact plugs 60 b. In the present embodiment, the first and second contact plugs 60a and 60b may be substantially parallel to the dummy metal plug 50. For example, the first and second contact plugs 60a and 60b may extend in a direction substantially perpendicular to a longitudinal axis of the fuse link 20 f.
The first and second conductive patterns 90a and 90b may be formed by forming a plurality of via holes 71 and trenches 73 connected to the via holes 71 in the second interlayer insulating layer 70, and then sequentially forming a barrier metal layer and a metal layer in the via holes 71 and the trenches 73. The through hole 71 for the first conductive pattern 90a may be formed to expose the first contact plugs 60a adjacent to each other. The through hole 71 for the second conductive pattern 90b may be formed to expose the second contact plugs 60b adjacent to each other.
Fig. 22 and 23 illustrate an eighth embodiment of an electrical fuse structure, in which the electrical fuse structure includes an anode pattern 110a, a cathode pattern 110b, a fuse link 130, a first contact plug 125a connecting the anode pattern 110a and the fuse link 130, a second contact plug 125b connecting the cathode pattern 110b and the fuse link 130, and a dummy metal plug 150 contacting a portion of the fuse link 130. In this embodiment, the fuse link 130 may be located at a different level from the anode pattern 110a and the cathode pattern 110 b.
The anode pattern 110a and the cathode pattern 110b may be formed in the underlying layer 100, for example, by a damascene process, and may be separated from each other. The first contact plug 125a may be connected to the anode pattern 110a through the first interlayer insulating layer 120. The second contact plug 125b may be connected to the cathode pattern 110b through the first interlayer insulating layer 120.
The fuse link 130 may be formed by patterning a metal layer made of a first metal material, and may be disposed on the first interlayer insulating layer 120. The fuse link 130 may be connected to both the first contact plug 125a and the second contact plug 125 b. The second interlayer insulating layer 140 may be on the first interlayer insulating layer 120 provided with the fuse link 130. The capping dielectric 135 may be disposed between the second interlayer insulating layer 140 and the fuse link 130.
The dummy metal plug 150 may penetrate the second interlayer insulating layer 140 and the capping dielectric 135, and may contact a portion of the fuse link 130. The dummy metal plug 150 may include a barrier metal layer 151 and a metal layer 153. The barrier metal layer 151 may be formed of a second metal material different from the first metal material constituting the fuse link 130. The metal layer 153 may be formed of a third metal material different from the second metal material.
Referring to fig. 23, the anode pattern 110 may be disposed on the underlying layer 100, the fuse link 130 may be disposed at a first level with respect to the underlying layer 100, and the cathode pattern 160 may be disposed at a second level with respect to the underlying layer 100. The second level may be higher than the first level.
For example, the first interlayer insulating layer 120 may be located on the underlying layer 100 provided with the anode pattern 110. The first contact plug 125 may be connected to the anode pattern 110 through the first interlayer insulating layer 120. The fuse link 130 may be disposed on the first contact plug 125. The fuse link 130 may be formed of a first metal material. The first contact plug 125 may be connected to an end of the fuse link 130. The fuse link 130 may be formed in the first interlayer insulating layer 120, for example, by a damascene process.
The capping dielectric 135 and the second interlayer insulating layer 140 may be sequentially formed on the fuse link 130. The second contact plug 155 may be connected to the other end portion of the fuse link 130. The dummy metal plug 150 may be disposed in a portion of the second interlayer insulating layer 140 separated from the second contact plug 155. The dummy metal plug 150 may be formed simultaneously with the second contact plug 155. Each of the dummy metal plug 150 and the second contact plug 155 may include a barrier metal layer 151 and a metal layer 153.
The barrier metal layer 151 may be formed of a second metal material different from the first metal material. The metal layer 153 may be formed of a third metal material different from the second metal material. In addition, a cathode pattern 160 may be disposed in the second interlayer insulating layer 140 and may be connected to the second contact plug 155. The dummy metal plug 150 may include a contact portion and an interconnection portion.
Fig. 24A and 24B show a ninth embodiment of an electrical fuse structure having a three-dimensional structure. The electrical fuse structure may include a cathode pattern 210, a fuse link 220, and an anode pattern 230. The cathode pattern 210 may be located on the underlying layer 200, the fuse link 220 may be located at a first level with respect to the top surface of the underlying layer 200, and the anode pattern 230 may be disposed at a second level with respect to the top surface of the underlying layer 200. The second level may be higher than the first level. Further, the dummy fuse link 220d may be disposed at the same level as the fuse link 220.
In this embodiment, in order to effectively collect heat during the programming process, the cathode pattern 210 may include a first portion 210a extending in a first (e.g., x-axis) direction and a second portion 210b extending in a second (e.g., y-axis) direction. The first contact plug 215 may connect the cathode pattern 210 to the fuse link 220.
Similar to the cathode pattern 210, the anode pattern 230 may include a first portion 230a extending in a first (e.g., x-axis) direction and a second portion 230b extending in a second (e.g., y-axis) direction. The second contact plug 225 may connect the fuse link 220 to the anode pattern 230. The first contact plug 215 and the second contact plug 225 may not overlap each other in a plan view.
The cathode pattern 210, the fuse link 220, and the anode pattern 230 may be formed of a first metal material including at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy, for example. Examples of the copper alloy include copper-based materials containing at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr In a small amount or a predetermined amount.
The electrical fuse structure may include a dummy metal plug 235 and a dummy metal pattern 240. The dummy metal plug 235 may contact a portion of the anode pattern 230. According to the embodiment in fig. 24A, the dummy metal plug 235 may be connected to the first portion 230a of the anode pattern 230, and the dummy metal plug 235 may be disposed adjacent to the second contact plug 225 in a plan view. In contrast, in fig. 24B, the dummy metal plug 235 may be separated from the second contact plug 225 from a perspective of a plan view.
The dummy metal plug 235 may include a barrier metal layer and a metal layer. The barrier metal layer may be formed of a second metal material different from the first metal material for the anode pattern 230. The metal layer may be formed of a third metal material different from the barrier metal layer. The second metal material may have a conductivity less than that of the first metal material. In addition, the dummy metal pattern 240 may be connected to a top surface of the dummy metal plug 235.
The use of the three-dimensional electrical fuse structure in fig. 24A and 24B enables more effective collection of heat during a programming process, thereby improving the performance of the programming process. During the programming process, a negative voltage may be applied to the cathode pattern 210, a positive voltage may be applied to the anode pattern 230, and the dummy metal plugs 235 and the dummy metal pattern 240 may be in an electrically floating state.
The voltage difference between the cathode pattern 210 and the anode pattern 230 generates a programming current. As a result, electrons flow from the cathode pattern 210 toward the anode pattern 230 through the fuse link 220. The flow of electrons may change the electrical and thermal driving forces at the anode pattern 230 under the dummy metal plug 235. Accordingly, a void may be formed at a portion of the anode pattern 230 adjacent to the dummy metal plug 235.
Fig. 25A to 25C illustrate embodiments of semiconductor devices, each including at least one electrical fuse structure according to any one of the foregoing embodiments. Referring to fig. 25A to 25C, the semiconductor substrate 300 includes a memory cell region a and a fuse region B. The MOS transistor is formed on the memory cell region a of the semiconductor substrate 300, and the electric fuse structure is formed on the fuse region B of the semiconductor substrate 300.
The device isolation layer 301 may be formed on the semiconductor substrate 300 to define an active region, the gate electrode 310g may be formed to intersect the active region, and impurity regions may be formed in portions of the semiconductor substrate 300 located at respective sides of the gate electrode 310 g. The first interlayer insulating layer 320 may be on the semiconductor substrate 300 provided with the MOS transistor and the electrical fuse structure. The cell contact plug 321 may be electrically connected to the MOS transistor through the first interlayer insulating layer 310.
The first interconnection line 325 may be disposed on the first interlayer insulating layer 320 of the memory cell region a. Each of the first interconnection lines 325 may be electrically connected to at least one cell contact plug 321. The second interlayer insulating layer 330 may be disposed on the first interlayer insulating layer. The second interconnection line 335 may be disposed in the second interlayer insulating layer 330. The line width of the second interconnect lines 335 may be greater than the line width of the first interconnect lines 325.
In addition, a third interlayer insulating layer 340 may be disposed on the second interlayer insulating layer 330. The third interconnection lines 345 may be disposed in the third interlayer insulating layer 340. The line width of the third interconnection lines 345 may be greater than the line width of the second interconnection lines 335.
According to the embodiment in fig. 25A, the fuse link 310f may be formed on the device isolation layer 301 of the fuse region B, and a top surface of the fuse link 310f may be covered with the capping dielectric 315. The fuse link 310f may be formed simultaneously with the gate electrode 310g of the memory cell region a, and may be formed of a first metal material. The first metal material may be formed of at least one of tungsten (W), aluminum (Al), copper (Cu), and a copper alloy. Examples of the copper alloy include copper-based materials containing at least one of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and Zr In a small amount or a predetermined amount.
In the fuse region B, the first contact plug 321a, the second contact plug 321B, and the dummy metal plug 321d may be connected to the fuse link 310f through the first interlayer insulating layer 320. The dummy metal plug 321d may include a barrier metal layer and a metal layer. The barrier metal layer may be formed of a second metal material different from the first metal material. The metal layer may be formed of a third metal material. The dummy metal plug 321d may be formed simultaneously with the cell contact plug 321 of the memory cell region a.
The first conductive pattern 325a, the second conductive pattern 325B, and the dummy metal pattern 325d may be disposed on the first interlayer insulating layer 320 of the fuse region B. The first conductive pattern 325a may be electrically connected to the first contact plug 321a, and the second conductive pattern 325b may be electrically connected to the second contact plug 321 b. The dummy metal pattern 325d may contact the top surface of the dummy metal plug 321 d. The first conductive pattern 325a, the second conductive pattern 325b, and the dummy metal pattern 325d may be formed simultaneously with the first interconnection line 325 of the memory cell area a.
According to the embodiment in fig. 25B, the electric fuse structure of the fuse region B may be formed simultaneously with the first interconnection line 325 of the memory cell region a. The fuse link 325f of the electrical fuse structure may be formed on the first interlayer insulating layer 320 and may be separated from the top surface of the semiconductor substrate 300. The first interconnection line 325 and the fuse link 325f may be formed of a first metal material, and a top surface of the fuse link 325f may be covered with a cover dielectric 327.
In the fuse region B, the first contact plug 331a, the second contact plug 331B, and the dummy metal plug 331d may be connected to the fuse link 310f through the second interlayer insulating layer 330 and the capping dielectric 327. The dummy metal plug 331d may include a barrier metal layer and a metal layer. The barrier metal layer may be formed of a second metal material different from the first metal material. The metal layer is formed of a third metal material.
The first conductive pattern 335a, the second conductive pattern 335B, and the dummy metal pattern 335d may be disposed on the second interlayer insulating layer 330 of the fuse region B. The first conductive pattern 335a may be electrically connected to the first contact plug 331a, and the second conductive pattern 335b may be electrically connected to the second contact plug 331 b.
According to the embodiment in fig. 25C, the electric fuse structure of the fuse region B may be formed simultaneously with the third interconnection lines 345 of the memory cell region a. The electrical fuse structure may include a fuse link 345f spaced apart from the top surface of the semiconductor substrate 300. The third interconnection line 345 and the fuse link 345f may be formed of a first metal material, and a top surface of the fuse link 345f may be covered with a capping dielectric 347.
In the fuse region B, the first contact plug 351a, the second contact plug 351B, and the dummy metal plug 351d may be connected to the fuse link 345f through the third interlayer insulating layer 340 and the capping dielectric 347. The dummy metal plug 351d may include a barrier metal layer formed of a second metal material different from the first metal material and a metal layer formed of a third metal material.
The first conductive pattern 353a, the second conductive pattern 353B, and the dummy metal pattern 353d may be disposed on the third interlayer insulating layer 340 of the fuse region B. The first conductive pattern 353a may be electrically connected to the first contact plug 351a, and the second conductive pattern 353b may be electrically connected to the second contact plug 351 b.
Fig. 26 illustrates an embodiment of a memory system 1100 including a semiconductor device according to any one of the preceding embodiments. Referring to fig. 26, the memory system 1100 may be applied to, for example, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, and/or all devices that can transmit and/or receive data in a wireless communication environment.
The memory system 1100 includes a controller 1110, an input/output device 1120 (e.g., a keyboard and/or a display device), a memory 1130, an interface 1140, and a bus 1150. The memory 1130 and the interface 1140 may communicate with each other through a bus 1150.
The controller 1110 may include a microprocessor, digital signal processor, microcontroller, and/or other processing device similar to a microprocessor, digital signal processor, microcontroller. The memory 1130 may be used to store instructions that are executed by the controller 1110. Input/output device 1120 may receive and/or transmit data and/or signals from/to the exterior of system 1100. For example, input/output devices 1120 may include a keyboard, a keypad, and/or a display.
The memory 1130 may include the semiconductor device according to any one of the foregoing embodiments. The memory 1130 may also include different types of memory, for example, volatile storage such as random access memory and/or other types of memory. The interface 1140 may transmit data to and/or receive data from a communication network.
Fig. 27 shows an embodiment of a memory card 1200 including a semiconductor device according to any one of the foregoing embodiments. Referring to fig. 27, a memory card 1200 may have a storage capacity of a large capacity or other predetermined capacity and may include a semiconductor storage device 1210 according to any one of the foregoing embodiments. The memory card 1200 includes a memory controller 1220 that can control data exchange between a host and the semiconductor memory device 1210.
A Static Random Access Memory (SRAM)1221 can be used as an operation memory of, for example, a Central Processing Unit (CPU) 1222. The host interface 1223 may include a data exchange protocol of a host that can be connected to the memory card 1200. Error correction block 1224 may detect and/or correct errors in data read from multi-bit semiconductor memory device 1210.
The memory interface 1225 may interface with the semiconductor memory device 1210. The processing unit 1222 may perform control operations for exchanging data of the memory controller 1220. The memory card 1200 may include, for example, a ROM for storing code, instructions, or other information for connecting with a host.
Fig. 28 illustrates an embodiment of an information processing system 1300 including a semiconductor device according to any one of the foregoing embodiments. Referring to fig. 28, an information processing system 1300 includes a memory system 1310 having a semiconductor device.
Storage system 1310 may be mounted to an information handling system, which may be a mobile device and/or a desktop computer, for example. The information handling system 1300 may include a modem 1320, a Central Processing Unit (CPU)1330, RAM 1340, and a user interface 1350 electrically connected to the system bus 1360. The memory system 1310 may be configured in a similar manner to fig. 20A and 20B, and may include a semiconductor device (e.g., flash memory) 1311 and a memory controller 1312.
The storage system 1310 may be, for example, a solid state drive SSD, and may store data to be processed by the CPU 1330 or already processed by the CPU 1330 and/or data input from an external source. The information processing system 1300 can reliably store a large amount of data or a predetermined amount of data in the storage system 1310. Memory system 1310 may conserve resources for error correction and may also provide high-speed data exchange functionality. In one embodiment, the information processing system 1300 may include an application chipset, a camera image processor (CIS), and/or an input/output device.
According to one or more of the foregoing embodiments, the electrical fuse structure includes a dummy metal plug attached to the fuse link. The fuse link may be formed of a first metal material, and the dummy metal plug may include a second metal material. Therefore, during the process of programming the electrical fuse structure, the driving force caused by electromigration and the temperature gradient of the fuse link may be controlled to increase the total driving force applied to the fuse link. As a result, the electrical fuse structure can be programmed with a reduced operating voltage.
According to one or more of the foregoing embodiments, the total driving force applied to the fuse link may be controlled by adjusting the volume or contact area of the dummy metal plugs and/or the number of the dummy metal plugs. In addition, the position of the dummy metal plug may be adjusted to control the position of a void to be formed in a programming process of the electrical fuse structure.
Example embodiments have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to one of ordinary skill in the art from the time of filing the present application, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless otherwise indicated. It will, therefore, be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims (18)

1. An electrical fuse structure of a semiconductor device, the electrical fuse structure comprising:
a fuse link of a first metal material connecting the cathode and the anode;
a cover dielectric covering a top surface of the fuse link;
a dummy metal plug penetrating the cover dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer includes a second metal material different from the first metal material;
a dummy metal pattern on a top surface of the dummy metal plug; and
dummy fuses located at respective sides of the fuses,
wherein the dummy metal pattern has a thickness greater than that of the fuse links and a width less than a distance between the dummy fuse links, and
wherein the width of the fuse link is smaller than the width of the anode and the width of the cathode.
2. The electrical fuse structure as recited in claim 1, wherein a plurality of dummy metal plugs are located between the anode and the cathode.
3. The electrical fuse structure as recited in claim 1, wherein the dummy metal plug extends in a direction perpendicular to a longitudinal axis of the fuse link.
4. The electrical fuse structure as recited in claim 1, wherein:
the fuse link will conduct the programming current, an
The dummy metal plug alters the temperature gradient in the fuse link while the fuse link conducts the programming current.
5. The electrical fuse structure as recited in claim 4, wherein:
the fuse link includes a first region in contact with the dummy metal plug and a second region in contact with the capping dielectric, and
the temperature of the fuse link has a maximum value at the second region when the fuse link conducts the programming current.
6. The electrical fuse structure as recited in claim 1, wherein:
the fuse link includes a first area in contact with the dummy metal plug and a second area in contact with the capping dielectric,
the electrical fuse structure will conduct a programming current, an
During the supplying of the programming current, a first electrical actuation force caused by electromigration at the first region of the fuse link is different from a second electrical actuation force caused by electromigration at the second region of the fuse link.
7. An electrical fuse structure of a semiconductor device, the electrical fuse structure comprising:
a fuse link of a first metal material connecting the cathode and the anode;
an interlayer insulating layer covering the anode, the cathode and the fuse;
a cover dielectric between the top surface of the fuse link and the interlayer insulating layer, the cover dielectric including an insulating material different from an insulating material of the interlayer insulating layer;
a dummy metal plug penetrating the interlayer insulating layer and the cover dielectric and contacting the fuse link, the dummy metal plug including a barrier metal layer between the metal layer and the fuse link, wherein the barrier metal layer includes a second metal material different from the first metal material;
a dummy metal pattern on a top surface of the dummy metal plug; and
dummy fuses located at respective sides of the fuses,
wherein the dummy metal pattern has a thickness greater than that of the fuse links and a width less than a distance between the dummy fuse links, and
wherein the barrier metal layer covers a bottom surface and a side surface of the metal layer.
8. The electrical fuse structure as recited in claim 7, wherein:
the first metallic material includes at least one of tungsten, aluminum, copper, and copper alloy, and the second metallic material includes at least one of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, and combinations thereof.
9. The electrical fuse structure as claimed in claim 7, wherein the barrier metal layer is thicker on a bottom surface of the metal layer than on a side surface of the metal layer.
10. The electrical fuse structure as recited in claim 7, wherein:
the fuse link will conduct the programming current, an
In the programmed state, the fuse link has a void between the anode and the dummy metal plug.
11. The electrical fuse structure as recited in claim 10, wherein:
the distance between the void and the dummy metal plug is smaller than the distance between the void and the anode.
12. An electrical fuse structure of a semiconductor device, the electrical fuse structure comprising:
a fuse connecting the anode to the cathode and to be programmed based on a programming current;
a dummy metal plug in contact with the fuse link;
a dummy metal pattern on a top surface of the dummy metal plug; and
dummy fuses located at respective sides of the fuses,
wherein the dummy metal pattern has a thickness greater than that of the fuse links and a width less than a distance between the dummy fuse links, and
wherein the fuse link includes a first metal material, the dummy metal plug includes a second metal material different from the first metal material, the dummy metal plug changes an electrical driving force and a thermal driving force when the fuse link conducts a programming current, wherein the electrical driving force and the thermal driving force are based on electro-migration and thermo-migration in the fuse link.
13. The electrical fuse structure as recited in claim 12, wherein:
the dummy metal plug includes a barrier metal layer between the metal layer and the fuse link, and
the barrier metal layer includes a second metal material.
14. The electrical fuse structure as recited in claim 12, wherein an electrical conductivity of the first metal material is greater than an electrical conductivity of the second metal material.
15. The electrical fuse structure as recited in claim 12, wherein:
the total driving force has a maximum value between the anode and the dummy metal plug when the fuse link conducts the programming current, and
the total driving force is based on the sum of the electrical driving force and the thermal driving force.
16. The electrical fuse structure as recited in claim 12, further comprising:
an interlayer insulating layer covering the anode, the cathode and the fuse; and
and a cover dielectric between the top surface of the fuse link and the interlayer insulating layer, the cover dielectric including an insulating material different from that of the interlayer insulating layer, wherein the fuse link includes a first region in contact with the dummy metal plug and a second region in contact with the cover dielectric.
17. The electrical fuse structure as recited in claim 16, wherein a first electrical actuation force resulting from electromigration at the first region of the fuse link is less than a second electrical actuation force resulting from electromigration at the second region of the fuse link.
18. The electrical fuse structure as recited in claim 17, wherein a temperature of the fuse link has a maximum value at the second region when the fuse link conducts the programming current.
CN201810309622.0A 2013-10-11 2014-10-09 Electric fuse structure of semiconductor device Active CN108305867B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361889911P 2013-10-11 2013-10-11
US61/889,911 2013-10-11
KR10-2014-0022774 2014-02-26
KR1020140022774A KR102096614B1 (en) 2013-10-11 2014-02-26 e-fuse structure of a semiconductor device
CN201410528528.6A CN104576604B (en) 2013-10-11 2014-10-09 The electric fuse structure of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201410528528.6A Division CN104576604B (en) 2013-10-11 2014-10-09 The electric fuse structure of semiconductor device

Publications (2)

Publication Number Publication Date
CN108305867A CN108305867A (en) 2018-07-20
CN108305867B true CN108305867B (en) 2021-06-15

Family

ID=53037021

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201810309622.0A Active CN108305867B (en) 2013-10-11 2014-10-09 Electric fuse structure of semiconductor device
CN201410528528.6A Active CN104576604B (en) 2013-10-11 2014-10-09 The electric fuse structure of semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201410528528.6A Active CN104576604B (en) 2013-10-11 2014-10-09 The electric fuse structure of semiconductor device

Country Status (3)

Country Link
KR (1) KR102096614B1 (en)
CN (2) CN108305867B (en)
TW (1) TWI691054B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786364A (en) * 2017-11-14 2019-05-21 中芯国际集成电路制造(上海)有限公司 Fusing structure and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156333A (en) * 1995-11-15 1997-08-06 日本电气株式会社 Semiconductor device
JP2008277412A (en) * 2007-04-26 2008-11-13 Renesas Technology Corp Fusing element
US20090039480A1 (en) * 2007-08-07 2009-02-12 Kyoung-Woo Lee Semiconductor device and methods of forming the same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115535A (en) * 2001-10-04 2003-04-18 Hitachi Ltd Semiconductor integrated circuit device
TWI274410B (en) * 2005-09-05 2007-02-21 United Microelectronics Corp Fuse structure for a semiconductor device
US20070252238A1 (en) * 2006-04-27 2007-11-01 Charles Lin Tungstein plug as fuse for IC device
JP5132162B2 (en) * 2006-08-11 2013-01-30 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
JP5230105B2 (en) * 2007-01-10 2013-07-10 ルネサスエレクトロニクス株式会社 Semiconductor device
US7411818B1 (en) * 2007-02-07 2008-08-12 International Business Machines Corporation Programmable fuse/non-volatile memory structures using externally heated phase change material
US20090243032A1 (en) * 2008-03-27 2009-10-01 Shi-Bai Chen Electrical fuse structure
JP2010040904A (en) * 2008-08-07 2010-02-18 Nec Electronics Corp Semiconductor device and method of manufacturing the same
CN101752344B (en) * 2008-12-08 2012-11-21 联华电子股份有限公司 Contact plug electric fuse structure and method for manufacturing contact plug electric fuse device
CN101771021B (en) * 2008-12-29 2013-07-24 联华电子股份有限公司 Electric fuse structure and manufacture method thereof
US8890260B2 (en) * 2009-09-04 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Polysilicon design for replacement gate technology
KR20110114047A (en) * 2010-04-12 2011-10-19 주식회사 하이닉스반도체 Semiconductor device
KR20110135501A (en) * 2010-06-11 2011-12-19 주식회사 하이닉스반도체 Semiconductor device with fuse part
CN102347269B (en) * 2010-07-30 2014-03-12 上海丽恒光微电子科技有限公司 Fuse structure and method for forming same
US20120154102A1 (en) * 2010-12-16 2012-06-21 Shi-Bai Chen Electrical fuse structure
US8716831B2 (en) * 2011-09-29 2014-05-06 Broadcom Corporation One time programmable structure using a gate last high-K metal gate process
CN103208456B (en) * 2013-03-22 2016-12-28 上海华虹宏力半导体制造有限公司 The forming method of semiconductor structure
CN104681422B (en) * 2013-11-27 2018-09-07 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1156333A (en) * 1995-11-15 1997-08-06 日本电气株式会社 Semiconductor device
JP2008277412A (en) * 2007-04-26 2008-11-13 Renesas Technology Corp Fusing element
US20090039480A1 (en) * 2007-08-07 2009-02-12 Kyoung-Woo Lee Semiconductor device and methods of forming the same

Also Published As

Publication number Publication date
CN104576604A (en) 2015-04-29
TWI691054B (en) 2020-04-11
TW201528477A (en) 2015-07-16
CN108305867A (en) 2018-07-20
CN104576604B (en) 2018-04-24
KR102096614B1 (en) 2020-04-03
KR20150044789A (en) 2015-04-27

Similar Documents

Publication Publication Date Title
US9368445B2 (en) E-fuse structure of semiconductor device
KR100918161B1 (en) Vertically oriented nano-fuse and nano-resistor circuit elements
EP2313921B1 (en) Metal wiring structure for integration with through substrate vias
US10727181B2 (en) Fuse structure having air dummy fuses and semiconductor device including the same
TWI666734B (en) Elevationally-extending string of memory cells and methods of forming an elevationally-extending string of memory cells
US7615448B2 (en) Method of forming low resistance void-free contacts
US8970040B1 (en) Contact structure and forming method
US9679903B2 (en) Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse
US20130119509A1 (en) Forming beol line fuse structure
JP2007243176A (en) Fuse for ic, and its manufacturing method (fuse structure with terminal parts existing in different heights which is electrically programmable, and its manufacturing method)
US9935049B2 (en) E-fuse structure of semiconductor device
KR102021978B1 (en) Semiconductor device having blocking layer and method of forming the same
CN108305867B (en) Electric fuse structure of semiconductor device
US20120098141A1 (en) Semiconductor device and method for forming the same
CN101393904B (en) Semiconductor devices including interconnections and contact plugs and methods of forming the same
US20160379877A1 (en) Optimized wires for resistance or electromigration
KR20150032609A (en) Fuse structure and method of blowing the same
US6686241B2 (en) Method of forming low-resistivity connections in non-volatile memories
TWI572074B (en) Resistive random access memory and method for manufacturing the same
CN110556380B (en) Fuse unit, fuse bit cell structure and manufacturing method thereof
US20230343698A1 (en) Interconnect structure of semiconductor device including metal pattern or via structure with sidewall spacer structure
KR100483201B1 (en) Method of forming a metal wiring in a semiconductor device
US20100005441A1 (en) Method of Designing a Mask Layout
KR20230150772A (en) Method of manufacturing semiconductor device
WO2007067860A2 (en) Low- resistance void-free contacts for eeprom devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant