CN102347269B - Fuse structure and method for forming same - Google Patents
Fuse structure and method for forming same Download PDFInfo
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- CN102347269B CN102347269B CN201010244197.5A CN201010244197A CN102347269B CN 102347269 B CN102347269 B CN 102347269B CN 201010244197 A CN201010244197 A CN 201010244197A CN 102347269 B CN102347269 B CN 102347269B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A fuse structure and a method for forming the same are disclosed. The method is characterized in that: a semiconductor substrate is provided, wherein a circuit structure is formed on the semiconductor substrate and a metal interconnection layer is formed on the circuit structure; a fuse and an interconnection structure of the fuse and the metal interconnection layer are formed on the metal interconnection layer, wherein a material of the fuse is selected from polycrystalline germanium silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon. Resistances of the polycrystalline germanium silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon are high. When a polycrystalline germanium silicon fuse, a polycrystalline germanium fuse, an amorphous silicon fuse, an amorphous germanium fuse or an amorphous germanium silicon fuse are fused, a needed fusing current is small so that a relevant circuit structure is not easy to be destroyed. The fuse structure formed by using the method does not occupy a chip area when stacking on the metal interconnection layer. Therefore, the chip area can be saved and manufacturing costs can be reduced. A formation process is simple.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method that forms fuse-wires structure.
Background technology
Semiconductor integrated circuit comprises fuse-wires structure, is conventionally applied in output logic value two aspects of circuit reparation and change memory.Aspect circuit reparation, when circuit is repaired, by the fuse opening being connected with faulty circuit, make out of order circuit structure unavailable, with the circuit of redundancy, replace out of order circuit.Changing aspect the output logic value of memory blowing or not blowing and determine the logical value of exporting by fuse.
In prior art, there is several frequently seen fuse-wires structure.The first fuse-wires structure, is directly used the metal interconnecting wires of metal interconnecting layer as fuse, when circuit is repaired, utilize laser by fuse cut, so its cost is higher.The second fuse-wires structure is at one-time programming circuit (one time programm, OTP), programmed circuit (multiple time programm repeatedly, MTP) or EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-Only Memory, EEPROM) fuse-wires structure using in, this kind of fuse-wires structure and OTP/MTP/EEPROM device non-stacking formation, waste chip area, and complex process, caused cost high.The third fuse-wires structure is polysilicon fuse structure, it uses CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) polysilicon gate in technique is as fuse, because the resistance of polysilicon is large, therefore its blowout current is little, can not destroy relevant circuit structure, but it takies COMS area, therefore make the manufacturing cost of semiconductor device increase.
In prior art, there are many patents about fuse, disclosed fuse of Chinese patent that for example application number is 200480011464 and forming method thereof, and the application number disclosed semiconductor fuse of Chinese patent that is 99108915.Yet, all do not solve the shortcoming in above-described prior art.
Summary of the invention
The problem that will solve of the present invention is to provide a kind of method that forms fuse-wires structure, in CMOS postchannel process, carries out, and the stack of the fuse-wires structure of formation and cmos circuit, can saving chip area, reduces costs; And technique is simple.
For addressing the above problem, the invention provides a kind of method that forms fuse-wires structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with circuit structure, on described circuit structure, be formed with metal interconnecting layer;
On described metal interconnecting layer, form the interconnection structure of fuse and fuse and described metal interconnecting layer, described fuse materials is selected from poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.
Optionally, the described interconnection structure that forms fuse fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
In described first medium layer, form the first embolism, this first embolism bottom contacts with the interconnection line of described metal interconnecting layer;
On described first medium layer and the first embolism, form fuse layer, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical described fuse layer forms fuse, and this fuse contacts with described the first embolism;
On described fuse and first medium layer, form second medium layer;
In described first medium layer and second medium layer, form the second embolism, this second embolism bottom contacts with the interconnection line of described metal interconnecting layer;
On described the second embolism, form weld pad and interconnection line.
Optionally, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
In described first medium layer, form the first through hole;
Deposit described fuse materials, in described the first through hole, form the first embolism, on described first medium layer, form fuse layer, described the first embolism bottom contacts with the interconnection line of described metal interconnecting layer;
Graphical described fuse layer forms fuse, and this fuse contacts with described the first embolism;
On described fuse and first medium layer, form second medium layer;
In described first medium layer and second medium layer, form the second through hole, in described second medium layer, form groove and opening;
Fill interconnection line and weld pad that described the second through hole, groove and opening form respectively the second embolism, connect described the second embolism, this second embolism bottom contacts with the interconnection line of described metal interconnecting layer.
Optionally, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
On described first medium layer, form fuse layer, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical described fuse layer forms fuse;
On described fuse and first medium layer, form second medium layer;
In described first medium layer, form the first embolism, described the first embolism bottom contacts with described fuse, in described first medium layer and second medium layer, forms the second embolism, and this second embolism bottom contacts with the interconnection line of described metal interconnecting layer;
On described second medium layer, form interconnection line and weld pad, connect described the first embolism and the second embolism.
Optionally, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
On described first medium layer, form fuse layer, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical described polycrystalline germanium silicon layer, polycrystalline germanium layer, amorphous silicon layer, amorphous germanium layer or amorphous germanium silicon layer form fuse;
On described fuse and first medium layer, form second medium layer;
In described first medium layer, form the first through hole, in described first medium layer and second medium layer, form the second through hole, in described second medium layer, form groove and opening;
Fill described the first through hole, the second through hole, groove and opening and form respectively the first embolism, the second embolism, interconnection line and weld pad, described the first embolism bottom contacts with described fuse, the second embolism bottom contacts with the interconnection line of described metal interconnecting layer, and described interconnection line and weld pad connect described the first embolism and the second embolism.
Optionally, also comprise: on described second medium layer, form opening, expose described fuse.
Optionally, described first medium layer, second medium layer are silicon dioxide, carborundum, silicon nitride, silicon oxynitride or their combination.
Optionally, described interconnection line and weld pad are aluminum interconnecting and aluminium welding pad, and described the first embolism, the second embolism are tungsten plug.
Optionally, described interconnection line and weld pad are copper interconnecting line and copper pad, and described the second embolism is copper embolism.
Optionally, described interconnection line and weld pad are copper interconnecting line and copper pad, and described the first embolism, the second embolism are copper embolism.
The present invention also provides the fuse-wires structure that method forms described in more than one.
Compared with prior art, the present invention has the following advantages:
Can, after forming circuit structure and metal interconnecting layer, on metal interconnecting layer, form the interconnection structure of poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse and fuse and metal interconnecting layer.Because the resistance value of poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium, amorphous germanium silicon is high, when fusing poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse, required blowout current is little, can not destroy relevant circuit structure; And the fuse-wires structure that the method forms is stacked on metal interconnecting layer, can chip occupying area, so saving chip area, reduce manufacturing cost; And its formation technique is simple.
Accompanying drawing explanation
Fig. 1 is the flow chart that the present invention forms fuse-wires structure;
Fig. 2 is the cross-sectional view of substrate provided by the invention;
Fig. 3 a～3i is the cross-sectional view of the formation fuse-wires structure of the present invention's the first specific embodiment;
Fig. 4 a～4f is the cross-sectional view of the formation fuse-wires structure of the present invention's the second specific embodiment;
Fig. 5 a～5g is the cross-sectional view of the formation fuse-wires structure of the present invention's the 3rd specific embodiment;
Fig. 6 a～6c is the cross-sectional view of the formation fuse-wires structure of the present invention's the 4th specific embodiment.
Embodiment
In prior art, have and use polysilicon as the fuse-wires structure of fuse, yet, because the depositing temperature of polysilicon is more than 600 ℃, therefore must before CMOS last part technology, form, and walk abreast at same plane with cmos circuit, so fuse-wires structure can take the area of chip, increase cost.Inventor studies intensively repeatedly, hope can find a kind of can be formed on CMOS last part technology after, be stacked on cmos circuit fuse-wires structure that can chip occupying area.
The method of the formation fuse-wires structure of the specific embodiment of the invention after forming circuit structure and metal interconnecting layer, forms the interconnection structure of fuse and many fuses and metal interconnecting layer on metal interconnecting layer.
For the spirit that those skilled in the art be can better understand the present invention, be described with reference to the accompanying drawings the method for the formation fuse-wires structure of the specific embodiment of the invention.
Fig. 1 is the flow chart that the present invention forms fuse-wires structure, and with reference to figure 1, the method for the formation fuse-wires structure of the specific embodiment of the invention, comprising:
Step S1, provides Semiconductor substrate, in described Semiconductor substrate, is formed with circuit structure, on described circuit structure, is formed with metal interconnecting layer;
Step S2 forms the interconnection structure of fuse and fuse and described metal interconnecting layer on described metal interconnecting layer, and the material of described fuse is selected from poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.
Below in conjunction with specific embodiment, describe the method for the formation fuse-wires structure of the specific embodiment of the invention in detail.
In conjunction with reference to figure 1 and Fig. 2, perform step S1, Semiconductor substrate 20 is provided, in described Semiconductor substrate, be formed with circuit structure, on described circuit structure, be formed with metal interconnecting layer: described Semiconductor substrate 20 can be monocrystalline silicon or SiGe; Also can be silicon-on-insulator (SOI); Or the material that can also comprise other, such as III-V compounds of group such as GaAs.In described Semiconductor substrate 20, there is certain isolation structure, can be for shallow trench isolation be from (STI), local field oxidation isolation (LOCOS).In described Semiconductor substrate, be formed with device layer 21, in this device layer 21, be formed with circuit structure, concrete circuit structure is not shown in diagram, this circuit structure can be various cmos circuit structures, for example, can be eeprom memory circuit structure.On device layer 21, forming metal interconnecting layer 22, illustrate two interconnection lines 221,222 in figure, has been signal effect, and the layout of interconnection line is according to the difference of actual circuit structure and difference.Fuse-wires structure of the present invention (back end of line) after completing the last part technology of semiconductor technology carries out, the fuse forming is connected with the interconnection line in metal interconnecting layer, by interconnection line, connect to relevant circuit structure, do not relate in the present invention the improvement of circuit structure and metal interconnecting wires, and the circuit structure in the present invention and metal interconnecting wires are circuit structure conventional in this area and metal interconnecting wires, at this, it are not elaborated.
After execution of step S1, perform step S2, on described metal interconnecting layer, form the interconnection structure of fuse and fuse and described metal interconnecting layer.In this first specific embodiment of the present invention, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
Step S31 forms first medium layer on described metal interconnecting layer;
Step S32 forms the first embolism in described first medium layer, and this first embolism bottom contacts with described metal interconnecting layer;
Step S33 forms fuse layer on described first medium layer and the first embolism, and the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Step S34, graphical described fuse layer forms fuse, and this fuse contacts with described the first embolism;
Step S35 forms second medium layer on described fuse and first medium layer;
Step S36 forms the second embolism in described first medium layer and second medium layer, and this second embolism bottom contacts with described metal interconnecting layer;
Step S37 forms weld pad and interconnection line on described the second embolism.
Fig. 3 a～3h is the cross-sectional view of the formation fuse-wires structure of the present invention's the first specific embodiment, describes the method for the formation fuse-wires structure of this first specific embodiment in conjunction with Fig. 3 a～3h in detail.
With reference to figure 3a, execution step S31, on described metal interconnecting layer 22, form first medium layer 31, utilize chemical vapour deposition (CVD) to deposit on described metal interconnecting layer 22 and form first medium layer 31, this first medium layer is silicon dioxide, and in other embodiments, first medium layer also can play for other dielectric layer of insulation buffer action, for example carborundum, silicon nitride, silicon oxynitride, can be also the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 3b, execution step S32, at interior formation the first embolism 32 of described first medium layer 31, these the first embolism 32 bottoms contact with described metal interconnecting layer, the concrete grammar that forms the first embolism 32 is: utilize photoetching, the graphical described first medium layer 31 of etching technics to form through hole, fill metal and form the first embolism 32, in through hole in this specific embodiment, the metal of filling is tungsten, and the first embolism 32 is tungsten plug.This forms the common practise that the technique of the first embolism 32 is those skilled in the art, does not describe in detail.
With reference to figure 3c, execution step S33, on described first medium layer 31 and the first embolism 32, form fuse layer 33, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon, fuse layer 33 thickness are 500 dust～8000 dusts, and its specifically formation method is the chemical phase deposition CVD in technical field of semiconductors, for example PECVD, LPCVD, depositing temperature is at 150 ℃～500 ℃.
Step S34, graphical described fuse layer 33 form fuses 33 ', fuse 33 ' contact with described the first embolism 32, with reference to figure 3d, in this specific embodiment, utilize photoetching, the graphical fuse layer formation of etching technics fuse 33 '.
With reference to figure 3e, execution step S35, described fuse 33 ' and first medium layer 31 on form second medium layer 34, utilize chemical vapour deposition (CVD) described fuse 33 ' and first medium layer 31 on form second medium layer 34, this second medium layer is silicon dioxide layer, in other embodiments, second medium layer also can play for other dielectric layer of insulation buffer action, for example carborundum, silicon nitride, silicon oxynitride, can be also the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 3f, execution step S36, at described first medium layer 31 and interior formation the second embolism 35 of second medium layer 34, these the second embolism 35 bottoms contact with the interconnection line 221,222 in described metal interconnecting layer 22, the concrete grammar that forms the second embolism 35 is: utilize photoetching, the graphical described first medium layer 31 of etching technics and second medium layer 34 to form through hole at first medium layer 31 and second medium layer 34, in through hole, fill metal and form the second embolism 35, in this specific embodiment, the metal of filling is tungsten, and the second embolism 35 is tungsten plug.This forms the common practise that the technique of the second embolism 35 is those skilled in the art, does not describe in detail.
With reference to figure 3g, 3h, execution step S37, on described the second embolism 35, form weld pad 37 and interconnection line (not shown), be specially: first on the surface of second medium layer 34 and the second embolism 35 formation, form metal level 36 (with reference to figure 3g), in this specific embodiment, metal level 36 is aluminium (Al) layer, utilizes photoetching, the graphical described metal level 36 of etching technics, form weld pad 37 (with reference to figure 3h) and interconnection line (not shown), with reference to figure 3h.The quantity of described the second embolism 35 can be for a plurality of, and wherein, some second embolisms 35 connect weld pad 37, and some second embolisms 35 connect interconnection line, and two the second embolisms 35 that are connected with weld pad 37 are schematically shown in figure.
Complete after above step, the fuse-wires structure of the present invention's the first specific embodiment forms, and next needs, by fuse 33 ' come out, so that when blow out fuse, molten metal can evaporate, can not remain on chip.If molten metal can not evaporate away, after metal is cooling, reconnect together possibly, even if do not link together, remain in chip, also can affect the performance of chip.
With reference to figure 3i, after forming fuse-wires structure, utilize photoetching and plasma etch process on second medium layer 34, to form opening 38, expose fuse 33 ', can expose part fuse, also can expose whole fuses.
With reference to figure 3i, the fuse-wires structure of the present invention's the first specific embodiment is stacking to be formed on metal interconnecting layer 22, and this fuse-wires structure comprises: fuse 33 ' and, the interconnection structure of fuse and described metal interconnecting layer.Wherein, described interconnection structure comprises: connect fuse 33 ' with metal interconnecting layer 22 in the first embolism 32 of interconnection line 221,222, interconnection line and weld pad 37, the second embolism 35 that interconnection line and weld pad 37 are connected with interconnection line 221,222 in metal interconnecting layer 22.
In the second specific embodiment of the present invention, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
Step S41 forms first medium layer on described metal interconnecting layer;
Step S42 forms the first through hole in described first medium layer;
Step S43, deposits described fuse materials, in described the first through hole, forms the first embolism, on described first medium layer, forms fuse layer, and described the first embolism bottom contacts with the interconnection line of described metal interconnecting layer;
Step S44, graphical described many fuse layers form fuse, and this fuse contacts with described the first embolism;
Step S45 forms second medium layer on described fuse and first medium layer;
Step S46 forms the second through hole in described first medium layer and second medium layer, in described second medium layer, forms groove and opening;
Step S47, fills interconnection line and weld pad that described the second through hole, groove and opening form respectively the second embolism, connect described the second embolism, and this second embolism bottom contacts with the interconnection line of described metal interconnecting layer.
Fig. 4 a～4f is the cross-sectional view of the formation fuse-wires structure of the present invention's the second specific embodiment, describes the method for the formation fuse-wires structure of this second specific embodiment in conjunction with Fig. 4 a～4f in detail.
With reference to figure 4a, execution step S41, on described metal interconnecting layer 22, form first medium layer 41, utilize chemical vapour deposition (CVD) to deposit on described metal interconnecting layer 22 and form first medium layer 41, this first medium layer is silicon dioxide, and in other embodiments, first medium layer also can play for other dielectric layer of insulation buffer action, for example carborundum, silicon nitride, silicon oxynitride, can be also the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
After execution of step S41, with reference to figure 4b, execution step S42, at interior formation the first through hole of described first medium layer 41; Then perform step S43, deposit described fuse materials, form the first embolism 42 in described the first through hole, on described first medium layer 41, form fuse layer 43, described the first embolism 42 bottoms contact with the interconnection line 221,222 of described metal interconnecting layer.In this second specific embodiment, form after the first through hole, utilize chemical phase deposition CVD, PECVD for example, LPCVD, depositing temperature is within the scope of 150 ℃～500 ℃, deposition fuse materials, is filled in fuse materials in the first through hole, forms the first embolism 42 in the first through hole, and on described first medium layer 41, forming the fuse layer 43 that thickness is 500 dust～8000 dusts, this fuse materials is poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.In this second specific embodiment, the first embolism 42 is poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon embolism.
Form after fuse layer 43, with reference to figure 4c, execution step S44, graphical described fuse layer 43 formation fuses 43 '.Utilize the graphical fuse layer 43 of photoetching, etching technics form fuses 43 '.
Form fuse 43 ' after, with reference to figure 4d, perform step S45, described fuse 43 ' and first medium layer 41 on form second medium layer 44.Utilize chemical vapour deposition (CVD) described fuse 43 ' and first medium layer 41 on deposition form second medium layer 44, this second medium layer 44 is silicon dioxide, in other embodiments, second medium layer also can play for other dielectric layer of insulation buffer action, for example carborundum, silicon nitride, silicon oxynitride, can be also the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
Afterwards, with reference to figure 4e, execution step S46 forms the second through hole in described first medium layer and second medium layer, forms groove and opening (not shown) in described second medium layer; Afterwards, execution step S47, fill described the second through hole, groove and opening and form respectively the second embolism 45, interconnection line (not shown) and weld pad 47, these the second embolism 45 bottoms contact with the interconnection line of described metal interconnecting layer, corresponding second embolism that forms of the second through hole, the corresponding interconnection line that forms of groove, the corresponding weld pad that forms of opening.In this second specific embodiment, utilize copper (Cu) technique, be that dual-damascene technics well known in the art forms the second embolism 45, interconnection line (not shown) and weld pad 47, the second embolism 45 is copper embolism, weld pad 47 is copper pad, and interconnection line is copper interconnecting line (not shown).The quantity of described the second embolism 45 is a plurality of, and wherein, some second embolisms 45 are connected with weld pad 47, and some second embolisms 45 are connected with interconnection line, and two the second embolisms 45 that are connected with weld pad 47 are schematically shown in figure.
Complete after above step, the fuse-wires structure of the present invention's the second specific embodiment forms, and next needs, by fuse 43 ' come out, so that when blow out fuse, molten metal can evaporate, can not remain on chip.If molten metal can not evaporate away, after metal is cooling, reconnect together possibly, even if do not link together, remain in chip, also can affect the performance of chip.
With reference to figure 4f, after forming fuse-wires structure, utilize photoetching and plasma etch process on second medium layer 44, to form opening 48, expose fuse 43 ', can expose part fuse, also can expose whole fuses.
With reference to figure 4f, the fuse-wires structure of the present invention's the second specific embodiment is stacking to be formed on metal interconnecting layer 22, and the structure of the fuse-wires structure of itself and the first specific embodiment is basic identical.Just, owing to forming the difference of technique, weld pad 47 and the second embolism 45 are structure as a whole.
In the 3rd specific embodiment of the present invention, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
Step S51 forms first medium layer on described metal interconnecting layer;
Step S52 forms fuse layer on described first medium layer, and the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Step S53, graphical described fuse layer forms fuse;
Step S54 forms second medium layer on described fuse and first medium layer;
Step S55 forms the first embolism in described first medium layer, and described the first embolism bottom contacts with described fuse, in described first medium layer and second medium layer, forms the second embolism, and this second embolism bottom contacts with described metal interconnecting layer;
Step S56 forms interconnection line and weld pad on described second medium layer, connects described the first embolism and the second embolism.
Fig. 5 a～5g is the cross-sectional view of the formation fuse-wires structure of the present invention's the 3rd specific embodiment, describes the method for the formation fuse-wires structure of the 3rd specific embodiment in conjunction with Fig. 5 a～5g in detail.
With reference to figure 5a, execution step S51, on described metal interconnecting layer 22, form first medium layer 51, be specially: utilize chemical vapour deposition (CVD) CVD to deposit on described metal interconnecting layer 22 and form first medium layer 51, this first medium layer 51 is silicon dioxide layer, and in other embodiments, first medium layer also can play for other dielectric layer of insulation buffer action, for example carborundum, silicon nitride, silicon oxynitride, can be also the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 5b, execution step S52, on described first medium layer 51, form fuse layer 52, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon, its concrete formation method is the chemical vapour deposition (CVD) CVD in technical field of semiconductors, PECVD for example, LPCVD, depositing temperature is within the scope of 150 ℃～500 ℃, and deposit thickness is the fuse layer of 500 dust～8000 dusts.
With reference to figure 5c, execution step S53, graphical described fuse layer 52 formation fuses 52 '.Utilize the graphical fuse layer 52 of photoetching, etching technics form fuses 52 '.
With reference to figure 5d, execution step S54, described fuse 52 ' and the surface that forms of first medium layer 51 on form second medium layer 53, be specially: utilize chemical vapour deposition (CVD) CVD to form second medium layer 53, this second medium layer 53 is silicon dioxide layer, and in other embodiments, second medium layer also can play for other dielectric layer of insulation buffer action, for example carborundum, silicon nitride, silicon oxynitride, can be also the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 5e, execution step S55, at interior formation the first embolism 54 of described first medium layer 51, described the first embolism 54 bottoms and described fuse 52 ' contact, at described first medium layer 51 and interior formation the second embolism 55 of second medium layer 53, these the second embolism 55 bottoms contact with the interconnection line 222,221 of described metal interconnecting layer, and specifically formation method is: utilize photoetching, the graphical described second medium layer 53 of etching technics, at interior formation the first through hole of second medium layer 53; Utilize photoetching, the graphical described first medium layer 51 of etching technics and second medium layer 53 at second medium layer 53 and interior formation the second through hole of first medium layer 51, in the first through hole, fill metal and form the first embolism 54, the first embolism 54 bottoms and fuse 52 ' contact, in the second through hole, filling metal forms the second embolism 55, the second embolisms 55 and contacts with the interconnection line 222,221 in metal interconnecting layer.In this specific embodiment, the metal of filling is tungsten, and the first embolism 54 and the second embolism 55 are tungsten plug.
With reference to figure 5f, execution step S56, on described second medium layer 53, form interconnection line (not shown) and weld pad 57, connect described the first embolism 54 and the second embolism 55, its concrete formation method is: on described second medium layer 53, utilize physical vapour deposition (PVD) to form metal level, this metal level is aluminium lamination, then utilizes photoetching, etching technics etching aluminium lamination to form interconnection line (not shown) and weld pad 57, connects described the first embolism 54 and the second embolism 55.The quantity of described the first embolism 54, the second embolism 55 is a plurality of, connection between a plurality of the first embolisms 54 and the second embolism 55 can connect by weld pad 57 or interconnection line (not shown), wherein, some first embolisms 54 are connected by weld pad 57 with the second embolism 55, some first embolisms 54 are connected by interconnection line with the second embolism 55, only the first embolism 54 are schematically shown, the second embolism 55 connects by weld pad 57 in figure.
Complete after above step, the fuse-wires structure of the present invention's the 3rd specific embodiment forms, next need fuse 52 ' come out, with reference to figure 5g, after forming fuse-wires structure, utilize photoetching and plasma etch process to form openings 58 at second medium layer 53, expose fuse 52 ', part fuse can be exposed, also whole fuses can be exposed.
With reference to figure 5f, the fuse-wires structure of the present invention's the 3rd specific embodiment is stacking to be formed on metal interconnecting layer 22, and this fuse-wires structure comprises: fuse 52 ' and, the interconnection structure of fuse and described metal interconnecting layer.Wherein, described interconnection structure comprises: the first embolism 54, the second embolism 55, interconnection line and weld pad 57, the described fuse 52 of the first embolism 54 connection ', interconnection line 221,222 in described the second embolism 55 connection metal interconnection layers 22 connects, and described interconnection line or weld pad 57 are connected the first embolism 54 with the second embolism 55.
In the 4th specific embodiment of the present invention, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
Step S61 forms first medium layer on described metal interconnecting layer;
Step S62 forms fuse layer on described first medium layer, and the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Step S63, graphical described fuse layer forms fuse;
Step S64 forms second medium layer on described fuse and first medium layer;
Step S65 forms the first through hole in described first medium layer, in described first medium layer and second medium layer, forms the second through hole, in described second medium layer, forms groove and opening;
Step S66, fill described the first through hole, the second through hole, groove and opening and form respectively the first embolism, the second embolism, interconnection line and weld pad, described the first embolism bottom contacts with described fuse, the second embolism bottom contacts with the interconnection line of described metal interconnecting layer, and described interconnection line and weld pad connect described the first embolism and the second embolism.
Fig. 6 a～6c is the cross-sectional view of the formation fuse-wires structure of the present invention's the 4th specific embodiment, describes the method for the formation fuse-wires structure of the 4th specific embodiment in conjunction with Fig. 6 a～6c in detail.
In the 4th specific embodiment, step S61, step S62, step S63 and step S64 are identical with step S51, step S52, step S53 and the step S54 of described the 3rd specific embodiment, this is not described in detail, specifically can be referring to the detailed description to correlation step in the 3rd specific embodiment.
Execution of step S61, step S62, step S63 and step S64 form fuse 62 ', after second medium layer 63 and first medium layer 61 (with reference to figure 6a), with reference to figure 6b, execution step S65, at interior formation the first through hole of described second medium layer 63, at described first medium layer 61 and interior formation the second through hole of second medium layer 63, in described second medium layer, form groove and opening (not shown); And step S66, fill described the first through hole, the second through hole, groove and opening and form respectively the first embolism 64, the second embolism 65, interconnection line and weld pad 67, described the first embolism 64 bottoms and described fuse 62 ' contact, the second embolism 65 bottoms contact with the interconnection line 222,221 of described metal interconnecting layer, described interconnection line (not shown) and weld pad 67 connect described the first embolism and the second embolism, corresponding first embolism that forms of the first through hole, corresponding second embolism that forms of the second through hole, the corresponding interconnection line that forms of groove, the corresponding weld pad that forms of opening.In the 4th specific embodiment, utilize copper (Cu) technique, be that dual-damascene technics well known in the art forms the first embolism 64, the second embolism 65, interconnection line (not shown) and weld pad 67, the first embolism 64, the second embolism 65 is copper embolism, weld pad 67 is copper pad, and interconnection line is copper interconnecting line (not shown).The quantity of described the first embolism 64, the second embolism 65 is a plurality of, two the first embolisms 64, the second embolism 65 are schematically shown in figure, connection between a plurality of the first embolisms 64 and the second embolism 65 connects by weld pad 67 or interconnection line (not shown), wherein, some first embolisms 64 are connected by weld pad 67 with the second embolism 65, some first embolisms 64 are connected by interconnection line with the second embolism 65, only the first embolism 64 are schematically shown, the second embolism 65 connects by weld pad 67 in figure.
Complete after above step, the fuse-wires structure of the present invention's the 4th specific embodiment forms, and next needs, by fuse 62 ' come out, so that when blow out fuse, molten metal can evaporate, can not remain on chip.If molten metal can not evaporate away, after metal is cooling, reconnect together possibly, even if do not link together, remain in chip, also can affect the performance of chip.
With reference to figure 6c, after forming fuse-wires structure, utilize photoetching/etching, and plasma etch process forms opening 68 on second medium layer 63, expose fuse 62 ', can expose part fuse, also can expose whole fuses.
With reference to figure 6c, the fuse-wires structure of the present invention's the 4th specific embodiment is stacking to be formed on metal interconnecting layer 22, basic identical with the structure of the fuse-wires structure of described the 3rd specific embodiment.Just, owing to forming the difference of technique, weld pad 67 and the first embolism 64, the second embolism 65 are structure as a whole.
It should be noted that, the fuse-wires structure of the specific embodiment of the invention is stacked on metal interconnecting layer, no longer continues to form metal interconnecting layer on fuse-wires structure, in other embodiments, can continue stacking formation metal interconnecting layer on fuse-wires structure.In such cases, the fuse of formation and the interconnection structure of metal interconnecting layer comprise embolism and interconnection line, do not comprise weld pad.And the specific embodiment of the invention exposes fuse by opening, in other embodiments of the invention, fuse can not come out yet, but is embedded in dielectric layer.
The present invention, after forming circuit structure and metal interconnecting layer, forms poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse, the interconnection structure of fuse and metal interconnecting layer on metal interconnecting layer.Because the resistance value of poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon is high, when fusing poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse, can not destroy relevant circuit structure, and the fuse-wires structure that the method forms is stacked on metal interconnecting layer, can chip occupying area, therefore saving chip area, reduces manufacturing cost; And its formation technique is simple.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (11)
1. a method that forms fuse-wires structure, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with circuit structure, on described circuit structure, be formed with metal interconnecting layer;
On described metal interconnecting layer, form the interconnection structure of fuse and fuse and described metal interconnecting layer, described fuse is stacked on described metal interconnecting layer, can chip occupying area, and described interconnection structure comprises the weld pad that is positioned at top layer; Described fuse materials is selected from poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.
2. the method for formation fuse-wires structure as claimed in claim 1, is characterized in that, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
In described first medium layer, form the first embolism, this first embolism bottom contacts with the interconnection line of described metal interconnecting layer;
On described first medium layer and the first embolism, form fuse layer, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical described fuse layer forms fuse, and this fuse contacts with described the first embolism;
On described fuse and first medium layer, form second medium layer;
In described first medium layer and second medium layer, form the second embolism, this second embolism bottom contacts with the interconnection line of described metal interconnecting layer;
On described the second embolism, form weld pad and interconnection line.
3. the method for formation fuse-wires structure as claimed in claim 1, is characterized in that, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
In described first medium layer, form the first through hole;
Deposit described fuse materials, in described the first through hole, form the first embolism, on described first medium layer, form fuse layer, described the first embolism bottom contacts with the interconnection line of described metal interconnecting layer;
Graphical described fuse layer forms fuse, and this fuse contacts with described the first embolism;
On described fuse and first medium layer, form second medium layer;
In described first medium layer and second medium layer, form the second through hole, in described second medium layer, form groove and opening;
Fill interconnection line and weld pad that described the second through hole, groove and opening form respectively the second embolism, connect described the second embolism, this second embolism bottom contacts with the interconnection line of described metal interconnecting layer.
4. the method for formation fuse-wires structure as claimed in claim 1, is characterized in that, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
On described first medium layer, form fuse layer, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical described fuse layer forms fuse;
On described fuse and first medium layer, form second medium layer;
In described first medium layer, form the first embolism, described the first embolism bottom contacts with described fuse, in described first medium layer and second medium layer, forms the second embolism, and this second embolism bottom contacts with the interconnection line of described metal interconnecting layer;
On described second medium layer, form interconnection line and weld pad, connect described the first embolism and the second embolism.
5. the method for formation fuse-wires structure as claimed in claim 1, is characterized in that, the described interconnection structure that forms fuse and fuse and described metal interconnecting layer on described metal interconnecting layer comprises:
On described metal interconnecting layer, form first medium layer;
On described first medium layer, form fuse layer, the material of described fuse layer is selected from described poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical described fuse layer forms fuse;
On described fuse and first medium layer, form second medium layer;
In described second medium layer, form the first through hole, in described first medium layer and second medium layer, form the second through hole, in described second medium layer, form groove and opening;
Fill described the first through hole, the second through hole, groove and opening and form respectively the first embolism, the second embolism, interconnection line and weld pad, described the first embolism bottom contacts with described fuse, the second embolism bottom contacts with the interconnection line of described metal interconnecting layer, and described interconnection line and weld pad connect described the first embolism and the second embolism.
6. the method for the formation fuse-wires structure as described in claim 2～5 any one, is characterized in that, also comprises: on described second medium layer, form opening, expose described fuse.
7. the method for the formation fuse-wires structure as described in claim 2～5 any one, is characterized in that, described first medium layer, second medium layer are silicon dioxide, carborundum, silicon nitride, silicon oxynitride or their combination.
8. the method for the formation fuse-wires structure as described in claim 2 or 4, is characterized in that, described interconnection line and weld pad are aluminum interconnecting and aluminium welding pad, and described the first embolism, the second embolism are tungsten plug.
9. the method for formation fuse-wires structure as claimed in claim 3, is characterized in that, described interconnection line and weld pad are copper interconnecting line and copper pad, and described the second embolism is copper embolism.
10. the method for formation fuse-wires structure as claimed in claim 5, is characterized in that, described interconnection line and weld pad are copper interconnecting line and copper pad, and described the first embolism, the second embolism are copper embolism.
The fuse-wires structure that the method for the formation fuse-wires structure described in 11. 1 kinds of claim 1～10 any one forms.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010244197.5A CN102347269B (en) | 2010-07-30 | 2010-07-30 | Fuse structure and method for forming same |
| PCT/CN2011/073850 WO2012013061A1 (en) | 2010-07-30 | 2011-05-10 | Fuse structure and method for forming the same |
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| CN201010244197.5A CN102347269B (en) | 2010-07-30 | 2010-07-30 | Fuse structure and method for forming same |
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| CN103296005B (en) * | 2012-02-27 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of redundant interconnections structure for interconnecting between silicon |
| KR102096614B1 (en) * | 2013-10-11 | 2020-04-03 | 삼성전자주식회사 | e-fuse structure of a semiconductor device |
| CN113013090B (en) * | 2021-02-07 | 2022-06-24 | 长鑫存储技术有限公司 | Fusing filling method of semiconductor structure and semiconductor structure |
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| US6451681B1 (en) * | 1999-10-04 | 2002-09-17 | Motorola, Inc. | Method of forming copper interconnection utilizing aluminum capping film |
| CN1776910A (en) * | 2004-11-15 | 2006-05-24 | 台湾积体电路制造股份有限公司 | Passive device of integrated circuit and method for forming the same |
| CN101170099A (en) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
| CN101501848A (en) * | 2005-10-11 | 2009-08-05 | 飞思卡尔半导体公司 | Programmable fuse with silicon germanium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6249010B1 (en) * | 1998-08-17 | 2001-06-19 | National Semiconductor Corporation | Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture |
| US6958523B2 (en) * | 2000-09-15 | 2005-10-25 | Texas Instruments Incorporated | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits |
| US6518642B2 (en) * | 2001-06-06 | 2003-02-11 | Samsung Electronics Co., Ltd. | Integrated circuit having a passive device integrally formed therein |
| US7242072B2 (en) * | 2004-11-23 | 2007-07-10 | International Business Machines Corporation | Electrically programmable fuse for silicon-on-insulator (SOI) technology |
| KR100791071B1 (en) * | 2006-07-04 | 2008-01-02 | 삼성전자주식회사 | One time programmable device, electronic system including the same and operating method of the same |
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2010
- 2010-07-30 CN CN201010244197.5A patent/CN102347269B/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6451681B1 (en) * | 1999-10-04 | 2002-09-17 | Motorola, Inc. | Method of forming copper interconnection utilizing aluminum capping film |
| CN1776910A (en) * | 2004-11-15 | 2006-05-24 | 台湾积体电路制造股份有限公司 | Passive device of integrated circuit and method for forming the same |
| CN101501848A (en) * | 2005-10-11 | 2009-08-05 | 飞思卡尔半导体公司 | Programmable fuse with silicon germanium |
| CN101170099A (en) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
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| WO2012013061A1 (en) | 2012-02-02 |
| CN102347269A (en) | 2012-02-08 |
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