CN102347269A - Fuse structure and method for forming the same - Google Patents
Fuse structure and method for forming the same Download PDFInfo
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- CN102347269A CN102347269A CN2010102441975A CN201010244197A CN102347269A CN 102347269 A CN102347269 A CN 102347269A CN 2010102441975 A CN2010102441975 A CN 2010102441975A CN 201010244197 A CN201010244197 A CN 201010244197A CN 102347269 A CN102347269 A CN 102347269A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
A fuse structure and a method for forming the same are disclosed. The method is characterized in that: a semiconductor substrate is provided, wherein a circuit structure is formed on the semiconductor substrate and a metal interconnection layer is formed on the circuit structure; a fuse and an interconnection structure of the fuse and the metal interconnection layer are formed on the metal interconnection layer, wherein a material of the fuse is selected from polycrystalline germanium silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon. Resistances of the polycrystalline germanium silicon, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon are high. When a polycrystalline germanium silicon fuse, a polycrystalline germanium fuse, an amorphous silicon fuse, an amorphous germanium fuse or an amorphous germanium silicon fuse are fused, a needed fusing current is small so that a relevant circuit structure is not easy to be destroyed. The fuse structure formed by using the method does not occupy a chip area when stacking on the metal interconnection layer. Therefore, the chip area can be saved and manufacturing costs can be reduced. A formation process is simple.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method that forms fuse-wires structure.
Background technology
Semiconductor integrated circuit comprises fuse-wires structure, is applied in output logic value two aspects of circuit reparation and change memory usually.Aspect the circuit reparation, when circuit was repaired, the fuse opening that will be connected with faulty circuit made out of order circuit structure unavailable, replaced out of order circuit with redundant circuit.Aspect the output logic value that changes memory, through the logical value of blowing or not blowing next definite output of fuse.
Several frequently seen fuse-wires structure is arranged in the prior art.First kind of fuse-wires structure, the metal interconnecting wires that directly uses metal interconnecting layer when circuit is repaired, utilize laser with fuse cut, so its cost are higher as fuse.Second kind of fuse-wires structure is at one-time programming circuit (one time programm; OTP), programmed circuit (multiple time programm repeatedly; MTP) or EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-Only Memory; EEPROM) fuse-wires structure that uses in; This kind fuse-wires structure and OTP/MTP/EEPROM device are not to pile up formation; Waste chip area, and complex process have caused cost high.The third fuse-wires structure is the polysilicon fuse structure; It uses CMOS (Complementary Metal Oxide Semiconductor; Complementary metal oxide semiconductors (CMOS)) polysilicon gate in the technology is as fuse; Because the resistance of polysilicon is big; Therefore its blowout current is little; Can not destroy relevant circuit structure, but it takies the COMS area, the manufacturing cost of semiconductor device is increased.
Many patents about fuse are arranged in the prior art, and for example application number is disclosed fuse of Chinese patent of 200480011464 and forming method thereof, and application number is 99108915 the disclosed semiconductor fuse of Chinese patent.Yet, all do not solve the shortcoming that exists in the above-described prior art.
Summary of the invention
The problem that will solve of the present invention provides a kind of method that forms fuse-wires structure, in the CMOS postchannel process, carries out, and the fuse-wires structure of formation and cmos circuit stack can be saved chip area, reduce cost; And technology is simple.
For addressing the above problem, the present invention provides a kind of method that forms fuse-wires structure, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, is formed with circuit structure, on said circuit structure, be formed with metal interconnecting layer;
On said metal interconnecting layer, form the interconnection structure of fuse and fuse and said metal interconnecting layer, said fuse materials is selected from poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.
Optional, the said interconnection structure that on said metal interconnecting layer, forms fuse fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
In said first dielectric layer, form first embolism, this first embolism bottom contacts with the interconnection line of said metal interconnecting layer;
On said first dielectric layer and first embolism, form fuse layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical said fuse layer forms fuse, and this fuse contacts with said first embolism;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer and second dielectric layer, form second embolism, this second embolism bottom contacts with the interconnection line of said metal interconnecting layer;
On said second embolism, form weld pad and interconnection line.
Optional, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
In said first dielectric layer, form first through hole;
Deposit said fuse materials, in said first through hole, form first embolism, on said first dielectric layer, form fuse layer, said first embolism bottom contacts with the interconnection line of said metal interconnecting layer;
Graphical said fuse layer forms fuse, and this fuse contacts with said first embolism;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer and second dielectric layer, form second through hole, in said second dielectric layer, form groove and opening;
Fill interconnection line and weld pad that said second through hole, groove and opening form second embolism respectively, connect said second embolism, this second embolism bottom contacts with the interconnection line of said metal interconnecting layer.
Optional, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
On said first dielectric layer, form fuse layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical said fuse layer forms fuse;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer, form first embolism, said first embolism bottom contacts with said fuse, in said first dielectric layer and second dielectric layer, forms second embolism, and this second embolism bottom contacts with the interconnection line of said metal interconnecting layer;
On said second dielectric layer, form interconnection line and weld pad, connect said first embolism and second embolism.
Optional, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
On said first dielectric layer, form fuse layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical said polycrystalline germanium silicon layer, polycrystalline germanium layer, amorphous silicon layer, amorphous germanium layer or amorphous germanium silicon layer form fuse;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer, form first through hole, in said first dielectric layer and second dielectric layer, form second through hole, in said second dielectric layer, form groove and opening;
Fill said first through hole, second through hole, groove and opening and form first embolism, second embolism, interconnection line and weld pad respectively; Said first embolism bottom contacts with said fuse; Second embolism bottom contacts with the interconnection line of said metal interconnecting layer, and said interconnection line and weld pad connect said first embolism and second embolism.
Optional, also comprise: on said second dielectric layer, form opening, expose said fuse.
Optional, said first dielectric layer, second dielectric layer are silicon dioxide, carborundum, silicon nitride, silicon oxynitride or their combination.
Optional, said interconnection line and weld pad are aluminum interconnecting and aluminium welding pad, said first embolism, second embolism are tungsten plug.
Optional, said interconnection line and weld pad are copper interconnecting line and copper pad, said second embolism is the copper embolism.
Optional, said interconnection line and weld pad are copper interconnecting line and copper pad, said first embolism, second embolism are the copper embolism.
The present invention also provides more than one fuse-wires structures that said method forms.
Compared with prior art, the present invention has the following advantages:
Can after forming circuit structure and metal interconnecting layer, on metal interconnecting layer, form the interconnection structure of poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse and fuse and metal interconnecting layer.Because the resistance value of poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium, amorphous germanium silicon is high; When fusing poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse; Required blowout current is little, can not destroy relevant circuit structure; And the fuse-wires structure that this method forms is stacked on the metal interconnecting layer, can chip occupying area, therefore save chip area, and reduce manufacturing cost; And its formation technology is simple.
Description of drawings
Fig. 1 is the flow chart that the present invention forms fuse-wires structure;
Fig. 2 is the cross-sectional view of substrate provided by the invention;
Fig. 3 a～3i is the cross-sectional view of the formation fuse-wires structure of the present invention's first specific embodiment;
Fig. 4 a～4f is the cross-sectional view of the formation fuse-wires structure of the present invention's second specific embodiment;
Fig. 5 a～5g is the cross-sectional view of the formation fuse-wires structure of the present invention's the 3rd specific embodiment;
Fig. 6 a～6c is the cross-sectional view of the formation fuse-wires structure of the present invention's the 4th specific embodiment.
Embodiment
Have in the prior art and use the fuse-wires structure of polysilicon as fuse, yet, because the depositing temperature of polysilicon is more than 600 ℃; Therefore must before the CMOS last part technology, form; And walk abreast on same plane with cmos circuit, so fuse-wires structure can take area of chip, the increase cost.The inventor studies intensively repeatedly, and hope can be found a kind of can being formed on after the CMOS last part technology, is stacked on the cmos circuit fuse-wires structure that can chip occupying area.
The method of the formation fuse-wires structure of the specific embodiment of the invention after forming circuit structure and metal interconnecting layer, forms the interconnection structure of fuse and many fuses and metal interconnecting layer on metal interconnecting layer.
In order to make those skilled in the art can better understand spirit of the present invention, be described with reference to the accompanying drawings the method for the formation fuse-wires structure of the specific embodiment of the invention.
Fig. 1 is the flow chart that the present invention forms fuse-wires structure, and with reference to figure 1, the method for the formation fuse-wires structure of the specific embodiment of the invention comprises:
Step S1 provides Semiconductor substrate, on said Semiconductor substrate, is formed with circuit structure, on said circuit structure, is formed with metal interconnecting layer;
Step S2, the interconnection structure of formation fuse and fuse and said metal interconnecting layer on said metal interconnecting layer, the material of said fuse is selected from poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.
Describe the method for the formation fuse-wires structure of the specific embodiment of the invention in detail below in conjunction with specific embodiment.
In conjunction with reference to figure 1 and Fig. 2, execution in step S1 provides Semiconductor substrate 20, on said Semiconductor substrate, is formed with circuit structure, on said circuit structure, is formed with metal interconnecting layer: said Semiconductor substrate 20 can be monocrystalline silicon or SiGe; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.Have certain isolation structure on the said Semiconductor substrate 20, can isolate (LOCOS) from (STI), local field oxidation for shallow trench isolation.On said Semiconductor substrate, be formed with device layer 21, in this device layer 21, be formed with circuit structure, concrete circuit structure is not shown in the diagram, this circuit structure can be various cmos circuit structures, for example can be the eeprom memory circuit structure.On device layer 21, forming metal interconnecting layer 22, illustrate two interconnection lines 221,222 among the figure, has been the signal effect, and the layout of interconnection line is according to the difference of actual circuit structure and difference.Fuse-wires structure of the present invention (back end of line) behind the last part technology of accomplishing semiconductor technology carries out; The fuse that forms is connected with interconnection line in the metal interconnecting layer; Connect with relevant circuit structure through interconnection line; Do not relate to the improvement of circuit structure and metal interconnecting wires in the present invention; And circuit structure among the present invention and metal interconnecting wires are circuit structure and metal interconnecting wires commonly used in this area, it are not elaborated at this.
Behind the execution of step S1, execution in step S2, the interconnection structure of formation fuse and fuse and said metal interconnecting layer on said metal interconnecting layer.In this first specific embodiment of the present invention, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
Step S31 forms first dielectric layer on said metal interconnecting layer;
Step S32 forms first embolism in said first dielectric layer, this first embolism bottom contacts with said metal interconnecting layer;
Step S33 forms fuse layer on said first dielectric layer and first embolism, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Step S34, graphical said fuse layer forms fuse, and this fuse contacts with said first embolism;
Step S35 forms second dielectric layer on the said fuse and first dielectric layer;
Step S36 forms second embolism in said first dielectric layer and second dielectric layer, this second embolism bottom contacts with said metal interconnecting layer;
Step S37 forms weld pad and interconnection line on said second embolism.
Fig. 3 a～3h is the cross-sectional view of the formation fuse-wires structure of the present invention's first specific embodiment, describes the method for the formation fuse-wires structure of this first specific embodiment in detail in conjunction with Fig. 3 a～3h.
With reference to figure 3a; Execution in step S31; On said metal interconnecting layer 22, form first dielectric layer 31; Utilize chemical vapour deposition (CVD) on said metal interconnecting layer 22, to deposit and form first dielectric layer 31; This first dielectric layer is a silicon dioxide, and in other embodiments, first dielectric layer also can play the dielectric layer of insulation buffer action for other; For example carborundum, silicon nitride, silicon oxynitride also can be the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 3b; Execution in step S32; In said first dielectric layer 31, form first embolism 32; These first embolism, 32 bottoms contact with said metal interconnecting layer; The concrete grammar that forms first embolism 32 is: utilize photoetching, graphical said first dielectric layer 31 of etching technics to form through hole, in through hole, fill metal and form first embolism 32, in this specific embodiment; The metal of filling is a tungsten, and first embolism 32 is a tungsten plug.This forms the common practise of the technology of first embolism 32 for those skilled in the art, does not do detailed description.
With reference to figure 3c; Execution in step S33; On said first dielectric layer 31 and first embolism 32, form fuse layer 33; The material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon; Fuse layer 33 thickness are 500 dusts～8000 dusts, and its specifically formation method is the chemical phase deposition CVD in the technical field of semiconductors, for example PECVD; LPCVD, depositing temperature is at 150 ℃～500 ℃.
Step S34, graphical said fuse layer 33 form fuses 33 ', fuse 33 ' contact with said first embolism 32, with reference to figure 3d, in this specific embodiment, utilize photoetching, the graphical fuse layer formation of etching technics fuse 33 '.
With reference to figure 3e; Execution in step S35; Said fuse 33 ' and first dielectric layer 31 on form second dielectric layer 34; Utilize chemical vapour deposition (CVD) said fuse 33 ' and first dielectric layer 31 on form second dielectric layer 34; This second dielectric layer is a silicon dioxide layer; In other embodiments; Second dielectric layer also can play the dielectric layer of insulation buffer action for other; For example carborundum, silicon nitride, silicon oxynitride also can be the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 3f; Execution in step S36; In said first dielectric layer 31 and second dielectric layer 34, form second embolism 35; These second embolism, 35 bottoms contact with interconnection line 221,222 in the said metal interconnecting layer 22; The concrete grammar that forms second embolism 35 is: utilize photoetching, graphical said first dielectric layer 31 of etching technics and second dielectric layer 34 to form through hole at first dielectric layer 31 and second dielectric layer 34; In through hole, fill metal and form second embolism 35; In this specific embodiment; The metal of filling is a tungsten, and second embolism 35 is a tungsten plug.This forms the common practise of the technology of second embolism 35 for those skilled in the art, does not do detailed description.
With reference to figure 3g, 3h; Execution in step S37; On said second embolism 35, form weld pad 37 and interconnection line (not shown); Be specially: at first on the surface of second dielectric layer 34 and 35 formation of second embolism, form metal level 36 (with reference to figure 3g); In this specific embodiment, metal level 36 is aluminium (Al) layer, utilizes photoetching, the graphical said metal level 36 of etching technics; Form weld pad 37 (with reference to figure 3h) and interconnection line (not shown), with reference to figure 3h.The quantity of said second embolism 35 can be for a plurality of, and wherein, some second embolisms 35 connect weld pad 37, and some second embolisms 35 connect interconnection line, and two second embolisms 35 that are connected with weld pad 37 schematically are shown among the figure.
After accomplishing above step, the fuse-wires structure of the present invention's first specific embodiment forms, and next fuse 33 ' come out so that when blow out fuse, molten metal can evaporate, can need not remained on the chip.If molten metal can not evaporate away, after the metal cools, link together again possibly, even do not link together, remain in the chip, also can influence the performance of chip.
With reference to figure 3i, form after the fuse-wires structure, utilize photoetching and plasma etch process on second dielectric layer 34, to form opening 38, expose fuse 33 ', can expose the part fuse, also can expose whole fuses.
With reference to figure 3i, the fuse-wires structure of the present invention's first specific embodiment piles up and is formed on the metal interconnecting layer 22, and this fuse-wires structure comprises: fuse 33 ' and, the interconnection structure of fuse and said metal interconnecting layer.Wherein, Said interconnection structure comprises: connect fuse 33 ' with metal interconnecting layer 22 in first embolism 32 of interconnection line 221,222; Interconnection line and weld pad 37, second embolism 35 that interconnection line and weld pad 37 are connected with interconnection line 221,222 in the metal interconnecting layer 22.
In second specific embodiment of the present invention, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
Step S41 forms first dielectric layer on said metal interconnecting layer;
Step S42 forms first through hole in said first dielectric layer;
Step S43 deposits said fuse materials, in said first through hole, forms first embolism, on said first dielectric layer, forms fuse layer, and said first embolism bottom contacts with the interconnection line of said metal interconnecting layer;
Step S44, graphical said many fuse layers form fuse, and this fuse contacts with said first embolism;
Step S45 forms second dielectric layer on the said fuse and first dielectric layer;
Step S46 forms second through hole in said first dielectric layer and second dielectric layer, in said second dielectric layer, form groove and opening;
Step S47 fills interconnection line and weld pad that said second through hole, groove and opening form second embolism respectively, connect said second embolism, and this second embolism bottom contacts with the interconnection line of said metal interconnecting layer.
Fig. 4 a～4f is the cross-sectional view of the formation fuse-wires structure of the present invention's second specific embodiment, describes the method for the formation fuse-wires structure of this second specific embodiment in detail in conjunction with Fig. 4 a～4f.
With reference to figure 4a; Execution in step S41; On said metal interconnecting layer 22, form first dielectric layer 41; Utilize chemical vapour deposition (CVD) on said metal interconnecting layer 22, to deposit and form first dielectric layer 41; This first dielectric layer is a silicon dioxide, and in other embodiments, first dielectric layer also can play the dielectric layer of insulation buffer action for other; For example carborundum, silicon nitride, silicon oxynitride also can be the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
Behind the execution of step S41, with reference to figure 4b, execution in step S42 forms first through hole in said first dielectric layer 41; Execution in step S43 deposits said fuse materials then, in said first through hole, forms first embolism 42, on said first dielectric layer 41, forms fuse layer 43, and said first embolism 42 bottoms contact with the interconnection line 221,222 of said metal interconnecting layer.In this second specific embodiment; After forming first through hole; Utilize chemical phase deposition CVD, PECVD for example, LPCVD; Depositing temperature is in 150 ℃～500 ℃ scopes; The deposition fuse materials is filled in fuse materials in first through hole, in first through hole, forms first embolism 42; And formation thickness is the fuse layer 43 of 500 dusts～8000 dusts on said first dielectric layer 41, and this fuse materials is poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.In this second specific embodiment, first embolism 42 is poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon embolism.
After forming fuse layer 43, with reference to figure 4c, execution in step S44, graphical said fuse layer 43 formation fuses 43 '.Utilize the graphical fuse layer 43 of photoetching, etching technics form fuses 43 '.
Form fuse 43 ' after, with reference to figure 4d, execution in step S45, said fuse 43 ' and first dielectric layer 41 on formation second dielectric layer 44.Utilize chemical vapour deposition (CVD) said fuse 43 ' and first dielectric layer 41 on deposition form second dielectric layer 44; This second dielectric layer 44 is a silicon dioxide; In other embodiments; Second dielectric layer also can play the dielectric layer of insulation buffer action for other; For example carborundum, silicon nitride, silicon oxynitride also can be the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
Afterwards, with reference to figure 4e, execution in step S46 forms second through hole in said first dielectric layer and second dielectric layer, in said second dielectric layer, form groove and opening (not shown); Afterwards; Execution in step S47; Fill said second through hole, groove and opening and form second embolism 45, interconnection line (not shown) and weld pad 47 respectively; These second embolism, 45 bottoms contact with the interconnection line of said metal interconnecting layer; Corresponding second embolism that forms of second through hole; The corresponding interconnection line that forms of groove, the corresponding weld pad that forms of opening.In this second specific embodiment; Utilize copper (Cu) technology, promptly to form second embolism 45, interconnection line (not shown) and weld pad 47, the second embolisms 45 be the copper embolism to the dual-damascene technics known of those skilled in the art; Weld pad 47 is a copper pad, and interconnection line is the copper interconnecting line (not shown).The quantity of said second embolism 45 is a plurality of, and wherein, some second embolisms 45 are connected with weld pad 47, and some second embolisms 45 are connected with interconnection line, and two second embolisms 45 that are connected with weld pad 47 schematically are shown among the figure.
After accomplishing above step, the fuse-wires structure of the present invention's second specific embodiment forms, and next fuse 43 ' come out so that when blow out fuse, molten metal can evaporate, can need not remained on the chip.If molten metal can not evaporate away, after the metal cools, link together again possibly, even do not link together, remain in the chip, also can influence the performance of chip.
With reference to figure 4f, form after the fuse-wires structure, utilize photoetching and plasma etch process on second dielectric layer 44, to form opening 48, expose fuse 43 ', can expose the part fuse, also can expose whole fuses.
With reference to figure 4f, the fuse-wires structure of the present invention's second specific embodiment piles up and is formed on the metal interconnecting layer 22, and the structure of the fuse-wires structure of itself and first specific embodiment is basic identical.Just owing to form the difference of technology, the weld pad 47 and second embolism 45 are structure as a whole.
In the 3rd specific embodiment of the present invention, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
Step S51 forms first dielectric layer on said metal interconnecting layer;
Step S52 forms fuse layer on said first dielectric layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Step S53, graphical said fuse layer forms fuse;
Step S54 forms second dielectric layer on the said fuse and first dielectric layer;
Step S55 forms first embolism in said first dielectric layer, said first embolism bottom contacts with said fuse, in said first dielectric layer and second dielectric layer, forms second embolism, and this second embolism bottom contacts with said metal interconnecting layer;
Step S56 forms interconnection line and weld pad on said second dielectric layer, connect said first embolism and second embolism.
Fig. 5 a～5g is the cross-sectional view of the formation fuse-wires structure of the present invention's the 3rd specific embodiment, describes the method for the formation fuse-wires structure of the 3rd specific embodiment in detail in conjunction with Fig. 5 a～5g.
With reference to figure 5a; Execution in step S51; On said metal interconnecting layer 22, form first dielectric layer 51; Be specially: utilize chemical vapour deposition (CVD) CVD on said metal interconnecting layer 22, to deposit and form first dielectric layer 51; This first dielectric layer 51 is a silicon dioxide layer, and in other embodiments, first dielectric layer also can play the dielectric layer of insulation buffer action for other; For example carborundum, silicon nitride, silicon oxynitride also can be the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 5b; Execution in step S52; On said first dielectric layer 51, form fuse layer 52; The material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon; Its concrete formation method is the chemical vapour deposition (CVD) CVD in the technical field of semiconductors, PECVD for example, LPCVD; Depositing temperature is in 150 ℃～500 ℃ scopes, and deposit thickness is the fuse layer of 500 dusts～8000 dusts.
With reference to figure 5c, execution in step S53, graphical said fuse layer 52 formation fuses 52 '.Utilize the graphical fuse layer 52 of photoetching, etching technics form fuses 52 '.
With reference to figure 5d; Execution in step S54; Said fuse 52 ' and the surface that forms of first dielectric layer 51 on form second dielectric layer 53; Be specially: utilize chemical vapour deposition (CVD) CVD to form second dielectric layer 53; This second dielectric layer 53 is a silicon dioxide layer, and in other embodiments, second dielectric layer also can play the dielectric layer of insulation buffer action for other; For example carborundum, silicon nitride, silicon oxynitride also can be the combination in any of silicon dioxide, carborundum, silicon nitride, silicon oxynitride.
With reference to figure 5e; Execution in step S55; In said first dielectric layer 51, form first embolism 54; Said first embolism 54 bottoms and said fuse 52 ' contact; In said first dielectric layer 51 and second dielectric layer 53, form second embolism 55; These second embolism, 55 bottoms contact with the interconnection line 222,221 of said metal interconnecting layer, and specifically formation method is: utilize photoetching, graphical said second dielectric layer 53 of etching technics, in second dielectric layer 53, forming first through hole; Utilize photoetching, graphical said first dielectric layer 51 of etching technics and second dielectric layer 53 in second dielectric layer 53 and first dielectric layer 51, to form second through hole; In first through hole, fill metal and form first embolism 54; First embolism, 54 bottoms and fuse 52 ' contact; In second through hole, filling metal forms second embolism, 55, the second embolisms 55 and contacts with interconnection line 222,221 in the metal interconnecting layer.In this specific embodiment, the metal of filling is a tungsten, and first embolism 54 and second embolism 55 are tungsten plug.
With reference to figure 5f; Execution in step S56; On said second dielectric layer 53, form interconnection line (not shown) and weld pad 57; Connect said first embolism 54 and second embolism 55; Its concrete formation method is: on said second dielectric layer 53, utilize physical vapour deposition (PVD) to form metal level; This metal level is an aluminium lamination, utilizes photoetching, etching technics etching aluminium lamination to form interconnection line (not shown) and weld pad 57 then, connects said first embolism 54 and second embolism 55.The quantity of said first embolism 54, second embolism 55 is a plurality of; Connection between a plurality of first embolisms 54 and second embolism 55 can connect through weld pad 57 or interconnection line (not shown); Wherein, Some first embolisms 54 are connected through weld pad 57 with second embolism 55; Some first embolisms 54 are connected through interconnection line with second embolism 55, first embolism 54 only are shown schematically among the figure, second embolism 55 connects through weld pad 57.
After accomplishing above step; The fuse-wires structure of the present invention's the 3rd specific embodiment forms; Next need be with fuse 52 ' come out; With reference to figure 5g; Form after the fuse-wires structure, utilize photoetching and plasma etch process to form openings 58 at second dielectric layer 53, expose fuse 52 '; The part fuse can be exposed, also whole fuses can be exposed.
With reference to figure 5f, the fuse-wires structure of the present invention's the 3rd specific embodiment piles up and is formed on the metal interconnecting layer 22, and this fuse-wires structure comprises: fuse 52 ' and, the interconnection structure of fuse and said metal interconnecting layer.Wherein, Said interconnection structure comprises: first embolism 54; Second embolism 55; Interconnection line and weld pad 57; The said fuse 52 of first embolism, 54 connections '; The interconnection line 221,222 that said second embolism 55 connects in the metal interconnecting layer 22 connects, and said interconnection line or weld pad 57 are connected first embolism 54 with second embolism 55.
In the 4th specific embodiment of the present invention, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
Step S61 forms first dielectric layer on said metal interconnecting layer;
Step S62 forms fuse layer on said first dielectric layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Step S63, graphical said fuse layer forms fuse;
Step S64 forms second dielectric layer on the said fuse and first dielectric layer;
Step S65 forms first through hole in said first dielectric layer, in said first dielectric layer and second dielectric layer, form second through hole, in said second dielectric layer, forms groove and opening;
Step S66; Fill said first through hole, second through hole, groove and opening and form first embolism, second embolism, interconnection line and weld pad respectively; Said first embolism bottom contacts with said fuse; Second embolism bottom contacts with the interconnection line of said metal interconnecting layer, and said interconnection line and weld pad connect said first embolism and second embolism.
Fig. 6 a～6c is the cross-sectional view of the formation fuse-wires structure of the present invention's the 4th specific embodiment, describes the method for the formation fuse-wires structure of the 4th specific embodiment in detail in conjunction with Fig. 6 a～6c.
In the 4th specific embodiment; Step S61, step S62, step S63 and step S64 are identical with step S51, step S52, step S53 and the step S54 of said the 3rd specific embodiment; This does not do detailed description, specifically can be referring to the detailed description to correlation step in the 3rd specific embodiment.
Execution of step S61, step S62, step S63 and step S64 form fuse 62 ', second dielectric layer 63 and first dielectric layer, 61 backs (with reference to figure 6a); With reference to figure 6b; Execution in step S65; In said second dielectric layer 63, form first through hole; In said first dielectric layer 61 and second dielectric layer 63, form second through hole, in said second dielectric layer, form groove and opening (not shown); And step S66; Fill said first through hole, second through hole, groove and opening and form first embolism 64, second embolism 65, interconnection line and weld pad 67 respectively; Said first embolism 64 bottoms and said fuse 62 ' contact; Second embolism, 65 bottoms contact with the interconnection line 222,221 of said metal interconnecting layer; Said interconnection line (not shown) and weld pad 67 connect said first embolism and second embolism; Corresponding first embolism that forms of first through hole; Corresponding second embolism that forms of second through hole; The corresponding interconnection line that forms of groove, the corresponding weld pad that forms of opening.In the 4th specific embodiment; Utilize copper (Cu) technology; Be that dual-damascene technics that those skilled in the art know forms first embolism 64, second embolism 65, interconnection line (not shown) and weld pad 67; First embolism 64; Second embolism 65 is the copper embolism; Weld pad 67 is a copper pad, and interconnection line is the copper interconnecting line (not shown).The quantity of said first embolism 64, second embolism 65 is a plurality of; Two first embolisms 64, second embolism 65 schematically are shown among the figure; Connection between a plurality of first embolisms 64 and second embolism 65 connects through weld pad 67 or interconnection line (not shown); Wherein, Some first embolisms 64 are connected through weld pad 67 with second embolism 65; Some first embolisms 64 are connected through interconnection line with second embolism 65, first embolism 64 only are shown schematically among the figure, second embolism 65 connects through weld pad 67.
After accomplishing above step, the fuse-wires structure of the present invention's the 4th specific embodiment forms, and next fuse 62 ' come out so that when blow out fuse, molten metal can evaporate, can need not remained on the chip.If molten metal can not evaporate away, after the metal cools, link together again possibly, even do not link together, remain in the chip, also can influence the performance of chip.
With reference to figure 6c, form after the fuse-wires structure, utilize photoetching/etching, and plasma etch process forms opening 68 on second dielectric layer 63, expose fuse 62 ', can expose the part fuse, also can expose whole fuses.
With reference to figure 6c, the fuse-wires structure of the present invention's the 4th specific embodiment piles up and is formed on the metal interconnecting layer 22, and is basic identical with the structure of the fuse-wires structure of said the 3rd specific embodiment.Just owing to form the difference of technology, weld pad 67 and first embolism 64, second embolism 65 are structure as a whole.
Need to prove that the fuse-wires structure of the specific embodiment of the invention is stacked on the metal interconnecting layer, on fuse-wires structure, no longer continue to form metal interconnecting layer, in other embodiments, can continue to pile up the formation metal interconnecting layer on the fuse-wires structure.In such cases, the fuse of formation and the interconnection structure of metal interconnecting layer comprise embolism and interconnection line, do not comprise weld pad.And the specific embodiment of the invention exposes fuse by opening, and in other embodiments of the invention, fuse can not come out yet, but is embedded in the dielectric layer.
The present invention forms poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse, the interconnection structure of fuse and metal interconnecting layer on metal interconnecting layer after forming circuit structure and metal interconnecting layer.Because the resistance value of poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon is high; When fusing poly-SiGe fuse, polycrystalline germanium fuse, amorphous silicon fuse, amorphous germanium fuse or amorphous germanium silicon fuse; Can not destroy relevant circuit structure; And the fuse-wires structure that this method forms is stacked on the metal interconnecting layer; Can chip occupying area; Therefore save chip area, reduce manufacturing cost; And its formation technology is simple.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification; Therefore; Every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. a method that forms fuse-wires structure is characterized in that, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, is formed with circuit structure, on said circuit structure, be formed with metal interconnecting layer;
On said metal interconnecting layer, form the interconnection structure of fuse and fuse and said metal interconnecting layer, said fuse materials is selected from poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon.
2. the method for formation fuse-wires structure as claimed in claim 1 is characterized in that, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
In said first dielectric layer, form first embolism, this first embolism bottom contacts with the interconnection line of said metal interconnecting layer;
On said first dielectric layer and first embolism, form fuse layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical said fuse layer forms fuse, and this fuse contacts with said first embolism;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer and second dielectric layer, form second embolism, this second embolism bottom contacts with the interconnection line of said metal interconnecting layer;
On said second embolism, form weld pad and interconnection line.
3. the method for formation fuse-wires structure as claimed in claim 1 is characterized in that, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
In said first dielectric layer, form first through hole;
Deposit said fuse materials, in said first through hole, form first embolism, on said first dielectric layer, form fuse layer, said first embolism bottom contacts with the interconnection line of said metal interconnecting layer;
Graphical said fuse layer forms fuse, and this fuse contacts with said first embolism;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer and second dielectric layer, form second through hole, in said second dielectric layer, form groove and opening;
Fill interconnection line and weld pad that said second through hole, groove and opening form second embolism respectively, connect said second embolism, this second embolism bottom contacts with the interconnection line of said metal interconnecting layer.
4. the method for formation fuse-wires structure as claimed in claim 1 is characterized in that, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
On said first dielectric layer, form fuse layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical said fuse layer forms fuse;
On the said fuse and first dielectric layer, form second dielectric layer;
In said first dielectric layer, form first embolism, said first embolism bottom contacts with said fuse, in said first dielectric layer and second dielectric layer, forms second embolism, and this second embolism bottom contacts with the interconnection line of said metal interconnecting layer;
On said second dielectric layer, form interconnection line and weld pad, connect said first embolism and second embolism.
5. the method for formation fuse-wires structure as claimed in claim 1 is characterized in that, the said interconnection structure that on said metal interconnecting layer, forms fuse and fuse and said metal interconnecting layer comprises:
On said metal interconnecting layer, form first dielectric layer;
On said first dielectric layer, form fuse layer, the material of said fuse layer is selected from said poly-SiGe, polycrystalline germanium, amorphous silicon, amorphous germanium or amorphous germanium silicon;
Graphical said fuse layer forms fuse;
On the said fuse and first dielectric layer, form second dielectric layer;
In said second dielectric layer, form first through hole, in said first dielectric layer and second dielectric layer, form second through hole, in said second dielectric layer, form groove and opening;
Fill said first through hole, second through hole, groove and opening and form first embolism, second embolism, interconnection line and weld pad respectively; Said first embolism bottom contacts with said fuse; Second embolism bottom contacts with the interconnection line of said metal interconnecting layer, and said interconnection line and weld pad connect said first embolism and second embolism.
6. like the method for each described formation fuse-wires structure of claim 2～5, it is characterized in that, also comprise: on said second dielectric layer, form opening, expose said fuse.
7. like the method for each described formation fuse-wires structure of claim 2～5, it is characterized in that said first dielectric layer, second dielectric layer are silicon dioxide, carborundum, silicon nitride, silicon oxynitride or their combination.
8. like the method for claim 2 or 4 described formation fuse-wires structures, it is characterized in that said interconnection line and weld pad are aluminum interconnecting and aluminium welding pad, said first embolism, second embolism are tungsten plug.
9. the method for formation fuse-wires structure as claimed in claim 3 is characterized in that, said interconnection line and weld pad are copper interconnecting line and copper pad, and said second embolism is the copper embolism.
10. the method for formation fuse-wires structure as claimed in claim 5 is characterized in that, said interconnection line and weld pad are copper interconnecting line and copper pad, and said first embolism, second embolism are the copper embolism.
11. the fuse-wires structure that the method for each described formation fuse-wires structure of claim 1～10 forms.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010244197.5A CN102347269B (en) | 2010-07-30 | 2010-07-30 | Fuse structure and method for forming same |
| PCT/CN2011/073850 WO2012013061A1 (en) | 2010-07-30 | 2011-05-10 | Fuse structure and method for forming the same |
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| CN201010244197.5A CN102347269B (en) | 2010-07-30 | 2010-07-30 | Fuse structure and method for forming same |
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| WO (1) | WO2012013061A1 (en) |
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| CN104576604A (en) * | 2013-10-11 | 2015-04-29 | 三星电子株式会社 | E-fuse structure of a semiconductor device |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102347269B (en) | 2014-03-12 |
| WO2012013061A1 (en) | 2012-02-02 |
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