CN103296005B - A kind of redundant interconnections structure for interconnecting between silicon - Google Patents
A kind of redundant interconnections structure for interconnecting between silicon Download PDFInfo
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- CN103296005B CN103296005B CN201210046598.9A CN201210046598A CN103296005B CN 103296005 B CN103296005 B CN 103296005B CN 201210046598 A CN201210046598 A CN 201210046598A CN 103296005 B CN103296005 B CN 103296005B
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- redundant interconnections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The invention provides the redundant interconnections structure for interconnecting between silicon, comprise: multiple main interconnecting channel, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with soldered ball, and upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface; Multiple redundant interconnections passage, each each side be formed in described multiple main interconnecting channel in described multiple redundant interconnections passage; Multiple antifuse element, in each described metal interconnecting wires be formed between each upper end in described multiple main interconnecting channel and each upper end in described multiple redundant interconnections passage in described multiple antifuse element; Multiple fuse element, each in described multiple fuse element is formed at each lower end in described multiple main interconnecting channel with the described pad be connected between the pad of described silicon lower surface and the solder joint of described soldered ball.According to the present invention, can circuit structure be simplified, mutually compatible with existing semiconductor fabrication process better.
Description
Technical field
The present invention relates to semiconductor device, in particular to a kind of redundant interconnections structure for interconnecting between silicon.
Background technology
In order to realize higher transistor integrated level, existing semiconductor design technology adopts stacked semiconductor chip as shown in Figure 1, in FIG, Semiconductor substrate 100 is formed with the semiconductor chip 101 stacked gradually from bottom to top, 102 and 103, between semiconductor chip 101 and Semiconductor substrate 100, connected by wire bonding element (illustrating with the square frame with oblique line in Fig. 1) between semiconductor chip 102 and semiconductor chip 101 and between semiconductor chip 103 and semiconductor chip 102, in the inside of semiconductor chip 102 and semiconductor chip 101, by silicon pass element (TSV) 104, the metal interconnecting wires of described semiconductor chip inside and described wire bonding element are coupled together, thus the communication realized between stacked semiconductor chip inner. layers chip as shown in Figure 1.
But, through the use of certain hour, the described silicon pass element performance of described stacked semiconductor chip inside will be degenerated, such as, the inside of described silicon pass element or near appearance hole 200 as shown in Figure 2, described hole 200 appears in the pad 202 below silicon pass element 201.Described degeneration will cause the inefficacy of described stacked semiconductor chip.
Because the manufacturing cost of the stacked semiconductor chip with multiple described silicon pass element is very high, therefore, one in described multiple silicon pass element is avoided to lose efficacy and caused the inefficacy of whole stacked semiconductor chip to be very necessary.Existing semiconductor technology usually in described multiple silicon pass element configuring redundancy silicon pass element and corresponding to detect and starting component, when described detecting element detects that one in described multiple silicon pass element is broken down, the silicon pass element then starting described redundancy replaces the silicon pass element broken down, thus ensures the normal work of described semiconductor chip.But the usual more complicated of structure of described detection and starting component, takies more chip and utilize area, be unfavorable for the reduction of manufacturing cost, the technique that some detects and starting component needs increase extra simultaneously, is unfavorable for the compatibility with existing manufacturing process.
Therefore, need to propose a kind of redundant interconnections structure for described stacked semiconductor chip, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of redundant interconnections structure for interconnecting between silicon, be fixedly connected with by multiple soldered ball between described silicon, described redundant interconnections structure comprises: multiple main interconnecting channel, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, and upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface; Multiple redundant interconnections passage, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface, each each side be formed in described multiple main interconnecting channel in described multiple redundant interconnections passage; Multiple antifuse element, in each described metal interconnecting wires be formed between each upper end in described multiple main interconnecting channel and each upper end in corresponding described multiple redundant interconnections passages in described multiple antifuse element; Described antifuse element and corresponding described redundant interconnections passage are in series, and the described antifuse element be in series and described redundant interconnections passage form parallel-connection structure with corresponding described main interconnecting channel again.
Further, described antifuse element controls the unlatching of described redundant interconnections passage.
Further, when any one in described multiple main interconnecting channel breaks down, the antifuse element corresponding with the described main interconnecting channel broken down changes conducting state into by nonconducting state, realizes the unlatching of the described redundant interconnections passage on the main interconnecting channel side of breaking down described in being positioned at.
Further, described multiple main interconnecting channel and described multiple redundant interconnections passage are made up of silicon pass element.
Further, the material of described silicon pass element is electric conducting material.
Further, the described electric conducting material forming described silicon pass element comprise in copper, tungsten, titanium or polysilicon one or more.
Further, the material of described multiple antifuse element is electric conducting material.
Further, the described electric conducting material forming described multiple antifuse element comprises alloys of one or more formations in tungsten, titanium or polysilicon.
The present invention is also by a kind of redundant interconnections structure for interconnecting between silicon, be fixedly connected with by multiple soldered ball between described silicon, described redundant interconnections structure comprises: multiple main interconnecting channel, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, and upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface; Multiple redundant interconnections passage, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface, each each side be formed in described multiple main interconnecting channel in described multiple redundant interconnections passage; Multiple antifuse element, in each described metal interconnecting wires be formed between each upper end in described multiple main interconnecting channel and each upper end in described multiple redundant interconnections passage in described multiple antifuse element; Multiple fuse element, each in described multiple fuse element is formed at each lower end in described multiple main interconnecting channel with the described pad be connected between the pad of described silicon lower surface and the solder joint of described soldered ball; Described antifuse element and corresponding described redundant interconnections passage are in series, described fuse element and corresponding described main interconnecting channel are in series, and the described fuse element be in series and described main interconnecting channel form parallel-connection structure with the described antifuse element be in series and described redundant interconnections passage again.
Further, described antifuse element controls the unlatching of described redundant interconnections passage.
Further, when any one in described multiple main interconnecting channel breaks down, the antifuse element corresponding with the described main interconnecting channel broken down changes conducting state into by nonconducting state, realizes the unlatching of the described redundant interconnections passage on the main interconnecting channel side of breaking down described in being positioned at.
Further, when the described main interconnecting channel broken down does not damage completely, described fuse element can be fused by applying enough large electric current, thus the main interconnecting channel broken down described in can blocking completely.
Further, described multiple main interconnecting channel and described multiple redundant interconnections passage are made up of silicon pass element.
Further, the material of described silicon pass element is electric conducting material.
Further, the described electric conducting material forming described silicon pass element comprise in copper, tungsten, titanium or polysilicon one or more.
Further, the material of described multiple antifuse element is electric conducting material.
Further, the described electric conducting material forming described multiple antifuse element comprises alloys of one or more formations in tungsten, titanium or polysilicon.
According to the present invention, can circuit structure be simplified, mutually compatible with existing semiconductor fabrication process better.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the structural representation of stacked semiconductor chip;
Fig. 2 is the inefficacy schematic diagram of silicon pass element;
Fig. 3 is the schematic diagram of the first execution mode of the redundant interconnections structure that the present invention proposes;
Fig. 4 is the schematic diagram of the second execution mode of the redundant interconnections structure that the present invention proposes.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the redundant interconnections structure of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the first execution mode of the redundant interconnections structure that the present invention proposes is described with reference to Fig. 3.
In figure 3, semiconductor chip 301 and 302 stacks gradually from bottom to top, the lower surface of described semiconductor chip 302 is formed with pad 304, the upper surface of described semiconductor chip 301 is formed with pad (not shown) equally, be formed with soldered ball 303 between two pads, described pad 304 is fixedly connected with by solder joint with described soldered ball 303.In described semiconductor chip 302, there is main interconnecting channel 307, its lower end is connected to described pad 304, and upper end is connected to metal interconnecting wires 305.In described semiconductor chip 302, there is multiple main interconnecting channel 307, its concrete number is relevant to the number of described pad 304, can determine according to the specific requirement of semiconductor chip design and encapsulation.In figure 3, be brief description, two main interconnecting channels 307 are only shown.
Redundant interconnections passage 306 is formed on the side of each described main interconnecting channel 307.The lower end of described redundant interconnections passage 306 is also connected to described pad 304, and upper end is also connected to metal interconnecting wires 305.When described main interconnecting channel 307 breaks down, the described redundant interconnections passage 306 being configured in its side can substitute the described main interconnecting channel 307 broken down and work.In the present embodiment, described main interconnecting channel 307 is formed by silicon pass element with described redundant interconnections passage 306.
Be formed with an antifuse element 308 in described metal interconnecting wires 305 between the upper end of described main interconnecting channel 307 and the upper end of described redundant interconnections passage 306, described antifuse element 308 is in series with described redundant interconnections passage 306; The described antifuse element 308 be in series and described redundant interconnections passage 306 form parallel-connection structure with described main interconnecting channel 307 again.Described antifuse element 308 controls the unlatching of described redundant interconnections passage 306, when described main interconnecting channel 307 breaks down, is blocked, then flow to described antifuse element 308 from the electric current in described metal interconnecting wires 305; When described electric current reaches certain numerical value (such as 5mA, concrete numerical value is determined by experiment), described antifuse element 308 changes conducting state into by nonconducting state, and described redundant interconnections passage 306 opens to substitute the described main interconnecting channel 307 broken down.
In described semiconductor chip 301, be also configured with above-mentioned redundant interconnections structure, be brief description, do not give in figure 3 and illustrating; With the redundant interconnections structure in described semiconductor chip 302 unlike, one end of the metal interconnecting wires in described semiconductor chip 301 is connected to the pad of described semiconductor chip 301 upper surface.
Below, the second execution mode of the redundant interconnections structure that the present invention proposes is described with reference to Fig. 4.
In the diagram, semiconductor chip 401 and 402 stacks gradually from bottom to top, the lower surface of described semiconductor chip 402 is formed with pad 404, the upper surface of described semiconductor chip 401 is formed with pad (not shown) equally, be formed with soldered ball 403 between two pads, described pad 404 is fixedly connected with by solder joint with described soldered ball 403.In described semiconductor chip 402, there is main interconnecting channel 407, its lower end is connected to described pad 404, and upper end is connected to metal interconnecting wires 405.In described semiconductor chip 402, there is multiple main interconnecting channel 407, its concrete number is relevant to the number of described pad 404, can determine according to the specific requirement of semiconductor chip design and encapsulation.In the diagram, be brief description, two main interconnecting channels 407 are only shown.
Redundant interconnections passage 406 is formed on the side of each described main interconnecting channel 407.The lower end of described redundant interconnections passage 406 is also connected to described pad 404, and upper end is also connected to metal interconnecting wires 405.When described main interconnecting channel 407 breaks down, the described redundant interconnections passage 406 being configured in its side can substitute the described main interconnecting channel 407 broken down and work.In the present embodiment, described main interconnecting channel 407 is formed by silicon pass element with described redundant interconnections passage 406.
Be formed with an antifuse element 408 in described metal interconnecting wires 405 between the upper end of described main interconnecting channel 407 and the upper end of described redundant interconnections passage 406, described antifuse element 408 is in series with described redundant interconnections passage 406.Described antifuse element 408 controls the unlatching of described redundant interconnections passage 406, when described main interconnecting channel 407 breaks down, is blocked, then flow to described antifuse element 408 from the electric current in described metal interconnecting wires 405; When described electric current reaches certain numerical value (such as 5mA, concrete numerical value is determined by experiment), described antifuse element 408 changes conducting state into by nonconducting state, and described redundant interconnections passage 406 opens to substitute the described main interconnecting channel 407 broken down.
Meanwhile, the lower end of described main interconnecting channel 407 is formed with a fuse element 409 with the described pad 404 be connected between described pad 404 and the solder joint of described soldered ball 403, and described fuse element 409 is in series with described main interconnecting channel 407; The described fuse element 409 be in series and described main interconnecting channel 407 form parallel-connection structure with the described antifuse element 408 be in series and described redundant interconnections passage 406 again.When the described main interconnecting channel 407 broken down does not damage completely, described fuse element 409 can be fused by applying enough large electric current, thus described main interconnecting channel 407 can be blocked completely.When described antifuse element 408 changes conducting state into by nonconducting state, described redundant interconnections passage 406 is opened, the electric current of described antifuse element 408 conducting is made to change described fuse element 409 into nonconducting state by conducting state, thus when described main interconnecting channel 407 break down but non-complete failure, block described main interconnecting channel 407 completely.
In described semiconductor chip 401, be also configured with above-mentioned redundant interconnections structure, be brief description, do not give in the diagram and illustrating; With the redundant interconnections structure in described semiconductor chip 402 unlike, one end of the metal interconnecting wires in described semiconductor chip 401 is connected to the pad of described semiconductor chip 401 upper surface.
In two kinds of redundant interconnections structures described above, described main interconnecting channel and described redundant interconnections passage are formed by silicon pass element, and the material of described silicon pass element can be one or more of copper, tungsten, titanium, polysilicon or other electric conducting material; The material of described antifuse element can be electric conducting material, comprises one or more alloys formed in tungsten, titanium or polysilicon.According to the present invention, can circuit structure be simplified, mutually compatible with existing semiconductor fabrication process better.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (17)
1. the redundant interconnections structure for interconnecting between silicon, is fixedly connected with by multiple soldered ball between described silicon, and described redundant interconnections structure comprises:
Multiple main interconnecting channel, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, and upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface;
Multiple redundant interconnections passage, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface, each each side be formed in described multiple main interconnecting channel in described multiple redundant interconnections passage;
Multiple antifuse element, in each described metal interconnecting wires be formed between each upper end in described multiple main interconnecting channel and each upper end in corresponding described multiple redundant interconnections passages in described multiple antifuse element;
Described antifuse element and corresponding described redundant interconnections passage are in series, and the described antifuse element be in series and described redundant interconnections passage form parallel-connection structure with corresponding described main interconnecting channel again.
2. redundant interconnections structure according to claim 1, is characterized in that, described antifuse element controls the unlatching of described redundant interconnections passage.
3. redundant interconnections structure according to claim 2, it is characterized in that, when any one in described multiple main interconnecting channel breaks down, the antifuse element corresponding with the described main interconnecting channel broken down changes conducting state into by nonconducting state, realizes the unlatching of the described redundant interconnections passage on the main interconnecting channel side of breaking down described in being positioned at.
4. redundant interconnections structure according to claim 1, is characterized in that, described multiple main interconnecting channel and described multiple redundant interconnections passage are made up of silicon pass element.
5. redundant interconnections structure according to claim 4, is characterized in that, the material of described silicon pass element is electric conducting material.
6. redundant interconnections structure according to claim 5, is characterized in that, the described electric conducting material forming described silicon pass element comprise in copper, tungsten, titanium or polysilicon one or more.
7. redundant interconnections structure according to claim 1, is characterized in that, the material of described multiple antifuse element is electric conducting material.
8. redundant interconnections structure according to claim 7, is characterized in that, the described electric conducting material forming described multiple antifuse element comprises alloys of one or more formations in tungsten, titanium or polysilicon.
9. the redundant interconnections structure for interconnecting between silicon, is fixedly connected with by multiple soldered ball between described silicon, and described redundant interconnections structure comprises:
Multiple main interconnecting channel, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, and upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface;
Multiple redundant interconnections passage, its lower end is connected to the pad of the described silicon lower surface that solder joint is connected with described soldered ball, upper end is connected to the metal interconnecting wires be connected with the pad of described silicon upper surface, each each side be formed in described multiple main interconnecting channel in described multiple redundant interconnections passage;
Multiple antifuse element, in each described metal interconnecting wires be formed between each upper end in described multiple main interconnecting channel and each upper end in described multiple redundant interconnections passage in described multiple antifuse element;
Multiple fuse element, each in described multiple fuse element is formed at each lower end in described multiple main interconnecting channel with the described pad be connected between the pad of described silicon lower surface and the solder joint of described soldered ball;
Described antifuse element and corresponding described redundant interconnections passage are in series, described fuse element and corresponding described main interconnecting channel are in series, and the described fuse element be in series and described main interconnecting channel form parallel-connection structure with the described antifuse element be in series and described redundant interconnections passage again.
10. redundant interconnections structure according to claim 9, is characterized in that, described antifuse element controls the unlatching of described redundant interconnections passage.
11. redundant interconnections structures according to claim 10, it is characterized in that, when any one in described multiple main interconnecting channel breaks down, the antifuse element corresponding with the described main interconnecting channel broken down changes conducting state into by nonconducting state, realizes the unlatching of the described redundant interconnections passage on the main interconnecting channel side of breaking down described in being positioned at.
12. redundant interconnections structures according to claim 11, it is characterized in that, when the described main interconnecting channel broken down does not damage completely, described fuse element can be fused by applying enough large electric current, thus the main interconnecting channel broken down described in can blocking completely.
13. redundant interconnections structures according to claim 9, is characterized in that, described multiple main interconnecting channel and described multiple redundant interconnections passage are made up of silicon pass element.
14. redundant interconnections structures according to claim 13, is characterized in that, the material of described silicon pass element is electric conducting material.
15. redundant interconnections structures according to claim 14, is characterized in that, the described electric conducting material forming described silicon pass element comprise in copper, tungsten, titanium or polysilicon one or more.
16. redundant interconnections structures according to claim 9, is characterized in that, the material of described multiple antifuse element is electric conducting material.
17. redundant interconnections structures according to claim 16, is characterized in that, the described electric conducting material forming described multiple antifuse element comprises alloys of one or more formations in tungsten, titanium or polysilicon.
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| CN103296005B true CN103296005B (en) | 2015-11-25 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320696A (en) * | 2007-06-04 | 2008-12-10 | 矽品精密工业股份有限公司 | Stack type packaging structure and its manufacturing method |
| CN102347269A (en) * | 2010-07-30 | 2012-02-08 | 江苏丽恒电子有限公司 | Fuse structure and method for forming the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080029844A1 (en) * | 2006-08-03 | 2008-02-07 | Adkisson James W | Anti-fuse structure optionally integrated with guard ring structure |
| US7935621B2 (en) * | 2008-02-15 | 2011-05-03 | International Business Machines Corporation | Anti-fuse device structure and electroplating circuit structure and method |
| US7839163B2 (en) * | 2009-01-22 | 2010-11-23 | International Business Machines Corporation | Programmable through silicon via |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320696A (en) * | 2007-06-04 | 2008-12-10 | 矽品精密工业股份有限公司 | Stack type packaging structure and its manufacturing method |
| CN102347269A (en) * | 2010-07-30 | 2012-02-08 | 江苏丽恒电子有限公司 | Fuse structure and method for forming the same |
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