TWI817546B - Method for activating semiconductor backup unit - Google Patents

Abstract

A method for activating a semiconductor backup unit includes providing a fuse element connected to the backup unit. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. The method also includes applying a stress voltage on the drain region of the fuse element; accumulating electrons in a portion of the STI structure adjacent to the drain region; generating a conductive path through the drain region and the source region so that the fuse element is conductive; and activating the backup unit through the fuse element.

Description

How to start a semiconductor backup unit

This application claims priority to U.S. Patent Application Nos. 17/691,264 and 17/691,932 (that is, the priority date is "March 10, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a startup method of a semiconductor backup unit.

Fuses and electronic fuses are commonly used in memory devices to activate semiconductor backup cells (or redundant memory cells). Fuses and electronic fuses convert the semiconductor backup unit into a normal circuit for normal operation. For currently available oxide fuses, the melting voltage/current depends on process variations, so that the melting efficiency decreases with inaccuracy. Additionally, currently available fuses blow at extremely high voltages. Therefore, there is a need for an improved fuse with stable and relatively low melting voltage.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a fuse element. The fuse element includes an active region, including: a source region; a drain region disposed next to the source region; a gate region disposed on the active region; and a shallow trench isolation structure surrounding The active zone. Additionally, the drain region includes a terminal configured to receive a stress voltage to establish a conductive path through the drain region to the source region.

Another embodiment of the present disclosure provides a semiconductor device including a PMOS. The PMOS includes an active region, including: a source region; a drain region disposed next to the source region; a gate region disposed on the active region; and a shallow trench isolation structure disposed on the around the active zone. Additionally, the drain region includes a terminal configured to receive a first voltage to establish a conductive path from the drain region to the source region, wherein when no external voltage is applied to the gate region, The conductive path remains unchanged.

Another embodiment of the present disclosure provides a method of activating a semiconductor backup unit. The method includes providing a fuse element for connection to the semiconductor backup unit. The fuse element includes an active region, including: a source region; a drain region disposed next to the source region; a gate region disposed on the active region; and a shallow trench isolation structure surrounding The active zone. The method also includes applying a stress voltage to the drain region of the fuse element; accumulating a plurality of electrons in a portion of the shallow trench isolation structure adjacent to the active region; and generating a conductive path through the conductive path. a drain region to the source region so that the fuse element is conductive; and the semiconductor backup unit is activated via the fuse element.

The present disclosure provides a fuse element with a structure similar to a PMOS, so that the required area of the fuse element can be reduced with the development of manufacturing technology. The fuse element of the present disclosure utilizes a stress signal applied to its drain electrode to cause an effect to establish a conductive path from the drain electrode to the source electrode. When the conductive path is established, the fuse element is deemed to have blown. That is, the PMOS is turned on regardless of whether the gate is configured to receive a control signal. As a result, the channel of this PMOS can be generated without gate voltage. The stress signal that causes this effect is lower than that of a conventional fuse.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it is either directly connected or coupled to the other element, or other intermediate components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

It will be understood that in the description of the present disclosure, the term "about" is used to alter the amount of an ingredient, composition, or reactant of the present disclosure, meaning, for example, by typical measurements and liquid handling used to prepare concentrates or solutions. Quantity changes may occur due to the procedure. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or practice the methods, and the like. In one aspect, the term "about" means within 10% of a reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

1A and 1B are schematic structural diagrams illustrating a semiconductor device 100 used to activate a semiconductor backup unit according to some embodiments of the present disclosure.

Referring to FIG. 1A , the semiconductor component 100 includes a fuse component 110 and a semiconductor backup unit 120 . The difference between FIG. 1A and FIG. 1B is that the semiconductor element 100 in FIG. 1B includes a blown fuse element 110a. In some embodiments, the semiconductor device 100 may be a memory, a memory device, a memory die or a memory chip. For example, the memory may be a dynamic random access memory (DRAM). In some embodiments, memory includes one or more memory cells (or memory bits/memory blocks). In some embodiments, the memory may include a normal memory cell and a semiconductor spare unit (a redundant memory cell) that is a backup when the normal memory cell is unavailable.

In some embodiments, the normal memory may include an array of memory cells (not shown). Each memory cell can store a single bit of information. A particular bit within the array of normal memory cells is specified by a special address. Similarly, each redundant memory cell can store a single bit of information. A specific bit within the array of redundant memory cells is specified by a special address.

The semiconductor device 100 may include only one redundant memory cell 120 connected to other devices via a fuse element 110 . In some embodiments, fuse element 110 may have two terminals. One terminal of fuse element 110 may be configured to receive a relatively high voltage _VH , while the other terminal may be coupled to a node with a relatively low voltage _VL .

The fuse element 110 can be blown by a fuse circuit (not shown). In some embodiments, fuse element 110 may be an antifuse. Fuse element 110 may be an electronic fuse. In another embodiment, the fuse element 110 may be an oxide fuse. When the fuse element 110 has not been blown/melted, it will have a high resistance. The resistance of the fuse element 110 is high enough to disconnect the redundant memory cell 120 . Referring to FIG. 1B , when the fuse element 110a is blown/melted, it will have a low resistance. The resistance of the blown fuse element 110a may be low enough to establish a conductive path through the blown fuse element 110a so that the redundant memory cell 120 may be connected to other components in the semiconductor device 100 via the blown fuse element 110a.

In some embodiments, the fuse element 110a can be blown after a blowing operation, and then the redundant memory cell 120 is connected to other elements in the semiconductor device 100. After being connected to other devices in the semiconductor device 100, the redundant memory cell 120 can operate as a normal memory cell.

In more detail, after the semiconductor device 100 is manufactured, a plurality of tests are performed on the semiconductor device 100 to determine which memory cells, if any, have defects. When some normal memory cells fail to operate, the fuse element 110 can be blown to switch the redundant memory element 120 to a normal memory cell. Therefore, the redundant memory cell can alternatively be regarded as a repair circuit.

FIG. 2A is a top view schematic diagram illustrating a semiconductor device 200 according to some embodiments of the present disclosure. Semiconductor element 200 may include a fuse element. Semiconductor device 200 may include a transistor. For example, the semiconductor device 200 may include a PMOS. Figure 2A shows sections A-A and B-B, and Figures 2B and 2C provide details of sections along these sections.

Referring to FIG. 2A , the semiconductor device 200 may include a gate region 210 , a drain region 220 , a source region 230 , a shallow trench isolation structure 240 and an oxide layer 265 . Semiconductor device 200 may include a substrate (not shown in FIG. 2A). In some embodiments, the semiconductor device 200 may include an active region 250 (as shown in FIGS. 2B and 2C ).

In some embodiments, active region 250 may include a source region 230 in semiconductor device 200 . In some embodiments, active region 250 may include a drain region 220 in semiconductor device 200 . The drain region 220 may be disposed next to the source region 230. In some embodiments, drain region 220 may be separated from source region 230 . In some embodiments, the drain region 220 and the source region 230 may be doped with the same dopant. For example, the drain region 220 and the source region 230 may be doped with P-type dopants. In some embodiments, drain region 220 may have a different area than source region 230 . For example, the area of the drain region 220 may exceed the area of the source region 230 . The drain region 220 may have a width exceeding the source region 230 . In another embodiment, the drain region 220 may have a length exceeding the source region 230 . In some embodiments, drain region 220 may have the same area as source region 230 . In one embodiment, the width of the drain region 220 may be the same as the width of the source region 230 . In some embodiments, the drain region 220 may have a rectangular shape. In some embodiments, source region 230 may be rectangular in shape. In some embodiments, the drain region 220 and the source region 230 may extend vertically.

The gate region 210 may be disposed on the active region 250 . In some embodiments, the gate region 210 may be disposed on the drain region 220 and the source region 230 . Gate region 210 may extend vertically. In some embodiments, gate region 210 may be rectangular. In some embodiments, gate region 210 may be disposed adjacent drain region 220 . Gate region 210 may be disposed adjacent to source region 230 . In some embodiments, the gate region 210 may be disposed between the drain region 220 and the source region 230 .

A shallow trench isolation structure 240 may be disposed around the active region 250 . That is, the shallow trench isolation structure 240 may be disposed around the source region 230 and the drain region 220 . In some embodiments, shallow trench isolation structure 240 may surround active region 250 . In some embodiments, gate region 210 may be disposed on shallow trench isolation structure 240 . In some embodiments, gate region 210 may be disposed across shallow trench isolation structure 240 .

In some embodiments, oxide layer 265 may be disposed between active region 250 and shallow trench isolation structure 240 . Oxide layer 265 may be disposed around active region 250 . That is, the oxide layer 265 may be disposed around the source region 230 and the drain region 220 . In some embodiments, oxide layer 265 may surround active region 250 . In some embodiments, gate region 210 may be disposed on oxide layer 265 . In some embodiments, gate region 210 may be disposed across oxide layer 265 .

FIG. 2B is a schematic cross-sectional view illustrating the semiconductor device 200 along the cross-section line A-A of FIG. 2A according to some embodiments of the present disclosure. FIG. 2B shows a semiconductor device 200A, which is a cross-section of the semiconductor device 200 of FIG. 2A . The semiconductor device 200A may include a gate region 210, a drain region 220, a source region 230, a shallow trench isolation structure 240, an active region 250, a gate oxide layer 260, an oxide layer 265, contacts Points 211, 221, 231 and metal layers 212, 222, 232. In some embodiments, the semiconductor device 200A may be a PMOS structure.

Referring to FIG. 2B , the active region 250 includes a drain region 220 and a source region 230 . In some embodiments, active region 250 may be doped. For example, active region 250 may be doped with N-type dopants. In some embodiments, the drain region 220 and the source region 230 may be doped with different dopants than the active region 250 . For example, the drain region 220 and the source region 230 may be doped with P-type dopants.

The gate area 210 is provided on the active area 250. In some embodiments, the gate region 210 may be disposed on the drain region 220 and the source region 230 . In one embodiment, a portion of the gate region 210 may overlap a portion of the drain region 220 . In another embodiment, a portion of the gate region 210 may overlap a portion of the source region 230 . In some embodiments, an edge portion of the gate region 210 may overlap an edge portion of the drain region 220 . In some embodiments, an edge portion of the gate region 210 may overlap an edge portion of the source region 230 .

In some embodiments, gate oxide layer 260 may be disposed between gate region 210 and active region 250 . In some embodiments, the gate oxide layer 260 may be horizontally disposed between the drain region 220 and the source region 230 . Gate oxide layer 260 may have a width that is approximately the same as gate region 210 . In some embodiments, the width of gate oxide layer 260 may exceed the width of gate region 210 .

In some embodiments, the gate oxide layer 260 may be disposed on the drain region 220 and the source region 230 . In one embodiment, a portion of the gate oxide layer 260 may overlap a portion of the drain region 220 . In another embodiment, a portion of gate oxide layer 260 may overlap a portion of source region 230 .

In some embodiments, the gate oxide layer 260 may have a side surface that is coplanar with a side surface of the drain region 220 . The gate oxide layer 260 may have one side surface that is coplanar with one side surface of the source region 230 . That is, the width of the gate oxide layer may be the same as the distance between the drain region 220 and the source region 230 .

Referring to FIGS. 2A and 2B , the shallow trench isolation structure 240 may be disposed around the active region 250 . In some embodiments, shallow trench isolation structure 240 may surround active region 250 . The shallow trench isolation structure 240 may have an upper surface substantially aligned with an upper surface of the active region 250 . In some embodiments, the upper surface of shallow trench isolation structure 240 may be misaligned with the upper surface of active region 250 . Shallow trench isolation structure 240 may be separated from active region 250 by a distance. In some embodiments, shallow trench isolation structure 240 may be separated from drain region 220 by a distance. In some embodiments, the shallow trench isolation structure 240 may include a material of silicon nitride (SiN) or other suitable materials.

The oxide layer 265 is disposed between the active region 250 and the shallow trench isolation structure 240 . In some embodiments, oxide layer 265 may surround active region 250 . In some embodiments, the material of oxide layer 265 may be similar to the material of gate oxide layer 260 . In another embodiment, the material of oxide layer 265 may be different from the material of gate oxide layer 260 . Oxide layer 265 may have an upper surface generally aligned with the upper surface of active region 250 . In some embodiments, the upper surface of oxide layer 265 may be misaligned with the upper surface of active region 250 . In some embodiments, oxide layer 265 may be a sidewall oxide. The sidewall oxide is disposed adjacent the drain region 220, the source region 230, or the active region 250.

In some embodiments, contact point 211 is provided on gate region 210 . Contact point 211 may have an upper width and a lower width. In one embodiment, the upper width of the contact point 211 may be the same as the lower width. In another embodiment, the upper width of the contact point 211 may exceed the lower width. In other words, the contact point 211 tapers toward the gate region 210 .

In some embodiments, contact point 221 is provided on drain region 220 . Contact point 221 may have an upper width and a lower width. In some embodiments, the upper width of contact point 221 may exceed the lower width. In other words, the contact point 221 may taper toward the drain region 220 .

In some embodiments, contact 231 is provided on source region 230 . Contact point 231 may have an upper width and a lower width. In some embodiments, the upper width of contact point 231 may exceed the lower width. In other words, the contact point 231 may be tapered toward the source region 230 .

Metal layer 212 may be disposed on gate region 210 . The metal layer 212 is electrically connected to the gate region 210 via the contact point 211 . In some embodiments, gate region 210 is configured to receive electrical signals (voltage or current) from metal layer 212 . In some embodiments, a voltage V _G of the gate region 210 may be obtained at the metal layer 212 .

Metal layer 222 may be disposed on drain region 220 . The metal layer 222 is electrically connected to the drain region 220 via the contact point 221 . In some embodiments, drain region 220 is configured to receive an electrical signal (voltage or current) from metal layer 222 . In some embodiments, a voltage V _D of the drain region 220 may be obtained at the metal layer 222 .

Metal layer 232 may be disposed on source region 230. The metal layer 232 is electrically connected to the source region 230 via the contact point 231 . In some embodiments, source region 230 is configured to receive electrical signals (voltage or current) from metal layer 232 . In some embodiments, a voltage V _B of source region 230 may be obtained at metal layer 232 .

In some embodiments, metal layer 222 may be flush with metal layer 232 . In some embodiments, metal layer 212 may be flush with metal layer 222 . In some embodiments, metal layer 212 may be flush with metal layer 232 . That is, the metal layers 212, 222, and 232 may be substantially on the same plane.

FIG. 2C is a schematic cross-sectional view illustrating the semiconductor device 200 along the cross-section line B-B of FIG. 2A according to some embodiments of the present disclosure. FIG. 2C shows a semiconductor device 200B, which is a cross-section of the semiconductor device 200 of FIG. 2A . The semiconductor device 200B may include a gate region 210, a shallow trench isolation structure 240, an active region 250, a gate oxide layer 260 and an oxide layer 265.

As shown in FIG. 2C , gate oxide layer 260 is disposed on oxide layer 265 . In some embodiments, gate oxide layer 260 may be disposed on a portion of oxide layer 265 . Gate oxide layer 260 may be disposed on shallow trench isolation structure 240 . In some embodiments, gate oxide layer 260 is disposed over a portion of shallow trench isolation structure 240 . In some embodiments, shallow trench isolation structure 240 may be laterally spaced apart from the active region by a distance. In some embodiments, oxide layer 265 may fill between shallow trench isolation structure 240 and active region 250 .

Referring back to FIG. 2B , metal layer 222 of drain region 220 may be configured to receive a stress voltage. In some embodiments, the stress voltage may have a magnitude that exceeds an operating voltage of the semiconductor device (or PMOS) 200A. For example, the magnitude of the stress voltage may be more than twice the operating voltage. When the operating voltage of PMOS 200A is -2.5V, the stress voltage can be less than -5V.

When a stress voltage is applied to the drain region 220, a plurality of electrons accumulate in the drain region 220, and the drain region 220 is doped with N-type dopants. The electrons accumulated in the drain region 220 may cause holes to accumulate in that portion of the active region 250, which is doped with P-type dopants. In some embodiments, the holes may accumulate in the portion of active region 250 adjacent drain region 220 . In some embodiments, the holes accumulate in the portion of the active region 250 between the drain region 220 and the source region 230 . Since the holes are accumulated in the portion of the active region 250 (as shown in FIG. 2C ), the electrons can be accumulated in the portion of the shallow trench isolation structure 240 . In some embodiments, the electrons accumulated in the portion of shallow trench isolation structure 240 may correspond to the portion of holes accumulated in active region 250 . Therefore, the electrons accumulate in the portion of the shallow trench isolation structure 240 adjacent the active region 250 , which is adjacent the drain region 220 . In some embodiments, the electrons may accumulate in a portion of shallow trench isolation structure 240 adjacent to drain region 220.

In some embodiments, the electrons are easily trapped in the shallow trench isolation structure 240 once attracted to the holes in the portion of the active region 250 . Even if the stress voltage is no longer applied to the drain region 220, the electrons may still be trapped in the shallow trench isolation structure 240 (as shown in FIG. 2C). Therefore, due to the electrons trapped in the shallow trench isolation structure 240, the holes are still accumulated in that portion of the active region 250, so that a conductive path can be established through the drain region 220 to the source region 230 (eg, shown in Figure 2B).

Under normal operation of PMOS 200A, a conductive path through drain region 220 to source region 230 is established via a gate voltage applied across gate region 210 . Conversely, after trapping the electrons in the shallow trench isolation structure 240, a conductive path can be established without a voltage being applied to the gate region. PMOS 200A may be a fuse element with high resistance before the stress voltage is applied, where the fuse element has not yet been blown. After applying a stress voltage to the drain region 220 to accumulate the electrons in the shallow trench isolation structure 240, the fuse element 200A can be blown to a lower resistance.

In order to activate this effect or to blow the fuse element 200, the shallow trench isolation structure 240 and the active region 250 must be close enough. For example, the distance between the shallow trench isolation structure 240 and the active region 250 can be less than 14 nm, whereby the electrons can be easily trapped in the shallow trench isolation structure 240 . In some embodiments, PMOS 200 may be a short channel device. The channel of the PMOS 200 may be located between the drain region 220 and the source region 230 . In some embodiments, a length of the channel of the PMOS 200 may be the distance between the drain region 220 and the source region 230 . Due to the short channel, PMOS 200 can be easily blown. For example, the length of the channel may be less than 0.20 μm. In some embodiments, the length of the channel may be less than 0.18 μm. In some embodiments, PMOS 200 may be a planar transistor.

Currently available oxide fuse elements blow at an extremely high voltage to break down the gate oxide. The breakdown voltage of an oxide fuse element can change due to process variations, thereby reducing the efficiency of the oxide fuse element. The present disclosure provides a fuse element that can blow at relatively low voltage. Compared with traditional antifuses, the fuse element of the present disclosure requires a reduced area.

FIG. 3 is a schematic structural diagram illustrating a semiconductor device 300 according to some embodiments of the present disclosure. The semiconductor component 300 includes a fuse component 310 and a semiconductor backup unit 320 . In some embodiments, semiconductor backup unit 320 may correspond to semiconductor backup unit 120 in FIGS. 1A and 1B .

In some embodiments, the fuse element 310 may be the fuse element 200 described above. The fuse element 310 may have a gate terminal, a drain terminal, and a source terminal. In some embodiments, semiconductor backup unit 320 may be electrically connected to the source terminal of fuse element 310 . The gate terminal, drain terminal, and source terminal of fuse element 310 may be configured to receive voltage or current. In some embodiments, the source terminal may be configured to receive a power signal. When the fuse element 310 has not been blown, the semiconductor backup unit 320 cannot be started due to insufficient current passing through it. Before the fuse element 310 blows, the fuse element 310 has a high resistance drain terminal and a source terminal. Therefore, the semiconductor backup unit 320 is considered disconnected.

To activate fuse element 310, a stress signal V _B (voltage or current) may be applied to the drain terminal of fuse element 310. Therefore, a plurality of electrons accumulate in a portion of the shallow trench isolation structure of the fuse element 310 so that a conductive path 301 can be created through the drain terminal and the source terminal. In other words, blow fuse element 310 may be electrically conductive. After the fuse element 310 is blown, it has a conductive path 301 from the drain terminal to the source terminal, and therefore the semiconductor backup unit 320 can be activated.

FIG. 4 is a graph illustrating a graph of gate voltage VG versus current Id flowing through the drain of some embodiments of the semiconductor device of the present disclosure. Please refer to FIG. 4. The x-axis represents the voltage VG of the gate of the fuse element 310 in FIG. 3 in arbitrary units (A.U.). The y-axis represents the current Id in arbitrary units (A.U.) through the drain of fuse element 310 in FIG. 3 . Line segment 401 indicates that the unblown fuse element 310 operates as a normal PMOS. According to line segment 401, the unblown fuse element 310 may have an increasing current Id through the drain (from source to drain) as the voltage VG decreases, where decreasing voltage means a greater voltage magnitude. Line segment 402 shows that blown fuse element 310 is conductive even though it has no voltage applied to its gate. According to the line segment 402, when the voltage VG is zero, the blown fuse element 310 has a current Id passing through the drain region.

FIG. 5 is a flowchart illustrating a method 500 for activating a semiconductor backup unit according to some embodiments of the present disclosure. In some embodiments, this method may be implemented on semiconductor device 300 in FIG. 3 . Method 500 may be used to activate a semiconductor backup unit 320 as shown in FIG. 3 . In some embodiments, the method 500 for activating a semiconductor spare unit of a memory may include steps 510, 520, 530, 540, and 550.

For better understanding, the method 500 may be described with reference to FIGS. 2A to 2C and the semiconductor element (fuse element or PMOS) 200/200A/200B/310 shown in FIG. 3.

In step 510, a fuse element may be provided in a memory. The fuse element can be connected to the semiconductor spare unit (redundant memory cell or bit). In some embodiments, the fuse element 200/200A/200B may include an active region, a gate region, and a shallow trench isolation structure. The gate region is disposed on the active region, and the shallow trench isolation structure surrounds the active region. district. In some embodiments, the active region includes a source region and a drain region, and the drain region is disposed next to the source region.

In step 520, a stress voltage may be applied to the drain region of the fuse element. Details of this stress voltage have been provided previously and are therefore omitted here for the sake of clarity.

In step S530, a plurality of electrons are accumulated in a portion of the shallow trench isolation structure adjacent to the drain region. As shown in FIGS. 2B and 2C , since the stress voltage is applied to the drain region, the electrons may accumulate in the portion of the shallow trench isolation structure adjacent to the active region and the drain region.

In step 540, a conductive path may be created through the drain region and the source region of the fuse element so that the fuse element may be conductive. According to the description related to FIGS. 2B and 2C , with the electrons accumulated in the portion of the shallow trench isolation structure, the fuse element may have a conductive path through the drain region to the source region. In other words, the PMOS channel can be created in response to the electrons trapped in the shallow trench isolation structure.

In step 550 , the semiconductor backup unit 320 may be activated via blowing the fuse element 310 . In some embodiments, semiconductor backup unit 320 may be electrically connected to other components via blown fuse component 310 . That is, the semiconductor backup unit 320 can be switched from redundant to normal.

An embodiment of the present disclosure provides a fuse element. The fuse element includes an active region, including: a source region; a drain region disposed next to the source region; a gate region disposed on the active region; and a shallow trench isolation structure surrounding The active zone. Additionally, the drain region includes a terminal configured to receive a stress voltage to establish a conductive path through the drain region to the source region.

Another embodiment of the present disclosure provides a semiconductor device including a PMOS. The PMOS includes an active region, including: a source region; a drain region disposed next to the source region; a gate region disposed on the active region; and a shallow trench isolation structure disposed on the around the active zone. Additionally, the drain region includes a terminal configured to receive a first voltage to establish a conductive path from the drain region to the source region, wherein when no external voltage is applied to the gate region, The conductive path remains unchanged.

Another embodiment of the present disclosure provides a method of activating a semiconductor backup unit. The method includes providing a fuse element for connection to the semiconductor backup unit. The fuse element includes an active region, including: a source region; a drain region disposed next to the source region; a gate region disposed on the active region; and a shallow trench isolation structure surrounding The active zone. The method also includes applying a stress voltage to the drain region of the fuse element; accumulating a plurality of electrons in a portion of the shallow trench isolation structure adjacent to the active region; and generating a conductive path through the conductive path. a drain region to the source region so that the fuse element is conductive; and the semiconductor backup unit is activated via the fuse element.

The present disclosure provides a fuse element with a structure similar to a PMOS, so that the required area of the fuse element can be reduced with the development of manufacturing technology. The fuse element of the present disclosure utilizes a stress signal applied to its drain electrode to cause an effect to establish a conductive path from the drain electrode to the source electrode. When the conductive path is established, the fuse element is deemed to have blown. That is, the PMOS is turned on regardless of whether the gate is configured to receive a control signal. In other words, the PMOS channel can be generated without gate voltage. The stress signal that causes this effect is lower than that of a conventional fuse.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100: semiconductor element 110: fuse element 110a: fuse element 120: semiconductor backup unit 200: semiconductor element 200A: semiconductor element 200B: semiconductor element 210: gate region 211: contact point 212: metal layer 220: drain region 221 :Contact point 222: Metal layer 230: Source area 231: Contact point 232: Metal layer 240: Shallow trench isolation structure 250: Active area 260: Gate oxide layer 265: Oxide layer 300: Semiconductor element 301: Conductive path 310: Fuse element 320: Semiconductor backup unit 401: Line segment 402: Line segment 500: Method 510: Step 520: Step 530: Step 540: Step 550: Step Id: Current V _B : Voltage V _D : Voltage V _G : Voltage VG : Voltage V _H : Relatively high voltage V _L : Relatively low voltage

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like element numbers refer to similar elements throughout the drawings. 1A and 1B are schematic structural diagrams illustrating semiconductor devices used to activate a semiconductor backup unit according to some embodiments of the present disclosure. FIG. 2A is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic cross-sectional view illustrating a semiconductor device along the cross-section line A-A of FIG. 2A according to some embodiments of the present disclosure. FIG. 2C is a schematic cross-sectional view illustrating a semiconductor device along the cross-section line B-B of FIG. 2A according to some embodiments of the present disclosure. FIG. 3 is a schematic structural diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a graph illustrating a gate voltage versus a current flowing through a drain of a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a schematic flowchart illustrating a method of activating a semiconductor backup unit according to some embodiments of the present disclosure.

200:Semiconductor components 210: Gate area 220: Drainage area 230: Source region 240:Shallow trench isolation structure 265:Oxide layer

Claims (11)

A method for starting a semiconductor backup unit, including: Connect a fuse element to a semiconductor backup unit, wherein the fuse element includes: An active area, including: a source region; and a drain region, arranged next to the source region; a gate area disposed on the active area; and a shallow trench isolation structure surrounding the active area; applying a stress voltage to the drain region of the fuse element; A plurality of electrons are accumulated in a portion of the shallow trench isolation structure adjacent to the active region; and Creating a conductive path through the drain region to the source region such that the fuse element is conductive; and The semiconductor backup unit is activated via the fuse element. The startup method of a semiconductor backup unit as claimed in claim 1, wherein the fuse element includes a PMOS. The startup method of a semiconductor backup unit as described in claim 2, wherein the PMOS is a short channel element, and the short channel element has a channel length of less than 0.2 μm. The startup method of a semiconductor backup unit as described in claim 2, wherein the stress voltage has a magnitude greater than twice an operating voltage of the PMOS. The method for starting a semiconductor backup unit as described in claim 1, wherein the stress voltage has a magnitude greater than 5V. The startup method of a semiconductor backup unit as claimed in claim 1, wherein the shallow trench isolation structure is laterally separated from the active region by a distance. The startup method of a semiconductor backup unit as claimed in claim 6, wherein the distance between the shallow trench isolation structure and the active region is less than 14 nm. The startup method of a semiconductor backup unit as described in claim 6 further includes an oxide layer filling between the shallow trench isolation structure and the active region. The startup method of a semiconductor backup unit as claimed in claim 1, wherein when no external voltage is applied to the gate region, the conductive path remains unchanged. The startup method of a semiconductor backup unit as claimed in claim 1, wherein the shallow trench isolation structure includes a material of silicon nitride. The method for starting a semiconductor backup unit as claimed in claim 1 further includes a gate oxide layer disposed between the gate region and the active region.