TW201523791A - 用於三維結構塡充的方法與系統 - Google Patents
用於三維結構塡充的方法與系統 Download PDFInfo
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- TW201523791A TW201523791A TW103132503A TW103132503A TW201523791A TW 201523791 A TW201523791 A TW 201523791A TW 103132503 A TW103132503 A TW 103132503A TW 103132503 A TW103132503 A TW 103132503A TW 201523791 A TW201523791 A TW 201523791A
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- Prior art keywords
- trench
- sidewall
- ion beam
- deposition
- angle
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- 238000000034 method Methods 0.000 title claims abstract description 131
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- 238000000231 atomic layer deposition Methods 0.000 claims description 12
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Classifications
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本文之實施例包括用於三維結構填充之方法及系統。在一個實施例中,用於填充晶圓中之溝槽之方法包括利用與溝槽側壁成一角度之離子射束執行定向電漿處理以形成側壁之已處理部分及溝槽之未處理底部。材料沉積在溝槽中。材料在側壁之已處理部分上之沉積速率不同於在溝槽之未處理底部上之第二沉積速率。在一個實施例中,一種方法包括在晶圓上沉積材料,填充溝槽之底部,及在溝槽之側壁及溝槽鄰近處之頂表面上形成層。該方法包括利用與側壁成一角度之離子射束蝕刻該層。
Description
本發明之實施例係關於半導體處理之領域,及特定
而言係關於用於三維(three-dimensional;3D)結構填充之方法。
半導體晶圓處理可涉及在半導體晶圓或基板中形成
及填充溝槽。利用材料填充半導體晶圓或基板中之溝槽可被稱作「間隙填充」。間隙填充用於多種應用,如用於矽通孔(through-silicon via;TSV)之形成。隨著溝槽寬度變得更狹窄及溝槽深寬比增大,填充溝槽之製程變得更具挑戰性。
一種現有間隙填充方法是旋塗。旋塗通常涉及利用
旋塗機器用液體材料塗佈晶圓或基板。旋塗機可包括固持及旋轉晶圓或基板之旋轉軌道,及位於旋轉軌道中心之施配液體材料之噴嘴。旋塗機使晶圓或基板旋轉,及由此將材料施配至整個晶圓表面及溝槽內。在旋塗方法中,溶劑用以控制所施配之液體材料的黏度,此溶劑將雜質引入所填充之溝槽內。所填充的溝槽中之雜質可能降低由所填充之溝槽形成之
裝置的效能及良率。此外,旋塗涉及在沉積液體材料之後的後處理步驟,如固化所沉積之材料。
另一現有間隙填充方法涉及經由化學氣相沉積
(chemical vapor deposition;CVD)、原子層沉積(atomic layer deposition;ALD)、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition;PECVD),或物理氣相沉積(physical vapor deposition;PVD)進行之填充材料之沉積。填充溝槽之CVD、ALD、PECVD,及PVD方法通常導致沉積在溝槽之上部側壁上的材料多於沉積在溝槽之底部及下部側壁上的材料。該等方法亦導致更多材料沉積在溝槽鄰近處之頂表面上。第1圖圖示具有溝槽101之半導體晶圓100之橫剖面視圖,該溝槽101已經由該種沉積製程而填充。該沉積製程使材料103中沉積在溝槽側壁104之上部及頂表面108上的材料多於沉積在溝槽101底部102上之材料。不均勻的沉積形成凸起,此凸起可使溝槽開口在完全填充間隙之前閉合,從而導致空隙106。
諸如有害空隙之間隙填充缺陷可導致不良的裝置效
能、有缺陷的裝置,及晶粒間或晶圓間之高變異性。
本發明之一或更多個實施例係針對三維(three-dimensional;3D)結構填充之方法。
在一個實施例中,填充半導體晶圓中之溝槽之方法涉及利用與溝槽側壁成一角度之離子射束執行定向電漿處理以形成側壁之已處理部分及溝槽之未處理底部。該方法亦包
括在溝槽中沉積材料。材料在側壁之已處理部分上之沉積速率不同於在溝槽之未處理底部上之第二沉積速率。
在一個實施例中,用以填充半導體晶圓中之溝槽之
系統包括電漿腔室以產生與溝槽側壁成一角度之離子射束,以形成側壁之已處理部分及溝槽之未處理底部。系統亦包括沉積腔室以將材料沉積在溝槽中,其中材料在側壁之已處理部分上之沉積速率不同於在溝槽之未處理底部上之第二沉積速率。
在一個實施例中,填充半導體晶圓中之溝槽之方法
涉及將材料沉積在半導體晶圓上,填充溝槽底部,及在溝槽側壁及在溝槽鄰近處之頂表面上形成層。該方法亦涉及利用與側壁成一角度之離子射束蝕刻溝槽側壁及頂表面上之層。
100‧‧‧半導體晶圓
101‧‧‧溝槽
102‧‧‧底部
103‧‧‧材料
104‧‧‧側壁
106‧‧‧空隙
108‧‧‧頂表面
200‧‧‧方法
202‧‧‧操作
204‧‧‧操作
300A‧‧‧橫剖面視圖
300B‧‧‧橫剖面視圖
300C‧‧‧橫剖面視圖
300D‧‧‧橫剖面視圖
302‧‧‧半導體晶圓
304‧‧‧溝槽
306‧‧‧底部
308‧‧‧側壁
310‧‧‧頂表面
312‧‧‧已處理表面/已處理部分
314A‧‧‧帶角度離子射束
314B‧‧‧帶角度離子射束
316‧‧‧箭頭
318‧‧‧材料
320‧‧‧箭頭
400‧‧‧方法
402‧‧‧操作
404‧‧‧操作
406‧‧‧操作
500A‧‧‧橫剖面視圖
500B‧‧‧橫剖面視圖
500C‧‧‧橫剖面視圖
500D‧‧‧橫剖面視圖
500E‧‧‧橫剖面視圖
500F‧‧‧橫剖面視圖
502‧‧‧層
504A‧‧‧帶角度離子射束
504B‧‧‧帶角度離子射束
506‧‧‧箭頭
600‧‧‧系統
602‧‧‧主機
604‧‧‧晶圓裝載埠
606‧‧‧處理腔室
608‧‧‧處理腔室
610‧‧‧處理腔室
700‧‧‧系統
702‧‧‧掃描系統
704‧‧‧處理站
706‧‧‧處理站
708‧‧‧處理站
800‧‧‧系統
801‧‧‧半導體晶圓
802‧‧‧腔室
803‧‧‧閥
804‧‧‧平臺
805‧‧‧泵
806‧‧‧箭頭
807‧‧‧離子射束
808‧‧‧頂部
812‧‧‧射頻來源
814‧‧‧螺旋天線
816‧‧‧偏壓電源
820‧‧‧平面天線
900A‧‧‧圖
900B‧‧‧圖
902‧‧‧底部
904‧‧‧側壁
906‧‧‧離子射束
1000‧‧‧電腦系統
1002‧‧‧處理器
1004‧‧‧主記憶體
1006‧‧‧靜態記憶體
1008‧‧‧網路介面裝置
1010‧‧‧視訊顯示單元
1012‧‧‧文數字輸入裝置
1014‧‧‧游標控制裝置
1016‧‧‧信號產生裝置
1018‧‧‧輔助記憶體
1020‧‧‧網路
1022‧‧‧軟體
1026‧‧‧處理邏輯
1030‧‧‧匯流排
1031‧‧‧機器可存取儲存媒體
本發明之實施例是以實例而非限制之方式進行說明,及可在結合以下圖式進行考慮的情況下,藉由參考下文中之詳細描述而得以更充分地理解本發明之實施例:第1圖圖示具有溝槽之半導體晶圓之橫剖面視圖,該溝槽已經由沉積製程而填充,該沉積製程使溝槽中產生未填充的空隙;第2圖是表示依據本發明之一實施例用於填充半導體晶圓中之溝槽的方法中之操作的流程圖;第3A圖、第3B圖、第3C圖,及第3D圖圖示在執行依據本發明之實施例對應於第2圖之流程圖中之操作的間隙填充方法期間,包括溝槽之半導體晶圓之橫剖面視圖;
第4圖是表示依據本發明之一實施例用於填充半導體晶圓中之溝槽的間隙填充方法中之操作的流程圖;第5A圖、第5B圖、第5C圖、第5D圖、第5E圖,及第5F圖圖示在執行依據本發明之實施例對應於第4圖之流程圖中之操作的間隙填充方法期間,包括溝槽之半導體晶圓之橫剖面視圖;第6圖圖示依據本發明之一實施例位於群集配置中之整合系統的平面示意圖,該整合系統用以填充半導體晶圓中之溝槽;第7圖圖示依據本發明之一實施例之位於線性配置中之整合系統的平面示意圖,該整合系統用以填充半導體晶圓中之溝槽;第8圖圖示依據本發明之一實施例之示例性定向電漿處理系統,該系統用以產生用於間隙填充方法中之帶角度離子射束;第9A圖圖示依據本發明之一實施例用於間隙填充方法中之離子射束的示例性離子角分佈圖;第9B圖圖示依據本發明之一實施例正在被帶角度離子射束擊打之溝槽的橫剖面視圖,該等離子射束具有如第9A圖之圖中所示之角分佈;及第10圖圖示依據本發明之一實施例之示例性電腦系統的方塊圖,該電腦系統控制本文所述之方法中之一或更多個操作之執行。
本文描述用於三維結構填充之設備、系統,及方法。
三維結構填充可包括利用材料填充半導體晶圓或基板中之溝槽,亦被稱作間隙填充。術語「溝槽」用於以下描述中以指示能夠在半導體晶圓或基板中經填充之任何孔或其他三維結構。
本發明之實施例涉及利用一或更多個帶角度離子射
束以處理溝槽側壁之部分以更改填充材料在已處理部分上之沉積速率。側壁之已處理「部分」可包括整體側壁,或小於整體側壁。帶角度離子射束可在不處理溝槽底部之情況下處理部分或全部溝槽側壁。填充材料在已處理部分上之沉積速率可低於在未處理底部上之沉積速率,從而在不在溝槽開口處形成凸起或由該等凸起產生空隙之情況下自底向上進行填充。其他實施例涉及處理側壁之部分以相對於在未處理溝槽底部提高填充材料在側壁上之沉積速率。在溝槽側壁上之提高的沉積速率可導致層在溝槽側壁上之形成,該層被稱作間隔層。
在本發明之一個實施例中,間隙填充方法涉及多步
驟製程之一或更多個循環,該製程包括材料沉積及利用一或更多個帶角度離子射束進行蝕刻。帶角度離子射束允許在不顯著蝕刻溝槽底部之情況下對凸起進行蝕刻以保持溝槽開口清潔。一個該種實施例賦能在不形成空隙之情況下自底向上之間隙填充。
在下文之描述中,闡述諸如用於產生帶角度離子射
束之特定系統之多數個特定細節,以便提供對本發明之實施
例的全面理解。熟習該項技術者將顯而易見,本發明之實施例可在沒有該等特定細節之情況下得以實施。在其他情況中,並未詳細描述眾所熟知之態樣,如用於在半導體晶圓或基板上形成層之沉積化學品,以免不必要地使本發明之實施例模糊不清。此外,將理解,圖式中圖示之多種實施例是說明性表示,及不一定按比例繪製。
第2圖是依據本發明之一實施例之表示用於填充半
導體晶圓中之溝槽的方法中之操作的流程圖。第3A圖、第3B圖、第3C圖,及第3D圖圖示在執行依據本發明之實施例對應於第2圖之方法200中之操作的用於填充溝槽之方法期間,包括溝槽之半導體晶圓之橫剖面視圖。
第2圖中之方法200開始於包括溝槽之半導體晶圓
或基板,如第3A圖中之半導體晶圓或基板。第3A圖圖示具有溝槽304之半導體晶圓302之橫剖面視圖300A。溝槽304具有底部306及側壁308。溝槽304可藉由例如對半導體晶圓302進行電漿蝕刻或藉由任何其他形成溝槽之手段而形成。第3A圖中圖示之溝槽304具有垂直輪廓,然而,半導體晶圓302可包括具有錐形輪廓或其他輪廓之溝槽,或其他能夠經填充之三維結構。半導體晶圓302之頂表面310鄰近於溝槽304。
方法200之操作202對應於第3B圖,及該操作涉及
利用帶角度離子射束314A處理溝槽側壁308之一部分及頂表面310。由此,在操作202中,離子射束產生設備產生帶角度離子射束314A以擊打溝槽側壁308之一部分及半導體晶圓302之頂表面310,以形成已處理之表面312。第8圖圖示用
以產生帶角度離子射束之離子射束產生設備(定向電漿處理系統800)之一個實例,及該實例在下文中進行更詳細之論述。在第3B圖中圖示之實施例中,離子射束產生設備產生兩個帶角度離子射束314A及314B以利用離子同時轟擊兩個側壁部分。其他實施例可包括單個帶角度離子射束,或兩個以上之帶角度離子射束。
離子射束314A及314B處理經轟擊之表面。根據實
施例,定向電漿處理涉及離子輔助電漿處理以更改已處理區域之性質,以影響已處理區域表面上之沉積速率。離子輔助電漿處理可包括例如離子佈植、離子輔助沉積,或離子混合。
已處理區域可產生與未處理區域相比較高或較低之沉積速率,如下文中更為詳細之解釋。用以更改已處理表面312上之沉積速率之處理可涉及例如增大摻雜劑濃度、更改已處理區域之摻雜劑或雜質分佈、更改表面疏水性、使用雜質污染表面,或損害已處理表面。在涉及更改摻雜劑或雜質分佈之一實施例中,處理可使示例性實施例中之已處理區域具有表面峰值、倒退,或箱形摻雜劑分佈。在一個實施例中,離子射束處理使用低能單體之分子離子。離子種類可為例如Si+、O+、N+、As+、B+、P+、H+、Al+、C+、F+,或適合於給定應用之任何其他分子離子。第3B圖圖示沉積在側壁表面上之已處理層312,該層增大側壁厚度。然而,在其他實施例中,定向電漿處理在不增大側壁厚度之情況下更改側壁之表面性質。
與傳統電漿製程中不同,離子射束314A及314B與
溝槽側壁308成一角度(亦即非零角度)。離子射束可包括離子之角分佈。角分佈之中心是「中心角」。由此,離子射束的角度由角分佈之中心角界定。第9A圖是一圖900A,該圖圖示離子角分佈之一個實例。圖900A圖示兩個離子射束906之雙向離子角分佈,如第9B圖中所圖示。離子射束906如圖900B中所圖示具有-30度及30度之中心角,且因此離子射束906與溝槽側壁904成30度角。帶角度離子射束906擊打溝槽側壁904,但不擊打溝槽底部902。返回第3B圖,該圖類似於第9B圖之離子射束906,離子射束314A及314B與側壁308成非零角度。例如,在一個實施例中,離子射束314A及314B與側壁308成1至85度範圍內之角度。由此,帶角度離子射束314A及314B可在不處理溝槽底部306之情況下處理側壁308之一些或全部部分。
在一個實施例中,根據一或更多個因素而決定離子
射束314A及314B之角度,該等因素例如溝槽304之深寬比、填充材料之化學組分、離子種類,及影響填充材料之沉積速率之其他製程參數。離子射束產生設備可針對狹窄的深溝槽產生與側壁308成更小角度之離子射束,及針對較寬之淺溝槽產生與側壁308成更大角度之離子射束。根據一實施例,最大離子射束角度經選擇以處理側壁308之一些或全部部分,但不處置溝槽底部306。儘管第3B圖圖示整體側壁308已經處理,但側壁之已處理部分312僅可包括上部側壁一定百分比。該等實施例可處理溝槽之上部側壁,同時保留底部側壁未經處理。如上文所指示,離子射束角度及待處理之溝
槽側壁之百分比可依據溝槽開口之寬度及溝槽深寬比而定。例如,根據一個實施例,為處理深寬比為大約5比1之溝槽之側壁,離子射束產生設備可產生具有一角度之離子射束以處理側壁頂部20%至30%。在另一實例中,為處理深寬比為大約4比1之溝槽之側壁,離子射束產生設備可產生具有一角度之離子射束以處理側壁之至少頂部80%。
離子射束產生設備可產生具有不同角度之離子射束以針對不同溝槽或甚至溝槽中之每一側壁實現不同效應。例如,在一個實施例中,離子射束產生設備利用具有第一角度之離子射束處理一個溝槽之側壁,然後利用具有第二角度之離子射束處理另一溝槽之側壁。該種處理可用於例如具有不同深寬比及/或寬度之溝槽的半導體晶圓。在另一實施例中,離子射束產生設備產生具有第一角度之一個離子射束以處理第一側壁,及產生具有第二角度之第二離子射束以處理同一溝槽之另一側壁。該種處理可用於以下溝槽:該等溝槽中有一面針對處理而言比另一面更為堅固。
如上文所指示,離子射束產生設備可產生一個帶角度離子射束或多個帶角度離子射束。同時產生多個離子射束賦能一個以上之側壁部分得經同時處理,從而縮減處理時間。然而,在一個實施例中,單個帶角度離子射束可較佳。例如,在一些情況下,處理側壁308之單個部分可足以阻止溝槽中出現有害的空隙。在實施例中,超出防止產生空隙所需之側壁以外處理其他側壁可能是不合乎需要的,因為處理表面涉及引入雜質或損害側壁表面。在溝槽側壁之一個面鄰
近於易於因側壁處理而受損害之特徵之一個實施例中,離子射束產生設備可處理側壁中針對處理而言更為堅固之一或更多個其他面。
在一些應用中,可能需要處理溝槽之全部面。例如,
對於圓柱形溝槽而言,離子射束產生設備可處理溝槽之整體周緣附近之上表面部分。在一個該種實施例中,離子射束產生設備包括旋轉台,半導體晶圓302經支撐在該旋轉臺上。
在處理側壁308之一個或兩個面之後,平臺可旋轉半導體晶圓302以處理側壁308之其他面。處理側壁面及旋轉半導體晶圓302之製程可持續直至處理了全部側壁面。離子射束產生設備亦可包括掃描系統以處理整個半導體晶圓302之多個溝槽中之側壁。掃描系統包括一機構,該機構用以使半導體晶圓302或離子射束來源相對於彼此移動,以處理相鄰溝槽,如箭頭316所圖示。
在操作202中處理側壁308之部分之後,沉積系統
在操作204中及如第3C圖之橫剖面視圖300C中所示將材料沉積在半導體晶圓302上。沉積可包括藉由CVD、ALD、PVD、PECVD,或其他類似之沉積方法進行之材料沉積。所沉積之材料可包括介電質、金屬(例如鈷、鋁,或其他金屬),或用於間隙填充之任何其他材料。材料在已處理表面312上以不同於在未處理的溝槽底部306上之速率沉積在溝槽304中。第3C圖圖示沉積速率在已處理表面312上較慢之一實例。由此,材料318在未處理的溝槽底部306處以較快速率沉積,及在已處理側面及已處理頂表面上以較慢速率沉積。
沉積之不同速率賦能在不產生有害空隙之情況下對深寬比較高的狹窄溝槽進行自底向上之填充(如箭頭320所指示)。
如上所述之自底向上填充方法之一個實例涉及利用
氮氣處理矽上部側壁以形成上部側壁之已處理之氮化矽部分。如在自正矽酸四乙酯(tetraethyl orthosilicate;TEOS)/臭氧中沉積氧化物之製程中,材料在未處理的溝槽底部上之沉積速率高於在已處理之上部側壁之沉積速率。因此,如第1圖所圖示,隨後之沉積製程不產生典型的凸起邊緣特徵,及溝槽可自底向上得以填充,而不會形成空隙。
在另一實施例中,及如第3D圖中所圖示,側壁308
經處理以加快在上部側壁上之沉積速率以在上部溝槽側壁上形成層,該層被稱作間隔層。
如第3D圖之橫剖面視圖300D中所圖示,離子射束
產生設備處理頂表面310及溝槽側壁308之上部部分以形成已處理部分312。然後,沉積系統在溝槽304中沉積材料。在圖示之實施例中,處理導致在已處理部分上之沉積速率高於在未處理之底部及未處理之下部側壁上之沉積速率。由此,所沉積之材料318在已處理之上部側壁上及在頂表面310上較厚。根據一個實施例,所沉積之材料318充當間隔層,該間隔層可在下面的層與沉積在溝槽304中之材料之間提供隔離。例如,定向電漿處理可在溝槽304頂部形成間隔層介電質,該間隔層介電質可賦能位於沉積在溝槽304中之多晶矽與下面的矽基板中有效面積之間之間隔層的所在位置中的改良隔離。
儘管第3D圖圖示溝槽304之兩個側壁308上之間
隔層,但其他實施例可僅在溝槽304之側壁308之一者上形成間隔層。此外,第3D圖圖示具有同等厚度及在溝槽304中延伸至同等深度之間隔層。在其他實施例中,間隔層可具有不同的厚度及/或延伸至溝槽304中之不同的深度。在一個該種實施例中,離子射束產生設備產生與側壁308成不同角度之離子射束以處理不同百分比之上部側壁。例如,離子射束產生設備可產生具有一角度之離子射束以處理溝槽之一側壁頂部20%,及產生另一離子射束以處理溝槽之相對側壁之頂部30%。在其他實施例中,如上文中之解釋,單個離子射束可處理溝槽304之一側,此舉可導致在溝槽304之一側壁上形成間隔層。為形成具有不同厚度之間隔層,離子射束產生設備可使用一化學品產生一離子射束以處理溝槽之一側壁,及使用不同的化學品產生另一離子射束以處理溝槽之相對側壁。
由此,第2圖之方法200圖示間隙填充方法,該方
法包括利用帶角度離子射束處理修改溝槽側壁之部分之材料性質。經修改之材料性質可導致在已處理部分上之更慢或更快的沉積速率,從而賦能對間隙填充製程之更精細之控制。
該方法可賦能在不產生空隙之情況下的自底向上之間隙填充,或可賦能間隔層之可控的產生。
第4圖是表示依據本發明之一實施例用於填充半導
體晶圓中之溝槽的另一方法中之操作的流程圖。第5A圖、第5B圖、第5C圖、第5D圖、第5E圖,及第5F圖圖示在執行
依據本發明之實施例對應於第4圖之流程圖中之操作的溝槽填充方法期間,包括溝槽之半導體晶圓之橫剖面視圖。與第2圖之方法200類似,第4圖之方法400開始於具有溝槽304之半導體晶圓302,如第5A圖之橫剖面視圖500A中所圖示。
方法400可涉及材料沉積及利用帶角度離子射束進行之蝕刻之多次迭代。在操作402中,及對應於第5B圖,沉積腔室將材料沉積在半導體晶圓302上,填充溝槽304之底部306,及在溝槽側壁及頂表面310上形成層502。沉積製程可使更多材料沉積在頂表面310及溝槽304之上部側壁上,如第5B圖之橫剖面視圖500B中所圖示。材料在上部側壁上之更多沉積導致凸起,使得溝槽304之開口開始閉合。
在操作402中之材料沉積之後,離子射束產生設備
在操作404中利用一或更多個帶角度離子射束蝕刻側壁上之層502,如第5C圖之橫剖面視圖500C中所圖示。在一個實施例中,將帶角度離子射束504A及504B導引至晶圓表面使所沉積之材料發生定向濺射或定向反應性離子蝕刻。不同於現有間隙填充方法,離子射束504A及504B與側壁308成一定角度,從而導致在不顯著蝕刻位於溝槽底部306處之所沉積材料之情況下,蝕刻側壁308及頂表面310上之層502。由此,帶角度離子射束504A及504B濺射形成於上部溝槽側壁上之凸起,從而再次打開溝槽304之頂部。儘管第5C圖中圖示兩個離子射束504A及504B,但其他實施例可使用一個帶角度離子射束或兩個以上之帶角度離子射束。
離子射束角度係指離子角分佈中之中心角,如第9A
圖之圖900A中所圖示之分佈。在實施例中,離子射束與側壁308所成之角度在1至85度範圍內。根據一個實施例,利用帶角度離子射束504A及504B蝕刻材料層包括使半導體晶圓302及離子射束來源相對於彼此移動,如藉由箭頭506所圖示。例如,在一個實施例中,掃描系統包括移動台以支撐及移動半導體晶圓302以將不同的溝槽304及頂表面310曝露於離子射束504A及504B。
如上文所提及,間隙填充法400可涉及沉積及帶角
度離子射束蝕刻之多次迭代。在一個實施例中,間隙填充系統執行操作402及404之四個或四個以上循環。由此,在操作406中,間隙填充系統控制器決定是否已完成操作402及404之所需循環數目。如若處理完成,則方法400終止。如若要執行額外的循環,則方法涉及重複操作402及404。第5D圖至第5F圖圖示操作402及404的額外循環。第5D圖圖示在第二沉積操作之後的半導體晶圓302之溝槽之橫剖面視圖500D,此操作導致對溝槽底部306之進一步填充及在溝槽側壁308及頂表面310上產生更厚的材料層502。第5E圖圖示在第二帶角度離子射束蝕刻操作之後之橫剖面視圖500E,該蝕刻操作用以在不顯著蝕刻溝槽304之底部306中沉積之材料的情況下蝕刻上部側壁及頂表面310上之材料。第5F圖圖示在第三沉積操作之後的橫剖面視圖500F,該操作使溝槽304之填充完成。如第5A圖至第5F圖中所圖示,方法400可在不形成空隙之情況下實現對狹窄溝槽之自底向上的間隙填充製程。
在另一實施例中,用於間隙填充之方法可結合第2
圖之方法200及第4圖之方法400,以包括利用帶角度離子射束對溝槽側壁308之一部分進行首次處理,隨後進行沉積與利用帶角度離子射束進行蝕刻之迭代。一個該種實施例可賦能利用更少側壁處理及/或第4圖之方法400中所述之沉積及蝕刻操作之更少迭代進行自底向上之間隙填充。例如,一個實施例可包括如方法200中所述之定向電漿處理以更改上部側壁之表面性質,以略微減慢在已處理部分上之沉積速率,但不減緩足以完全防止溝槽中之空隙形成之沉積速率。該種示例性方法可隨後繼續進行如第4圖之方法400中所述之一或更多個循環之沉積及定向蝕刻。
第6圖及第7圖圖示依據上述實施例之用於執行間
隙填充之示例性系統。第6圖圖示依據本發明之一實施例位於群集配置中之整合系統的平面示意圖。系統600之所圖示之群集配置包括連接至晶圓裝載埠604之中心定位主機602以將半導體晶圓或基板載入系統,及包括處理腔室606、608,及610以用於執行多種處理操作。主機包括機器人機構以用於在晶圓裝載埠604與處理腔室606、608,及610之間移送半導體晶圓或基板。
系統600包括預清潔腔室606以用於在腔室608及
610中進行處理之前清潔及準備好晶圓或基板。帶角度離子射束腔室608可包括可產生帶角度離子射束之任何設備。第8圖圖示能夠產生帶角度離子射束之電漿產生設備之一個該種實例,及該設備在下文中進行更詳細的描述。然而,亦可使
用能夠產生帶角度離子射束之其他系統,如射束線佈植系統。帶角度離子射束腔室608可為在例如50eV至50keV之範圍中操作之低能或高能系統,該系統具有多種劑量和佈植深度能力。在一個實施例中,帶角度離子射束腔室608產生帶角度離子射束以用於處理溝槽側壁,如上文針對第2圖之方法200所述。在一個實施例中,帶角度離子射束腔室608產生帶角度離子射束以用於對沉積在側壁上之材料執行定向蝕刻,如上文針對第4圖之方法400所述。
系統600亦包括沉積腔室610。沉積腔室可為任何
化學氣相沉積(chemical vapor deposition;CVD)腔室、原子層沉積(atomic layer deposition;ALD)腔室、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition;PECVD)、物理氣相沉積(physical vapor deposition;PVD)腔室,或任何其他適當之沉積腔室。其他系統可包括其他或不同處理腔室。
第7圖圖示依據本發明之一實施例之位於線性配置
中之整合系統的平面示意圖,該整合系統用以填充半導體晶圓中之溝槽。系統700之線性配置包括掃描系統702,該系統能夠在處理站704、706、708之間移動。儘管箭頭指示自預清洗站704至帶角度離子射束站706及最終至沉積站708之運動,但在一個實施例中,掃描系統亦可將半導體晶圓在帶角度離子射束站706與沉積站708之間來回移動。例如,第7圖中圖示之線性配置可用於間隙填充方法,該方法包括材料沉積及帶角度離子射束蝕刻之多個循環,如第4圖中描述之方法。在一個該種實施例中,掃描系統將正在處理之半導體
晶圓或基板在帶角度離子射束站706與沉積站708之間來回移動,直至間隙填充製程完成。
第8圖圖示依據本發明之一實施例之示例性定向電
漿處理系統,該系統用以產生用於間隙填充方法中之帶角度離子射束。系統800包括製程腔室802,該腔室可為根據一個實施例之真空腔室。系統800包括平臺804以用於支撐半導體晶圓801或基板用於處理。系統800包括掃描系統以移動平臺804,及因此相對於產生一或更多個帶角度離子射束807之離子射束來源而移動支撐在平臺804上方之半導體晶圓801。箭頭806圖示一個可能之軸,系統800可沿該軸移動平臺。平臺亦可在其他方向上移動,如沿垂直於頁之軸(亦即沿從頁出來之軸)移動,在由箭頭806及垂直於頁之表面所界定之平面內在其他方向上移動,及/或移向或移離離子射束來源。
在一個實施例中,平臺旋轉。平臺旋轉賦能利用離
子射束807擊打溝槽側壁之多個面。例如,在使用單一帶角度離子射束之一個實施例中,一種方法包括在每一處理操作中旋轉平臺804達180度。在一個該種實例中,離子射束處理溝槽側壁之一個面,系統800旋轉平臺804達180度,及離子射束處理溝槽側壁之相對面。由此,在一個該種實施例中,系統800利用兩次處理及一次平臺804旋轉來處理側壁之整體周緣或周長。在其它實施例中,兩次定向電漿處理可能不足以處理整體溝槽側壁周緣或周長。在一個該種實施例中,系統旋轉平臺804一次以上及執行兩次以上之定向電漿
處理。例如,在一個實施例中,系統800旋轉平臺804達0度、45度、90度、135度、180度、225度、270度,及315度。在每一次旋轉之後,系統800可處理側壁表面之一部分。
在其它實施例中,可在無平臺旋轉之情況下處理整體側壁周緣。例如,在具有能夠處理整體周緣或周長之兩個離子射束807之一實施例中,可在無平臺旋轉之情況下處理整體周緣。
在其他實施例中,不處理整體周緣或周長。例如,處理側壁之一半周緣或周長,及剩餘一半保留不處理。在進行定向電漿處理及/或平臺旋轉以處理一或更多個溝槽之後,系統800可隨後移動平臺(例如在箭頭806所指示之方向中之一方向上)以處理相鄰一或更多個溝槽。系統800可執行數個循環之平臺旋轉及/或移動以處理整個半導體晶圓或基板上之溝槽。
注入系統800中之氣體經由腔室802之頂部808進
入,及可由擋氣板810偏斜。閥803(例如擺閥)及泵805(例如渦輪泵)控制腔室802中之壓力。一個實施例進一步包括離子來源中之泵以用於來源與腔室802之間的壓力控制。射頻來源812將射頻功率供應至平面天線820及螺旋天線814中之一或兩者以產生電漿。偏壓電源816可提供脈衝信號(例如在50至20000伏特範圍內),該脈衝信號連接至平臺及具有脈衝啟動及關閉時段以使平臺804偏壓,及由此使半導體晶圓801偏壓以使離子自電漿向半導體晶圓801加速。圖示之系統800亦包括一或更多個電漿外鞘修改器822,該等修改器可為絕緣體、半導體,或導體。電漿外鞘修改器822控制
離子射束807之發射角度。由此,帶角度離子射束807可用於執行如上所述之一或更多個間隙填充實施例中。
第10圖圖示電腦系統1000,該電腦系統內可執行
指令集,該指令集用於使機器執行本文討論之刻劃方法中之一或更多者。示例性電腦系統1000包括經由匯流排1030彼此通信之處理器1002、主記憶體1004(例如唯讀記憶體(read-only memory;ROM)、快閃記憶體、諸如同步動態隨機存取記憶體(synchronous dynamic random access memory;SDRAM)或Rambus動態隨機存取記憶體(Rambus dynamic random access memory;RDRAM)之動態隨機存取記憶體(dynamic random access memory;DRAM),等)、靜態記憶體1006(例如快閃記憶體、靜態隨機存取記憶體(static random access memory;SRAM),等),及輔助記憶體1018(例如資料儲存裝置)。
處理器1002表示諸如微處理器、中央處理單元,或
類似物之一或更多個通用處理裝置。更特定而言,處理器1002可為複雜指令集計算(complex instruction set computing;CISC)微處理器、精簡指令集計算(reduced instruction set computing;RISC)微處理器、超長指令字(very long instruction word;VLIW)微處理器,等。處理器1002亦可是諸如特殊應用積體電路(application specific integrated circuit;ASIC)、現場可程式化閘陣列(field programmable gate array;FPGA)、數位信號處理器(digital signal processor;DSP)、網路處理器,或類似物之一或更多個專用處理裝置。處理器1002經配
置以執行處理邏輯1026以用於執行本文中論述之操作及步驟。
電腦系統1000可進一步包括網路介面裝置1008。
電腦系統1000亦可包括視訊顯示單元1010(例如液晶顯示器(liquid crystal display;LCD)或陰極射線管(cathode ray tube;CRT))、文數字輸入裝置1012(例如鍵盤)、游標控制裝置1014(例如滑鼠),及信號產生裝置1016(例如揚聲器)。
輔助記憶體1018可包括機器可存取儲存媒體(或更
特定而言電腦可讀取儲存媒體)1031,該儲存媒體上儲存有包含本文所述之方法或功能中任何一或更多個者之一或更多個指令集(例如軟體1022)。在藉由電腦系統1000對軟體1022之執行期間,軟體1022亦可完全或至少部分地位於主記憶體1004內及/或處理器1002內,主記憶體1004及處理器1002亦組成機器可讀取儲存媒體。可進一步經由網路介面裝置1008而在網路1020上傳輸或接收軟體1022。
儘管機器可存取儲存媒體1031在一示例性實施例中經圖示為單個媒體,但術語「機器可讀取儲存媒體」應被視作包括儲存一或更多個指令集之單個媒體或多個媒體(例如集中或分散式資料庫,及/或關連之快取記憶體及伺服器)。術語「機器可讀取儲存媒體」亦應被視作包括以下任何媒體:該媒體能夠儲存或編碼指令集以用於由機器執行,及使機器執行本發明之方法中之一或更多者。術語「機器可讀取儲存媒體」應由此被視作包括但不限定於固態記憶體、光學媒體及磁性媒體,及其他非臨時性機器可讀取儲存媒體。
由此,以上描述描述了用於三維結構填充之方法及
系統。應理解,以上描述旨在說明,而非限制性。例如,儘管圖式中之流程圖圖示由本發明之某些實施例執行之操作之特定次序,但應理解,該種次序並非必需(例如,替代性實施例可以不同次序執行操作,組合某些操作,重疊某些操作,等)。此外,熟習該項技術者在閱讀及理解以上描述之後將顯而易見諸多其他實施例。儘管本發明已藉由參考特定示例性實施例而進行描述,但應認識到,本發明並非限定於已描述之實施例,而是可在符合所附專利申請範圍之精神及範疇的潤飾及更改之情況下得以實施。因此,本發明之範疇應藉由參考所附之專利申請範圍及該專利申請範圍權利覆蓋之同等內容之完全範疇而經決定。
200‧‧‧方法
202‧‧‧操作
204‧‧‧操作
Claims (20)
- 一種用於填充一半導體晶圓中之一溝槽之方法,該方法包括以下步驟:利用與該溝槽之一側壁成一角度之一離子射束執行定向電漿處理,以形成該側壁之一已處理部分及該溝槽之一未處理底部;以及將一材料沉積在該溝槽中,其中該材料在該側壁之該已處理部分上之一沉積速率不同於在該溝槽之該未處理底部上之一第二沉積速率。
- 如請求項1所述之方法,其中執行該定向電漿處理之步驟包括產生與該側壁成在1至85度之一範圍中的角度之該離子射束。
- 如請求項1所述之方法,其中該溝槽具有大約5比1之一深寬比,及其中利用成該角度之該離子射束執行定向電漿處理之步驟包括處理該側壁之一頂部20%至30%。
- 如請求項1所述之方法,其中該溝槽具有大約4比1之一深寬比,及其中利用成該角度之該離子射束執行定向電漿處理之步驟包括處理該側壁之至少一頂部80%。
- 如請求項1所述之方法,其中執行該定向電漿處理之步驟包括產生與該溝槽之一第二側壁成一第二角度之一第二離子射束以形成該第二側壁之一第二已處理部分。
- 如請求項1所述之方法,其中執行該定向電漿處理之步驟損害該側壁之該已處理部分之一表面,以及其中該材料在該已處理部分上之該沉積速率慢於在該溝槽之該未處理底部上之該第二沉積速率。
- 如請求項1所述之方法,其中執行該定向電漿處理之步驟包括利用一離子種類產生該離子射束以更改該側壁之該已處理部分之一表面之一摻雜劑或雜質濃度、摻雜劑或雜質分佈或疏水性。
- 如請求項1所述之方法,其中該材料在該已處理部分上之該沉積速率快於在該溝槽之該未處理底部上之該第二沉積速率,以及其中將該材料沉積在該溝槽中之步驟包括在該溝槽之該底部處形成一空隙。
- 如請求項1所述之方法,該方法進一步包括以下步驟:將該半導體晶圓支撐在一平臺上;旋轉該平臺;以及利用與該溝槽之一第二側壁成該角度之該離子射束執行定向電漿處理以形成該第二側壁之一第二已處理部分。
- 如請求項1所述之方法,其中沉積該材料之步驟包括經由化學氣相沉積(CVD)、物理氣相沉積PVD)、電漿增強化學氣相沉積(PECVD)或原子層沉積(ALD)沉積一介電質或金屬。
- 一種用於填充一半導體晶圓中之一溝槽之系統,該系統包括:一電漿腔室,用以產生與該溝槽之一側壁成一角度之一離子射束以形成該側壁之一已處理部分及該溝槽之一未處理底部;以及一沉積腔室,用以將一材料沉積在該溝槽中,其中該材料在該側壁之該已處理部分上之一沉積速率不同於在該溝槽之該未處理底部上之一第二沉積速率。
- 如請求項11所述之系統,其中該電漿腔室用以產生與該側壁成在1至85度之一範圍中的角度之該離子射束。
- 如請求項11所述之系統,進一步包括:一平臺,用以在該電漿腔室中支撐該半導體晶圓,其中該平臺旋轉,從而將該溝槽之一第二側壁曝露於與該第二側壁成該角度之該離子射束。
- 如請求項11所述之系統,其中該沉積腔室包括一化學氣相沉積(CVD)腔室、一物理氣相沉積(PVD)腔室、一電漿增強 化學氣相沉積(PECVD)腔室或一原子層沉積(ALD)腔室以利用一介電質或金屬填充該溝槽。
- 一種用於填充一半導體晶圓中之一溝槽之方法,該方法包括以下步驟:將一材料沉積在該半導體晶圓上,填充該溝槽之一底部,及在該溝槽之一側壁上及該溝槽鄰近處之一頂表面上形成一層;以及利用與該側壁成一角度之一離子射束蝕刻該溝槽之該側壁上及該頂表面上之該層。
- 如請求項15所述之方法,該方法進一步包括以下操作的多次迭代:將該材料沉積在該半導體晶圓上,以及利用與該側壁成該角度之該離子射束蝕刻該溝槽之該側壁上及該頂表面上之該層。
- 如請求項15所述之方法,其中蝕刻該溝槽之該側壁上及該頂表面上之該層之步驟包括產生與該側壁成在1至85度之一範圍內的該角度之該離子射束。
- 如請求項15所述之方法,其中該溝槽具有大約5比1之一深寬比,以及其中蝕刻該溝槽之該側壁上及該頂表面上之該層之步驟包括產生與該側壁成在1至20度之一範圍內的該角度之該離子射束。
- 如請求項15所述之方法,其中該溝槽具有大約5比1之一深寬比,以及其中蝕刻該溝槽之該側壁上及該頂表面上之該層之步驟包括蝕刻該側壁之一頂部20%至30%上之該層。
- 如請求項15所述之方法,其中在該半導體晶圓上沉積該材料之步驟包括經由化學氣相沉積(CVD)、物理氣相沉積(PVD)、電漿增強化學氣相沉積(PECVD)或原子層沉積(ALD)利用一介電質或金屬填充該溝槽之一底部。
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2014
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2016
- 2016-11-18 US US15/356,475 patent/US10943779B2/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI750642B (zh) * | 2019-07-17 | 2021-12-21 | 日商柯尼卡美能達股份有限公司 | 微結構體之製造方法及微結構體之製造裝置 |
TWI789657B (zh) * | 2020-05-05 | 2023-01-11 | 台灣積體電路製造股份有限公司 | 半導體配置及製造方法 |
US11562923B2 (en) | 2020-05-05 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor arrangement including a first electrical insulator layer and a second electrical insulator layer and method of making |
Also Published As
Publication number | Publication date |
---|---|
US10943779B2 (en) | 2021-03-09 |
US20170069488A1 (en) | 2017-03-09 |
US20150093907A1 (en) | 2015-04-02 |
WO2015050707A1 (en) | 2015-04-09 |
US9530674B2 (en) | 2016-12-27 |
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