TW201519719A - Wiring board and method for manufacturing same - Google Patents

Wiring board and method for manufacturing same Download PDF

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Publication number
TW201519719A
TW201519719A TW103129456A TW103129456A TW201519719A TW 201519719 A TW201519719 A TW 201519719A TW 103129456 A TW103129456 A TW 103129456A TW 103129456 A TW103129456 A TW 103129456A TW 201519719 A TW201519719 A TW 201519719A
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Taiwan
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layer
wiring
resin insulating
insulating layer
wiring board
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TW103129456A
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Chinese (zh)
Inventor
Erina Miyamoto
Hironori Sato
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Ngk Spark Plug Co
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Publication of TW201519719A publication Critical patent/TW201519719A/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098Special shape of the cross-section of conductors, e.g. very thick plated conductors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

To provide a wiring board applicable to micro-miniaturization of wiring, and a method for manufacturing the wiring board. A wiring board (1) is configured by laminating a resin insulating layer (20) and a conductor layer (33). The conductor layer (33) includes wiring (36) having a width equal to or less than 5 [mu]m, and the wiring (36) is formed on a resin insulating layer (20) surface having a maximum height (Rz) of less than 1.0 [mu]m.

Description

配線基板及其製造方法 Wiring substrate and method of manufacturing same

本發明係關於積層有樹脂絕緣層與導體層而成之配線基板及其製造方法。 The present invention relates to a wiring board in which a resin insulating layer and a conductor layer are laminated, and a method of manufacturing the same.

近年來,伴隨著電氣機器等的小型化,搭載於此等機器的配線基板等亦被要求小型化、高密度化。作為此配線基板,以交互積層複數層樹脂絕緣層與複數層導體層的增建法所製造的配線基板被實用化。又,此種配線基板中,為了提升在樹脂絕緣層上以半加成法(Semi-additive Process)所形成的導體層與樹脂絕緣層的密接性,在表面已進行粗化的樹脂絕緣層上形成導體層者亦被實用化。(例如參照專利文獻1)。 In recent years, with the miniaturization of electrical equipment and the like, wiring boards and the like to be mounted on such devices have been required to be downsized and increased in density. As this wiring board, a wiring board manufactured by an extension method in which a plurality of layers of a resin insulating layer and a plurality of layer conductor layers are alternately laminated is put into practical use. Further, in such a wiring board, in order to improve the adhesion between the conductor layer formed by the semi-additive process and the resin insulating layer on the resin insulating layer, the surface of the resin insulating layer which has been roughened is used. The conductor layer is also put into practical use. (For example, refer to Patent Document 1).

在一般的半加成法中,係藉由依序實施以下的步驟而形成由無電解鍍銅層與電解鍍銅層所構成的導體層,即依序實施:將樹脂絕緣層的表面粗化的步驟、在已粗化的樹脂絕緣層的表面整體形成無電解鍍銅層之步驟、在無電解鍍銅層上形成感光性的乾膜阻劑之步驟、藉由實施曝光顯影而於乾膜阻劑形成既定圖案之開口的步驟、在乾膜阻劑的開口內形成電解鍍銅層之步驟、去除乾膜阻劑之步驟、藉由蝕刻去除因去除乾膜阻劑而露出之無電解鍍銅層之步驟。 In the general semi-additive method, a conductor layer composed of an electroless copper plating layer and an electrolytic copper plating layer is formed by sequentially performing the following steps, that is, sequentially: roughening the surface of the resin insulating layer a step of forming an electroless copper plating layer on the entire surface of the roughened resin insulating layer, a step of forming a photosensitive dry film resist on the electroless copper plating layer, and a dry film resistance by performing exposure development The step of forming an opening of a predetermined pattern, the step of forming an electrolytic copper plating layer in the opening of the dry film resist, the step of removing the dry film resist, and removing the electroless copper plating exposed by removing the dry film resist by etching The steps of the layer.

先前技術文獻 Prior technical literature 專利文獻 Patent literature

專利文獻1 日本特開2005-150553號公報 Patent Document 1 Japanese Patent Laid-Open Publication No. 2005-150553

然而,若因應配線基板的小型化、高密度化之要求而將構成導體層的配線愈趨細微化,則會有無法充分確保表面已粗化的樹脂絕緣層與細微的配線的密接強度的問題。具體而言,如圖9所示,在表面已粗化的樹脂絕緣層60上形成有無電鍍解銅層61及電解鍍銅層62之製造中途的配線基板中,在藉由蝕刻去除不要的無電解鍍銅層61時,電解鍍銅層62正下方的無電解鍍銅層61會被局部性地蝕刻,即,會形成底切(undercut)。結果,如圖10所示之配線基板10所示,會有因無法充分確保由無電解鍍銅層61及電解鍍銅層62所構成之配線66與樹脂絕緣層60的接觸面積,而造成配線66從樹脂絕緣層60剝離的問題。 However, in order to miniaturize the wiring constituting the conductor layer in response to the demand for miniaturization and high density of the wiring board, there is a problem that the adhesion strength between the resin insulating layer and the fine wiring in which the surface is roughened cannot be sufficiently ensured. . Specifically, as shown in FIG. 9, in the wiring substrate in which the electroless copper-plated layer 61 and the electrolytic copper-plated layer 62 are formed on the resin insulating layer 60 whose surface has been roughened, unnecessary etching is removed by etching. When the copper plating layer 61 is electrolytically plated, the electroless copper plating layer 61 directly under the electrolytic copper plating layer 62 is partially etched, that is, an undercut is formed. As a result, as shown in the wiring board 10 shown in FIG. 10, the contact area between the wiring 66 composed of the electroless copper plating layer 61 and the electrolytic copper plating layer 62 and the resin insulating layer 60 cannot be sufficiently ensured, resulting in wiring. The problem of peeling off from the resin insulating layer 60 is 66.

就抑制在配線形成底切的方法而言,亦有縮短無電解鍍敷層的蝕刻處理時間等之對策。然而,在已粗化之樹脂絕緣層表面的凹陷深度較大的情形下,若蝕刻處理的時間太短則如圖11所示,會有在已粗化之樹脂絕緣層60表面之凹陷殘留有應去除的無電解鍍銅層61,而相鄰配置的複數條配線66會藉由殘留於樹脂絕緣層60之表面的無電解鍍銅層61而產生短路的問題。 In order to suppress the undercut of the wiring, there is also a countermeasure for shortening the etching treatment time of the electroless plating layer. However, in the case where the depth of the surface of the roughened resin insulating layer is large, if the etching treatment time is too short, as shown in FIG. 11, there is a recess in the surface of the roughened resin insulating layer 60. The electroless copper plating layer 61 to be removed, and the plurality of adjacent wirings 66 are caused to be short-circuited by the electroless copper plating layer 61 remaining on the surface of the resin insulating layer 60.

本發明係為解決上述問題而完成者,其目的在提供可因應構成導體層的配線細微化之配線基板及其製造方法。 The present invention has been made to solve the above problems, and an object thereof is to provide a wiring board which can be made fine in accordance with wiring constituting a conductor layer, and a method of manufacturing the same.

就解決上述課題之手段(手段1)而言,係一種積層有樹脂絕緣層與導體層而成之配線基板,其特徵為:前述導體層包含寬度為5μm以下之配線,在最大高度Rz小於1.0μm的前述樹脂絕緣層表面形成有配線。 A means for solving the above-mentioned problems (method 1) is a wiring board in which a resin insulating layer and a conductor layer are laminated, wherein the conductor layer includes a wiring having a width of 5 μm or less, and the maximum height Rz is less than 1.0. Wiring is formed on the surface of the aforementioned resin insulating layer of μm.

根據手段1所記載之發明,因為樹脂絕緣層表面的最大高度Rz小於1.0μm,故可形成能抑制底切形成之配線,因而可確保樹脂絕緣層與配線的接觸面積足夠。因此,在形成具有5μm以下之寬度的細微配線的情況下,可防止配線剝離。 According to the invention of the first aspect, since the maximum height Rz of the surface of the resin insulating layer is less than 1.0 μm, wiring capable of suppressing undercut formation can be formed, and thus the contact area between the resin insulating layer and the wiring can be ensured. Therefore, in the case of forming fine wiring having a width of 5 μm or less, peeling of the wiring can be prevented.

又,就解決上述課題之手段(手段2)而言,係一種積層有樹脂絕緣層與導體層而成之配線基板的製造方法,其特徵為依序具有:第1金屬層形成步驟,在前述樹脂絕緣層的表面形成第1金屬層;樹脂薄膜配置步驟,在前述第1金屬層上配置樹脂薄膜;開口形成步驟,在前述樹脂薄膜形成開口;第2金屬層形成步驟,在從前述樹脂薄膜的開口露出之前述第1金屬層上藉由電解鍍敷形成第2金屬層;樹脂薄膜去除步驟,去除前述樹脂薄膜;及導體層形成步驟,將因前述樹脂薄膜的去除而露出之前述第1金屬層藉由蝕刻加以去除,形成由前述第1金屬層及前述第2金屬層所構成之前述導體層; 在前述第1金屬層形成步驟中,於最大高度Rz小於1.0μm的前述樹脂絕緣層表面形成前述第1金屬層,且在前述導體層形成步驟中,形成含有寬度為5μm以下的配線之前述導體層。 In addition, a means for producing a wiring board in which a resin insulating layer and a conductor layer are laminated is provided, and the first metal layer forming step is performed in the order described above. a first metal layer is formed on the surface of the resin insulating layer; a resin film is disposed on the first metal layer; an opening forming step forms an opening in the resin film; and a second metal layer forming step is performed on the resin film The second metal layer is formed by electrolytic plating on the first metal layer exposed; the resin film removing step removes the resin film; and the conductor layer forming step is performed by exposing the resin film The metal layer is removed by etching to form the conductor layer composed of the first metal layer and the second metal layer; In the first metal layer forming step, the first metal layer is formed on the surface of the resin insulating layer having a maximum height Rz of less than 1.0 μm, and the conductor including the wiring having a width of 5 μm or less is formed in the conductor layer forming step. Floor.

根據手段2所記載的發明,因為是在最大高度Rz小於1.0μm的樹脂絕緣層表面形成第1金屬層及第2金屬層,所以在導體層形成步驟中,可以抑制第1金屬層被過度蝕刻之底切的形成。因此,可確保樹脂絕緣層與配線有足夠的接觸面積,且在形成含有寬度5μm以下的細微配線的情況下亦可防止配線剝離。 According to the invention of the second aspect, since the first metal layer and the second metal layer are formed on the surface of the resin insulating layer having a maximum height Rz of less than 1.0 μm, the first metal layer can be prevented from being excessively etched in the conductor layer forming step. The formation of the undercut. Therefore, it is possible to ensure a sufficient contact area between the resin insulating layer and the wiring, and to prevent peeling of the wiring when forming a fine wiring having a width of 5 μm or less.

1、10‧‧‧配線基板 1, 10‧‧‧ wiring substrate

20、40、60‧‧‧樹脂絕緣層 20, 40, 60‧‧‧ resin insulation

31、61‧‧‧無電解鍍銅層 31, 61‧‧‧ Electroless copper plating

32、62‧‧‧電解鍍銅層 32, 62‧‧‧ electrolytic copper plating

33‧‧‧導體層 33‧‧‧Conductor layer

34‧‧‧貫通孔 34‧‧‧through holes

35‧‧‧通路導體 35‧‧‧ Path conductor

36、46、66‧‧‧配線 36, 46, 66‧‧‧ wiring

DF‧‧‧樹脂薄膜(乾膜阻劑) DF‧‧ resin film (dry film resist)

41‧‧‧金屬箔 41‧‧‧metal foil

50‧‧‧開口 50‧‧‧ openings

W1‧‧‧寬度 W1‧‧‧Width

H1、H2‧‧‧高度 H1, H2‧‧‧ height

圖1顯示本實施型態之配線基板的概略構成的剖面圖。 Fig. 1 is a cross-sectional view showing a schematic configuration of a wiring board of the present embodiment.

圖2顯示本實施型態之配線基板的製造方法的說明圖。 Fig. 2 is an explanatory view showing a method of manufacturing the wiring board of the embodiment.

圖3顯示本實施型態之配線基板的製造方法的說明圖。 Fig. 3 is an explanatory view showing a method of manufacturing the wiring board of the embodiment.

圖4顯示本實施型態之配線基板的製造方法的說明圖。 Fig. 4 is an explanatory view showing a method of manufacturing the wiring board of the embodiment.

圖5顯示本實施型態之配線基板的製造方法的說明圖。 Fig. 5 is an explanatory view showing a method of manufacturing the wiring board of the present embodiment.

圖6顯示本實施型態之配線基板的製造方法的說明圖。 Fig. 6 is an explanatory view showing a method of manufacturing the wiring board of the embodiment.

圖7顯示其他實施型態之配線基板的製造方法的說明圖。 Fig. 7 is an explanatory view showing a method of manufacturing a wiring board of another embodiment.

圖8顯示其他實施型態之配線基板的製造方法的說明圖。 Fig. 8 is an explanatory view showing a method of manufacturing a wiring board of another embodiment.

圖9顯示以往的配線基板的製造方法的說明圖。 FIG. 9 is an explanatory view showing a method of manufacturing a conventional wiring board.

圖10顯示以往的配線基板的製造方法的說明圖。 FIG. 10 is an explanatory view showing a method of manufacturing a conventional wiring board.

圖11顯示以往的配線基板的製造方法的說明圖。 FIG. 11 is an explanatory view showing a method of manufacturing a conventional wiring board.

以下,依據圖1~圖6詳細說明將本發明作為配線基板而具體化的一實施型態。圖1係顯示本實施型態之配線基板1的概略構成的剖面圖。 Hereinafter, an embodiment in which the present invention is embodied as a wiring board will be described in detail with reference to FIGS. 1 to 6. Fig. 1 is a cross-sectional view showing a schematic configuration of a wiring board 1 of the present embodiment.

如圖1所示,本實施型態之配線基板1具有樹脂絕緣層20與積層於樹脂絕緣層20上的導體層33。樹脂絕緣層20係由環氧樹脂等之熱硬化性樹脂所構成,樹脂絕緣層20的表面之最大高度Rz小於1.0μm。又,本說明書中所謂最大高度Rz係依據JISB0601(2001)之規格所定義。 As shown in FIG. 1, the wiring board 1 of this embodiment has a resin insulating layer 20 and a conductor layer 33 laminated on the resin insulating layer 20. The resin insulating layer 20 is made of a thermosetting resin such as an epoxy resin, and the maximum height Rz of the surface of the resin insulating layer 20 is less than 1.0 μm. In addition, the maximum height Rz in this specification is defined by the specification of JIS B0601 (2001).

導體層33係以銅為主體而構成,且係由形成於樹脂絕緣層20之表面的無電解鍍銅層31(第1金屬層)及形成於無電解鍍銅層31上的電解鍍銅層32(第2金屬層)所構成。又,導體層33具有相互電性獨立之複數條配線36,配線36具有5μm以下的寬度。 The conductor layer 33 is mainly composed of copper, and is composed of an electroless copper plating layer 31 (first metal layer) formed on the surface of the resin insulating layer 20 and an electrolytic copper plating layer formed on the electroless copper plating layer 31. 32 (second metal layer). Further, the conductor layer 33 has a plurality of wires 36 electrically independent of each other, and the wiring 36 has a width of 5 μm or less.

本說明書中所謂配線36的寬度係指以與樹脂絕緣層20相接之配線36的下端為基準時的上端之高度H1的一半高度H2的位置之寬度W1。 The width of the wiring 36 in the present specification means the width W1 of the position at the half height H2 of the height H1 of the upper end when the lower end of the wiring 36 that is in contact with the resin insulating layer 20 is used as a reference.

其次,依據圖2~圖6說明本實施型態之配線基板1的製造方法 Next, a method of manufacturing the wiring board 1 of the present embodiment will be described with reference to FIGS. 2 to 6 .

首先,準備由環氧樹脂等之熱硬化性樹脂所構成之厚度約30μm的樹脂絕緣層20。然後,以表面之最大高度Rz小於1.0μm的方式,因應需求使用過錳酸鉀等之蝕刻液對樹脂絕緣層20的表面實施粗化處理。 First, a resin insulating layer 20 having a thickness of about 30 μm made of a thermosetting resin such as an epoxy resin is prepared. Then, the surface of the resin insulating layer 20 is roughened by an etching liquid such as potassium permanganate so as to have a maximum height Rz of the surface of less than 1.0 μm.

之後,對樹脂絕緣層20的整個表面實施無電解鍍銅處理,在樹脂絕緣層20上形成無電解鍍銅層31(第1金屬層)。(參照圖2) Thereafter, an electroless copper plating treatment is performed on the entire surface of the resin insulating layer 20, and an electroless copper plating layer 31 (first metal layer) is formed on the resin insulating layer 20. (Refer to Figure 2)

然後,如圖3所示,在無電解鍍銅層31上貼附感光性的乾膜阻劑DF(樹脂薄膜),進行乾膜阻劑DF的曝光顯影。藉由此曝光顯影,在乾膜阻劑DF形成對應於應形成之配線36的形狀之開口50。(參照圖4) Then, as shown in FIG. 3, a photosensitive dry film resist DF (resin film) is attached to the electroless copper plating layer 31, and exposure and development of the dry film resist DF are performed. By this exposure development, an opening 50 corresponding to the shape of the wiring 36 to be formed is formed in the dry film resist DF. (Refer to Figure 4)

又,開口50亦可藉由乾膜阻劑DF(樹脂薄膜)的雷射加工而形成。 Further, the opening 50 can also be formed by laser processing of a dry film resist DF (resin film).

在乾膜阻劑DF曝光顯影後,實施電解鍍銅處理,在從開口50露出之無電解鍍銅層31上形成電解鍍銅層32(第2金屬層)。(參照圖5) After the dry film resist DF is exposed and developed, electrolytic copper plating is performed to form an electrolytic copper plating layer 32 (second metal layer) on the electroless copper plating layer 31 exposed from the opening 50. (Refer to Figure 5)

形成電解鍍銅層32後,如圖6所示將乾膜阻劑DF去除。然後,藉由去除乾膜阻劑DF,利用使用周知之蝕刻液的蝕刻將露出於表面的無電解鍍銅層31去除至樹脂絕緣層20的表面露出為止。經由以上之步驟製造如圖1所示之配線基板1。 After the electrolytic copper plating layer 32 is formed, the dry film resist DF is removed as shown in FIG. Then, by removing the dry film resist DF, the electroless copper plating layer 31 exposed on the surface is removed by etching using a well-known etching liquid until the surface of the resin insulating layer 20 is exposed. The wiring substrate 1 shown in FIG. 1 is manufactured through the above steps.

因此,根據本實施型態可得到以下效果。 Therefore, according to this embodiment, the following effects can be obtained.

在本實施型態的配線基板1中,因為係在最 大高度Rz未滿1.0μm的樹脂絕緣層20的表面形成由無電解鍍銅層31及電解鍍銅層32所構成之導體層33,所以即使是形成具有5μm以下之寬度的配線36也不易在配線36形成底切,而能確保樹脂絕緣層20與配線36的密接面積足夠。因此,可防止配線36從樹脂絕緣層20剝離。 In the wiring substrate 1 of the present embodiment, since it is the most Since the conductor layer 33 composed of the electroless copper plating layer 31 and the electrolytic copper plating layer 32 is formed on the surface of the resin insulating layer 20 having a large height Rz of less than 1.0 μm, it is difficult to form the wiring 36 having a width of 5 μm or less. The wiring 36 is formed as an undercut, and it is ensured that the adhesion area of the resin insulating layer 20 and the wiring 36 is sufficient. Therefore, the wiring 36 can be prevented from being peeled off from the resin insulating layer 20.

在本實施型態中,因為係在最大高度Rz未滿 1.0μm的樹脂絕緣層20的表面形成有無電解鍍銅層31,所以即使在導體層形成步驟中藉由蝕刻將不要的無電解鍍銅層31全部去除也不易在配線36形成底切,而能防止配線36從樹脂絕緣層20剝離。 In this embodiment, because the system is not full at the maximum height Rz The surface of the resin insulating layer 20 of 1.0 μm is formed with the electroless copper plating layer 31. Therefore, even if the unnecessary electroless copper plating layer 31 is completely removed by etching in the conductor layer forming step, it is difficult to form an undercut in the wiring 36, and The wiring 36 is prevented from being peeled off from the resin insulating layer 20.

<實施例> <Example>

接著,說明為確認本實施型態之效果而進行的實施例。 Next, an embodiment performed to confirm the effect of the present embodiment will be described.

在本實施例中,製作根據圖1~圖6而說明的 配線基板1中之樹脂絕緣層20的表面粗度(算術平均粗度Ra及最大高度Rz)相異之A~F樣品,針對各樣品形成寬度相異之複數種配線36,確認配線36有無剝離,將確認結果顯示於表1。 In the present embodiment, the description is made according to FIGS. 1 to 6 In the A to F samples in which the surface roughness (arithmetic mean roughness Ra and maximum height Rz) of the resin insulating layer 20 in the wiring board 1 are different, a plurality of types of wirings 36 having different widths are formed for each sample, and it is confirmed whether or not the wiring 36 is peeled off. , the confirmation results are shown in Table 1.

又,樹脂絕緣層20的表面粗度係藉由變更使用蝕刻液進行粗化處理的時間來控制。 Moreover, the surface roughness of the resin insulating layer 20 is controlled by changing the time of roughening treatment using an etching liquid.

如表1所示,可確認使用本發明之範圍內的 樹脂絕緣層的樣品D,E,在形成具有寬度5μm的配線後亦可與樹脂絕緣層密接。而另一方面,可確認本發明之範圍外的樣品A,B,C在形成具有5μm寬度的配線後,配線會從樹脂絕緣層剝離。 As shown in Table 1, it can be confirmed that the use within the scope of the present invention The samples D and E of the resin insulating layer may be in close contact with the resin insulating layer after forming wiring having a width of 5 μm. On the other hand, it was confirmed that the samples A, B, and C outside the range of the present invention were peeled off from the resin insulating layer after the wiring having a width of 5 μm was formed.

又,本發明之實施型態可如下進行變更。 Further, the embodiment of the present invention can be modified as follows.

在上述實施型態中,雖是由樹脂絕緣層20與導體層33分別一層一層地積層而成之配線基板1,但亦可是複數層樹脂絕緣層與複數層導體層相互積層之配線基板。 In the above-described embodiment, the wiring board 1 is formed by laminating the resin insulating layer 20 and the conductor layer 33 one by one. However, a wiring board in which a plurality of resin insulating layers and a plurality of conductor layers are laminated to each other may be used.

例如,在製造樹脂絕緣層與導體層各自積層複數層而成之配線基板的情況下,如圖7所示,亦可將 表面預先形成有銅箔等金屬箔41的樹脂絕緣層40積層於已形成有導體層33的樹脂絕緣層20上。在此情況下,可在以下的步驟中於樹脂絕緣層40表面形成導體層。首先,在積層後之樹脂絕緣層40的表面有金屬箔41的狀態下進行雷射加工,藉此,形成貫通金屬箔41及樹脂絕緣層40且使導體層33露出的貫通孔34。其次,在樹脂絕緣層40的表面有金屬箔41的狀態下進行去除貫通孔34內的汙跡之去汙(desmear)處理後,藉由蝕刻去除金屬箔41。然後,在去除金屬箔41後,藉由施行與導體層33相同之無電解鍍銅及電解鍍銅處理,而如圖8所示,可製造形成有由填充貫通孔內而成之通路導體35、無電解鍍銅層37、電解鍍銅層38所構成之導體層39的配線基板1’。 For example, in the case of manufacturing a wiring board in which a plurality of layers of a resin insulating layer and a conductor layer are laminated, as shown in FIG. The resin insulating layer 40 on which the metal foil 41 such as copper foil is formed in advance is laminated on the resin insulating layer 20 on which the conductor layer 33 has been formed. In this case, the conductor layer can be formed on the surface of the resin insulating layer 40 in the following steps. First, laser processing is performed in a state where the surface of the resin insulating layer 40 after lamination is provided with the metal foil 41, whereby the through hole 34 penetrating the metal foil 41 and the resin insulating layer 40 and exposing the conductor layer 33 is formed. Next, after the metal foil 41 is provided on the surface of the resin insulating layer 40, the desmear process for removing the stain in the through hole 34 is performed, and then the metal foil 41 is removed by etching. Then, after removing the metal foil 41, by performing the same electroless copper plating and electrolytic copper plating as the conductor layer 33, as shown in FIG. 8, the via conductor 35 formed by filling the through hole can be manufactured. A wiring board 1' of the conductor layer 39 composed of the electroless copper plating layer 37 and the electrolytic copper plating layer 38.

又,在上述使用金屬箔41之配線基板的製造 方法中,藉由施行去汙處理將露出於表面的樹脂絕緣層40粗化。然而,因為在樹脂絕緣層40的表面中供形成配線46的區域是被金屬箔41所被覆,所以樹脂絕緣層40的表面不會被不必要地粗化。因此,如此製造的配線基板1’具有藉由去汙處理而粗化的樹脂絕緣層40之貫通孔34的壁面之最大高度Rz比樹脂絕緣層40表面的最大高度Rz還大的特徴。 Moreover, the manufacture of the wiring board using the metal foil 41 mentioned above In the method, the resin insulating layer 40 exposed on the surface is roughened by performing a desmutting treatment. However, since the region where the wiring 46 is formed in the surface of the resin insulating layer 40 is covered by the metal foil 41, the surface of the resin insulating layer 40 is not unnecessarily roughened. Therefore, the wiring board 1' thus manufactured has a feature that the maximum height Rz of the wall surface of the through hole 34 of the resin insulating layer 40 roughened by the desmear process is larger than the maximum height Rz of the surface of the resin insulating layer 40.

在上述實施型態中,雖藉由無電解鍍銅形成 無電解鍍銅層31(第1金屬層),但第1金屬層的形成方法並未限定,亦可由濺鍍法或CVD等方法形成。 In the above embodiment, although formed by electroless copper plating The electroless copper plating layer 31 (first metal layer) is not limited, and the method of forming the first metal layer may be formed by a sputtering method or a CVD method.

1‧‧‧配線基板 1‧‧‧Wiring substrate

20‧‧‧樹脂絕緣層 20‧‧‧Resin insulation

31‧‧‧第1金屬層 31‧‧‧1st metal layer

32‧‧‧第2金屬層 32‧‧‧2nd metal layer

33‧‧‧導體層 33‧‧‧Conductor layer

36‧‧‧配線 36‧‧‧Wiring

W1‧‧‧寬度 W1‧‧‧Width

H1、H2‧‧‧高度 H1, H2‧‧‧ height

Claims (2)

一種配線基板,其係積層樹脂絕緣層與導體層而成之配線基板,其特徵為:前述導體層包含寬度為5μm以下之配線,在最大高度Rz小於1.0μm的前述樹脂絕緣層表面形成有前述配線。 A wiring board in which a wiring resin layer and a conductor layer are laminated, wherein the conductor layer includes a wiring having a width of 5 μm or less, and the surface of the resin insulating layer having a maximum height Rz of less than 1.0 μm is formed. Wiring. 一種配線基板之製造方法,其係積層樹脂絕緣層與導體層而成之配線基板之製造方法,其特徵為依序具有:第1金屬層形成步驟,在前述樹脂絕緣層的表面形成第1金屬層;樹脂薄膜配置步驟,在前述第1金屬層上配置樹脂薄膜;開口形成步驟,在前述樹脂薄膜形成開口;第2金屬層形成步驟,在從前述樹脂薄膜的開口露出之前述第1金屬層上藉由電解鍍敷形成第2金屬層;樹脂薄膜去除步驟,去除前述樹脂薄膜;及導體層形成步驟,將因前述樹脂薄膜的去除而露出之前述第1金屬層藉由蝕刻加以去除,而形成由前述第1金屬層及前述第2金屬層所構成之前述導體層;在前述第1金屬層形成步驟中,於最大高度Rz小於1.0μm的樹脂絕緣層表面形成前述第1金屬層,在前述導體層形成步驟中,形成含有寬度為5μm以下的配線之前述導體層。 A method for producing a wiring board, comprising: a method of manufacturing a wiring board formed by laminating a resin insulating layer and a conductor layer, wherein the first metal layer forming step sequentially forms a first metal on a surface of the resin insulating layer a resin film arranging step of disposing a resin film on the first metal layer; an opening forming step of forming an opening in the resin film; and a second metal layer forming step of exposing the first metal layer from an opening of the resin film Forming a second metal layer by electrolytic plating; removing the resin film by a resin film removing step; and forming a conductor layer, and removing the first metal layer exposed by the removal of the resin film by etching Forming the conductor layer composed of the first metal layer and the second metal layer; and forming the first metal layer on the surface of the resin insulating layer having a maximum height Rz of less than 1.0 μm in the first metal layer forming step; In the conductor layer forming step, the conductor layer including a wiring having a width of 5 μm or less is formed.
TW103129456A 2013-08-29 2014-08-27 Wiring board and method for manufacturing same TW201519719A (en)

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