TW201436206A - Embedded resistor - Google Patents

Abstract

An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer. Or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

Description

Buried resistor

This invention relates to a resistor, and in particular to a buried resistor.

In the semiconductor wafer process, a polysilicon material is often used to form a high-impedance resistor, which can replace a transistor as a load. For example, a transistor in a static random access memory (SRAM) can be replaced by a load resistor formed by polysilicon, so that the number of transistors in the SRAM is reduced, thereby achieving cost saving and integration. purpose.

Common load resistors can be broadly classified into polysilicon resistors and diffusion resistors. The polysilicon resistor includes a doped polysilicon layer, and its impedance can be adjusted and controlled by the dopant concentration in the polysilicon layer. As for the diffusion resistance, ions are implanted in a semiconductor substrate to form a doped layer, and then the ions in the doped layer are activated by thermal diffusion to adjust the impedance. In general, most of the polysilicon resistors or diffusion resistors have a sandwich-like structure, and the two sides of the structure are defined as a low-impedance region, which is used to make the contact plug of the interconnect to make the electrical connection with other wires. As for the high-impedance region sandwiched between the low-impedance regions on both sides, it is the main structure of the resistor, which is used to provide high impedance required in electronic components or circuit design. With electronics With the diversification and miniaturization of products, the circuit design using load resistors is becoming more and more complicated, and the conditions such as the volume occupied by the load resistor, the position formed, and the high impedance that can be provided are becoming more and more severe.

The present invention provides a buried resistor which first forms a trench in a material layer and then fills a resistive material therein to form a buried resistor having a U-shaped cross-sectional structure or a block shape.

The invention provides a buried resistor comprising a first interlayer dielectric layer, a cap layer, a resistive layer and a cover film. The first interlayer dielectric layer is on a substrate. The cap layer is on the first interlayer dielectric layer, wherein the cap layer has a trench. The resistive layer conforms to the trench and thus has a U-shaped cross-sectional structure. The cover film is located in the trench and on the resistive layer.

The invention provides a buried resistor comprising a first interlayer dielectric layer, a cap layer and a block-shaped resistor layer. The first interlayer dielectric layer is on a substrate. The cap layer is on the first interlayer dielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

Based on the above, the present invention provides a buried resistor which first forms a trench in a material layer such as a cap layer, and then forms a resistive layer or a bulk resistive layer having a U-shaped cross-sectional structure in the trench to form a buried type. resistance. In this way, the present invention can solve the problem of insufficient etching or over-etching due to excessive difference in depth of the trenches formed to form the contact plugs formed in different regions (for example, the transistor region and the resistive region); or, forming the trenches The contact plug has a problem of insufficient filling or overfilling due to the difference in length and length; even the interlayer dielectric layer is polished after the contact plug is formed. The shorter contact plugs are completely removed by the grinding of the interlayer dielectric layer. Furthermore, since the present invention is a buried resistor, it is possible to avoid the problem of undercut of the underlayer of the resistive layer when the resistive layer is etched to pattern it.

10‧‧‧Insulation structure

20, 20a‧‧‧ buffer layer

110, 110a‧‧‧ base

120‧‧‧First interlayer dielectric layer

130‧‧‧ cover

140, 140a‧‧‧resistive layer

140’, 140a’‧‧‧ block resistance layer

142, 142a‧‧‧ vertical

150, 150a‧‧ ‧ cover film

160‧‧‧Second interlayer dielectric layer

A‧‧‧First District

B‧‧‧Second District

C1‧‧‧Slot contact plug

C2‧‧‧Contact plug

D‧‧‧ source/bungee area

DG‧‧‧sacrificial gate

E1, E2‧‧‧ etching process

G‧‧‧ gate

K‧‧‧ epitaxial structure

M‧‧‧MOS transistor

P1, P2‧‧‧ patterned photoresist

R1, R2, R3‧‧‧ Ditch

T1, T2, T4, T5, T7‧‧‧ top surface

T3, T6‧‧‧ top

1 to 4 are schematic cross-sectional views showing a buried resistor process according to a first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a buried resistor process according to another embodiment of the present invention.

6-9 are schematic cross-sectional views showing a buried resistor process according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a buried resistor process according to another embodiment of the present invention.

Figure 11 is a cross-sectional view showing a buried resistor having a sacrificial gate according to a first embodiment of the present invention.

Figure 12 is a cross-sectional view showing a buried resistor having a sacrificial gate according to a second embodiment of the present invention.

1 to 4 are schematic cross-sectional views showing a buried resistor process according to a first embodiment of the present invention. As shown in FIG. 1, a substrate 110 includes a first region A and a second region B, wherein in the embodiment, the first region A is a transistor region, and the second region B is a resistance region. A first interlayer dielectric layer 120 is formed on the substrate 110 of the first region A and the second region B. The first interlayer dielectric layer 120 can be, for example, an oxide layer, but the invention is not limited thereto. A MOS transistor M is disposed in the first interlayer dielectric layer 120 of the first region A. A plurality of insulating structures 10 are respectively located in the second region B and the first region A beside the MOS transistor M. In this embodiment, The second region B is formed to form a resistor over the first interlayer dielectric layer 120. Therefore, the insulating structure 10 is particularly provided with a bulk insulating structure in the substrate 10 of the majority of the second region B to prevent subsequent formation of the resistor. The contact plug or the like connecting the resistors leaks through the first interlayer dielectric layer 120 to the substrate 110, but the invention is not limited thereto. In other embodiments, the insulating structure 10 in the substrate 110 of the second region B may also be composed of a plurality of insulating structures, or the substrate 110 of the second region B may have no insulating structure therein. In addition, the insulating structure 10 disposed in the substrate 110 of the first region A is used to electrically insulate the MOS transistor M from other semiconductor elements such as transistors not shown.

Next, a cap layer 130 is formed on the first interlayer dielectric layer 120. The cap layer 130 is, for example, a tantalum nitride layer, or a carbonized tantalum nitride layer or the like, but the invention is not limited thereto. The cap layer 130 can isolate one of the gates G of the MOS transistor M (in particular, when the gate G is a metal gate) to prevent damage in subsequent processes, or to be electrically connected to the metal wires formed subsequently. Connected and leaked or shorted. Then, for example, a lithography and etching process is performed, and the cap layer 130 and the first interlayer dielectric layer 120 are patterned to form a plurality of trenches (not shown) to expose a source/drain region D of the MOS transistor M. Then, a metal (not shown) is filled in and planarized to form a plurality of slot contact plugs C1 (Slot Contacts) or a plurality of columnar contact plugs (not shown) in the first interlayer dielectric layer 120. And in the cap layer 130, and electrically connected to the MOS transistor M. The MOS transistor M may further comprise an epitaxial structure K in the substrate 110 on the side of the gate G and may partially overlap the source/drain region D; and a metal telluride (not shown) in the source/drain region D is in contact with the socket contact plug C1, and the metal halide can be formed before or after the formation of the trench in which the slot contact plug C1 is to be formed. The slot contact plug C1 may be composed of, for example, a metal such as tungsten or copper, but the invention is not limited thereto. Thereafter, a patterned photoresist P1 is formed to cover the first region. A, but exposes the area of the second zone B where resistance is to be formed. The method of forming the patterned photoresist P1 may, for example, firstly cover a photoresist (not shown) and then pattern it.

Then, an etching process E1 is performed, and the exposed cap layer 130 is etched in conjunction with the patterned photoresist P1 to form a trench R1 in the cap layer 130. In this embodiment, the cap layer 130 and the first interlayer dielectric layer 120 are made of different materials. Therefore, when the etching process E1 is performed, the first interlayer dielectric layer 120 can be used as an etch stop layer to stop the etching. On the interlayer dielectric layer 120; however, in other embodiments, the etching process E1 may also etch a portion of the first interlayer dielectric layer 120, thereby placing the trench R1 in the cap layer 130 and a portion of the first interlayer dielectric layer. 120. As shown in FIG. 2, after the etching process E1 is completed, the patterned photoresist P1 is removed and the residue after etching is removed.

As shown in FIG. 3, a buffer layer 20 is selectively formed to conformably cover the cap layer 130 and the trench R1. The buffer layer 20 can be, for example, an oxide layer, but the invention is not limited thereto. The buffer layer 20 can further isolate the socket contact plug C1 from the metal layer such as a resistor formed thereon, and damage the socket contact plug C1. Then, a resistive layer (not shown) and a cover film (not shown) are sequentially formed to completely cover the cap layer 130 (or the buffer layer 20), and the buffer layer 20 (or the cap layer 130) is used as a stop layer. A planarization process such as chemical mechanical polishing is performed to remove a resistive layer (not shown) directly above the cap layer 130, and a cap film (not shown) to form a resistive layer 140 conforming to the trench R1. And a cover film 150 is located on the resistive layer 140 in the trench R1 and fills the trench R1, such that the resistive layer 140 has a U-shaped cross-sectional structure. The resistive layer 140 is, for example, a titanium nitride layer or a tantalum nitride layer, but the invention is not limited thereto. The cover film 150 may be, for example, a dielectric material such as a tantalum nitride layer.

As a result, the buffer layer 20 is disposed on the cap layer 130, but the resistive layer 140 and the cap film 150 are exposed. In the present embodiment, the buffer layer 20 extends into the trench R1 and covers the trench R1 but is located below the resistive layer 140. Moreover, a top surface T1 of the buffer layer 20 on the cap layer 130 is flush with a top surface T2 of the cover film 150; the U-shaped resistive layer 140 has at least one vertical portion 142 parallel to the side of the trench R1, and the cover The top surface T2 of the film 150 is flush with the top end T3 of the vertical portion 142.

In another embodiment, as shown in Fig. 5, the resistive layer 140 and the cover film 150 of the first embodiment described above are replaced by a one-piece resistive layer 140'. In other words, after the buffer layer 20 is formed, a resistive layer (not shown) is formed to completely cover the cap layer 130 (or the buffer layer 20), and the trench R1 is filled, and then the buffer layer 20 (or the cap layer 130) is used. A planarization process such as chemical mechanical polishing is performed as a stop layer to remove the resistance layer other than the trench R1, so that the bulk resistance layer 140' can be formed. In this embodiment, the cover film 150 is no longer formed, and a top surface T7 of the bulk resistive layer 140' is flush with the top surface T1 of the buffer layer 20.

The steps of Figure 3 of the first embodiment are continued below, however the following process steps are also applicable to the embodiment of Figure 5 above.

As shown in FIG. 4, a second interlayer dielectric layer 160 is formed on the cap layer 130 (or the buffer layer 20), the resistive layer 140, and the cap film 150, and a plurality of contact plugs C2 (Contact Plugs) are formed. At least two contact plugs are located in the second interlayer dielectric layer 160 and electrically connected to the two ends of the resistance layer 140, respectively, and the remaining contact plugs are located in the second interlayer dielectric layer 160, the cap layer 130 and the buffer layer 20 The gate G of the MOS transistor M and the corresponding slot contact plug C1 are electrically connected to each other. The second interlayer dielectric layer 160 can be, for example, an oxide layer, and can be covered, for example, by multiple process stacks; the contact plug C2 can be composed of a metal such as tungsten or copper, but the invention is not limited thereto. .

In detail, a second interlayer dielectric layer (not shown) may be completely covered on the flat cap layer 130 (or the buffer layer 20), the resistive layer 140, and the cap film 150; then the second interlayer dielectric layer is patterned. 160, the buffer layer 20 and the cap layer 130, to form a plurality of trenches R2 in the second interlayer dielectric layer 160, the buffer layer 20 and the cap layer 130; and subsequently, filled with metal (not shown) in each trench R2 And planarizing it to form each contact plug C2. At this time, the contact plug C2 located in the second region B is electrically connected to the resistance layer 140, and the contact plug C2 located in the first region A is electrically connected to the slot contact plug C1 and the MOS transistor M.

In general, the MOS transistor M is located in the first interlayer dielectric layer 120, and the resistive layer 140 is in a material layer above the cap layer 130, and has a protruding stepped cross-sectional structure. The difference in the depth of the trench R2 formed by the same process in the first region A and the second region B is too large to easily cause the etching of the first region A or the over etching of the second region B; or, by the same The process is filled with metal and electrically connected to the contact plug C2 of the MOS transistor M and the resistance layer 140 respectively, and the trench R2 in the first region A is insufficiently filled or the second region B is caused by the difference in the depth of the trench R2. The R2 metal overfill problem of the middle trench; even when the second interlayer dielectric layer 160 is polished after the contact plug C2 is formed, the shorter contact plug may even be completely polished by the second interlayer dielectric layer 160 Remove. In this embodiment, the resistive layer 140 is placed in the cap layer 130 in a buried manner, and the contact plug C2 located in the first region A and the second region B can be shortened. The height difference of the contact plug C2 is not caused by the aforementioned problems.

Furthermore, in the method of embedding the resistor, the trench R1 is formed in the cap layer 130, and the resistive layer 140 is filled in the cap layer 130, and the resistor layer can be directly formed in the process. On the material layer, a pattern is formed by etching to form a resistor. In this way, the problem of over-etching the underlayer of the resistive layer caused by etching the resistive layer to pattern it can be avoided.

A second embodiment will be further described below, and in addition to the advantages of the first embodiment, the problem of forming a photoresist of the first embodiment can be further improved. 6-9 are schematic cross-sectional views showing a buried resistor process according to a second embodiment of the present invention.

As shown in FIG. 6, a substrate 110 includes a first region A and a second region B. The second region B in the embodiment is a resistive region, and the first region A is a transistor region. A first interlayer dielectric layer 120 is formed on the substrate 110 of the first region A and the second region B. The first interlayer dielectric layer 120 can be, for example, an oxide layer, but the invention is not limited thereto. A MOS transistor M is disposed in the first interlayer dielectric layer 120 of the first region A. A plurality of insulating structures 10 are respectively located in the second region B and the first region A beside the MOS transistor. In this embodiment, the second region B is formed to form a resistor above the first interlayer dielectric layer 120, and thus is specifically provided with a bulk insulating structure 10 in the substrate 10 of the majority of the second region B to prevent subsequent The formed resistor or the contact plug or the like connecting the resistors leaks through the first interlayer dielectric layer 120 to the substrate 110, but the invention is not limited thereto. In other embodiments, the insulating structure 10 in the substrate 110 of the second region B may also be composed of a plurality of insulating structures, or the substrate 110 of the second region B may have no insulating structure therein. In addition, the insulating structure 10 disposed in the substrate 110 of the first region A is In order to electrically insulate the transistor M from other semiconductor elements such as transistors not shown.

Next, a cap layer 130 is formed on the first interlayer dielectric layer 120. The cap layer 130 is, for example, a tantalum nitride layer, or a carbonized tantalum nitride layer or the like, but the invention is not limited thereto. The cap layer 130 can isolate one of the gates G of the MOS transistor M (especially when the gate G is a metal gate) to prevent damage in subsequent processes, or to electrically leak with a metal formed subsequently. Or short circuit. Then, for example, a lithography and etching process is performed to pattern the cap layer 130 and the first interlayer dielectric layer 120 to form a trench (not shown) to expose a source/drain region D of the MOS transistor M, and then fill Inserting a metal (not shown) and planarizing it to form a plurality of slot contact plugs C1 (Slot Contacts) or a plurality of columnar contact plugs (not shown) in the first interlayer dielectric layer 120 and the cover In the layer 130, the MOS transistor M is electrically connected. The slot contact plug C1 may be made of, for example, a metal such as tungsten or copper, but the invention is not limited thereto. The MOS transistor M may further comprise an epitaxial structure K in the substrate 110 on the side of the gate G and may partially overlap the source/drain region D; and a metal telluride (not shown) in the source/drain region D is in contact with the socket contact plug C1, and the metal halide can be formed before or after the formation of the trench in which the slot contact plug C1 is to be formed.

Thereafter, a buffer layer 20a is formed on the flat cap layer 130. The buffer layer 20 can be, for example, an oxide layer, but the invention is not limited thereto. The buffer layer 20a can further isolate the socket contact plug C1 from the metal layer such as a resistor formed thereon, and damage the socket contact plug C1. Then, a patterned photoresist P2 is formed on the buffer layer 20a. In general, in this embodiment, the buffer layer 20a is completely formed and the patterned photoresist P2 is formed, so that the patterned photoresist P2 formed only on the buffer layer 20a can be more adhered. Furthermore, the material of the buffer layer 20a The material is generally an oxide layer, and the material of the cap layer 130 is generally a nitride layer, and the patterned photoresist P2 also reacts with the nitride layer to cause residue to be completely removed. Therefore, the patterned photoresist P2 is formed in this embodiment. This problem can be solved by the buffer layer 20a.

Then, an etching process E2 is performed to etch the exposed buffer layer 20a and a portion of the cap layer 130 to form a trench R3 in the buffer layer 20a and the cap layer 130, and then remove the patterned photoresist P2, as shown in FIG. Show. In other embodiments, the etching process E2 may also be etched to stop at the cap layer 130, and only the trench R3 is formed on the buffer layer 20a, and the invention is not limited thereto. Then, as shown in FIG. 8, a resistive layer (not shown) and a cover film (not shown) are sequentially formed to completely cover the buffer layer 20a and the cap layer 130 in the trench R3, and the buffer layer 20 is used again. As a stop layer, a planarization process such as chemical mechanical polishing is performed to remove a resistive layer (not shown) directly above the buffer layer 20a and a cap film (not shown) to form a resistive layer 140a to cover the substrate. The surface of the trench R3 and a cap film 150a are located in the trench R3 and the resistive layer 140a, such that the resistive layer 140a has a U-shaped cross-sectional structure. The resistive layer 140a is, for example, a titanium nitride layer or a tantalum nitride layer. The cover film 150a may be a dielectric material such as a tantalum nitride layer, but the invention is not limited thereto. As a result, the buffer layer 20a is disposed on the cap layer 130, but the resistive layer 140a and the cap film 150a are exposed. Moreover, a top surface T4 of the buffer layer 20a on the cap layer 130 is flush with a top surface T5 of the cover film 150a; the U-shaped resistive layer 140a has at least one vertical portion 142a parallel to the side of the trench R3, and the cover The top surface T5 of the film 150a is flush with the top end T6 of the vertical portion 142a.

In another embodiment, as shown in Fig. 10, the resistive layer 140a and the cover film 150a are replaced by a one-piece resistive layer 140a'. In other words, after the formation of the buffer layer 20a, when a resistive layer (not shown) is formed to completely cover the cap layer buffer layer 20a, That is, the trench R3 is filled, and then the resistive layer other than the trench R3 is removed by planarization, so that the bulk resistive layer 140a' can be formed. In this embodiment, the cover film 150a is no longer formed separately.

Please follow the steps of FIG. 8 (or FIG. 10). As shown in FIG. 9, a second interlayer dielectric layer 160 is formed on the buffer layer 20a, the resistive layer 140a, and the cap film 150a, and a plurality of contacts are formed. Plug C2 (Contact Plugs). At least two contact plugs are located in the second interlayer dielectric layer 160 and electrically connected to the two ends of the resistance layer 140a, respectively, and the remaining contact plugs are located in the second interlayer dielectric layer 160, the cap layer 130 and the buffer layer 20a. The gate G of the MOS transistor M and the corresponding slot contact plug C1 are electrically connected to each other. The second interlayer dielectric layer 160 may be, for example, an oxide layer, and may be covered by, for example, multiple process stacks; the contact plug C2 may be composed of a metal such as tungsten or copper, but the invention is not limited thereto. .

In detail, a second interlayer dielectric layer (not shown) may be completely covered on the flat buffer layer 20a, the resistance layer 140a, and the cover film 150a; then the second interlayer dielectric layer 160 is patterned to be second. A plurality of trenches R2 are formed in the interlayer dielectric layer 160. Thereafter, a metal (not shown) is filled in each of the trenches R2 and planarized to form a contact plug C2. At this time, the contact plug C2 located in the second region B is electrically connected to the resistance layer 140, and the contact plug C2 located in the first region A is electrically connected to the slot contact plug C1 and the MOS transistor M.

In this way, the embodiment can also have the advantages of the first embodiment, for example, the trenches R3 formed in the first region A and the second region B are caused by insufficient etching or overetching due to different depths; or Zone A and Zone 2 B The contact plug C2 has a problem of insufficient filling or overfilling due to a large difference in length; even when the second interlayer dielectric layer 160 is polished after forming the contact plug C2, the contact plug C2 having a shorter height is caused by The second interlayer dielectric layer 160 is completely removed by grinding. Moreover, since this embodiment is also a method of embedding the resistive layer, it is possible to avoid the problem of over-etching the underlayer of the resistive layer when etching the resistive layer to pattern it. Still further, this embodiment has the advantage of improving photoresist adhesion and removal.

Furthermore, the present invention may further selectively form at least one sacrificial gate in the first interlayer dielectric layer 120 under the resistive layer 140 or 140a; or replace the bulk of the second region B bulk insulating structure 10 with a plurality of A smaller insulating structure prevents the first interlayer dielectric layer 120 or the insulating structure 10 from being recessed.

FIG. 11 is a cross-sectional view showing a buried resistor having a sacrificial gate according to a first embodiment of the present invention, wherein the sacrificial gate DG in FIG. 11 is located in the first interlayer dielectric layer 120. The contact plug C2 of the middle and electrical connection resistance layer 140 is directly under, and the sacrificial gates DG are all a floating electrode. Furthermore, a plurality of smaller insulating structures replace the insulating structures 10 of the second region B bulk, and each of the smaller insulating structures corresponds to the position of each of the sacrificial gates DG or the contact plugs C2.

However, in still another embodiment, as shown in FIG. 12, a cross-sectional view of a buried resistor having a sacrificial gate according to a second embodiment of the present invention is shown in the first interlayer dielectric layer 120. The sacrificial gate DG is located directly below the resistive layer 140a, but is misaligned with each of the contact plugs C2. In this way, when the contact plug C2 is extended to the first interlayer dielectric layer 120 by over-etching, it can be changed. The problem of parasitic capacitance effect.

Of course, Figures 11-12 are only two embodiments of the application of the sacrificial gate DG, whether it is a sacrificial gate DG located directly under the contact plug C2 or offset from the contact plug C2, or extending through the substrate of the insulating structure 10. 110a can be selectively applied to the first or second embodiment, and the resistive layer 140, 140a or the bulk resistive layer 140', 140a' having a U-shaped cross-sectional structure.

In summary, the present invention provides a buried resistor, which first forms a trench in a material layer such as a cap layer or a buffer layer, and then forms a resistive layer or a bulk resistive layer having a U-shaped cross-sectional structure in the trench to A buried resistor is formed. In this way, the present invention can solve the problem of insufficient etching or over etching caused by different depths of the trenches forming the contact plugs formed in different regions (for example, the transistor region and the resistive region); or, forming the trenches Contact plugs have too much difference in length and length to cause insufficient filling or overfilling; even when the interlayer dielectric layer is polished after forming the contact plug, the shorter contact plug is ground due to the interlayer dielectric layer. Completely removed. Furthermore, since the present invention is a buried resistor, it is possible to avoid the problem of over-etching the underlayer of the resistive layer caused by etching the resistive layer to pattern it.

Furthermore, if a buried resistor is formed in the buffer layer; in other words, the process directly forms a photoresist on the buffer layer to form a trench, and then forms a resistive layer in the trench to enable light. Since the barrier is formed only on the buffer layer, the adhesion is better, and since the material of the buffer layer is generally an oxide layer, no photoresist is formed in other material layers such as a nitride layer (for example, a cap layer), and a reaction occurs. A problem that is difficult to remove.

In addition, the present invention may further be adapted to form a sacrificial gate in the first interlayer dielectric layer or to extend the substrate through the bulk insulating structure to prevent the first interlayer dielectric layer or the insulating structure from being recessed. Moreover, the sacrificial gate and the contact plug formed in the first interlayer dielectric layer may be dislocated to prevent the parasitic capacitance effect when the contact plug extends to the first interlayer dielectric layer by over-etching. The problem.

10‧‧‧Insulation structure

20a‧‧‧buffer layer

110‧‧‧Base

120‧‧‧First interlayer dielectric layer

130‧‧‧ cover

140a‧‧‧resistance layer

150a‧‧ ‧ cover film

160‧‧‧Second interlayer dielectric layer

A‧‧‧First District

B‧‧‧Second District

C1‧‧‧Slot contact plug

C2‧‧‧Contact plug

M‧‧‧MOS transistor

Claims (22)

A buried resistor comprising: a first interlayer dielectric layer on a substrate; a cap layer on the first interlayer dielectric layer, wherein the cap layer has a trench; a resistive layer, The trench is covered so as to have a U-shaped cross-sectional structure; and a cover film is located in the trench and on the resistive layer. The buried resistor of claim 1, further comprising: a MOS transistor disposed in the first interlayer dielectric layer beside the resistive layer. The embedded resistor of claim 2, further comprising: a plurality of slot contact plugs disposed in the first interlayer dielectric layer and electrically connected to the MOS transistor. The buried resistor of claim 1, wherein the resistive layer comprises a titanium nitride layer. The embedded resistor of claim 1, wherein the cover film comprises a dielectric material. The buried resistor of claim 1, further comprising: a buffer layer disposed on the cap layer, but exposing the resistive layer and the cap film. The buried resistor of claim 6, further comprising: the buffer layer extending into the trench and covering the trench but below the resistive layer. The embedded resistor of claim 6, wherein a top surface of the cover film is flush with a top surface of the buffer layer on the cover layer. The embedded resistor of claim 1, wherein the U-shaped resistive layer has at least one vertical portion parallel to a side of the trench, and a top surface of the cover film is flush with a top end of the vertical portion . The buried resistor of claim 2, further comprising: a second interlayer dielectric layer on the cap layer, the resistive layer and the cover film. The embedded resistor according to claim 10, further comprising: a plurality of contact plugs, wherein a part of the contact plugs are located in the second interlayer dielectric layer and electrically connected to the contact plugs respectively The resistive layer, and the other portion of the contact plugs are located in the second interlayer dielectric layer, the cap layer and the buffer layer and electrically connected to the MOS transistors, respectively. The buried resistor of claim 11, further comprising: at least one sacrificial gate is located directly under the first interlayer dielectric layer and electrically connected to the contact plugs of the resistive layer. The buried resistor of claim 11, further comprising: at least one sacrificial gate is located in the first interlayer dielectric layer and directly under the resistive layer, but is misaligned with the contact plugs ( Misalignment). A buried resistor comprising: a first interlayer dielectric layer on a substrate; a cap layer is disposed on the first interlayer dielectric layer, wherein the cap layer has a trench; and a block-shaped resistive layer is disposed in the trench. The buried resistor of claim 14, further comprising: a MOS transistor disposed in the first interlayer dielectric layer beside the bulk resistive layer. The buried resistor according to claim 14, further comprising: a buffer layer disposed on the cap layer, but exposing the block resistor layer. The buried resistor of claim 16, further comprising: the buffer layer extending into the trench and covering the trench but below the bulk resistive layer. The embedded resistor of claim 16, wherein a top surface of the bulk resistive layer is flush with a top surface of the buffer layer on the cap layer. The buried resistor according to claim 14, further comprising: a second interlayer dielectric layer on the cap layer and the block resistor layer. The buried resistor of claim 19, further comprising: a plurality of contact plugs, wherein a part of the contact plugs are located in the second interlayer dielectric layer and electrically connected to the contact plugs respectively The bulk resistive layer, and the other portion of the contact plugs are located in the second interlayer dielectric layer, the cap layer and the buffer layer and electrically connected to the MOS transistors, respectively. The buried resistor as described in claim 20, further comprising: At least one sacrificial gate is located directly under the first interlayer dielectric layer and the contact plugs electrically connected to the bulk resistive layer. The buried resistor of claim 20, further comprising: at least one sacrificial gate is located in the first interlayer dielectric layer and directly under the bulk resistive layer, but with the contact plugs Misalignment.