TW201436152A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TW201436152A TW201436152A TW102128726A TW102128726A TW201436152A TW 201436152 A TW201436152 A TW 201436152A TW 102128726 A TW102128726 A TW 102128726A TW 102128726 A TW102128726 A TW 102128726A TW 201436152 A TW201436152 A TW 201436152A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 229920005989 resin Polymers 0.000 claims abstract description 170
- 239000011347 resin Substances 0.000 claims abstract description 170
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910000679 solder Inorganic materials 0.000 claims description 53
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- 238000004519 manufacturing process Methods 0.000 description 16
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- 239000004925 Acrylic resin Substances 0.000 description 3
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- 239000004593 Epoxy Substances 0.000 description 3
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- 229920006122 polyamide resin Polymers 0.000 description 3
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- 229910007637 SnAg Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 229910052594 sapphire Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
[相關申請案] [Related application]
本申請案享受以日本專利出願2013-51947號(申請日：2013年3月14日)為基礎申請案之優先權。本申請案係藉由參照該基礎申請案而包含基礎申請案之所有內容。 This application is entitled to the priority of the application based on Japanese Patent Application No. 2013-51947 (application date: March 14, 2013). This application contains all of the basic application by reference to the basic application.
本發明之實施形態係關於一種再配置半導體晶片且進行再配線之扇出型晶圓級晶片尺寸封裝(WLCSP，Wafer Level Chip Scale Package)結構之半導體裝置。 An embodiment of the present invention relates to a semiconductor device having a structure of a fan-out wafer level wafer size package (WLCSP) in which a semiconductor wafer is re-arranged and re-wired.
先前，揭示有一種將半導體晶片再配置於支持基板上，進而進行再配線之扇出型WLCSP結構之半導體裝置技術。於該技術中，存在下述之課題。 Heretofore, there has been disclosed a semiconductor device technology of a fan-out type WLCSP structure in which a semiconductor wafer is rearranged on a support substrate and further rewiring. In this technique, there are the following problems.
半導體裝置係於實施溫度循環測試(TCT，Temperature Cycling Test)之情形時，存在再配線層中產生裂痕從而產生斷線之情形。又，於TCT中，形成於再配線層之絕緣樹脂中將產生裂痕，且每次TCT之循環增加時，裂痕均將發展。 In the case where the semiconductor device is subjected to a Temperature Cycling Test (TCT), there is a case where a crack occurs in the rewiring layer to cause a disconnection. Further, in the TCT, cracks are generated in the insulating resin formed in the rewiring layer, and cracks are developed each time the cycle of TCT is increased.
於將焊球以跨越半導體晶片與形成於該半導體晶片外側之模具樹脂之間之方式配置之情形時，存在於TCT中球體中將產生應力，從而更容易斷裂之課題。 In the case where the solder ball is disposed between the semiconductor wafer and the mold resin formed on the outer side of the semiconductor wafer, there is a problem that stress is generated in the sphere in the TCT, which is more likely to be broken.
若封裝內之半導體晶片厚度變厚，則於TCT時，存在角部球體所受之應變增加，從而容易斷裂之課題。 When the thickness of the semiconductor wafer in the package is increased, there is a problem that the strain on the corner sphere is increased at the time of TCT, and the crack is easily broken.
本發明之一個實施形態係以提供一種具有長期之TCT壽命且可靠性較高之半導體裝置為目的。 One embodiment of the present invention is directed to providing a semiconductor device having a long-term TCT lifetime and high reliability.
根據本發明之一個實施形態，半導體裝置之特徵在於，其係包含半導體晶片；第1樹脂，其係以露出上述半導體晶片之表面之方式，將上述半導體晶片嵌入；第2樹脂，其形成於與上述半導體晶片之表面位於同一面上之上述第1樹脂面；配線層，其形成於上述第2樹脂上，且電性連接於上述半導體晶片；外部連接端子，其形成於上述配線層上；及金屬板，其形成於與上述第1樹脂之嵌入有上述半導體晶片之面對向之相反側之面；且上述第1樹脂其彈性模數為0.5~5 GPa。 According to an embodiment of the present invention, a semiconductor device includes a semiconductor wafer, a first resin in which the semiconductor wafer is exposed to expose a surface of the semiconductor wafer, and a second resin formed in the second resin. a surface of the semiconductor wafer on the same surface as the first resin surface; a wiring layer formed on the second resin and electrically connected to the semiconductor wafer; and an external connection terminal formed on the wiring layer; The metal plate is formed on a surface opposite to a surface on which the first resin is embedded with the semiconductor wafer; and the first resin has a modulus of elasticity of 0.5 to 5 GPa.
1‧‧‧半導體晶片 1‧‧‧Semiconductor wafer
2‧‧‧第1樹脂 2‧‧‧1st resin
2A、2B‧‧‧第1樹脂之面 2A, 2B‧‧‧ the first resin surface
3‧‧‧樹脂層 3‧‧‧ resin layer
4‧‧‧再配線層 4‧‧‧Rewiring layer
5‧‧‧外部連接端子 5‧‧‧External connection terminal
5c、5p‧‧‧焊球 5c, 5p‧‧‧ solder balls
6‧‧‧金屬板 6‧‧‧Metal plates
7‧‧‧第4樹脂層 7‧‧‧4th resin layer
10‧‧‧矽基板 10‧‧‧矽 substrate
11‧‧‧鈍化膜(絕緣膜) 11‧‧‧ Passivation film (insulation film)
31‧‧‧第1開口 31‧‧‧ first opening
32‧‧‧第2樹脂層 32‧‧‧2nd resin layer
41‧‧‧配線層 41‧‧‧Wiring layer
42‧‧‧第3樹脂層 42‧‧‧3rd resin layer
43‧‧‧第2開口 43‧‧‧2nd opening
51‧‧‧基底層 51‧‧‧ basal layer
52‧‧‧焊球 52‧‧‧ solder balls
D.L.‧‧‧切晶線 D.L.‧‧‧Cut line
S1‧‧‧第1支持板 S1‧‧‧1st support board
S2‧‧‧第2支持板 S2‧‧‧2nd support board
S3‧‧‧第3支持板 S3‧‧‧3rd support board
圖1係示意性表示第1實施形態之半導體裝置之構成之圖，且(a)為平面圖，(b)為(a)之A-A剖面圖。 Fig. 1 is a view schematically showing the configuration of a semiconductor device according to a first embodiment, wherein (a) is a plan view and (b) is a cross-sectional view taken along line A-A of (a).
圖2係表示進行模擬之結果之圖，且(a)為表示進行配線層所受之應力之模擬之結果之圖，(b)為表示關於TCT壽命進行模擬之結果之圖。 Fig. 2 is a view showing the results of simulation, and (a) is a graph showing the results of simulation of the stress applied to the wiring layer, and (b) is a graph showing the results of simulation of the TCT lifetime.
圖3-1係表示觀察半導體晶片之晶片尺寸與邊緣部分之焊球之變形狀況之變化所得之結果之圖。 Fig. 3-1 is a view showing the result of observing the change in the wafer size of the semiconductor wafer and the deformation state of the solder ball at the edge portion.
圖3-2係表示晶片下之接近角部之部分中之焊球之應力狀況之圖。 Fig. 3-2 is a view showing the stress state of the solder balls in the portion near the corner under the wafer.
圖3-3係表示作為無晶片區域之封裝之接近角部之部分之焊球之應力狀況之圖。 Fig. 3-3 is a view showing the stress state of the solder ball as a portion close to the corner portion of the package of the wafer-free region.
圖3-4係表示焊球已變形之狀態之半導體裝置之圖。 Fig. 3-4 is a view showing a semiconductor device in a state in which the solder balls have been deformed.
圖4係表示使晶片厚度/金屬板厚度變化之情形時求出焊球之應變之結果之圖。 Fig. 4 is a view showing the result of determining the strain of the solder ball when the thickness of the wafer/the thickness of the metal plate is changed.
圖5-1係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-1 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-2係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-2 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-3係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-3 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-4係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-4 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-5係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-5 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-6係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-6 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-7係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-7 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖5-8係表示第1實施形態之半導體裝置之製造步驟之圖。 Fig. 5-8 is a view showing a manufacturing procedure of the semiconductor device of the first embodiment.
圖6係示意性表示第2實施形態之半導體裝置之構成之剖面圖。 Fig. 6 is a cross-sectional view schematically showing the configuration of a semiconductor device of a second embodiment.
圖7-1係表示第2實施形態之半導體裝置之製造步驟之圖。 Fig. 7-1 is a view showing a manufacturing procedure of the semiconductor device of the second embodiment.
圖7-2係表示第2實施形態之半導體裝置之製造步驟之圖。 Fig. 7-2 is a view showing a manufacturing procedure of the semiconductor device of the second embodiment.
圖7-3係表示第2實施形態之半導體裝置之製造步驟之圖。 Fig. 7-3 is a view showing a manufacturing procedure of the semiconductor device of the second embodiment.
圖7-4係表示第2實施形態之半導體裝置之製造步驟之圖。 Fig. 7-4 is a view showing a manufacturing procedure of the semiconductor device of the second embodiment.
圖7-5係表示第2實施形態之半導體裝置之製造步驟之圖。 Fig. 7-5 is a view showing a manufacturing procedure of the semiconductor device of the second embodiment.
以下參照隨附圖式，詳細地說明實施形態中之半導體裝置及其製造方法。再者，並非由該等實施形態限定本發明。又，於以下之圖式中，為便於理解，而存在各構件之縮尺與實際不同之情形，且表示上下左右之方向之用詞係表示將圖式上之符號設為正方向之情形之下作為基準之相對性方向。 Hereinafter, a semiconductor device and a method of manufacturing the same according to the embodiment will be described in detail with reference to the accompanying drawings. Furthermore, the invention is not limited by the embodiments. Further, in the following drawings, in order to facilitate understanding, there are cases where the scales of the respective members are different from the actual ones, and the words indicating the directions of the up, down, left, and right directions indicate that the symbol on the pattern is set to the positive direction. The relative direction of the benchmark.
圖1(a)係示意性表示第1實施形態之半導體裝置之構成之平面圖，且圖1(b)為圖1(a)之A-A剖面圖。該半導體裝置之特徵在於其係扇出型晶圓級封裝(WLCSP)結構之半導體裝置，且將嵌入半導體晶片1 之第1樹脂2之彈性模數設為2.0 GPa，熱膨脹率設為45 ppm。該半導體裝置包含：第1樹脂2，其係以露出半導體晶片1之表面之方式，嵌入半導體晶片1；第2樹脂3，其形成於與該半導體晶片1之表面位於同一面上之第1樹脂2之表面；再配線層4，其形成於第2樹脂3上，且電性連接於半導體晶片1；及外部連接端子5，其形成於再配線層4上。而且，該半導體裝置包含形成於與第1樹脂2之嵌入半導體晶片之面2A對向之相反側之面2B之金屬板7。第1樹脂2中，使用例如環氧樹脂。 Fig. 1(a) is a plan view schematically showing a configuration of a semiconductor device according to a first embodiment, and Fig. 1(b) is a cross-sectional view taken along line A-A of Fig. 1(a). The semiconductor device is characterized in that it is a semiconductor device of a fan-out wafer level package (WLCSP) structure, and will be embedded in the semiconductor wafer 1 The first resin 2 had an elastic modulus of 2.0 GPa and a thermal expansion coefficient of 45 ppm. The semiconductor device includes a first resin 2 that is embedded in the semiconductor wafer 1 so as to expose the surface of the semiconductor wafer 1, and a second resin 3 formed on the same surface as the surface of the semiconductor wafer 1. The surface of the second layer 3 is formed on the second resin 3 and electrically connected to the semiconductor wafer 1 and the external connection terminal 5 is formed on the rewiring layer 4. Further, the semiconductor device includes a metal plate 7 formed on a surface 2B opposite to the surface 2A of the first resin 2 opposite to the semiconductor wafer. For the first resin 2, for example, an epoxy resin is used.
而且，進而形成於半導體晶片1上之第2樹脂3係具有第1開口31之第2樹脂層32。第2樹脂層32中使用例如聚醯亞胺樹脂。繼而，於該第2樹脂3上形成再配線層4。再配線層4係包含接觸於半導體晶片1之配線層41、及將其之上層覆蓋且具有第2開口43之第3樹脂層42。於該上層形成有外部連接端子5。外部連接端子5係包含經由形成於第3樹脂層42之第2開口43連接於配線層41之基底層(UBM)51、及形成於該基底層51上之焊球52。第3樹脂層42係相當於第3樹脂3。本實施形態係相較半導體晶片1之邊緣在外側形成有外部連接端子5之對於所謂扇出型WLCSP極為有用的半導體裝置。 Further, the second resin 3 formed on the semiconductor wafer 1 has the second resin layer 32 of the first opening 31. For example, a polyimide resin is used for the second resin layer 32. Then, the rewiring layer 4 is formed on the second resin 3. The rewiring layer 4 includes a wiring layer 41 that is in contact with the semiconductor wafer 1 and a third resin layer 42 that covers the upper layer and has the second opening 43. An external connection terminal 5 is formed in the upper layer. The external connection terminal 5 includes a base layer (UBM) 51 connected to the wiring layer 41 via the second opening 43 formed in the third resin layer 42, and a solder ball 52 formed on the base layer 51. The third resin layer 42 corresponds to the third resin 3 . This embodiment is a semiconductor device which is extremely useful for the so-called fan-out type WLCSP in which the external connection terminal 5 is formed on the outer side of the edge of the semiconductor wafer 1.
根據本實施形態之半導體裝置，即便實施溫度循環測試(TCT)之情形時，亦幾乎不存在再配線層4裂痕導致成為開路之情況。進而，即便將焊球52以跨越半導體晶片1與形成於外側之第1樹脂2(模具樹脂)之間之方式配置之情形時，亦幾乎不存在TCT中於焊球52產生應力而斷裂之情況。又，即便封裝內之半導體晶片厚度變厚之情形時，亦幾乎不存在於TCT時，角部球體所受之應變增加而斷裂之情況。如表1所示，當將第1樹脂2之彈性模數設為0.5~5 GPa，熱膨脹係數設為30~150 ppm，第2及第3樹脂層32、42之彈性模數設為0.5~5 GPa時，於實驗結果中不存在再配線層出現裂痕，或者焊球中產生應力之 情況，從而可獲得可靠性較高之半導體裝置。 According to the semiconductor device of the present embodiment, even when the temperature cycle test (TCT) is performed, there is almost no case where the rewiring layer 4 is cracked and the circuit is opened. Further, even when the solder ball 52 is disposed so as to straddle the semiconductor wafer 1 and the first resin 2 (mold resin) formed on the outer side, there is almost no stress in the TCT when the solder ball 52 is broken. . Further, even when the thickness of the semiconductor wafer in the package is increased, the strain on the corner sphere is increased and broken when the TCT is hardly present. As shown in Table 1, when the elastic modulus of the first resin 2 is 0.5 to 5 GPa, the thermal expansion coefficient is 30 to 150 ppm, and the elastic modulus of the second and third resin layers 32 and 42 is 0.5 to 0.5. At 5 GPa, there is no crack in the rewiring layer or stress in the solder ball in the experimental results. In this case, a highly reliable semiconductor device can be obtained.
另一方面，比較例係使用表1之左側所示之材料。即，將第1樹脂2之彈性模數設為0.1 GPa，熱膨脹係數設為173 ppm，第2及第3樹脂層32、42之彈性模數設為0.1 GPa。於對該先前之半導體裝置實施TCT之情形時，因再配線層之變形或裂痕之產生而產生開路不良。又，於TCT時，作為用於形成再配線層之絕緣樹脂之第2及第3樹脂層32、42中產生裂痕，且每次TCT之循環增加時，裂痕均進行發展。進而，於將焊球52以跨越半導體晶片1與形成於外側之第1樹脂(模具樹脂)2之間之方式配置之情形時，於TCT中，焊球52中產生應力，從而斷裂。又，若構成封裝之第1樹脂2內之半導體晶片1之厚度變厚，則於TCT時，存在封裝角部之焊球5c(參照圖1(a))所受之應變增加從而斷裂之情形。 On the other hand, the comparative examples used the materials shown on the left side of Table 1. That is, the elastic modulus of the first resin 2 was 0.1 GPa, the thermal expansion coefficient was 173 ppm, and the elastic modulus of the second and third resin layers 32 and 42 was 0.1 GPa. When the TCT is applied to the conventional semiconductor device, an open failure occurs due to deformation or cracking of the rewiring layer. Further, at the time of TCT, cracks are generated in the second and third resin layers 32 and 42 which are insulating resins for forming the rewiring layer, and cracks are developed every time the cycle of TCT is increased. Further, when the solder ball 52 is disposed so as to straddle the semiconductor wafer 1 and the first resin (mold resin) 2 formed on the outer side, stress is generated in the solder ball 52 in the TCT and is broken. Further, when the thickness of the semiconductor wafer 1 in the first resin 2 constituting the package is increased, the strain applied to the solder ball 5c (see FIG. 1(a)) at the package corner portion is increased at the time of TCT, and the crack is increased. .
其次，於圖2(a)中表示進行Cu再配線(RDL)所受之應力之模擬之結果。縱軸中表示相對於Cu斷裂之應力之相對值。La表示相對值為1之線。若相對值超過1(區域RNG)，則意味著Cu將斷裂。於相對值為1以下之區域(區域ROK)，Cu不會斷裂。S係表示比較例(現狀)之情形。橫軸係將第1樹脂之熱膨脹係數繪圖，且將改變第1樹脂之彈性模數之情形進行繪圖。為變得小於Cu斷裂之應力，而必須將第1樹脂之熱膨脹係數設為150 ppm以下，且將彈性模數設為0.5 GPa以上。圖2(b)中表示進行焊球之TCT壽命之模擬之結果。縱軸表示於安裝基板上安裝 有扇出型WLCSP時之TCT壽命之、以對於-25℃/125℃、1000循環產生1%不良為基準之情形之相對值。Lb表示相對值為1之線。於相對值為1以下之情形時(區域RNG)，意味著TCT壽命並不充分。於相對值為1以上之區域(區域ROK)，TCT壽命充分。S係表示比較例之情形。橫軸標繪出第1樹脂之熱膨脹係數，且標繪出改變第1樹脂之彈性模數之情形。若要滿足TCT壽命，必須將熱膨脹係數設為30 ppm以上，且將彈性模數設為5 GPa以下。 Next, the result of the simulation of the stress applied to the Cu rewiring (RDL) is shown in Fig. 2(a). The relative value of the stress with respect to Cu fracture is indicated in the vertical axis. La represents a line with a relative value of 1. If the relative value exceeds 1 (region R NG ), it means that Cu will break. In a region where the relative value is 1 or less (region R OK ), Cu does not break. The S system indicates the case of the comparative example (status). The horizontal axis is a graph in which the thermal expansion coefficient of the first resin is plotted, and the elastic modulus of the first resin is changed. In order to become less than the stress of Cu fracture, the thermal expansion coefficient of the first resin must be 150 ppm or less, and the elastic modulus should be 0.5 GPa or more. Fig. 2(b) shows the result of simulation of the TCT life of the solder ball. The vertical axis indicates the relative value of the TCT life when the fan-out type WLCSP is mounted on the mounting substrate, and the case is 1% defect at -25 ° C / 125 ° C and 1000 cycles. Lb represents a line with a relative value of one. When the relative value is 1 or less (region R NG ), it means that the TCT life is not sufficient. In a region where the relative value is 1 or more (region R OK ), the life of the TCT is sufficient. The S system indicates the case of the comparative example. The horizontal axis plots the thermal expansion coefficient of the first resin, and plots the change in the elastic modulus of the first resin. To meet the TCT life, the thermal expansion coefficient must be set to 30 ppm or more, and the elastic modulus should be set to 5 GPa or less.
其次，圖3-1中表示觀察半導體晶片1之邊緣部分之焊球5p之變形狀況(deformation)之變化之結果。此處，晶片尺寸設為1邊為2.0 mm者、1邊為2.35 mm者、1邊為2.50 mm者、及1邊為2.65 mm者。 Next, the result of the change in the deformation of the solder ball 5p at the edge portion of the semiconductor wafer 1 is shown in Fig. 3-1. Here, the wafer size is set to be 2.0 mm for one side, 2.35 mm for one side, 2.50 mm for one side, and 2.65 mm for one side.
例如，第1列之正中間揭示之晶片尺寸設為1邊2.0 mm之正方形時之半導體晶片1之邊緣部分之焊球5p幾乎未變形。此係本實施形態1之情形，且第1樹脂2之彈性模數為2 GPa，熱膨脹係數為45 ppm。與此相對，作為現狀之第1樹脂2之彈性模數設為0.1 GPa且熱膨脹係數設為170 ppm之第1列左例之情形時，半導體晶片1之邊緣部分之焊球5p較大地變形。又，第1樹脂2之彈性模數設為24 GPa且熱膨脹係數設為8 ppm之第1列右例之情形時，半導體晶片1之邊緣部分之焊球5p幾乎未變形。該圖雖未圖示，但第1樹脂2之彈性模數設為24 GPa且熱膨脹係數設為8 ppm之第1列右例之情形，存在半導體裝置自身產生翹曲之情況。 For example, the solder ball 5p at the edge portion of the semiconductor wafer 1 when the wafer size shown in the middle of the first column is set to a square of 2.0 mm on one side is hardly deformed. In the case of the first embodiment, the first resin 2 has an elastic modulus of 2 GPa and a thermal expansion coefficient of 45 ppm. On the other hand, when the elastic modulus of the first resin 2 of the present state is 0.1 GPa and the coefficient of thermal expansion is 170 ppm, the solder ball 5p at the edge portion of the semiconductor wafer 1 is largely deformed. When the elastic modulus of the first resin 2 is 24 GPa and the coefficient of thermal expansion is 8 ppm, the solder ball 5p at the edge portion of the semiconductor wafer 1 is hardly deformed. Although not shown in the figure, the first resin 2 has a modulus of elasticity of 24 GPa and a coefficient of thermal expansion of 8 ppm, which is the case of the right example of the first column, and the semiconductor device itself may be warped.
以此方式，在圖3-1之各列中表示半導體晶片及焊球之變形狀況，但半導體晶片1之邊緣部分與焊球之位置關係相應於半導體晶片之晶片尺寸而不同。如此地求得半導體晶片1之邊緣部分之焊球5p(參照圖1(a))之應變之結果，可知藉由將第1樹脂2之彈性模數設為2 GPa，且熱膨脹係數設為45 ppm，焊球之應變減少。 In this manner, the deformation state of the semiconductor wafer and the solder balls is shown in each column of FIG. 3-1, but the positional relationship between the edge portion of the semiconductor wafer 1 and the solder balls differs depending on the wafer size of the semiconductor wafer. As a result of obtaining the strain of the solder ball 5p (see FIG. 1(a)) at the edge portion of the semiconductor wafer 1, the elastic modulus of the first resin 2 was set to 2 GPa, and the thermal expansion coefficient was 45. Ppm, the strain of the solder ball is reduced.
其次，為求出改變第2及第3樹脂之彈性模數之情形時之配線層 之通孔所受之剪切應力之結果。如圖3-2所示，可知晶片下之接近角部之部分中之焊球5p之應力係於第2及第3樹脂層32、42之彈性模數為0.1 GPa的情況下較大，但該彈性模數為3.5PGa的情況下變小。與此相對，如圖3-3所示，可知作為無晶片之區域之封裝之接近角部之部分之焊球5c之應力係於第2及第3樹脂層32、42之彈性模數為0.1 GPa及3.5PGa的情況下為大致相同程度。 Next, in order to find the wiring layer when changing the elastic modulus of the second and third resins The result of the shear stress experienced by the through hole. As shown in FIG. 3-2, it is understood that the stress of the solder balls 5p in the portion near the corner portion of the wafer is large when the elastic modulus of the second and third resin layers 32 and 42 is 0.1 GPa, but When the elastic modulus is 3.5 PPa, it becomes small. On the other hand, as shown in Fig. 3-3, it is understood that the stress of the solder balls 5c which is a portion close to the corner portion of the package in the wafer-free region is the elastic modulus of the second and third resin layers 32 and 42 which is 0.1. In the case of GPa and 3.5PGa, the degree is approximately the same.
如圖3-2所示，於晶片下之接近角部之部分之焊球5p之應力較大之情形時，如圖3-4中之一例所示，第2及第3樹脂層32、42中產生變形，配線層41變得與基底層51非接觸。其結果，導致連接於半導體晶片之配線層41對焊球52產生連接不良。於圖3-2及圖3-3中，結構1(2層)表示形成有第2及第3樹脂層32、42之情形，結構2(3層)表示於第2及第3樹脂層32、42之上進而形成有配線層及第4樹脂層之情形即樹脂層成為3層之情形。 As shown in FIG. 3-2, when the stress of the solder ball 5p near the corner portion of the wafer is large, as shown in an example of FIG. 3-4, the second and third resin layers 32 and 42 are shown. The deformation occurs in the middle, and the wiring layer 41 becomes non-contact with the base layer 51. As a result, the wiring layer 41 connected to the semiconductor wafer causes connection failure to the solder balls 52. In Fig. 3-2 and Fig. 3-3, the structure 1 (two layers) indicates that the second and third resin layers 32 and 42 are formed, and the structure 2 (three layers) indicates the second and third resin layers 32. Further, in the case where the wiring layer and the fourth resin layer are formed on the 42nd, the resin layer is formed into three layers.
其次，將求出如表2所示地使晶片厚度/金屬板厚度變化之情形時之焊球52之非線性等效應變振幅之結果示於圖4。焊料之接合壽命係與非線性等效應變振幅成反比例，故非線性等效應變振幅變小，則壽命變長。縱軸表示焊料接合部之非線性等效應變振幅，橫軸表示晶片厚度/金屬板厚度。a表示將角部球體所受之非線性等效應變振幅繪圖所得之結果，b表示將最差球體所受之非線性等效應變振幅繪圖所得之結果。根據其結果，藉由將晶片厚度/金屬板厚度設為4以下，a與b之應變振幅分別變小至10%以下，進而，藉由將晶片厚度/金屬板厚度設為2以下，a與b之應變振幅分別進而變小至7%以下，焊料接合壽命變長。由此，可藉由將晶片厚度/金屬板厚度設為4以下，較理想為設為2以下，而使焊料連接壽命實現長壽命化。 Next, the results of the nonlinear equivalent strain amplitude of the solder balls 52 when the wafer thickness/metal plate thickness is changed as shown in Table 2 are shown in Fig. 4. The bonding life of the solder is inversely proportional to the nonlinear equivalent strain amplitude, so that the nonlinear equivalent strain amplitude becomes smaller, and the life becomes longer. The vertical axis represents the nonlinear equivalent strain amplitude of the solder joint, and the horizontal axis represents the wafer thickness/metal plate thickness. a represents the result of plotting the nonlinear equivalent strain amplitude of the corner sphere, and b represents the result of plotting the nonlinear equivalent strain amplitude of the worst sphere. According to the result, the thickness of the wafer/the thickness of the metal plate is set to 4 or less, and the strain amplitudes of a and b are respectively reduced to 10% or less, and further, by setting the thickness of the wafer/the thickness of the metal plate to 2 or less, a and The strain amplitude of b is further reduced to 7% or less, respectively, and the solder joint life becomes long. Therefore, by setting the thickness of the wafer/the thickness of the metal plate to 4 or less, or preferably 2 or less, the solder connection life can be extended.
(表2)
其次，一面參照圖5-1至圖5-8，一面說明第1實施形態之半導體裝置之製造步驟。首先，準備12英吋之半導體晶圓。於半導體晶圓，以100 μm間距形成有A1焊墊。切削半導體晶圓之背面，使之變薄為100 μm厚。進而進行切晶，使之單片化。藉由貼晶機而將以此方式製成之半導體晶片1再配置於形成在第1支持板S1上之接著劑層(未圖示)之上(圖5-1)。再者，半導體晶片1係於矽基板10之表面上形成有SiN等鈍化膜11。進而，於鈍化膜上可形成聚醯亞胺等有機膜。此處，作為第1支持板S1，使用Si、玻璃、藍寶石板、印刷基板、金屬板等。第1支持板S1之厚度係設為0.3~2 mm。作為接著劑，使用熱塑性樹脂、熱固性樹脂、PET材料、可因熱而膨脹剝離之樹脂等。例如，可使用聚醯亞胺樹脂、丙烯酸樹脂、環氧樹脂、及聚醯胺樹脂等。接著劑既可為液狀，亦可為薄片狀物。使用厚度為10 μm以上200 μm以下者。若薄於10 μm，則接著性之效果減弱，若超過200 μm，則變得過厚，平坦性惡化。 Next, the manufacturing steps of the semiconductor device of the first embodiment will be described with reference to Figs. 5-1 to 5-8. First, prepare a 12-inch semiconductor wafer. On the semiconductor wafer, an A1 pad is formed at a pitch of 100 μm. The back side of the semiconductor wafer was cut to a thickness of 100 μm. Further, the crystal is cut and singulated. The semiconductor wafer 1 produced in this manner is placed on the adhesive layer (not shown) formed on the first support plate S1 by a die attacher (Fig. 5-1). Further, the semiconductor wafer 1 is formed with a passivation film 11 such as SiN on the surface of the germanium substrate 10. Further, an organic film such as polyimide can be formed on the passivation film. Here, as the first support plate S1, Si, glass, sapphire plate, printed circuit board, metal plate, or the like is used. The thickness of the first support plate S1 is set to 0.3 to 2 mm. As the adhesive, a thermoplastic resin, a thermosetting resin, a PET material, a resin which can be expanded and peeled off by heat, or the like is used. For example, a polyimide resin, an acrylic resin, an epoxy resin, a polyamide resin, or the like can be used. The subsequent agent may be either liquid or flake. Use a thickness of 10 μm or more and 200 μm or less. When it is thinner than 10 μm, the effect of adhesion is weakened, and if it exceeds 200 μm, it becomes too thick and the flatness is deteriorated.
繼而，如圖5-2所示，於第1支持板S1上塗佈第1樹脂2。於塗佈時，可適用使用模具之模具法、使用印刷掩模之印刷法等。此時，將第1樹脂2之彈性模數設為0.5 GPa以上5 GPa以下。若彈性模數未達0.5 GPa，則如圖2(a)所示，存在產生TCT時於樹脂中產生裂痕，或配線層出現斷線之問題之情況。若彈性模數超過5 GPa，則如圖2(b)所示，產生如下問題：安裝於安裝基板之情形時焊料連接部之TCT壽命惡化，或翹曲變大，流動變得困難，此後經封裝之情形時翹曲變大，或無法滿足製品規格。進而，若將第1樹脂之熱膨脹係數設為30以上150 ppm以下，則可靠性進一步提昇。若熱膨脹係數未達30 ppm，則 如圖2(b)所示，產生如下問題：安裝於安裝基板之情形時焊料連接部之TCT壽命惡化，或因必須將填料較多地填入樹脂中，導致彈性模數變大，從而如上述所示，翹曲變大。若熱膨脹係數超過150 ppm，則如圖2(a)所示，TCT時於樹脂產生裂痕，或配線層出現斷線。作為第1樹脂之例，可使用環氧樹脂、聚矽氧樹脂、環氧/聚矽氧混合樹脂、丙烯酸樹脂、聚醯亞胺樹脂、聚醯胺樹脂、酚樹脂等之液狀者或薄片狀之增層膜、薄片狀之環氧樹脂等。第1樹脂之厚度係設為100 μm至1 mm以內。第1樹脂之厚度雖取決於晶片厚度，但若薄於100 μm則將變得難以保護晶片。若第1樹脂之厚度超過1 mm則樹脂之翹曲増大。 Next, as shown in FIG. 5-2, the first resin 2 is applied onto the first support sheet S1. At the time of coating, a mold method using a mold, a printing method using a printing mask, or the like can be applied. At this time, the elastic modulus of the first resin 2 is set to 0.5 GPa or more and 5 GPa or less. When the modulus of elasticity is less than 0.5 GPa, as shown in Fig. 2(a), there is a problem that cracks occur in the resin when the TCT is generated, or the wiring layer is broken. When the modulus of elasticity exceeds 5 GPa, as shown in FIG. 2(b), there is a problem that the TCT life of the solder joint portion is deteriorated when the mounting substrate is mounted, or the warpage becomes large, and the flow becomes difficult. In the case of packaging, the warpage becomes large, or the product specifications cannot be satisfied. Further, when the thermal expansion coefficient of the first resin is 30 or more and 150 ppm or less, the reliability is further improved. If the coefficient of thermal expansion is less than 30 ppm, then As shown in FIG. 2(b), there is a problem that the TCT life of the solder joint portion is deteriorated in the case of mounting on the mounting substrate, or the filler is required to be filled in the resin more, resulting in an increase in the modulus of elasticity. As shown above, the warpage becomes large. If the coefficient of thermal expansion exceeds 150 ppm, as shown in Fig. 2(a), cracks may occur in the resin at TCT or the wiring layer may be broken. As an example of the first resin, a liquid or sheet such as an epoxy resin, a polyoxymethylene resin, an epoxy/polyoxymethylene mixed resin, an acrylic resin, a polyimide resin, a polyamide resin, or a phenol resin can be used. A build-up film or a sheet-like epoxy resin. The thickness of the first resin is set to be within 100 μm to 1 mm. Although the thickness of the first resin depends on the thickness of the wafer, it is difficult to protect the wafer if it is thinner than 100 μm. If the thickness of the first resin exceeds 1 mm, the warpage of the resin is large.
繼而，如圖5-3所示，於第1樹脂2之上形成金屬板6。作為金屬板6，可使用Cu、Ni、Fe、及該等之混合材料例如42合金等。金屬板6之厚度係設為50 μm以上500 μm以下。金屬板6係為了抑制封裝之翹曲而形成，但若厚度未達50 μm則效果較少，若超過500 μm則封裝厚度變厚。金屬板6之形成係於使第1樹脂2半硬化時將金屬板6抵住使之密接接著。或者，亦可於第1樹脂2之上進而塗佈接著劑，貼附金屬板6。除了金屬板以外，亦可使用彈性模數較高之樹脂、矽、玻璃等。 Then, as shown in FIG. 5-3, a metal plate 6 is formed on the first resin 2. As the metal plate 6, Cu, Ni, Fe, and a mixed material such as a 42 alloy or the like can be used. The thickness of the metal plate 6 is set to 50 μm or more and 500 μm or less. The metal plate 6 is formed to suppress warpage of the package. However, if the thickness is less than 50 μm, the effect is small, and if it exceeds 500 μm, the package thickness becomes thick. The formation of the metal plate 6 is performed by bringing the metal plate 6 into contact with each other when the first resin 2 is semi-hardened. Alternatively, an adhesive may be applied to the first resin 2 to adhere the metal plate 6. In addition to the metal plate, a resin having a high modulus of elasticity, enamel, glass, or the like can also be used.
繼之，如圖5-4所示，自第1支持板S1將第1樹脂2剝離。剝離係於使用密接性較弱之接著劑之情形時，在第1支持板S1與第1樹脂2之間一面插入刀片狀之工具等一面進行剝離。於使用熱塑性樹脂之情形時，對金屬板6之面與第1支持板S1一面施加熱一面進行剝離。於使用因熱而膨脹之接著劑之情形時，同樣地可藉由施加熱而將接著劑剝離。半導體晶片1之表面露出，但於附著有樹脂之情形時，利用溶劑等進行去除。 Next, as shown in FIG. 5-4, the first resin 2 is peeled off from the first support sheet S1. When the peeling is performed using an adhesive having a weak adhesiveness, a blade-like tool or the like is inserted between the first support sheet S1 and the first resin 2 to be peeled off. When a thermoplastic resin is used, the surface of the metal plate 6 and the first support plate S1 are peeled off while applying heat. In the case where an adhesive which expands due to heat is used, the adhesive can be peeled off by applying heat as well. The surface of the semiconductor wafer 1 is exposed, but when a resin is attached, it is removed by a solvent or the like.
繼而，如圖5-5所示，使用接著劑(未圖示)貼附第2支持板S2。作為第2支持板S2，可與第1支持板S1同樣地使用Si基板、玻璃基板、藍寶石基板、印刷基板、金屬板等。厚度係設為0.3至2 mm以下。作為 接著劑，可使用熱塑性樹脂、熱固性樹脂、PET材料、及因熱而膨脹剝離之樹脂等。例如，可使用聚醯亞胺樹脂、丙烯酸樹脂、環氧樹脂、聚醯胺樹脂等。接著劑既可為液狀，亦可為薄片狀之物。使用厚度為10 μm以上200 μm以下者。但，在圖5-4之狀態下剛性較高之情形時，可不利用第2支持體S2貼附。 Next, as shown in FIG. 5-5, the second support plate S2 is attached using an adhesive (not shown). As the second support plate S2, a Si substrate, a glass substrate, a sapphire substrate, a printed substrate, a metal plate, or the like can be used similarly to the first support plate S1. The thickness is set to be 0.3 to 2 mm or less. As As the adhesive, a thermoplastic resin, a thermosetting resin, a PET material, a resin which is expanded and peeled off by heat, or the like can be used. For example, a polyimide resin, an acrylic resin, an epoxy resin, a polyamide resin, or the like can be used. The subsequent agent may be in the form of a liquid or a flake. Use a thickness of 10 μm or more and 200 μm or less. However, in the case where the rigidity is high in the state of Fig. 5-4, the second support S2 may not be attached.
繼而，將第2樹脂層32形成於半導體晶片1上。第2樹脂層32之厚度係設為2 μm以上20 μm以下。作為樹脂材料，可使用聚醯亞胺系、環氧系、聚矽氧系、環氧/聚矽氧系、丙烯酸系、酚系、聚醯胺系等。將第2樹脂層32之彈性模數設為0.5 GPa以上5 GPa以下。若未達0.5 GPa，則TCT時於樹脂產生裂痕，或配線層出現斷線。若超過5 GPa，則樹脂變硬，翹曲増大。第2樹脂層32係使用感光性材料，對準半導體晶片1之A1焊墊，形成第1開口31。藉由曝光顯影，而形成例如50 μm直徑之開口。繼之，於第2樹脂層32之整面，形成作為配線層41之金屬膜。金屬膜係採用濺鍍法、蒸鍍法、鍍敷法等而形成。作為金屬膜，可使用Ti/Cu等材料。Ti係形成為0.03~0.5 μm厚度，Cu係形成為0.1~1.0 μm厚度。作為除Ti/Cu以外之金屬，可使用Cr、TiN、Ni、Au、Pd等材料。 Then, the second resin layer 32 is formed on the semiconductor wafer 1. The thickness of the second resin layer 32 is set to be 2 μm or more and 20 μm or less. As the resin material, a polyimide, an epoxy, a polyoxygen, an epoxy/polyoxygen, an acrylic, a phenol, a polyamine or the like can be used. The elastic modulus of the second resin layer 32 is set to 0.5 GPa or more and 5 GPa or less. If it is less than 0.5 GPa, cracks may occur in the resin at TCT, or the wiring layer may be broken. If it exceeds 5 GPa, the resin becomes hard and the warpage is large. The second resin layer 32 is formed by using a photosensitive material and aligning the A1 pads of the semiconductor wafer 1 to form the first opening 31. An opening of, for example, a diameter of 50 μm is formed by exposure development. Then, a metal film as the wiring layer 41 is formed on the entire surface of the second resin layer 32. The metal film is formed by a sputtering method, a vapor deposition method, a plating method, or the like. As the metal film, a material such as Ti/Cu can be used. The Ti system is formed to have a thickness of 0.03 to 0.5 μm, and the Cu system is formed to have a thickness of 0.1 to 1.0 μm. As the metal other than Ti/Cu, materials such as Cr, TiN, Ni, Au, and Pd can be used.
繼而，將抗蝕劑塗佈10 μm左右，開設開口。例如形成L/S=50/50 μm之開口。於開口部分，進行電鍍形成1~15 μm厚度之Cu。本次形成為例如5 μm。將抗蝕劑剝離，蝕刻籽晶層之Cu與Ti。作為Cu之蝕刻液，可使用硫酸與H2O2混合而成者，Ti之蝕刻液係使用HF或H2O2中添加KOH而成者等。於Cu之再配線上塗佈第3樹脂層42，形成焊球用之第2開口43。第3樹脂層42可為與第2樹脂層32相同之樹脂。將第3樹脂層42之彈性模數設為0.5 GPa以上5 GPa。若未達0.5 GPa，則TCT時於樹脂產生裂痕，或配線層出現斷線。若超過5 GPa，則樹脂變硬，翹曲増大。 Then, the resist was applied to a thickness of about 10 μm to open an opening. For example, an opening of L/S = 50/50 μm is formed. In the opening portion, electroplating is performed to form Cu having a thickness of 1 to 15 μm. This time is formed to be, for example, 5 μm. The resist is peeled off, and Cu and Ti of the seed layer are etched. As the etching liquid for Cu, a mixture of sulfuric acid and H 2 O 2 can be used, and an etching solution for Ti is obtained by adding KOH to HF or H 2 O 2 . The third resin layer 42 is applied to the rewiring of Cu to form a second opening 43 for the solder ball. The third resin layer 42 may be the same resin as the second resin layer 32. The elastic modulus of the third resin layer 42 is set to 0.5 GPa or more and 5 GPa. If it is less than 0.5 GPa, cracks may occur in the resin at TCT, or the wiring layer may be broken. If it exceeds 5 GPa, the resin becomes hard and the warpage is large.
繼而，如圖5-6所示，於第3樹脂層42之開口部分形成基底層(UBM)51。首先，於第3樹脂層42整面形成金屬膜。金屬膜係利用濺鍍法、蒸鍍法、鍍敷法等形成。形成Ti/Cu等材料，作為金屬膜。Ti係形成為0.03~0.5 μm厚度，Cu係形成為0.1~1.0 μm厚度。使用Cr、TiN、Ni、Au、Pd等材料，作為除Ti/Cu以外之金屬。接著，將抗蝕劑塗佈10 μm左右，開設例如400 μm直徑之第2開口43。於該開口利用鍍敷法形成Cu/Ni/Au等。Cu係形成3 μm，Ni係形成2 μm，Au係形成0.3 μm。將抗蝕劑剝離，蝕刻籽晶層之Cu與Ti。作為Cu之蝕刻液，可使用硫酸與H2O2混合而成者，且Ti之蝕刻液使用HF或H2O2中添加KOH而成者等。 Then, as shown in FIGS. 5-6, a base layer (UBM) 51 is formed in the opening portion of the third resin layer 42. First, a metal film is formed on the entire surface of the third resin layer 42. The metal film is formed by a sputtering method, a vapor deposition method, a plating method, or the like. A material such as Ti/Cu is formed as a metal film. The Ti system is formed to have a thickness of 0.03 to 0.5 μm, and the Cu system is formed to have a thickness of 0.1 to 1.0 μm. Materials such as Cr, TiN, Ni, Au, and Pd are used as metals other than Ti/Cu. Next, the resist is applied to a thickness of about 10 μm to open a second opening 43 having a diameter of, for example, 400 μm. Cu/Ni/Au or the like is formed by plating in the opening. The Cu system forms 3 μm, the Ni system forms 2 μm, and the Au system forms 0.3 μm. The resist is peeled off, and Cu and Ti of the seed layer are etched. As the etching liquid for Cu, it is possible to use a mixture of sulfuric acid and H 2 O 2 , and the etching solution for Ti is obtained by adding KOH to HF or H 2 O 2 .
再者，本實施形態係圖示再配線為1層配線之情形，但亦可形成2層以上。於該情形時，進而反覆地形成第2、第3樹脂層，從而形成再配線層。又，可將半導體晶圓上先形成第2樹脂且進而形成再配線層者進行切晶，且再配置於形成於第1支持板S1上之接著劑層之上，實施相同之製程。 In the present embodiment, the case where the rewiring is one-layer wiring is shown, but two or more layers may be formed. In this case, the second and third resin layers are further formed to form a rewiring layer. Further, the second resin is formed on the semiconductor wafer, and the rewiring layer is formed to be diced, and then placed on the adhesive layer formed on the first support S1, and the same process is performed.
繼而，於基底層51上塗佈焊劑後，裝載焊球52(圖5-7)。焊球52係使用SnAg、SnAgCu等無Pb焊料。接著，投入至回焊爐，使焊球熔融，與基底層51進行接合。進而，以焊劑溶劑或純水洗淨進行去除。 Then, after the flux is applied onto the base layer 51, the solder balls 52 are loaded (Figs. 5-7). The solder ball 52 is made of a Pb-free solder such as SnAg or SnAgCu. Next, it is thrown into a reflow furnace, and a solder ball is melted, and it joins with the base layer 51. Further, it is removed by washing with a flux solvent or pure water.
又，本實施形態係對形成基底層51之情形進行了說明，勿庸置疑，亦可不形成基底層51，而於第2開口43裝載球體，將配線層與焊球接合。 Further, in the present embodiment, the case where the underlayer 51 is formed has been described. It is needless to say that the underlayer 51 is not formed, and the sphere is placed in the second opening 43 to bond the wiring layer to the solder ball.
繼而，使用晶片切割機，沿著切晶線D.L.進行封裝切晶，使之單片化，藉此，完成扇出型WLCSP(圖5-8)。 Then, using a wafer dicing machine, package dicing is performed along the dicing line D.L. to singulate it, thereby completing the fan-out type WLCSP (Fig. 5-8).
對以此方式製作之扇出型WLCSP實施-55℃/125℃之TCT之後，即便2000次循環，亦未產生配線層之斷線或絕緣層(第1樹脂至第3樹脂層)之裂痕。又，於安裝後，實施-25/125℃之TCT之後，即便1000 次循環，亦未產生焊球之斷裂。 After the TCR of -55 ° C / 125 ° C was applied to the fan-out type WLCSP produced in this manner, the breakage of the wiring layer or the crack of the insulating layer (the first resin to the third resin layer) did not occur even in 2000 cycles. Also, after installation, after implementing a TCT of -25/125 ° C, even 1000 In the secondary cycle, no breakage of the solder balls occurred.
又，本實施形態係對將焊球用作外部連接端子之例進行了說明，但亦可適用於具備焊墊型之外部連接端子等其他結構之外部連接端子者。 Further, in the present embodiment, an example in which the solder ball is used as the external connection terminal has been described. However, the present invention can also be applied to an external connection terminal having another structure such as a pad type external connection terminal.
圖6係示意性表示第2實施形態之半導體裝置之構成之剖面圖。第2實施形態之半導體裝置不同於圖1(a)及圖1(b)所示之第1實施形態之半導體裝置之處係金屬板6之外緣。即，金屬板6到達半導體裝置之外緣、即第1樹脂2之外緣為止，且以外緣一致之方式進行切晶，與此相對，本實施形態係金屬板6之外緣較第1樹脂2之外緣更為內側，且由第4樹脂7覆蓋背面。其他與上述第1實施形態相同，故此處省略說明。即，於金屬板6上形成第1樹脂2，且將半導體晶片1嵌入於該第1樹脂2內。而且，本實施形態係進而於形成於半導體晶片1上之第2樹脂層32上形成再配線層，且於該再配線層上形成第3樹脂層43、且形成焊球52之結構。又，金屬板6形成為較封裝尺寸小50 μm~1 mm左右，且於金屬板面形成有第4樹脂層7。 Fig. 6 is a cross-sectional view schematically showing the configuration of a semiconductor device of a second embodiment. The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment shown in FIGS. 1(a) and 1(b) in the outer edge of the metal plate 6. In other words, the metal plate 6 reaches the outer edge of the semiconductor device, that is, the outer edge of the first resin 2, and the outer edge thereof is diced, and the outer edge of the metal plate 6 is the first resin. 2 The outer edge is further inside, and the back surface is covered by the fourth resin 7. Others are the same as those of the first embodiment described above, and thus the description thereof is omitted here. That is, the first resin 2 is formed on the metal plate 6, and the semiconductor wafer 1 is embedded in the first resin 2. Further, in the present embodiment, a rewiring layer is formed on the second resin layer 32 formed on the semiconductor wafer 1, and the third resin layer 43 is formed on the rewiring layer, and the solder balls 52 are formed. Further, the metal plate 6 is formed to be smaller than the package size by about 50 μm to 1 mm, and the fourth resin layer 7 is formed on the metal plate surface.
其次，參照圖7-1至圖7-5，對第2實施形態之半導體裝置之製造步驟進行說明。於本實施形態中，截至第1實施形態中之圖5-6亦與第1實施形態同樣地實施，故此處省略說明。於上述第1實施形態中，如圖5-6所示，於第3樹脂層42之開口部分形成基底層(UBM)51之後，將背面側之第2支持板S2剝離(圖7-1)。剝離係於使用密接性較弱之接著劑之情形時，於第2支持板S2與第1樹脂2間一面插入刀片狀之工具等一面進行剝離。於使用熱塑性之樹脂之情形時，對金屬板6之面與第2支持板S2一面施加熱一面進行剝離。於使用會因熱而膨脹之接著劑之情形時，可同樣地藉由施加熱而將接著劑剝離。金屬板6之面露出，但於附著有樹脂之情形時，利用溶劑等進行去除。 Next, a manufacturing procedure of the semiconductor device of the second embodiment will be described with reference to FIGS. 7-1 to 7-5. In the present embodiment, FIG. 5-6 as in the first embodiment is also implemented in the same manner as the first embodiment, and thus the description thereof is omitted. In the first embodiment, as shown in FIG. 5-6, after the base layer (UBM) 51 is formed in the opening portion of the third resin layer 42, the second support plate S2 on the back side is peeled off (FIG. 7-1). . When the peeling is performed by using an adhesive having a weak adhesiveness, a blade-like tool or the like is inserted between the second support sheet S2 and the first resin 2 to be peeled off. When a thermoplastic resin is used, the surface of the metal plate 6 and the second support plate S2 are peeled off while applying heat. In the case where an adhesive which expands due to heat is used, the adhesive can be peeled off by applying heat in the same manner. The surface of the metal plate 6 is exposed, but when a resin is attached, it is removed by a solvent or the like.
繼而，蝕刻金屬板6(圖7-2)。於金屬板6形成抗蝕劑(未圖示)，且藉由利用光微影法進行曝光顯影而形成晶格狀之開口。接著，蝕刻成晶格狀開口之部分之金屬板6。晶格狀之開口係設為100 μm~2 mm。於蝕刻後，將抗蝕劑剝離。金屬板6可以刮刀晶格狀地去除，亦可使用雷射描繪而晶格狀地去除。 Then, the metal plate 6 is etched (Fig. 7-2). A resist (not shown) is formed on the metal plate 6, and an opening of a lattice shape is formed by exposure and development by photolithography. Next, the metal plate 6 is etched into a portion of the lattice-like opening. The lattice-like opening is set to 100 μm to 2 mm. After the etching, the resist was peeled off. The metal plate 6 can be removed in a lattice shape by a doctor blade, or can be removed in a lattice shape by laser drawing.
繼之，於金屬板6上形成第4樹脂層7(圖7-3)。於第4樹脂層7之形成時，既可採用旋轉塗佈法，亦可採用印刷法。第4樹脂層7既可為液狀，亦可貼附膜狀者。再者，亦可不形成第4樹脂層7。 Next, a fourth resin layer 7 is formed on the metal plate 6 (Fig. 7-3). In the formation of the fourth resin layer 7, either a spin coating method or a printing method may be employed. The fourth resin layer 7 may be in the form of a liquid or a film. Further, the fourth resin layer 7 may not be formed.
繼而，於第4樹脂層7之面，使用接著劑貼附第3支持板S3。於基底層51上塗佈焊劑後，裝載焊球52(圖7-4)。作為焊球52，可使用SnAg、SnAgCu等無Pb焊料。接著，投入回焊爐中使焊球52熔融，從而與基底層51接合。進而利用溶劑或純水洗淨將焊劑去除。雖對形成基底層51之情形進行了說明，但亦可不形成基底層51地將球體裝載於第3開口43，且將配線層41與焊球52接合。 Then, on the surface of the fourth resin layer 7, the third support plate S3 is attached using an adhesive. After the flux is applied to the base layer 51, the solder balls 52 are loaded (Fig. 7-4). As the solder ball 52, a Pb-free solder such as SnAg or SnAgCu can be used. Next, the solder ball 52 is melted in the reflow furnace to be bonded to the underlayer 51. Further, the flux is removed by washing with a solvent or pure water. Although the case where the underlayer 51 is formed has been described, the sphere may be placed on the third opening 43 without forming the underlayer 51, and the wiring layer 41 may be bonded to the solder ball 52.
接著，使用晶片切割機，將利用蝕刻而將金屬板6開口之部分作為切晶線D.L進行切晶，使之單片化，藉此，完成扇出型WLCSP(圖7-5)。 Next, using a wafer dicing machine, a portion in which the metal plate 6 is opened by etching is diced as a dicing line D.L, and is singulated, whereby the fan-out type WLCSP is completed (FIG. 7-5).
上述第1實施形態係將金屬板6與第1樹脂2統一地進行切晶，但存在因切晶之影響導致金屬板6與第1樹脂2剝離之可能性。第2實施形態係為避免該現象而首先蝕刻金屬板6，從而預先於切晶線D.L.附近形成槽，僅蝕刻第1樹脂2之製程。 In the first embodiment described above, the metal plate 6 and the first resin 2 are collectively diced, but there is a possibility that the metal plate 6 and the first resin 2 are peeled off due to the influence of the dicing. In the second embodiment, in order to avoid this phenomenon, the metal plate 6 is first etched, and a groove is formed in the vicinity of the dicing line D.L., and only the process of the first resin 2 is etched.
將以上述方式製作之扇出型WLCSP實施-55℃/125℃之TCT之後，即便2000次循環，亦未產生配線層之斷線或樹脂層(第2及第3樹脂層)之裂痕。又，於安裝後，實施-25/125℃之TCT之後，即便1000次循環，亦未產生焊球之斷裂。此處所謂第2樹脂係包含第2及第3樹脂層者，且將第2樹脂層或第3樹脂層兩者維持彈性模數0.5~5 GP即 可，但將任一者維持彈性模數0.5~5 GP即可。 After the fan-out type WLCSP produced as described above was subjected to TCT at -55 ° C / 125 ° C, cracks in the wiring layer or cracks in the resin layers (second and third resin layers) did not occur even in 2000 cycles. Further, after the TCT of -25/125 ° C was applied after the mounting, no breakage of the solder balls occurred even in 1000 cycles. Here, the second resin includes the second and third resin layers, and both the second resin layer and the third resin layer are maintained at an elastic modulus of 0.5 to 5 GP. Yes, but you can maintain either the elastic modulus of 0.5~5 GP.
如以上說明所述， As stated in the above description,
(1)由於將第1樹脂之彈性模數設為0.5~5 GPa，故而於TCT中配線未斷裂，且絕緣層中未產生裂痕。再者，僅將第1樹脂之彈性模數設為0.5~5 GPa之情形亦為有效。 (1) Since the elastic modulus of the first resin is set to 0.5 to 5 GPa, the wiring is not broken in the TCT, and no crack is generated in the insulating layer. Further, it is also effective to set the elastic modulus of the first resin to 0.5 to 5 GPa.
(2)由於將第1樹脂之熱膨脹係數設為30~150 ppm，故而於TCT中配線未斷裂，且第2及第3樹脂層(絕緣層)之第1樹脂未產生裂痕。 (2) Since the thermal expansion coefficient of the first resin is 30 to 150 ppm, the wiring is not broken in the TCT, and the first resin of the second and third resin layers (insulating layers) is not cracked.
(3)由於包含第2及第3樹脂層，且將第2樹脂之彈性模數設為0.5~5 GPa，故而於TCT中配線未斷裂，且絕緣層未產生裂痕。 (3) Since the second and third resin layers are included and the elastic modulus of the second resin is 0.5 to 5 GPa, the wiring is not broken in the TCT, and the insulating layer is not cracked.
(4)由於將第1樹脂之彈性模數設為0.5~5 GPa，熱膨脹係數設為30~150 ppm，且第2樹脂之彈性模數設為0.5~5 GPa，故而獲得於TCT中配線未斷裂，且絕緣層未產生裂痕之進一步效果。 (4) Since the elastic modulus of the first resin is 0.5 to 5 GPa, the thermal expansion coefficient is 30 to 150 ppm, and the elastic modulus of the second resin is 0.5 to 5 GPa, so that the wiring is not obtained in the TCT. Breaking, and the insulation layer has no further effect of cracking.
(5)如(1)至(4)所述，其中因將晶片厚度/金屬板厚度之比設為4以下，故而獲得於TCT中配線未斷裂，且絕緣層未產生裂痕之進一步效果。 (5) As described in (1) to (4), in which the ratio of the thickness of the wafer to the thickness of the metal plate is set to 4 or less, the wiring is not broken in the TCT, and the insulating layer is not further cracked.
對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提示者，並非意圖限定發明之範圍。該等新穎之實施形態可由其他之各種形態實施，且於不脫離發明精神之範圍內，可進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或精神中，並且包含於申請專利之範圍中揭示之發明及其均等之範圍中。 The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The various embodiments of the invention may be embodied in a variety of other forms, and various omissions, substitutions and changes can be made without departing from the spirit of the invention. Such embodiments, or variations thereof, are included within the scope and spirit of the invention and are included in the scope of the invention disclosed in the scope of the claims.
1‧‧‧半導體晶片 1‧‧‧Semiconductor wafer
2‧‧‧第1樹脂 2‧‧‧1st resin
2A、2B‧‧‧第1樹脂之面 2A, 2B‧‧‧ the first resin surface
3‧‧‧樹脂層 3‧‧‧ resin layer
4‧‧‧再配線層 4‧‧‧Rewiring layer
5‧‧‧外部連接端子 5‧‧‧External connection terminal
5c、5p‧‧‧焊球 5c, 5p‧‧‧ solder balls
6‧‧‧金屬板 6‧‧‧Metal plates
7‧‧‧第4樹脂層 7‧‧‧4th resin layer
10‧‧‧矽基板 10‧‧‧矽 substrate
11‧‧‧鈍化膜(絕緣膜) 11‧‧‧ Passivation film (insulation film)
31‧‧‧第1開口 31‧‧‧ first opening
32‧‧‧第2樹脂層 32‧‧‧2nd resin layer
41‧‧‧配線層 41‧‧‧Wiring layer
42‧‧‧第3樹脂層 42‧‧‧3rd resin layer
43‧‧‧第2開口 43‧‧‧2nd opening
51‧‧‧基底層 51‧‧‧ basal layer
52‧‧‧焊球 52‧‧‧ solder balls
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| TWI667747B (en) * | 2016-10-19 | 2019-08-01 | 日商村田製作所股份有限公司 | Semiconductor device and method of manufacturing the same |
| TWI682509B (en) * | 2018-06-29 | 2020-01-11 | 台灣積體電路製造股份有限公司 | Package and method of forming the same |
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| JP6742593B2 (en) * | 2015-01-05 | 2020-08-19 | 日本電気硝子株式会社 | Method for manufacturing supporting glass substrate and method for manufacturing laminated body |
| CN107403784B (en) * | 2016-05-19 | 2020-04-24 | 胡川 | Circuit board manufacturing method and structure |
| EP3496138B1 (en) | 2016-08-05 | 2024-01-17 | Mitsubishi Gas Chemical Company, Inc. | Support substrate and method for manufacturing package substrate for mounting semiconductor element |
| TWI652774B (en) * | 2017-03-03 | 2019-03-01 | 矽品精密工業股份有限公司 | Electronic package manufacturing method |
| JP7178713B2 (en) | 2017-05-19 | 2022-11-28 | 学校法人早稲田大学 | Power semiconductor module device and power semiconductor module manufacturing method |
| CN111199935A (en) * | 2018-11-20 | 2020-05-26 | 奥特斯奥地利科技与系统技术有限公司 | Electronic package and method of producing an electronic package |
| JP7346906B2 (en) * | 2019-05-17 | 2023-09-20 | 株式会社レゾナック | Method for predicting crack occurrence rate, method for selecting resin composition that can suppress crack occurrence, and method for manufacturing electronic components |
| JP7051053B2 (en) * | 2020-07-20 | 2022-04-11 | 日本電気硝子株式会社 | Support glass substrate and laminate using it |
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| JP3180686B2 (en) * | 1996-10-09 | 2001-06-25 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
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| JP2001326304A (en) * | 2000-05-15 | 2001-11-22 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP3944874B2 (en) * | 2000-08-24 | 2007-07-18 | 東レ・デュポン株式会社 | Polyimide film, method for producing the same, and metal wiring board using the same |
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| JP2011187473A (en) * | 2010-03-04 | 2011-09-22 | Nec Corp | Wiring substrate with built-in semiconductor element |
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| TWI667747B (en) * | 2016-10-19 | 2019-08-01 | 日商村田製作所股份有限公司 | Semiconductor device and method of manufacturing the same |
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