KR101009158B1 - Wafer level chip scale package and fabricating method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level chip scale package, wherein the solder resist layer is formed only around the solder ball, or the solder resist layer having a high thermal expansion coefficient is higher than that of other components by minimizing the thickness of the solder resist layer in the region except the solder ball region. Provided are a structure of a wafer level chip scale package and a method of manufacturing the same, which minimize the use of layers to minimize stress generation.

Semiconductor chip, redistribution layer, solder resist layer, solder ball, non-oxide metal layer

Description

Wafer level chip scale package and fabrication method of the same

The present invention relates to a wafer level chip scale package and a method of manufacturing the same. More particularly, by selectively forming a solder resist layer having a high thermal expansion coefficient, stress generation due to a difference in thermal expansion coefficient of the material constituting the component can be minimized. A wafer level chip scale package and a method of manufacturing the same.

One of the major trends in technology development in the semiconductor industry is to reduce the size of semiconductor devices. Fine Pitch Ball Grid Array (FBGA) package that can implement a large number of pins in a small size in accordance with the rapidly increasing demand for small computer and portable electronic devices in the field of semiconductor device package or Semiconductor device packages such as a chip scale package (CSP) have been developed.

Semiconductor device packages such as fine pitch ball grid array packages or chip scale packages that are currently being developed have physical advantages such as miniaturization and light weight, but have not yet been as reliable as conventional plastic packages. In addition, the price competitiveness of raw and subsidiary materials and processes is high. In particular, the so-called micro BGA (micro BGA) package, which is a typical type of chip scale package, has better characteristics than the fine pitch ball grid array or chip scale package, but also has a disadvantage of low reliability and price competitiveness. have.

A so-called wafer level chip scale package (WLCSP) that uses redistribution or rerouting of a bonding pad of a semiconductor chip as a kind of package developed to overcome this disadvantage. There is.

The wafer-level chip scale package is a package that cuts the wafer on which the solder ball is formed at the chip level after collectively performing the redistribution layer and the solder ball forming process at the wafer level before cutting to the individual chip level.

1 is a cross-sectional view of a wafer level chip scale package according to the prior art.

First, referring to FIG. 1, a wafer level chip scale package 10 according to the related art may include a semiconductor chip 11 having a bonding pad 12 formed on an upper surface thereof, and a first insulating layer formed on an upper surface of the semiconductor chip 11. The redistribution layer 14 and the redistribution layer 14 extending from the bonding pad 12 to the first insulating layer 13 and having an under bump metallugy (UBM) 15 formed thereon. ) And a second insulating layer 16 formed on the first insulating layer 13, a solder ball 18 formed on the adhesive auxiliary layer 15, and an open part exposing the solder ball 18. And a solder resist layer 17 formed on the layer 16 and the redistribution layer 14.

However, the wafer level chip scale package 10 according to the related art shown in FIG. 1 has a problem in that stress due to a difference in coefficient of thermal expansion occurs due to different materials of each component. In particular, in the related art, a solder resist layer 17 having a larger thermal expansion coefficient than that of other components is applied to the entire surface of the redistribution layer 14 so that heat is generated during operation of the wafer level chip scale package 10 or heat from outside. In this case, stress is concentrated in the solder balls 18 contacting the solder resist layer 17 due to the difference in the coefficient of thermal expansion (CTE) according to the material difference, resulting in a weak bonding strength of the solder balls 18 or thermal expansion. Due to the difference in coefficients, there was a problem that the wafer level package was bent.

Accordingly, the present invention has been made to solve the above problems, the present invention can minimize the occurrence of stress due to the difference in thermal expansion coefficient of the material constituting the component by selectively forming a solder resist layer having a large thermal expansion coefficient To provide a wafer level chip scale package and a method of manufacturing the same.

A wafer level chip scale package according to a first embodiment of the present invention may include a semiconductor chip having a bonding pad formed on an upper surface thereof, a first insulating layer formed so that the bonding pad is exposed on an upper surface of the semiconductor chip, and the bonding pad. A redistribution layer extending on the first insulating layer, a non-oxide metal layer formed on the redistribution layer to cover the redistribution layer, and having an adhesive auxiliary layer at one end thereof, formed on the first insulating layer, and the non-oxidation And a second insulating layer exposing a metal layer, a solder ball formed in the adhesive auxiliary layer, and a patterned solder resist layer formed only in a region around the non-metal oxide layer and the solder ball on the second insulating layer.

In addition, the wafer level chip scale package according to the second exemplary embodiment of the present invention may include a semiconductor chip having a bonding pad formed on an upper surface thereof, a first insulating layer formed on an upper surface of the semiconductor chip and formed to expose the bonding pad. A redistribution layer extending from the bonding pads on the first insulating layer and having an adhesive auxiliary layer at one end thereof; a second insulating layer formed on the first insulating layer and exposing the redistribution layer; And a patterned solder resist layer formed on the rewiring layer and the second insulating layer, wherein the patterned solder resist layer comprises an open portion for exposing the adhesive auxiliary layer. A thickness smaller than the first solder resist layer formed in the peripheral region of the auxiliary layer and the first solder resist layer formed in the region other than the first solder resist layer It is characterized in that it comprises a second solder resist layer.

In addition, the method of manufacturing a wafer level chip scale package according to a preferred embodiment of the present invention, (A) forming a first insulating layer to expose a bonding pad on the semiconductor chip at the wafer level, (B) the bonding pad Forming a redistribution layer extending on the first insulating layer from (C) forming a non-oxide layer having an adhesive auxiliary layer formed on the redistribution layer at one end thereof, and (D) on the first insulating layer. Forming a second insulating layer exposing the non-oxide layer, and (E) a first open portion exposing the adhesive auxiliary layer on the non-oxide layer and the second insulating layer and an area around the adhesive auxiliary layer Forming a patterned solder resist layer formed only in an area around the adhesive auxiliary layer to include a second open portion exposing the non-oxidizing metal layer and the second insulating layer in an area except for It is characterized by.

In addition, a method of manufacturing a wafer level chip scale package according to a second preferred embodiment of the present invention comprises the steps of: (A) forming a first insulating layer exposing a bonding pad on the chip at the wafer level, (B) the bonding Forming a redistribution layer extending from the pad on the first insulating layer and having an adhesive auxiliary layer at one end thereof, (C) forming a second insulating layer exposing the redistribution layer on the first insulating layer; (D) a first solder resist layer and the first solder resist layer formed in a peripheral area of the adhesive auxiliary layer including a first open part exposing the adhesive auxiliary layer on the redistribution layer and the second insulating layer. And forming a patterned solder resist layer including a second solder resist layer having a thickness smaller than that of the first solder resist layer formed in a region other than the first solder resist layer.

According to the present invention, a solder resist layer having a large thermal expansion coefficient is formed only in the region around the solder ball, and the exposed redistribution layer is protected by using a non-metal oxide layer, thereby minimizing the use of the solder resist layer having a large thermal expansion coefficient to reduce stress generation in the solder ball. Minimize, thereby preventing the problem of weak bonding strength.

In addition, the present invention forms a thin solder resist layer having a high thermal expansion coefficient in a region other than the area around the solder ball, thereby minimizing the use of a solder resist layer having a high thermal expansion coefficient without exposing the redistribution layer, thereby minimizing stress generation in the solder ball. This prevents the problem of weak bonding strength.

In addition, the present invention minimizes the warpage problem of the resulting package by minimizing the use of a solder resist layer having a high coefficient of thermal expansion.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on the other drawings. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a wafer level chip scale package according to a first preferred embodiment of the present invention, FIG. 3 is a cross-sectional view of a wafer level chip scale package according to a second preferred embodiment of the present invention, and FIGS. 2 is a cross-sectional view of each process for explaining a method of manufacturing a wafer level chip scale package illustrated in FIG. 2, and FIGS. 11 to 16 illustrate a method of manufacturing a wafer level chip scale package illustrated in FIG. 3. 17 is a cross-sectional view of each process, and FIGS. 17 to 20 are cross-sectional views of respective processes for describing a manufacturing method according to another exemplary embodiment of the wafer level chip scale package shown in FIG. 3.

2 is a cross-sectional view of a wafer level chip scale package according to a first preferred embodiment of the present invention. Referring to this, a wafer level chip scale package 100 according to a first preferred embodiment of the present invention will be described as follows. .

The wafer level chip scale package 100 according to the present embodiment includes a semiconductor chip 101, a first insulating layer 103, a redistribution layer 104, a non-oxide layer 105, a second insulating layer 107, and a solder ball. (111), and the patterned solder resist layer (110).

The semiconductor chip 101 has a bonding pad 102 electrically connected to the integrated circuit on an upper surface of a chip body of silicon material in which an integrated circuit (not shown) is embedded, and the chip body is exposed to expose the bonding pad 102. The passivation layer is formed on the upper surface of the structure.

Here, the passivation layer is, for example, a thin insulating film, that is, a third insulating film composed of a first insulating film (not shown) made of silicon dioxide (SiO 2), a second insulating film (not shown), and silicon nitride (SiN). It is comprised by the lamination of (not shown), and has high heat resistance and high electrical insulation. The surface of this passivation layer functions as the surface of the semiconductor chip 101.

On the other hand, the bonding pad 102 is made of a metal such as aluminum.

The first insulating layer 103 is to protect the passivation layer and the active surface of the semiconductor chip 101 from heat or mechanical stress generated during the regeneration process. The bonding pad 102 is disposed on the upper surface of the semiconductor chip 101. Is formed to be exposed. Here, the first insulating layer 103 is made of polyimide, epoxy, or the like.

The redistribution layer 104 is used to guide the wiring from the bonding pad 102 formed on the semiconductor chip 101 to another position, and extends from the bonding pad 102 on the first insulating layer 103.

Here, one end of the redistribution layer 104 is connected to the bonding pad 102 and is made of a conductive metal such as aluminum (Al), copper (Cu), nickel (Ni), gold (Au), or the like.

The non-oxide metal layer 105 prevents the redistribution layer 104 from being exposed and oxidized when the solder resist layer is patterned to be formed only around the solder ball 111 in order to reduce the stress generated by the solder resist layer having a high thermal expansion coefficient. At the same time, it is electrically connected to the redistribution layer 104 to guide the wiring from the bonding pad 102 to another position, and is formed on the redistribution layer 104. Here, the non-oxide metal layer 105 is made of a non-oxide conductive metal, for example, gold (Au), silver (Ag), chromium (Cu), is formed by the electroplating on the redistribution layer 104.

In addition, an adhesive auxiliary layer (UBM) 106 is formed at a position corresponding to an extended portion of the redistribution layer 104 of the non-oxide metal layer 105 to be connected to a solder ball or an external connection terminal. Here, the adhesion auxiliary layer (UBM) 106 is to enhance the adhesion between the solder ball 111 and the non-oxide metal layer 105, although shown in Figure 2 can be selectively provided.

The second insulating layer 107 is formed on the first insulating layer 103 so that the non-oxide metal layer 105 and the adhesive auxiliary layer (UBM) 106 are exposed.

The solder ball 111 serves as an externally connected terminal for connecting the semiconductor chip 101 connected to the redistribution layer 104 and the non-oxide metal layer 105 to an external system or an electrically conductive connection terminal connected to another solder ball. In order to do so, it is formed in the adhesion auxiliary layer (UBM) 106 of the non-oxide metal layer 105.

The patterned solder resist layer 110 is to protect the layers formed on the semiconductor chip, and is formed only in the region around the solder ball 111 on the non-oxide layer 105 and the second insulating layer 107. That is, the non-oxide metal layer 105 and the second insulating layer 107 excluding the first open portion 109a exposing the adhesive auxiliary layer UBM 106 to which the solder balls 111 are attached and the region around the solder ball 111. It is patterned to include a second open portion (109b) that exposes.

That is, the wafer level chip scale package 100 according to the present embodiment is formed only in the region around the solder ball 111 necessary for forming the solder ball 111 in order to minimize the use of the solder resist layer having a higher coefficient of thermal expansion than the materials of the other layers. However, by forming a non-oxide metal layer 105 on the upper portion to protect the redistribution layer 104 is exposed because the solder resist layer is not formed to relieve the stress concentrated in the solder ball 111, and to prevent bending of the package.

3 is a cross-sectional view of a wafer level chip scale package according to a second preferred embodiment of the present invention. Referring to this, a wafer level chip scale package 200 according to a second preferred embodiment of the present invention will be described as follows. .

The wafer level chip scale package 200 according to the second preferred embodiment of the present invention has a periphery around the solder ball 111 necessary for forming the solder ball 111 in order to minimize the use of a solder resist layer having a higher coefficient of thermal expansion than other materials. The first embodiment is formed by forming a first solder resist layer 210a having a predetermined thickness in a region, but forming a second solder resist layer 210b having a thickness smaller than that of the first solder resist layer 210a in a region other than the first solder resist layer 210a. As such, it is configured to protect the redistribution layer without forming a separate non-oxidizing metal layer.

Except for this, since there is no significant difference from the wafer level chip scale package 100 according to the first embodiment, a redundant description will be omitted.

4 to 10 are cross-sectional views for each process for describing a method of manufacturing the wafer level chip scale package illustrated in FIG. 2, and a method of manufacturing the wafer level chip scale package 100 according to the present exemplary embodiment will be described with reference to the drawings. Is as follows.

First, as shown in FIG. 4, the first insulating layer 103 is formed on the semiconductor chip 101 to expose the bonding pads 102 of the semiconductor chip 101 at the wafer level.

At this time, the semiconductor chip 101 is formed with a bonding pad 102 electrically connected to the integrated circuit on the upper surface of the chip body of the silicon material having an integrated circuit (not shown), so that the bonding pad 102 is exposed. The passivation layer is formed on the upper surface of the chip body, and the bonding pad 102 and the passivation layer are formed in a fabrication (FAB) process.

Next, as shown in FIG. 5, the redistribution layer 104 is formed. At this time, the redistribution layer 104 is formed to be connected to the bonding pad 102 to extend on the first insulating layer 103.

Next, as shown in FIG. 6, a non-oxide metal layer 105 is formed. At this time, the non-oxide metal layer 105 is formed on the redistribution layer 104 to cover the redistribution layer 104 by electroplating. In addition, an adhesion assistant layer (UBM) 106 is formed on the non-oxide metal layer 105 corresponding to the extended portion of the bonding pad 102. As described above, the adhesion auxiliary layer (UBM) 106 may be selectively provided to reinforce the adhesion between the solder ball 111 and the non-oxide metal layer 105.

Next, as shown in FIG. 7, a second insulating layer 107 is formed. In this case, the second insulating layer 107 is formed on the first insulating layer 103 so that the non-oxide metal layer 105 is exposed.

Next, as shown in FIG. 8, the solder resist layer 108 is formed on the non-oxide metal layer 105 and the second insulating layer 107.

Next, as illustrated in FIG. 9, a second opening 109a exposing the adhesive auxiliary layer UBM 106 includes a second opening exposing an area except the peripheral region of the adhesive auxiliary layer UBM 106. A portion of the solder resist layer is removed to have the open portion 109b to form a patterned solder resist layer 110.

Here, the first open part 109a is formed to connect the solder ball, which is a conductive connection terminal for connecting the semiconductor chip 101 with an external connection terminal or another solder ball to the external system, to the adhesive auxiliary layer 106, The second open portion 109b is formed to prevent stress concentration and bending of the package by removing the solder resist layer having a high coefficient of thermal expansion except for the solder resist layer around the adhesive auxiliary layer (UBM) 106 for solder ball formation. . In this embodiment, since a separate non-oxide layer 105 is formed on the redistribution layer 104 exposed by the second opening 109b, the protection problem of the redistribution layer 104 is also solved.

In addition, the solder resist layer 108 may be removed by etching or laser direct ablation (LDA), and other known methods are also included within the scope of the present invention.

Next, as shown in FIG. 10, the solder ball 111 is attached to the adhesive auxiliary layer (UBM) 106.

By this manufacturing process, the wafer level chip scale package 100 as shown in FIG. 2 is manufactured.

11 to 16 are cross-sectional views of respective processes for describing a manufacturing method according to an exemplary embodiment of the wafer level chip scale package illustrated in FIG. 3, and with reference thereto, the wafer level chip scale package 200 according to the present exemplary embodiment. The manufacturing method of the following is as follows. Here, overlapping descriptions of components identical to or corresponding to those of the wafer level chip scale package 100 according to the first embodiment and a manufacturing process thereof will be omitted.

First, as shown in FIG. 11, the first insulating layer 203 is formed on the semiconductor chip 201 so that the bonding pads 202 of the semiconductor chip 201 are exposed at the wafer level.

Next, as shown in FIG. 12, the redistribution layer 204 is formed. In this case, the redistribution layer 204 is connected to the bonding pad 202 and is formed to extend on the first insulating layer 203, and the adhesive auxiliary layer (UBM) 206 is formed on the extended portion. In this embodiment, a separate adhesive auxiliary layer (UBM; 206) is shown and described as formed on top of the redistribution layer 204, but one end of the redistribution layer 204 without a separate adhesive auxiliary layer (UBM; 206) It may also be possible to perform a function as the adhesion assistant layer (UBM) 206.

Next, as shown in FIG. 13, a second insulating layer 107 is formed. In this case, the second insulating layer 107 is formed on the first insulating layer 203 so that the redistribution layer 204 is exposed.

Next, as shown in FIG. 14, a solder resist layer 208 is formed on the redistribution layer 204 and the second insulating layer 207.

Next, as shown in FIG. 15, the first solder resist formed in the peripheral area of the adhesive auxiliary layer including the first opening 209a exposing the adhesive auxiliary layer 106 by partially removing the solder resist layer 208. The patterned solder resist layer 210 including the second solder resist layer 210b having a thickness smaller than the first solder resist layer 201a formed in the regions other than the layer 210a and the first solder resist layer 210a. To form.

Here, the first open portion 209a is electrically connected to the auxiliary bonding layer 206 by the solder ball 211, which is a conductive connection terminal for connecting the semiconductor chip 101 to an external connection terminal for connecting to an external system or another solder ball. The second solder resist layer 210b is formed to be connected to each other, and the second solder resist layer 210b is formed in the width direction of the solder resist layer having a high coefficient of thermal expansion except for the first solder resist layer 210a in the area around the adhesive auxiliary layer (UBM) 106. It is formed to prevent stress concentration and bending of the package by removing some. In this embodiment, the second solder resist layer 210b protects the redistribution layer 204.

At this time, the solder resist layer 208 may be removed by etching or laser direct ablation (LDA), and other well-known methods are also included within the scope of the present invention.

Next, as shown in FIG. 16, the solder ball 211 is attached to the adhesion auxiliary layer (UBM) 206.

By this manufacturing process, the wafer level chip scale package 200 as shown in FIG. 3 is manufactured.

17 to 20 are cross-sectional views of respective processes for describing a manufacturing method according to another exemplary embodiment of the wafer level chip scale package illustrated in FIG. 3, and with reference thereto, the wafer level chip scale package 200 according to the present exemplary embodiment. The manufacturing method of the following is as follows. The present embodiment proposes another method of forming the patterned solder resist layer 210. For convenience of description, the same reference numerals are used for the same or corresponding components as the manufacturing method according to the embodiment. Detailed descriptions of overlapping portions will be omitted.

First, as shown in FIG. 17, the adhesive assisting layer including the first opening 209a exposing the adhesive assisting layer 206 to the solder resist layer 208 formed by the process of FIGS. 11 to 14. (206) Partially removed so as to have a second open portion 209b exposing a region other than the peripheral region.

Next, as shown in FIG. 18, the second solder resist layer 210b is formed in the second open part 209b to have a thickness smaller than that of the first solder resist layer 210a. Here, the second solder resist layer 210b is formed by spin coating.

Next, as shown in FIG. 19, the wafer level chip scale package 200 as shown in FIG. 3 may be manufactured by attaching the solder balls 211 to the adhesion assistant layer 206.

In the present embodiment, the first open portion 209a and the second open portion 209b are formed in the solder resist layer 208, and the first solder resist layer 210a is formed by spin coating the second open portion 209b. As the second solder resist layer 210b having a smaller thickness is formed, it is difficult to form the solder resist layer 208 at a time so as to have a different thickness as in the first embodiment, or to thereby form a desired thickness difference. Since there may be, it is proposed a method of forming the open portion in a batch and giving a difference in thickness of the solder resist layer.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and a wafer level chip scale package and a method of manufacturing the same according to the present invention are not limited thereto, and within the technical spirit of the present invention. It will be apparent that modifications and improvements are possible by one of ordinary skill in the art.

All simple modifications and variations of the present invention fall within the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the appended claims.

1 is a cross-sectional view of a wafer level chip scale package according to the prior art.

2 is a cross-sectional view of a wafer level chip scale package according to a first preferred embodiment of the present invention.

3 is a cross-sectional view of a wafer level chip scale package according to a second preferred embodiment of the present invention.

4 to 10 are cross-sectional views of respective processes for describing a method of manufacturing the wafer level chip scale package shown in FIG. 2.

11 to 16 are cross-sectional views of respective processes for describing a method of manufacturing a wafer level chip scale package shown in FIG. 3 according to an embodiment.

17 to 20 are cross-sectional views of respective processes for describing a method of manufacturing a wafer level chip scale package according to another embodiment of FIG. 3.

<Description of main parts of drawing>

101, 201: semiconductor chip 102, 202: bonding pad

103, 203: first insulating layer 104, 204: redistribution layer

105: non-oxide metal layer 106, 206: adhesive auxiliary layer

110, 210: solder resist layer 111, 211: solder ball

Claims (16)

A semiconductor chip having a bonding pad formed on an upper surface thereof; A first insulating layer formed to expose the bonding pads on an upper surface of the semiconductor chip; A redistribution layer extending from the bonding pads on the first insulating layer; A non-oxide metal layer formed on the redistribution layer to cover the redistribution layer and having an adhesive auxiliary layer at one end thereof; A second insulating layer formed on the first insulating layer and exposing the non-oxide layer; A solder ball formed on the adhesive auxiliary layer; And Patterned solder resist layer formed only in the area around the solder ball on the non-oxide layer and the second insulating layer Wafer level chip scale package comprising a. The method according to claim 1, The metal oxide layer is a wafer level chip scale package, characterized in that gold (Au), silver (Ag), chromium (Cr). A semiconductor chip having a bonding pad formed on an upper surface thereof; A first insulating layer formed on an upper surface of the semiconductor chip and formed to expose the bonding pads; A redistribution layer extending from the bonding pads on the first insulating layer and having an adhesive auxiliary layer at one end thereof; A second insulating layer formed on the first insulating layer and exposing the redistribution layer; A solder ball formed on the adhesive auxiliary layer of the redistribution layer; And Patterned solder resist layer formed on the redistribution layer and the second insulating layer Including, The patterned solder resist layer may include a first solder resist layer formed in a peripheral area of the adhesive auxiliary layer including an open portion exposing the adhesive auxiliary layer and a portion of the first solder resist layer formed in a region other than the first solder resist layer. A wafer level chip scale package comprising a second solder resist layer having a small thickness. Forming a first insulating layer exposing the bonding pads on the semiconductor chip at the wafer level; Forming a redistribution layer extending from the bonding pads on the first insulating layer; Forming a non-oxidizing metal layer having an adhesive auxiliary layer formed on one end of the redistribution layer; Forming a second insulating layer exposing the metal oxide layer on the first insulating layer; And A second open portion exposing the non-oxide layer and the second insulating layer in a region other than a first open portion exposing the adhesive auxiliary layer and a region around the adhesive auxiliary layer on the non-oxide layer and the second insulating layer Forming a patterned solder resist layer formed only in a region surrounding the adhesion assistant layer to include a portion; Method of manufacturing a wafer level chip scale package comprising a. The method according to claim 4, In the step of forming the non-oxide metal layer, And the non-oxide layer is formed by electroplating. The method according to claim 4, The non-oxide layer is gold (Au), silver (Ag), chromium (Cr) characterized in that the manufacturing method of the wafer level chip scale package. The method according to claim 4, Forming the patterned solder resist layer, Forming a solder resist layer on the non-oxide layer and the second insulating layer; And Removing the solder resist layer to form the first open part and the second open part; Method of manufacturing a wafer level chip scale package comprising a. The method of claim 7, In the forming of the first open portion and the second open portion, And the solder resist layer is removed by laser direct ablation (LDA). The method according to claim 4, After forming the patterned solder resist layer, Forming a solder ball on the adhesive auxiliary layer further comprising the step of manufacturing a wafer level chip scale package. Forming a first insulating layer on the chip at the wafer level to expose the bonding pads; Forming a redistribution layer extending from the bonding pads on the first insulating layer and having an adhesive auxiliary layer at one end thereof; Forming a second insulating layer exposing the redistribution layer on the first insulating layer; And The first solder resist layer formed in a peripheral area of the adhesive auxiliary layer including a first open part exposing the adhesive auxiliary layer on the redistribution layer and the second insulating layer and in a region other than the first solder resist layer; Forming a patterned solder resist layer comprising a second solder resist layer having a thickness less than the first solder resist layer Method of manufacturing a wafer level chip scale package comprising a. The method according to claim 10, Forming the patterned solder resist layer, Forming a solder resist layer on the redistribution layer and the second insulating layer; And Removing the solder resist layer to form the open part and the second solder resist layer; Method of manufacturing a wafer level chip scale package comprising a. The method of claim 11, In the forming of the open portion and the second solder resist layer, And the solder resist layer is removed by etching or laser direct ablation (LDA). The method according to claim 10, Forming the patterned solder resist layer, Forming a solder resist layer on the redistribution layer and the second insulating layer; Removing a portion of the solder resist layer to form a first open portion exposing the adhesive auxiliary layer and a second open portion exposing the redistribution layer and the second insulating layer in an area except the peripheral region of the adhesive auxiliary layer; And Forming a second solder resist layer having a thickness smaller than that of the first solder resist layer formed on the peripheral area of the adhesive auxiliary layer on the second open part; Method of manufacturing a wafer level chip scale package comprising a. 14. The method of claim 13, In the forming of the second open portion, And the solder resist layer is removed by etching or laser direct ablation (LDA). 14. The method of claim 13, In the step of forming the second solder resist layer, And the second solder resist layer is formed by spin coating. The method according to claim 10, After forming the patterned solder resist layer, Forming a solder ball on the adhesive auxiliary layer further comprising the step of manufacturing a wafer level chip scale package.

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