CN104051353A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN104051353A
CN104051353A CN201310349227.2A CN201310349227A CN104051353A CN 104051353 A CN104051353 A CN 104051353A CN 201310349227 A CN201310349227 A CN 201310349227A CN 104051353 A CN104051353 A CN 104051353A
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CN
China
Prior art keywords
resin
semiconductor chip
semiconductor device
wiring layer
spring rate
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Granted
Application number
CN201310349227.2A
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Chinese (zh)
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CN104051353B (en
Inventor
本间庄一
松浦永悟
志摩真也
向田秀子
青木秀夫
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Publication of CN104051353A publication Critical patent/CN104051353A/en
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Publication of CN104051353B publication Critical patent/CN104051353B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device which is high in reliability and does not rupture even in a TCT. The semiconductor device comprises a semiconductor chip (1). a first resin (2), a second resin (3), a wiring layer (4), an external connector (5) and a metal plate (6). The semiconductor chip (1) is embedded into the first resin (2) in a manner that the surface of the semiconductor chip (1) is exposed; the second resin (3) is formed on the face of the first resin (2) which is arranged on the plane being the same as the surface of the semiconductor chip (1); the wiring layer (4) is formed on the second resin (3) and is electrically connected with the semiconductor chip (1); the external connector (5) is formed on the wiring layer (4); and the metal plate (6) is formed on the surface, of the first resin (2), being on the reverse side being opposite to the surface where the semiconductor chip (1) is embedded. The modulus of elasticity of the first resin (2) is in a ranged from 0.5GPa to 5GPa.

Description

Semiconductor device
The application is taking Japanese patent application No. 2013-51947 (applying date: on March 14th, 2013) as basis and enjoy its priority.The application is by comprising its full content with reference to this earlier application.
Technical field
The present invention relates to semiconductor chip to be configured to again the semiconductor device of fan-out wafer-level chip scale package (WLCSP) structure connecting up again.
Background technology
In the past, disclosed semiconductor chip had been configured on supporting substrate again, then the semiconductor device technology of the fan-out WLCSP structure connecting up again.In this technology, there is following problem.
In semiconductor device, in the situation that carrying out temperature cycling test (TCT), likely crack and occur broken string at wiring layer again.In addition, the insulating resin that is formed at again wiring layer in TCT cracks, and crackle is along with the circulation of TCT increases and expands.
At semiconductor chip be formed between the moulded resin in its outside across ground configuration solder ball, in TCT, produce stress at solder ball, there is more crackly problem.
If the semiconductor chip thickness in encapsulation increases, in the time of TCT, there is crooked increase that bight solder ball produces and crackly problem.
Summary of the invention
The object of an embodiment of the invention is to provide has long-term TCT life-span and the high semiconductor device of reliability.
According to an embodiment of the invention, a kind of semiconductor device, has: semiconductor chip; The first resin, it exposes the surface of described semiconductor chip and imbeds described semiconductor chip; The second resin, its be positioned at the surperficial the same face of described semiconductor chip on the face of described the first resin on form; Wiring layer, it is formed on described the second resin and with described semiconductor chip and is electrically connected; External connection terminals, it is formed on described wiring layer; And metallic plate, its face in the relative opposition side of the face with imbedding described semiconductor chip of described the first resin forms, and this semiconductor device is characterised in that, and the spring rate of described the first resin is 0.5～5GPa.
Brief description of the drawings
Fig. 1 is the figure that schematically represents the formation of the semiconductor device of the first execution mode, (a) is vertical view, is (b) the A-A cutaway view of (a).
Fig. 2 is the figure that represents the result of simulating, and is (a) figure that represents the result of the simulation of the stress that acts on wiring layer, is (b) figure that represents to carry out about the result of the simulation in TCT life-span.
Fig. 3-1st, represents the figure of the result of the variation of the distortion situation of observing the chip size of semiconductor chip and the solder ball of marginal portion.
Fig. 3-2nd, represents the figure of the stress state of the solder ball of the part in the close bight under chip.
Fig. 3-3rd, represents that close conduct does not have the figure of the stress state of the solder ball of the part in the encapsulation bight in the region of chip.
Fig. 3-4th, represents the figure of the semiconductor device of the state of solder balls deform.
Fig. 4 is the figure that represents to obtain the crooked result of the solder ball in the situation that makes the variation of chip thickness/plate thickness.
Fig. 5-1st, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-2nd, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-3rd, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-4th, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-5th, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-6th, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-7th, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 5-8th, represents the figure of the manufacturing process of the semiconductor device of the first execution mode.
Fig. 6 is the cutaway view that schematically represents the formation of the semiconductor device of the second execution mode.
Fig. 7-1st, represents the figure of the manufacturing process of the semiconductor device of the second execution mode.
Fig. 7-2nd, represents the figure of the manufacturing process of the semiconductor device of the second execution mode.
Fig. 7-3rd, represents the figure of the manufacturing process of the semiconductor device of the second execution mode.
Fig. 7-4th, represents the figure of the manufacturing process of the semiconductor device of the second execution mode.
Fig. 7-5th, represents the figure of the manufacturing process of the semiconductor device of the second execution mode.
Description of reference numerals:
1 semiconductor chip 2 first resin 3 resin beds 4 are wiring layer 5 external connection terminals 6 metallic plates 7 the 4th resin bed 10 silicon substrate 11 passivating films (dielectric film) 31 first opening 32 second resin bed 41 wiring layers 42 the 3rd resin bed 43 second opening 51 substrate layer 52 solder ball D, L line of cut again
Embodiment
Describe with reference to the accompanying drawings semiconductor device and manufacture method thereof that execution mode relates in detail.Have again, the invention is not restricted to these execution modes.In addition, in accompanying drawing shown below, for the ease of understanding, and there is the engineer's scale of each parts and actual different situations, represent that the term of direction represents taking the lower relative direction as benchmark as positive direction situation by the mark on accompanying drawing up and down.
The first execution mode
Fig. 1 (a) is the vertical view that schematically represents the formation of the semiconductor device of the first execution mode, and Fig. 1 (b) is the A-A cutaway view of (a).This semiconductor device is the semiconductor device of fan-out wafer-level chip scale package (WLCSP) structure, it is characterized in that, making the spring rate of the first resin 2 of imbedding semiconductor chip 1 is 2.0GPa, and to make coefficient of thermal expansion be 45ppm.This semiconductor device possesses: the first resin 2 of ground embedded with semi-conductor chip 1 is exposed on the surface of semiconductor chip 1; In with the surperficial the same face of this semiconductor chip 1 on the second resin 3 of forming of the surface of the first resin 2; The wiring layer again 4 that forms and be electrically connected with semiconductor chip 1 on the second resin 3; With the external connection terminals 5 forming on wiring layer 4 again.And, have the opposition side relative at the face 2A with imbedding semiconductor chip of the first resin 2 face 2B form metallic plate 7.The first resin 2 uses for example epoxy resin.
And the second resin 3 forming on semiconductor chip 1 is second resin beds 32 with the first opening 31.The second resin bed 32 uses for example polyimide resin.And, on this second resin 3, form again wiring layer 4.Wiring layer 4 has again: the wiring layer 41 contacting with semiconductor chip 1; With cover the upper strata of wiring layer 41 and possess the 3rd resin bed 42 of the second opening 43.Be formed with external connection terminals 5 on the upper strata of wiring layer again.External connection terminals 5 possesses: the substrate layer (UBM) 51 being connected with wiring layer 41 through the second opening 43 of forming at the 3rd resin bed 42; With the solder ball 52 forming on this substrate layer 51.The 3rd resin bed 42 is equivalent to the 3rd resin.Present embodiment is the semiconductor device being specially adapted to locate in the outer part the so-called fan-out WLCSP that is formed with external connection terminals 5 than the edge of semiconductor chip 1.
According to the semiconductor device of present embodiment, in the situation that carrying out temperature cycling test (TCT), then wiring layer 4 also there will be crackle hardly and splits (open).Have again, at semiconductor chip 1 and be formed at the first resin 2(moulded resin in outside) between across ground configuration solder ball 52, in TCT, also can produce stress, break at solder ball hardly.In addition, in the case of encapsulation in semiconductor chip thickness increase, in the time of TCT bight solder ball produce crooked also can increasing hardly and break.As shown in table 1, be 0.5～5GPa at the spring rate that makes the first resin 2, making thermal coefficient of expansion is 30～150ppm, while making the spring rate of second and third resin bed 32,42 be 0.5～5GPa, in experimental result, can not crack or produce stress at solder ball at wiring layer again, can obtain the semiconductor device that reliability is high.
Table 1
? Comparative example Present embodiment
The first resin spring rate 0.1GPa 0.5～5GPa
The first resin thermal coefficient of expansion 173ppm 30～150ppm
Second and third resin spring rate 0.1GPa 0.5～5GPa
On the other hand, the material shown in the left side of comparative example use table 1., to make the spring rate of the first resin 2 be 0.1GPa, making thermal coefficient of expansion is 173ppm, the spring rate that makes second and third resin bed 32,42 is 0.1GPa.In the case of this semiconductor device is in the past carried out TCT, because the distortion of wiring layer or the generation of crackle have occurred to split bad again.In addition, crack at second and third resin bed 32,42 as insulating resin using in order to form again wiring layer in TCT, crackle is along with the circulation of TCT increases and expands.Have again, between the first resin (moulded resin) 2 at semiconductor chip 1 and outside being formed at, dispose solder ball 52 across ground, in TCT, produce stress and break at solder ball 52.In addition,, when the thickness of the semiconductor chip 1 in the first resin 2 that forms encapsulation carries out TCT while increase, the solder ball 5c(existing in encapsulation bight is with reference to Fig. 1 (a)) the crooked increase that produces and the situation of breaking.
Secondly, Fig. 2 (a) represents to act on connect up the again result of simulation of stress of (RDL) of Cu.Vertical pivot represents the relative relative value of stress of breaking with Cu.La represents that relative value is 1 line.At relative value (the region R that exceedes at 1 o'clock nG), mean that Cu breaks.Be region (the region R below 1 in relative value oK), Cu does not break.S represents the situation of comparative example (present situation).Describe the thermal coefficient of expansion of the first resin at transverse axis, and described the situation of the spring rate that changes the first resin.At the stress hour breaking than Cu, the thermal coefficient of expansion that need to make the first resin is below 150ppm, and it is more than 0.5GPa making spring rate.Fig. 2 (b) represents the result of the simulation in the TCT life-span of carrying out solder ball.TCT life-span when vertical pivot is illustrated in, on installation base plate, fan-out WLCSP is installed, the relative value of the situation to produce 1% waste products with respect to-25 DEG C/125 DEG C, 1000 circulations of representing in the situation of benchmark.Lb represents that relative value is 1 line, is region (the region R below 1 in relative value nG) TCT life-span deficiency.Be more than 1 region (region R in relative value oK) the TCT life-span is enough.S represents the situation of comparative example.Transverse axis is described the thermal coefficient of expansion of the first resin, and describes the situation of the spring rate that changes the first resin.In the time meeting TCT life-span, it is more than 30ppm need to making thermal coefficient of expansion, and making spring rate is below 5GPa.
Secondly, Fig. 3-1 represents the figure of the result of the variation of the distortion situation (deformation) of the solder ball 5p of the marginal portion of observing semiconductor chip 1.Here, chip size is respectively the product of 2.0mm on one side, on one side the product of 2.35mm, the on one side product of 2.50mm and the product of one side 2.65mm.
Solder ball 5p that for example, record in the center of the first row, chip size marginal portion while being 2.0mm on one side square, semiconductor chip 1 is out of shape hardly.This is the situation of present embodiment 1, and the spring rate of the first resin 2 is 2GPa, and thermal coefficient of expansion is 45ppm.In contrast, the spring rate of first resin 2 of existing (present situation) is that in the situation of example in 0.1GPa, the thermal coefficient of expansion the first row left side that is 170ppm, the solder ball 5p distortion of the marginal portion of semiconductor chip 1 is larger.In addition, the spring rate of the first resin 2 is that in the situation of example on 24GPa, the thermal coefficient of expansion the first row right side that is 8ppm, the solder ball 5p of the marginal portion of semiconductor chip 1 is out of shape hardly.Although it is not shown,, the example that is 24GPa, the thermal coefficient of expansion the first row right side that is 8ppm at the spring rate of the first resin 2, sometimes produce bending at semiconductor device self.
Like this, although in each line display semiconductor chip of Fig. 3-1 and the distortion situation of solder ball,, according to the chip size of semiconductor chip, and make the marginal portion of semiconductor chip 1 different with the position relationship of solder ball.Like this, obtain the solder ball 5p(of marginal portion of semiconductor chip 1 with reference to Fig. 1 (a)) crooked result, known, be that 2GPa, thermal coefficient of expansion are 45ppm by making the spring rate of the first resin 2, and make the crooked minimizing of solder ball.
Secondly, be the result of sharing stress (シ ェ ア ス ト レ ス) of the effect of the hole at wiring layer the spring rate of obtaining in the case of changing second and third resin.As shown in Fig. 3-2, known, the stress of the solder ball 5p of the part in the close bight under chip is larger in the time that the spring rate of second and third resin 32,42 is 0.1GPa, less in the time that spring rate is 3.5GPa.In contrast, as shown in Fig. 3-3, known, near substantially identical in the time that the spring rate of second and third resin 32,42 is 0.1GPa, 3.5GPa as there is no the stress of solder ball 5c in encapsulation bight in region of chip.
As shown in Fig. 3-2, the stress of the solder ball 5p of the part in the close bight under chip is large, as represented an example in Fig. 3-4, produce distortion at second and third resin 32,42, wiring layer 41 is noncontact with substrate layer 51.Its result, the wiring layer 41 being connected with semiconductor chip produces bad connection to solder ball 52.In Fig. 3-2 and Fig. 3-3, represented to be formed with structure 1(two-layer) the situation of second and third resin 32,42 and tri-layers of structure 2() the situation that is also formed with wiring layer and the 4th resin bed on second and third resin 32,42 be that resin bed is the situation of three layers.
Secondly, in Fig. 4, represent to obtain the result of the non-linear quite crooked amplitude (the quite askew body amplitude of non-Line shape) of the solder ball 52 make like that chip thickness/plate thickness change in the situation that as shown in table 2.The joint life-span of scolder and non-linear quite crooked amplitude are inversely proportional, therefore at non-linear quite crooked amplitude hour life.Vertical pivot represents the non-linear quite crooked amplitude of solder bonds portion, and transverse axis represents chip thickness/plate thickness.A represents the result of the non-linear quite crooked amplitude of describing bight solder ball, and b represents to describe the poorest (ワ ー ス ト) result of the non-linear quite crooked amplitude of solder ball.From this result, be below 4 by making chip thickness/plate thickness, and make respectively the crooked amplitude of a and b be reduced to below 10%, then have, by being below 2, and make respectively the crooked amplitude of a and b be further reduced to below 7%, solder bonds life.Therefore, be, below 4, to be preferably below 2 by making chip thickness/plate thickness, and can realize the prolongation of scolder connection lifetime.
Table 2
Chip thickness 125 365 525 600
Plate thickness 600 360 200 125
Chip thickness/plate thickness 0.21 1.0 2.6 4.8
Secondly, the manufacturing process of the semiconductor device of the first execution mode is described with reference to Fig. 5-1 to Fig. 5-8.First, prepare the semiconductor wafer of 12 inches.Be formed with Al pad at semiconductor wafer with 100 μ m spacing.By the back side cutting of semiconductor wafer, cut that to be as thin as 100 μ m thick.Cut again, become monolithic.The semiconductor chip 1 use chip mounter of producing is as described above disposed at again to the bond layer (not shown) upper (Fig. 5-1) forming on the first supporting bracket S1.Have, semiconductor chip 1 is formed with the passivating films such as SiN 11 on the surface of silicon substrate 10 again.Have again, can on passivating film, form the organic films such as polyimides.Here as the first supporting bracket S1, use Si, glass, sapphire plate, printed base plate, metallic plate etc..The thickness of the first supporting bracket S1 is 0.3～2mm.As bonding agent, the resin that use thermoplastic resin, thermosetting resin, PET material, energy thermal expansion are peeled off etc.For example, polyimide resin, allyl resin, epoxy resin, polyamide etc.Bonding agent can be aqueous, can be also flaky substance.Used thickness is the product below the above 200 μ m of 10 μ m.Than 10 μ m when thin, cementability weak effect, in the time exceeding 200 μ m, becomes blocked up and flatness is worsened.
Secondly,, as shown in Fig. 5-2, on the first supporting bracket S1, apply the first resin 2.In the time of coating, the print process of the die casting of applicable use mould, use printing mask etc.Now, the spring rate of the first resin 2 is below the above 5GPa of 0.5GPa.When the discontented 0.5GPa of spring rate, as shown in Figure 2 (a) shows, there is the problem that cracks or wiring layer fracture occurs in TCT.In the time that spring rate exceedes 5GPa, as shown in Fig. 2 (b), there is following problem: the TCT life-span of the scolder connecting portion in the situation that of installation worsens on installation base plate, or bending increase, or the mobile difficulty that becomes, then, bending in situation about encapsulating increases, and can not meet product design.Have, below the thermal coefficient of expansion that makes the first resin is 30 above 150ppm time, reliability further improves again.When the discontented 30ppm of thermal coefficient of expansion, as shown in Fig. 2 (b), there is following problem: the TCT life-span of the scolder connecting portion in the situation that of installation worsens on installation base plate, or in resin, need to put into more filler, therefore spring rate increases, and such bending increase as noted above.In the time that thermal coefficient of expansion exceedes 150ppm, as shown in Figure 2 (a) shows, in TCT, crack at resin, or wiring layer fracture.As the example of the first resin, use enhancing film (PVC Le De ア ッ プ Off ィ Le system), the epoxy resin of sheet etc. of the aqueous resins such as epoxy resin, silicones, epoxy/silicon hybrid resin, allyl resin, polyimide resin, polyamide, phenolic resin or sheet.The thickness of the first resin is that 100 μ m are in 1mm.With chip thickness relatively, be difficult to protect chip when thin at the Thickness Ratio 100 μ m of the first resin.In the time that the thickness of the first resin exceedes 1mm, the bending of resin increases.
Secondly,, as shown in Fig. 5-3, on the first resin 2, form metallic plate 6.As metallic plate, use Cu, Ni, Fe or for example 42 alloys of its composite material etc.The thickness of metallic plate 6 is below the above 500 μ m of 50 μ m.Form metallic plate 6 in order to suppress the bending of encapsulation, still, in the time of the discontented 50 μ m of thickness, effect is little, and in the time exceeding 500 μ m, package thickness becomes large.The formation of metallic plate 6 is by being close to and having adhered by laminated metal sheet 6 when semi-harden at the first resin 2.Or, also can be on the first resin 2 again adhesive-applying paste metallic plate 6.Except metallic plate, also can use resin that spring rate is high, silicon, glass etc.
Secondly,, as shown in Fig. 5-4, peel off the first resin 2 from the first supporting bracket S1.In the case of using the bonding agent a little less than adhibit quality, between the first supporting bracket S1 and the first resin 2, insert the instrument etc. of cutter shape and peel off.In the situation that using thermoplastic resin, peel off to face and the first supporting bracket S1 heating edge of metallic plate 6 on limit.In the case of using the bonding agent of thermal expansion, can similarly by heating, bonding agent be peeled off.In order to expose the surface of semiconductor chip 1, in the situation that being attached with resin, remove with solvent etc.
Secondly,, as shown in Fig. 5-5, use bonding agent (not shown) to paste the second supporting bracket S2.As the second supporting bracket S2, same with the first supporting bracket S1, use Si substrate, glass substrate, sapphire substrate, printed base plate, metallic plate etc.Thickness is 0.3 below 2mm.As bonding agent, the resin that use thermoplastic resin, thermosetting resin, PET resin, energy thermal expansion are peeled off etc.For example, use polyimide resin, allyl resin, epoxy resin, polyamide.Bonding agent can be aqueous, can be also flaky substance.Used thickness is the product below the above 200 μ m of 10 μ m.But, in the state of Fig. 5-4 rigidity high, also non-sticking subsides the second supporter S2.
Secondly, on semiconductor chip 1, form the second resin bed 32.The thickness of the second resin bed 32 is below the above 20 μ m of 2 μ m.As resin material, use polyimides system, epoxy system, silicon system, epoxy/silicon system, propylene system, phenol system, polyamide-based etc.The spring rate that makes the second resin bed 32 is below the above 5GPa of 0.5Pa.In the time of the discontented 0.5GPa of spring rate, in TCT, crack or wiring layer occurs at resin and rupture.In the time that spring rate exceedes 5GPa, resin hardens, bending increase.The second resin bed 32 uses photosensitive material and forms alignedly the first opening 31 with the Al pad locations of semiconductor chip 1.By exposure phenomenon, and form for example opening of 50 μ m diameters.Secondly, become the metal film of wiring layer 41 in whole formation of the second resin bed 32.The formation such as sputtering method, vapour deposition method, galvanoplastic for metal film.As metal film, use the materials such as Ti/Cu.It is thick that Ti is formed as 0.03～0.5 μ m, and it is thick that Cu is formed as 0.1～1.0 μ m.As the metal beyond Ti/Cu, use the materials such as Cr, TiN, Ni, Au, Pd.
Secondly, the resist of coating 10 μ m left and right, and leave opening.For example, form the opening of L/S=50/50 μ m.Form the Cu of 1～15 μ m thickness by plating at opening portion.This time, form for example thick Cu of 5 μ m.Peel off resist, and the Cu of etching Seed Layer and Ti.As the etching solution of Cu, use sulfuric acid and H 2o 2the material mixing, the etching solution of Ti uses to HF and H 2o 2add the material of KOH etc.In the wiring again of Cu, apply the 3rd resin bed 42, and form the second opening 43 that solder ball is used.The 3rd resin bed 42 can be the resin identical with the second resin bed 32.The spring rate of the 3rd resin bed 42 is below the above 5GPa of 0.5GPa.In the time of the discontented 0.5GPa of spring rate, in TCT, crack or wiring layer occurs at resin and rupture.In the time that spring rate exceedes 5GPa, resin hardens, bending increase.
Secondly, as shown in Fig. 5-6, the 3rd resin bed 42 opening portion form substrate layer (UBM) 51.First, form metal film whole of the 3rd resin bed 42.Metal film is by formation such as sputtering method, vapour deposition method, galvanoplastic.As metal film, with material formation such as Ti/Cu.It is thick that Ti is formed as 0.03～0.5 μ m, and it is thick that Cu is formed as 0.1～1.0 μ m.As the metal beyond Ti/Cu, use the materials such as Cr, TiN, Ni, Au, Pd.Secondly, the resist of coating 10 μ m left and right, and leave for example the second opening 43 of 400 μ m diameters.Form Cu/Ni/Au etc. at this opening by galvanoplastic.Cu is formed as 2 μ m, and Au is formed as 0.3 μ m.Peel off resist, and the Cu of etching Seed Layer and Ti.As the etching solution of Cu, use sulfuric acid and H 2o 2the material mixing, the etching solution of Ti uses to HF and H 2o 2add the material of KOH etc.
Have again, in the present embodiment, although illustrate again the situation that wiring is connected up for one deck,, also can form two-layer more than.In this situation, then repeat to form second, third resin bed, and form wiring layer again.In addition, also can be by first forming the second resin on semiconductor wafer, form again again the product cutting of wiring layer and be disposed at again on the bond layer forming on the first supporting bracket S1 to carry out same processing.
Secondly, carry solder ball 52(Fig. 5-7 apply solder flux on substrate layer 51 after).Solder ball 52 uses the Pb-free solder such as SnAg, SnAgCu.Secondly, enter reverberatory furnace and make melt solder balls, and engage with substrate layer 51.Then, solder flux is cleaned to remove by solvent and pure water.
In addition, in the present embodiment, the situation that forms substrate layer 51 has been described, still, certainly also can formed substrate layer 51 and carry solder ball at the second opening 43, and wiring layer and solder ball are engaged.
Secondly, encapsulate cutting along line of cut D, L with cutting machine, become monolithic, thereby complete fan-out WLCSP(Fig. 5-8).
In the time of the TCT that the fan-out WLCSP making is as described above carried out to-55 DEG C/125 DEG C, even through 2000 circulations, there is not the fracture of wiring layer and/or the crackle of insulating barrier (from the first resin to the three resins) yet.In addition,, after installation, in the time of the TCT that carries out-25 DEG C/125 DEG C, even through 1000 circulations, there is not breaking of solder ball yet.
In addition, in the present embodiment, illustrated and used solder ball to be used as the example of external connection terminals, still, also applicable to the product of external connection terminals with other structures such as earthing type (ラ Application De タ イ プ) external connection terminals.
The second execution mode
Fig. 6 is the cutaway view that schematically represents the formation of the semiconductor device of the second execution mode.The difference of the semiconductor device of the first execution mode shown in the semiconductor device of the second execution mode and Fig. 1 (a) and Fig. 1 (b) is the outer rim of metallic plate 6.The outer rim that, arrives semiconductor device with respect to metallic plate 6 the first resin 2 outer rim and outer rim is cut alignedly, in the present embodiment, compared with the outer rim of the outer rim of metallic plate 6 and the first resin 2, in inner side, and the back side is covered with the 4th resin 7.Other structures are identical with above-mentioned the first execution mode, and therefore here description thereof is omitted., on metallic plate 6, form the first resin 2, and imbedded semiconductor chip 1 in this first resin 2.And, also on the second resin bed 32 being formed on semiconductor chip 1, form wiring layer again, and form the 3rd resin bed 42 on the second resin bed 32, and form solder ball 52.In addition, metallic plate 6 is formed as the left and right than the little 50 μ m of package dimension～1mm, and on metal plate, is formed with the 4th resin bed 7.
Secondly, the manufacturing process of the semiconductor device of the second execution mode is described with reference to Fig. 7-1 to Fig. 7-5.In the present embodiment, until all similarly implement with the first execution mode Fig. 5-6 of the first execution mode, therefore, here description thereof is omitted.In the above-described first embodiment, as shown in Fig. 5-6, form after substrate layer (UBM) 51 second supporting bracket S2(Fig. 7-1 of peeling off rear side at the opening portion of the 3rd resin bed 42).In the case of using the bonding agent a little less than adhibit quality, between the second supporting bracket S2 and the first resin 2, insert the instrument etc. of cutter shape and peel off.In the situation that using thermoplastic resin, peel off to face and the second supporting bracket S2 heating edge of metallic plate 6 on limit.In the case of using the bonding agent of thermal expansion, can similarly by heating, bonding agent be peeled off.In order to expose the surface of metallic plate 6, in the situation that being attached with resin, remove with solvent etc.
Secondly, etching metal plate 6(Fig. 7-2).Form resist (not shown) at metallic plate 6, and carry out exposure imaging by photoetching and form cancellate opening.The metallic plate 6 of the part of then, etching clathrate opening.Cancellate opening is 100 μ m～2mm.After etching, peel off resist.Metallic plate 6 can with blade clathrate remove, or also can describe clathrate with laser and remove.
Secondly, on metallic plate 6, form the 4th resin bed 7(Fig. 7-3).In the time of the formation of the 4th resin bed 7, can use spin-coating method, also can use print process.The 4th resin bed 7 can be aqueous, the material on also can adhesive film.Have again, also can not form the 4th resin bed 7.
Secondly, use bonding agent on the 4th resin bed 7, to paste the 3rd supporting bracket S3.On substrate layer 51, apply after solder flux, carry solder ball 52(Fig. 7-4).Solder ball 52 uses the Pb-free solder such as SnAg, SnAgCu.Secondly, enter reverberatory furnace solder ball 52 is melted, and engage with substrate layer 51.Then, solder flux is cleaned to remove by solvent and pure water.Although the description of forming the situation of substrate layer 51, still, certainly also can not form substrate layer 51 and carry solder ball at the 3rd opening 43, and wiring layer 41 and solder ball 52 are engaged.
Secondly, the part of metallic plate 6 opening by etching is cut as line of cut D, L with cutting machine, become monolithic, thereby complete fan-out WLCSP(Fig. 7-5).
In the above-described first embodiment, metallic plate 6 and the first resin 2 are together cut, still, because the impact of cutting likely makes metallic plate 6 and the first resin 2 peel off.The second execution mode is following processing: for fear of this phenomenon and first etching metal plate 6 to form in advance groove near line of cut D, L, and etching the first resin 2 only.
In the time of the TCT that the fan-out WLCSP making is as described above carried out to-55 DEG C/125 DEG C, even through 2000 circulations, there is not the fracture of wiring layer and/or the crackle of insulating barrier (the second resin and the 3rd resin) yet.In addition,, after installation, in the time of the TCT that carries out-25 DEG C/125 DEG C, even through 1000 circulations, there is not breaking of solder ball yet.Here, the second resin comprises second and third resin bed, the second resin bed or the 3rd resin bed both to maintain spring rate be 0.5～5GP, still, but also any to maintain spring rate be 0.5～5GP.
As mentioned above,
(1) be that 0.5～5GPa and connecting up in TCT does not rupture by making the spring rate of the first resin, and do not crack at insulating barrier.Having, is also effective 0.5～5GPa in the case of only making the spring rate of the first resin again.
(2) be that 30～150ppm and connecting up in TCT does not rupture by making the thermal coefficient of expansion of the first resin, and do not crack at second and third resin bed (insulating barrier) or the first resin.
(3) be that 0.5～5GPa and connecting up in TCT does not rupture by making to comprise second and third resin bed at the spring rate of the second interior resin, and do not crack at insulating barrier.
(4) be that 0.5～5GPa, thermal coefficient of expansion are 30～150ppm by making the spring rate of the first resin, and to make the spring rate of the second resin be 0.5～5GPa, do not rupture and obtain connecting up in TCT, and the effect not cracking at insulating barrier.
(5) in (1) to (4), be, below 4, not rupture and obtain connecting up in TCT by the ratio of chip thickness/plate thickness, and the effect not cracking at insulating barrier.
Although the description of several execution modes of the present invention, but these execution modes are only for illustrating, and are not intended to limit scope of invention.These novel execution modes can be implemented with other variety of ways, not departing from the scope of inventive concept, can carry out various omissions, replacement, change.These execution modes and distortion thereof are contained in the scope and spirit of the present invention, and are contained in the scope equal with the invention of recording in the scope of request protection.

Claims (6)

1. a semiconductor device, has:
Semiconductor chip;
The first resin, it exposes the surface of described semiconductor chip and imbeds described semiconductor chip;
The second resin, its be positioned at the surperficial the same face of described semiconductor chip on the face of described the first resin on form;
Wiring layer, it is formed on described the second resin and with described semiconductor chip and is electrically connected;
External connection terminals, it is formed on described wiring layer; With
Metallic plate, its face in the relative opposition side of the face with imbedding described semiconductor chip of described the first resin forms,
This semiconductor device is characterised in that,
The spring rate of described the first resin is 0.5～5GPa, and thermal coefficient of expansion is 30～150ppm,
The spring rate of described the second resin is 0.5～5GPa,
The ratio of the chip thickness/plate thickness of described semiconductor chip is below 4.
2. a semiconductor device, has:
Semiconductor chip;
The first resin, it exposes the surface of described semiconductor chip and imbeds described semiconductor chip;
The second resin, its be positioned at the surperficial the same face of described semiconductor chip on the face of described the first resin on form;
Wiring layer, it is formed on described the second resin and with described semiconductor chip and is electrically connected;
External connection terminals, it is formed on described wiring layer; With
Metallic plate, its face in the relative opposition side of the face with imbedding described semiconductor chip of described the first resin forms,
This semiconductor device is characterised in that,
The spring rate of described the first resin is 0.5～5GPa.
3. semiconductor device according to claim 2, is characterized in that,
The spring rate of described the second resin is 0.5～5GPa.
4. according to the semiconductor device described in claim 2 or 3, it is characterized in that,
The thermal coefficient of expansion of described the first resin is 30～150ppm.
5. according to the semiconductor device described in claim 2 or 3, it is characterized in that,
The ratio of the chip thickness/plate thickness of described semiconductor chip is below 4.
6. a semiconductor device, has:
Semiconductor chip;
The first resin, it exposes the surface of described semiconductor chip and imbeds described semiconductor chip;
The second resin, its be positioned at the surperficial the same face of described semiconductor chip on the face of described the first resin on form;
Wiring layer, it is formed on described the second resin and with described semiconductor chip and is electrically connected;
Solder ball, it is formed on described wiring layer; With
Metallic plate, its face in the relative opposition side of the face with imbedding described semiconductor chip of described the first resin forms,
This semiconductor device is characterised in that,
The spring rate of described the second resin is 0.5～5GPa.
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