CN107403784B - Circuit board manufacturing method and structure - Google Patents
Circuit board manufacturing method and structure Download PDFInfo
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- CN107403784B CN107403784B CN201610335268.XA CN201610335268A CN107403784B CN 107403784 B CN107403784 B CN 107403784B CN 201610335268 A CN201610335268 A CN 201610335268A CN 107403784 B CN107403784 B CN 107403784B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to and provides a circuit board manufacturing method and a structure, comprising the following steps: the chip is arranged on the circuit substrate, chip pins are arranged on the chip, circuit pins are arranged on the circuit substrate, anisotropic conductive adhesive is arranged between the chip and the circuit substrate, and the chip pins are butted with the circuit pins through the anisotropic conductive adhesive; the packaging layer covers the chip, and the packaging layer and the circuit substrate surround the chip. The circuit board can be very thin, and meanwhile, the circuit board is prevented from deforming, and the performance of the circuit board is guaranteed.
Description
Technical Field
The invention belongs to the field of electronics, and particularly relates to a circuit board manufacturing method and a circuit board structure.
Background
Usually, a plurality of chips are mounted on a circuit substrate to form a circuit board, when the circuit board works, the heat productivity of the chips and the heat productivity of the circuit substrate are different, the area of the chips is smaller than that of the circuit substrate, and the chips and the circuit substrate are made of different materials commonly used, so that the chips and the circuit substrate are uneven in expansion with heat and contraction with cold after heating, the chips are easy to deform (when the environmental temperature of the circuit board changes, the circuit board may also deform), and the performance of the circuit board is affected. The smaller the thickness of the circuit board is, the more easily the circuit board is deformed, even distorted and wrinkled, and the influence on the performance of the chip is bad. The deformation of the circuit board makes the circuit board thick, which restricts the development of the circuit board to be light, thin and flexible.
Disclosure of Invention
Based on this, the invention provides a method and a device for ensuring the manufacture of a circuit board, which can obtain a very thin circuit board, prevent the circuit board from deforming and ensure the performance of the circuit board.
The technical scheme is as follows:
a circuit board manufacturing method comprises the following steps: the chip is arranged on the circuit substrate, chip pins are arranged on the chip, circuit pins are arranged on the circuit substrate, anisotropic conductive adhesive is arranged between the chip and the circuit substrate, and the chip pins are butted with the circuit pins through the anisotropic conductive adhesive; the packaging layer covers the chip, and the packaging layer and the circuit substrate surround the chip.
In one embodiment, the cross-sectional size of the packaging layer or/and the circuit substrate is selected according to a stress counteracting condition; wherein the stress counteracting condition is as follows: on the section where the packaging layer and the circuit substrate are stacked, the cross section of the packaging layer and the cross section of the circuit substrate meet the following conditions: when the temperature changes in the working temperature range of the chip, the stress generated on the cross section of the packaging layer due to thermal expansion and cold contraction of the packaging layer is correspondingly offset with the stress generated on the cross section of the circuit substrate due to thermal expansion and cold contraction of the circuit substrate.
In one embodiment, the method for manufacturing a circuit board further includes: and installing independent contact pins on the circuit substrate, enabling the circuit substrate to be positioned between the independent contact pins and the chip, arranging through holes on the circuit substrate, and electrically connecting the chip pins with the independent contact pins through the through holes.
In one embodiment, the number of the chips is at least two, the number of the packaging layers is at least two, each packaging layer at least covers one chip, and a bending gap is arranged between the two packaging layers.
In one embodiment, the circuit substrate is made of a flexible material.
A circuit board structure comprising: the circuit board is provided with circuit pins; an anisotropic conductive adhesive; the chip is provided with a chip pin; a packaging layer; the chip is arranged on the circuit substrate, the anisotropic conductive adhesive is arranged between the circuit substrate and the chip, and the chip pins are butted with the circuit pins through the anisotropic conductive adhesive; the packaging layer covers the chip, and the packaging layer and the circuit substrate surround the chip.
In one embodiment, on a section where the encapsulation layer is stacked with the circuit substrate, a cross section of the encapsulation layer and a cross section of the circuit substrate satisfy: when the temperature changes in the working temperature range of the chip, the stress generated on the cross section of the packaging layer due to thermal expansion and cold contraction of the packaging layer is correspondingly offset with the stress generated on the cross section of the circuit substrate due to thermal expansion and cold contraction of the circuit substrate.
In one embodiment, the circuit board structure further includes an independent contact pin mounted on the circuit substrate, the circuit substrate is located between the independent contact pin and the chip, a via hole is formed in the circuit substrate, and the chip pin is electrically connected to the independent contact pin through the via hole.
In one embodiment, the number of the chips is at least two, the number of the packaging layers is at least two, each packaging layer at least covers one chip, and a bending gap is arranged between the two packaging layers.
In one embodiment, the circuit substrate is a flexible circuit substrate.
The invention has the beneficial effects that:
1. when the circuit substrate and the packaging layer expand with heat and contract with cold along with the temperature change, the packaging layer covers the chip and encloses the chip between the packaging layer and the circuit substrate; for the part of the circuit substrate on which the chip is mounted, the circuit substrate and the packaging layer simultaneously extrude the chip from the upper part, the lower part and the periphery of the chip, and the chip is stressed simultaneously and cannot deform; for the part of the circuit substrate without the chip, the circuit substrate and the packaging layer expand with heat and contract with cold simultaneously, so that deformation is avoided, and the performance is not influenced by the deformation even if the circuit substrate is made to be very thin;
the chip pins and the circuit pins are butted through the anisotropic conductive adhesive, the anisotropic conductive adhesive can realize the electric connection of the chip and the circuit substrate only by a thin layer, and the thickness of the circuit substrate can be further reduced. The circuit substrate is provided with external pins connected with the circuit pin points, a lead wire is required to be arranged to connect the chip with the external pins, and the lead wire occupies a large space in the circuit substrate, so that the thickness and the volume of the circuit substrate are high. The anisotropic conductive adhesive is adopted, the occupied space is small, the thickness and the volume of the circuit board can be reduced, and the thickness of the circuit board can be further reduced.
2. The chip and the circuit substrate are usually flat and flaky, the area of the spreading direction is large, the area of the cross section vertical to the spreading direction is small, the size of the cross section of the packaging layer or/and the size of the cross section of the circuit substrate are/is selected according to stress counteracting conditions, when the temperature changes within the working temperature range of the chip, the stress generated on the cross section of the packaging layer by the expansion with heat and the contraction with cold of the packaging layer and the stress generated on the cross section of the circuit substrate by the expansion with heat and the contraction with cold of the circuit substrate are counteracted correspondingly, and the deformation of the chip is further prevented.
3. Independent contact pin of independent installation on circuit substrate alone, pass through the via hole with the chip pin and independently contact pin electricity and be connected, can be that the chip directly passes through the via hole and independently contact pin is connected with the external world, on the one hand, can support the high-power circular telegram of chip, for example, the power supply to the chip can go on through independent contact pin, can provide bigger power to the chip, also avoid high-power to produce too high energy loss through circuit substrate, on the other hand, adopt the form of via hole, do not occupy extra space, can reduce circuit substrate thickness and volume.
4. A bending gap is arranged between the two packaging layers, so that the using amount of the packaging layers can be reduced, and the average thickness of the circuit substrate can be reduced.
5. The circuit substrate is made of flexible materials, the thickness of the circuit board is reduced as much as possible, the flexible use of the flexible circuit board is facilitated, a bending gap is arranged between the two packaging layers, and when the circuit board is bent, the part between the two packaging layers is bent, so that the chip is prevented from being bent.
Drawings
FIG. 1 is a first schematic diagram of a circuit board manufacturing method according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of a circuit board manufacturing method according to an embodiment of the invention;
FIG. 3 is a third schematic view of a circuit board manufacturing method according to an embodiment of the invention;
FIG. 4 is a fourth schematic view of a circuit board manufacturing method according to an embodiment of the invention;
FIG. 5 is a fifth schematic view of a circuit board manufacturing method according to an embodiment of the invention;
FIG. 6 is a schematic structural diagram of a semiconductor substrate according to a second embodiment of the present invention;
FIG. 7 is a first structural diagram of a circuit substrate according to a second embodiment of the present invention;
FIG. 8 is a second structural diagram of the circuit substrate according to the second embodiment of the present invention;
fig. 9 is a first schematic structural diagram of a 3D circuit board according to a second embodiment of the invention;
fig. 10 is a second schematic structural diagram of a 3D circuit board according to a second embodiment of the invention;
FIG. 11 is a first schematic view illustrating a method of manufacturing a chip according to a second embodiment of the present invention;
FIG. 12 is a second schematic view illustrating a second method for manufacturing a chip according to a second embodiment of the present invention;
FIG. 13 is a third schematic view of a chip manufacturing method according to a second embodiment of the present invention;
FIG. 14 is a fourth schematic view illustrating a chip manufacturing method according to a second embodiment of the present invention;
FIG. 15 is a fifth schematic view of a chip manufacturing method according to a second embodiment of the present invention;
fig. 16 is a sixth schematic view of a chip manufacturing method according to a second embodiment of the invention.
Description of reference numerals:
100. chip 101, semiconductor layer 102, isolation layer 103, auxiliary layer 104, chip via 105, connection layer 106, conductive part 200, semiconductor board 210, carrier 220, first paste medium 230, extraction surface 310, circuit substrate 320, anisotropic conductive adhesive 330, via 340, encapsulation layer 350, bending gap 360, independent contact pin.
Detailed Description
The present invention will be described in further detail below, but the embodiments of the present invention are not limited thereto.
Example one
As shown in fig. 1, a wiring board structure includes: a circuit substrate 310, wherein circuit pins are arranged on the circuit substrate 310; an anisotropic conductive paste 320; the chip 100, wherein the chip 100 is provided with a chip 100 pin; an encapsulation layer 340; the chip 100 is mounted on the circuit substrate 310, the anisotropic conductive adhesive 320 is disposed between the circuit substrate 310 and the chip 100, and the pins of the chip 100 are butted with the pins of the circuit through the anisotropic conductive adhesive 320; the packaging layer 340 covers the chip 100, and the packaging layer 340 and the circuit substrate 310 surround the chip 100.
The circuit board structure further includes: on the cross section staggered from the chip 100 and formed by stacking the packaging layer 340 and the circuit substrate 310, the cross section of the packaging layer 340 and the cross section of the circuit substrate 310 satisfy: when the temperature changes within the operating temperature range of the chip 100, the thermal expansion and contraction of the encapsulation layer 340 generates a stress on the cross section of the encapsulation layer 340 that is offset corresponding to the thermal expansion and contraction of the wiring substrate 310.
As shown in fig. 2, the circuit board structure further includes an independent contact pin 360 mounted on the circuit substrate 310, the circuit substrate 310 is located between the independent contact pin 360 and the chip 100, a via hole 330 is formed on the circuit substrate 310, and the pin of the chip 100 is electrically connected to the independent contact pin 360 through the via hole 330.
The circuit board structure further includes: at least two chips 100 are provided, at least two packaging layers 340 are provided, each packaging layer 340 covers at least one chip 100, and a bending gap is provided between the two packaging layers 340.
The circuit board structure further includes: the circuit substrate 310 is a flexible circuit substrate 310.
Preferably, the thickness of the chip 100 is less than 10 μm, the circuit substrate 310 is a flexible circuit board, the obtained circuit board has good flexibility, and can be made into a wearable device, and the encapsulation layer 340 can effectively protect the chip 100 from being damaged by external force and can also prevent the chip 100 from being bent.
The chip 100 may be a bare chip or an already packaged integrated chip 100, but is not limited thereto, and may also be other electronic elements having circuit functions.
The circuit board manufacturing method comprises the following steps: the chip 100 is mounted on the circuit substrate 310, the chip 100 is provided with chip 100 pins, the circuit substrate 310 is provided with circuit pins, the anisotropic conductive adhesive 320 is arranged between the chip 100 and the circuit substrate 310, and the chip 100 pins are butted with the circuit pins through the anisotropic conductive adhesive 320; the encapsulation layer 340 covers the chip 100, and the encapsulation layer 340 and the circuit substrate 310 surround the chip 100. When the circuit substrate 310 and the encapsulation layer 340 expand with heat and contract with cold with temperature change, the encapsulation layer 340 covers the chip 100 and the encapsulation layer 340 and the circuit substrate 310 enclose the chip 100 therebetween; for the part of the circuit substrate 310 where the chip 100 is mounted, the circuit substrate 310 and the packaging layer 340 simultaneously press the chip 100 from the upper and lower sides and the periphery of the chip 100, and the chip 100 is simultaneously stressed and does not deform; for the part of the circuit substrate 310 without the chip 100, the circuit substrate 310 and the encapsulation layer 340 expand with heat and contract with cold simultaneously, so as to avoid deformation, and even if the circuit substrate 310 is made to be very thin, the performance is not affected by the deformation; the pins of the chip 100 are butted with the pins of the circuit through the anisotropic conductive adhesive 320, and the anisotropic conductive adhesive 320 can realize the electrical connection between the chip 100 and the circuit substrate 310 by only needing a thin layer, so that the thickness of the circuit board can be further reduced.
The circuit board manufacturing method further comprises the following steps: selecting the cross-sectional size of the encapsulation layer 340 or/and the circuit substrate 310 according to the stress counteracting condition; wherein, the stress counteracting condition is as follows: on the cross section staggered from the chip 100 and formed by stacking the packaging layer 340 and the circuit substrate 310, the cross section of the packaging layer 340 and the cross section of the circuit substrate 310 satisfy: when the temperature changes within the operating temperature range of the chip 100, the thermal expansion and contraction of the encapsulation layer 340 generates a stress on the cross section of the encapsulation layer 340 that is offset corresponding to the thermal expansion and contraction of the wiring substrate 310. The chip 100 and the circuit substrate 310 are generally flat and sheet-shaped, the area of the spreading direction is large, the area of the cross section perpendicular to the spreading direction is small, the size of the cross section of the packaging layer 340 or/and the circuit substrate 310 is selected according to stress counteracting conditions, when the temperature changes within the working temperature range of the chip 100, the stress generated on the cross section of the packaging layer 340 by the expansion with heat and the contraction with cold of the packaging layer 340 and the stress generated on the cross section of the circuit substrate 310 by the expansion with heat and the contraction with cold of the circuit substrate 310 are counteracted correspondingly, and the deformation of the chip 100 is further prevented.
The circuit board manufacturing method further comprises the following steps: the independent contact pins 360 are mounted on the circuit substrate 310, so that the circuit substrate 310 is located between the independent contact pins 360 and the chip 100, the via holes 330 are formed on the circuit substrate 310, and the pins of the chip 100 are electrically connected with the independent contact pins 360 through the via holes 330. Generally, the circuit substrate 310 is provided with external pins in point connection with the circuit pins, the chip 100 is connected to an external device through the external pins, the independent contact pins 360 are independently installed on the circuit substrate 310, the pins of the chip 100 are electrically connected to the independent contact pins 360 through the via holes 330, the chip 100 can be directly connected to the outside through the via holes 330 and the independent contact pins 360, and the high-power supply of the chip 100 can be supported, for example, the power supply to the chip 100 can be performed through the independent contact pins 360, so that higher power can be provided for the chip 100, and the high-power energy loss generated by the circuit substrate 310 can be avoided.
As shown in fig. 3, the method for manufacturing a circuit board further includes: at least two chips 100 are provided, at least two packaging layers 340 are provided, each packaging layer 340 covers at least one chip 100, and a bending gap 350 is provided between the two packaging layers 340. The bending gap 350 between the two packaging layers 340 can reduce the amount of the packaging layers 340 and the average thickness of the circuit board.
The circuit board manufacturing method further comprises the following steps: the circuit substrate 310 is made of a flexible material. Reducing the thickness of the circuit board as much as possible is beneficial to the flexible use of the flexible circuit board, and a bending gap 350 is arranged between the two packaging layers 340, so that when the circuit board is bent, the bending gap 350 between the two packaging layers 340 is bent, and the chip 100 is prevented from being bent.
Not limited thereto, as shown in fig. 4 and 5, the independent contact pins 360 and the bending gap 350 may be used simultaneously or separately as needed.
Example two
The difference between the second embodiment and the first embodiment is that:
in this embodiment, a semiconductor substrate is used to fabricate a semiconductor board, and then a chip is fabricated from the semiconductor board. As shown in fig. 6, the semiconductor substrate includes: the semiconductor layer 101, the isolation layer 102 and the auxiliary layer 103 with reduced thickness are reserved, and the thickness of the auxiliary layer 103 is larger than that of the semiconductor layer 101; the semiconductor layer 101, the isolation layer 102, and the auxiliary layer 103 are stacked in this order, and the auxiliary layer 103 has a thickness larger than that of the semiconductor layer 101. The method for manufacturing the semiconductor board 200 using the semiconductor substrate includes: a circuit fabrication process of fabricating a circuit on the semiconductor layer 101; a thickness reducing process, wherein the auxiliary layer 103 is ground or etched, and the thickness of the auxiliary layer 103 is reduced, so that the whole thickness of the semiconductor substrate is reduced, and a circuit substrate with small whole thickness is obtained; in the packaging process, the semiconductor board 200 is obtained by packaging the circuit substrate. The semiconductor layer 101 is used for forming a circuit, and as a functional portion of the circuit substrate, for example, a transistor and an interconnection line are formed on the semiconductor layer 101 to form a circuit.
When a circuit is manufactured on the semiconductor layer 101, the auxiliary layer 103 provides auxiliary support for the semiconductor layer 101, so that the semiconductor layer 101 is not easy to deform, and the performance of the semiconductor circuit can be ensured; when the processing of the semiconductor layer 101 is completed without using the auxiliary layer 103 as an auxiliary support, the thickness of the auxiliary layer 103 is reduced, so that the thickness of the semiconductor substrate is greatly reduced to become a circuit substrate. The isolation layer 102 is used to protect the semiconductor layer 101, so that on one hand, in the process of reducing the thickness, the semiconductor layer 101 can be protected to avoid accidental damage to the semiconductor layer 101 when the reduction auxiliary layer 103 is removed, and on the other hand, when the semiconductor board 200 or the circuit substrate is used, the damage such as cracks or fractures of the thin semiconductor layer 101 can be prevented. Further, on the premise of ensuring circuit performance, the thicknesses of the semiconductor layer 101 and the isolation layer 102 are reduced as much as possible, so that the thickness of the entire semiconductor board 200 can be further reduced.
In the process of reducing the thickness, the auxiliary layer 103 may be entirely removed as necessary to form the structure shown in fig. 7, or only a part of the auxiliary layer 103 may be removed to form the structure shown in fig. 8.
In this embodiment, the semiconductor layer 101 is made of single crystal silicon (not limited to this embodiment, but may be made of other semiconductor materials), the auxiliary layer 103 is made of silicon, preferably single crystal silicon, and the isolation layer 102 is made of silicon dioxide. The semiconductor layer 101 and the auxiliary layer 103 are made of the same material, and the auxiliary layer 103 and the semiconductor layer 101 have the same physical properties, so that the processing of the semiconductor layer 101 is maintained. Without being limited to this embodiment, the auxiliary layer 103 may be made of other silicon-containing materials.
In the process of reducing the thickness, the auxiliary layer 103 is etched by using a tetramethyl ammonium hydroxide solution or a potassium hydroxide solution, and the etching speed of the material of the isolation layer 102 by the tetramethyl ammonium hydroxide solution or the potassium hydroxide solution is less than the etching speed of the material of the auxiliary layer 103 under the same condition. When the auxiliary layer 103 is etched using a tetramethylammonium hydroxide solution or a potassium hydroxide solution to reduce the thickness of the auxiliary layer 103, when the thickness of the auxiliary layer 103 is reduced to 0, the tetramethylammonium hydroxide solution or the potassium hydroxide solution touches the isolation layer 102, and since the etching rate of the isolation layer 102 is lower than that of the auxiliary layer 103, the tetramethylammonium hydroxide solution or the potassium hydroxide solution can be prevented from etching the semiconductor layer 101 to damage the semiconductor circuit.
For this embodiment, the difference between the etching speed of the isolation layer 102 (silicon dioxide) and the etching speed of the auxiliary layer 103 (silicon) is about 10 times, when the tetramethyl ammonium hydroxide solution or potassium hydroxide solution touches the isolation layer 102, the etching speed of the isolation layer 102 is very slow, which can be regarded as that the etching is stopped at the isolation layer 102, and the isolation layer 102 can play a good role in protecting the semiconductor layer 101.
Without being limited to this embodiment, other etching solutions may be used to etch the auxiliary layer 103; when the auxiliary layer 103 is made of other materials, a corresponding etching solution can be used as required; the auxiliary layer 103 may also be reduced in thickness by physical means, such as laser etching or grinding.
After stacking at least two circuit boards, packaging to obtain a 3D circuit board, as shown in fig. 9. After at least two circuit boards are stacked, a wet etching process is used to fabricate the chip via 104. After the thickness of the reduction auxiliary layer 103 is reduced, the thickness of the whole circuit substrate is greatly reduced, the circuit substrates are stacked to form the 3D circuit board, the thickness of the whole 3D circuit board is still very thin, and the chip via holes 104 can be manufactured by adopting a wet etching process which is more convenient and rapid to operate. If the traditional 3D circuit board manufacturing method is adopted, because the thickness of each layer of circuit board is very thick, the whole thickness of the manufactured 3D circuit board is very large, the wet etching can cause wide erosion in the cross section direction of the chip through hole 104, the performance of the chip through hole 104 is deteriorated, only the dry etching can be adopted to manufacture the chip through hole 104, but the dry etching speed is slow, and the operation is complex. In contrast, the 3D circuit board manufactured by the embodiment has higher processing efficiency of the chip via hole 104. As shown in fig. 10, a connection layer 105 is disposed between two adjacent layers of circuit substrates of the 3D circuit board, the connection layer 105 bonds the two adjacent layers of circuit substrates, and a conductive portion 106 capable of conducting electricity is disposed in the connection layer 105, and circuit layers on each layer of circuit substrates (adjacent or non-adjacent) in the 3D circuit board can be mutually conducted through the chip via hole 104 and the conductive portion 106, so that functional communication of each layer of circuit substrates in the 3D circuit board is achieved.
The thickness of the circuit substrate manufactured by the method of the embodiment is less than or equal to 10 microns, the circuit substrate can be partially or completely covered with resin materials to manufacture the flexible circuit board, the whole flexible circuit board is thin in thickness and flexible, the flexible circuit board can be bent and twisted without damaging the flexible circuit board, and wearable equipment can be manufactured.
The semiconductor layer becomes a semiconductor function layer after the circuit manufacturing process, and the semiconductor function layer comprises a semiconductor triode, a metal interconnection line and an insulating layer. The semiconductor layer has a circuit function after a circuit manufacturing process, a finally obtained semiconductor board can be used as a chip, a plurality of circuit units can be manufactured on the semiconductor board in the circuit manufacturing process, the semiconductor board is cut into a plurality of chips to be used, and the circuit units correspond to the chips one to one.
The chip manufacturing method comprises the following steps: as shown in fig. 11 to 13, a semiconductor board 200 is flatly attached to a carrier 210, the semiconductor board 200 is attached to the carrier 210 by a first attaching medium 220, and the semiconductor board 200 is divided into at least two chips 100; attaching an extraction surface 230 of an extraction device to one of the chips 100, eliminating or weakening the viscosity of the first attaching medium 220 on the corresponding chip 100, and releasing or weakening the attaching relationship between the corresponding chip 100 and the carrier 210, wherein the extraction device extracts the semiconductor board 200 through the extraction surface 230; wherein the chip 100 is flatly attached to the extraction surface 230, and the chip 100 falls within the range of the extraction surface 230.
When the chip 100 is extracted, the viscosity of the first pasting medium 220 on the corresponding chip 100 is removed or weakened, and the pasting relationship between the corresponding chip 100 and the carrier 210 is released or weakened (hereinafter, the chip 100 is referred to as "released"), so that the corresponding chip 100 can be extracted by the extraction device; at this time, the viscosity of the first pasting medium 220 on the other chips 100 adjacent to the chip 100 to be extracted is not damaged, and the chips 100 are still pasted on the carrier 210 and cannot be extracted by the extraction device (i.e., the chips 100 are not "released"); when the extracting surface 230 of the extracting device is attached to the corresponding chip 100, the released chip 100 is extracted by the extracting surface 230, and the unreleased chip 100 is kept attached to the carrier 210 without being damaged due to the viscosity of the first attaching medium 220, so that the specific chip 100 can be conveniently extracted without damaging the chips 100 around the chip; moreover, the released chip 100 is laid on the extraction surface 230, the chip 100 falls into the extraction range of the extraction surface 230, and the coverage of the extraction surface 230 may be larger than or equal to the released chip 100, and at this time, the chip 100 is completely covered by the extraction surface 230, and the edge of the chip 100 is also attached to which of the extraction surface 230, so that the whole chip 100 is stressed, and has no bending wrinkles and stress concentration, thereby avoiding the deterioration of fine cracks caused by cutting, preventing the chip 100 from being broken to generate defective products, and improving the production yield. In particular, in the case of a very thin chip 100, for example, the thickness is less than or equal to 10 μm, the chip 100 needs to be separated from the carrier 210 when the chip 100 is extracted, and if the chip 100 does not fall within the range of the extraction surface 230, the portion of the chip 100 within the extraction range is pulled and stressed, and the chip 100 outside the extraction range is bent, so that the chip 100 cracks deeper, and the chip 100 is easily broken to generate defective products. By adopting the manufacturing method of the chip 100, the chip 100 can be effectively protected from being damaged in the process of extracting the chip 100, and the product percent of pass is improved.
On the other hand, even if the cover surface of the extraction surface 230 is larger than the chip 100 to be released, and the extraction surface 230 is in contact with the chip 100 not to be released, the chip 100 not to be released is not damaged by the extraction surface 230 since the chip 100 not to be released is always attached to the carrier 210 by the first adhesive medium 220.
By releasing the chip 100 to be extracted and not releasing the rest of the chips 100, the selective release of the chip 100 is realized, which is beneficial to make all the chips 100 flatly attached to the extraction surface 230, thereby avoiding the extracted chip 100 from being damaged, and simultaneously ensuring that the chip 100 which is not released is not lifted by the extraction surface 230 and is not damaged.
The first pasting medium 220 may be a photosensitive material or a heat-sensitive material, and the viscosity of the first pasting medium 220 may be controlled by controlling the illumination or temperature of the first pasting medium 220, in this embodiment, a photosensitive material is used (but not limited thereto, and other materials may be used to eliminate or weaken the viscosity), when the first pasting medium 220 receives illumination meeting conditions (for example, ultraviolet light with a certain intensity), the first pasting medium 220 loses viscosity, and the corresponding chip 100 is released. At least two light emitters corresponding to the positions of the chips 100 may be disposed on the carrier 210, and the corresponding chips 100 may be released by individually controlling the light emitters to irradiate the first paste medium 220 on the corresponding chips 100; when the first pasting medium 220 is irradiated, the first pasting medium 220 corresponding to the chip 100 which is not required to be released is shielded, and the selective release of the chip 100 is realized.
After a released chip 100 is extracted, the viscosity of the first pasting medium 220 on another chip 100 is eliminated or weakened, the pasting relation between the chip 100 and the carrier 210 is released or weakened, so that the chip 100 is released, and then the extraction is carried out by using an extraction device, wherein the extraction can be carried out again by using the same extraction surface 230, or can be carried out by using another extraction surface 230 on the extraction device; in this way, the specific chip 100 is extracted through the selective release of the specific chip 100, and meanwhile, the extracted chip 100 is not broken and the adjacent chips 100 are not affected.
A second adhesive medium may be provided on the extraction surface 230, by which the chip 100 is adhered to the extraction surface 230 when the extraction surface 230 is placed against the chip 100. The chip 100 is extracted by means of pasting, the structure is simple, the maintenance is convenient, and preferably, the second pasting medium makes all edges of the chip 100 pasted on the extraction surface 230.
A vacuum device may be provided on the extraction device, which creates a negative pressure on the extraction surface 230, so that the chip 100 is sucked onto the extraction surface 230 when the extraction surface 230 is placed against the chip 100. The vacuum mode does not pollute the chip 100, is beneficial to protecting semiconductors and carrying out subsequent operation on the chip 100; the vacuum suction surface may cover a part or all of the extracted chip 100, and preferably, the vacuum suction surface allows all edges of the chip 100 to be sucked onto the extraction surface 230, so that the chip 100 is more uniform.
The method for manufacturing the chip 100 further includes: at least two circuit units are fabricated on the semiconductor board 200, the circuit units corresponding to the chips 100. The circuit units may be fabricated on the semiconductor board 200, then the semiconductor board 200 is flatly attached to the carrier 210, and then the semiconductor board 200 is divided into the chips 100, which facilitates the streamline operation. The circuit unit may be made of the material of the semiconductor board 200 itself, or may be made by adding another material to the semiconductor board 200. The semiconductor board 200 having the circuit unit has a certain circuit function, and can be transferred to another place as the chip 100. Not limited to this, the semiconductor board 200 may be first attached to a flat surface, the semiconductor board 200 may be divided into the chips 100, and then the circuit units may be formed on the semiconductor board 200.
The method for manufacturing the chip 100 further includes: after the chip 100 is extracted, the chip is adhered to an extension sheet through an anisotropic conductive adhesive, wherein the extension sheet is provided with extension pins, and pins of a circuit unit of the chip 100 are butted with the extension pins. The circuit unit of the chip 100 generally has a small area, the pin interval of the circuit unit is small, the circuit unit is inconvenient to use and easy to damage, the area of the expansion sheet is larger than that of the chip 100, the interval of the expansion pins is larger than that of the pins on the chip 100, the chip 100 is convenient to use through the expansion of the expansion sheet, meanwhile, the expansion pins are used for realizing the connection of the chip 100 and other equipment, the chip 100 can be protected, and the service life is prolonged. On the other hand, the chip 100 and the expansion sheet are adhered by the anisotropic conductive adhesive, and the chip 100 and the expansion sheet can be butted by using a thin anisotropic conductive adhesive, so that the whole body formed by the chip 100 and the expansion sheet is thinner.
As shown in fig. 14 to 16, the semiconductor board 200 may be divided into at least three chips 100, at least two extraction surfaces 230 may be provided on the extraction device, the at least two extraction surfaces 230 may be simultaneously attached to the corresponding chips 100, the viscosity of the first attaching medium 220 on the corresponding chips 100 may be eliminated or weakened, the attaching relationship between the corresponding chips 100 and the carrier 210 may be released or weakened, and at least two chips 100 may be extracted at the same time; the two extraction surfaces 230 may be separated from each other, or the two extraction surfaces 230 may be adjacent to each other and integrated with each other. After the chips are extracted, at least two chips on the extraction device are attached to the first extension sheet, the corresponding chips are released by the extraction surface, and the chips are placed on the first extension sheet. In the transferring process of transferring the chips from the carrier to the first expansion sheet, the chips are attached to the extraction surface all the time, the mutual position relation and the mutual distance of two or more chips extracted in the transferring process are not changed, the chips are cut into the chips at the preset positions on the semiconductor board, the chips are transferred to the first expansion sheet, the mutual arrangement of the chips is not changed, and the further processing of the chips is facilitated. The first extension sheet can be provided with extension pins, the chip is provided with a circuit unit, and the circuit unit is electrically communicated with the extension pins; the first extension sheet is not provided with the extension pins, and the first extension sheet is not electrically connected with the circuit unit of the chip, the first extension sheet is only used as a support of the chip, more than two chips can be arranged on the first extension sheet, and the chips are electrically connected with each other.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. A circuit board manufacturing method is characterized by comprising the following steps:
the chip is arranged on the circuit substrate, chip pins are arranged on the chip, circuit pins are arranged on the circuit substrate, anisotropic conductive adhesive is arranged between the chip and the circuit substrate, and the chip pins are butted with the circuit pins through the anisotropic conductive adhesive; the packaging layer covers the chip, and the packaging layer and the circuit substrate surround the chip; and arranging independent contact pins on the circuit substrate, enabling the circuit substrate to be positioned between the independent contact pins and the chip, arranging through holes on the circuit substrate and the anisotropic conductive adhesive, and electrically connecting the chip pins with the independent contact pins through the through holes.
2. The manufacturing method of the circuit board according to claim 1, wherein the size of the cross section of the packaging layer or/and the circuit substrate is selected according to a stress counteracting condition;
wherein the stress counteracting condition is as follows: on the section where the packaging layer and the circuit substrate are stacked, the cross section of the packaging layer and the cross section of the circuit substrate meet the following conditions: when the temperature changes in the working temperature range of the chip, the stress generated on the cross section of the packaging layer due to thermal expansion and cold contraction of the packaging layer is correspondingly offset with the stress generated on the cross section of the circuit substrate due to thermal expansion and cold contraction of the circuit substrate.
3. The manufacturing method of the circuit board according to any one of claims 1 to 2, wherein the number of the chips is at least two, the number of the encapsulation layers is at least two, each encapsulation layer covers at least one of the chips, and a bending gap is arranged between the two encapsulation layers.
4. The manufacturing method of the circuit board according to any one of claims 1 to 2, wherein the circuit substrate is made of a flexible material.
5. A circuit board structure, comprising:
the circuit board is provided with circuit pins;
an anisotropic conductive adhesive;
the chip is provided with a chip pin;
a packaging layer;
the chip is arranged on the circuit substrate, the anisotropic conductive adhesive is arranged between the circuit substrate and the chip, and the chip pins are butted with the circuit pins through the anisotropic conductive adhesive; the packaging layer covers the chip, and the packaging layer and the circuit substrate surround the chip;
the circuit board is arranged between the independent contact pins and the chip, via holes are formed in the circuit board and the anisotropic conductive adhesive, and the chip pins are electrically connected with the independent contact pins through the via holes.
6. The circuit board structure according to claim 5, wherein, in a cross section where the encapsulation layer is stacked on the circuit board substrate, a cross section of the encapsulation layer and a cross section of the circuit board substrate satisfy:
when the temperature changes in the working temperature range of the chip, the stress generated on the cross section of the packaging layer due to thermal expansion and cold contraction of the packaging layer is correspondingly offset with the stress generated on the cross section of the circuit substrate due to thermal expansion and cold contraction of the circuit substrate.
7. The circuit board structure according to any one of claims 5 and 6, wherein the number of the chips is at least two, the number of the encapsulation layers is at least two, each encapsulation layer covers at least one of the chips, and a bending gap is arranged between the two encapsulation layers.
8. Circuit board structure according to any of claims 5, 6, characterized in that the circuit substrate is a flexible circuit substrate.
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| CN201610335268.XA CN107403784B (en) | 2016-05-19 | 2016-05-19 | Circuit board manufacturing method and structure |
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| CN201610335268.XA CN107403784B (en) | 2016-05-19 | 2016-05-19 | Circuit board manufacturing method and structure |
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| CN108415596B (en) * | 2018-02-08 | 2021-05-04 | 深圳市志凌伟业技术股份有限公司 | Conductive substrate and manufacturing method thereof |
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