JP2011243596A - Manufacturing method of package component and package component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a package component, which can improve package quality.SOLUTION: Semiconductor chips 2, which are functional components, are mounted on a mounting surface of a substrate 1a. Next, each semiconductor chip 2 is sealed by an encapsulation resin 3. Subsequently, polishing is performed from a surface of the encapsulation resin 3 opposite to a surface facing to the mounting surface of the substrate 1a, to polish the encapsulation resin 3 and each semiconductor chip.

Description

  The present invention relates to a package component manufacturing method and a package component, and more particularly to a semiconductor package having a structure in which a semiconductor chip is mounted on a substrate.

  As a conventional method for manufacturing a semiconductor package, Patent Document 1 describes a method of mounting a semiconductor chip on a substrate made of silicon. FIG. 12 is a diagram showing a conventional semiconductor package described in Patent Document 1. In FIG.

  As shown in FIG. 12, a conventional semiconductor package includes a silicon substrate 101 on which wiring is formed, a semiconductor chip 102 mounted on a mounting surface of the substrate 101, and a through electrode 103 penetrating the substrate 101. The rewiring layer 104 formed on the back surface opposite to the mounting surface of the substrate 101, the first protruding electrode 105 that electrically and mechanically connects the substrate 101 and the semiconductor chip 102, and the rewiring layer 104 And a second protruding electrode 106 provided thereon.

  In this semiconductor package manufacturing method, after the thickness of the substrate 101 is controlled by polishing in a wafer state, the through electrode 103 is formed from the back surface side of the substrate 101, the rewiring layer 104 is formed on the back surface of the substrate 101, and The first protruding electrode 105 is formed at a location where the semiconductor chip 102 is mounted, the substrate 101 is separated into pieces by a dicing method or the like, and the semiconductor chip 102 is aligned and mounted on the separated substrate 101. The second protruding electrode 106 is formed on the rewiring layer 104.

International Publication No. 2004/047167

  However, in the conventional semiconductor package manufacturing method described above, after the silicon wafer is subjected to a polishing process for thinning, the polished silicon wafer is divided into individual pieces, and the separated silicon substrate is obtained. Since the process of mounting a semiconductor chip on top is used, warpage of the silicon substrate due to processing distortion generated during polishing processing, and the surface resulting from handling a thin and fragile silicon substrate Due to the influence of contamination, scratches, etc., a connection failure may occur between the electrode of the silicon substrate and the electrode of the semiconductor chip, and the package quality may vary.

  The following can be considered as causes of processing distortion.

  First, it is considered that one of the causes is unevenness of the surface roughness generated on the processed surface of the silicon wafer by the polishing process. That is, when unevenness of the surface roughness occurs on the processed surface of the silicon wafer due to the polishing process, polishing is continued while pressure is applied along the unevenness, so that a portion that is polished strongly and a portion that is polished weakly are generated. In addition, the polishing conditions vary on the processed surface. Therefore, a difference in residual stress (processing distortion) occurs between the strongly polished portion and the weakly polished portion.

  Another possible cause is a polishing flaw generated on the processed surface of the silicon wafer due to the polishing process. That is, when a polishing flaw occurs on the processed surface of the silicon wafer due to the polishing process, the polishing is continued while pressure is applied along the polishing flaw, so that a strongly polished part and a weakly polished part are generated, Variations in polishing conditions occur on the processed surface. Therefore, a difference in residual stress (processing distortion) occurs between the strongly polished portion and the weakly polished portion.

  Another possible cause is a variation in the thickness of the silicon wafer. That is, when there is a thickness variation in the silicon wafer, a strongly polished portion and a weakly polished portion are generated, and polishing conditions are varied on the processed surface. Therefore, a difference in residual stress (processing distortion) occurs between the strongly polished portion and the weakly polished portion.

  Further, the warp of the silicon substrate due to the processing distortion is caused by the following reason. That is, the residual stress of a silicon wafer is determined when a semiconductor chip is bonded to an individual silicon substrate or when a sealing resin that seals a gap between the bonded semiconductor chip and the silicon substrate is cured. Although it is released by heat, in the conventional semiconductor package manufacturing method, processing stress (variation of residual stress) is generated in the separated silicon substrate, so the residual stress is not released uniformly and cannot be predicted. A large warp occurs.

  In view of the above-described conventional problems, an object of the present invention is to provide a method for manufacturing a package component and a package component capable of improving package quality.

  In order to achieve the above object, a method for manufacturing a package component according to the present invention includes mounting a plurality of functional components on a mounting surface of a substrate, and sealing each functional component on the mounting surface of the substrate with a sealing resin. Then, polishing is performed from the surface of the sealing resin opposite to the surface facing the mounting surface of the substrate, and the sealing resin and each functional component are polished.

  Further, according to another aspect of the method for manufacturing a package component according to the present invention, the sealing resin includes a first sealing resin and a second sealing resin, and when the sealing resin is sealed with the sealing resin, After sealing the gap between each functional component and the mounting surface of the substrate and the periphery of each functional component with the first sealing resin, the functional component is exposed from the first sealing resin. And the first sealing resin is sealed with the second sealing resin.

  In another aspect of the package component manufacturing method according to the present invention, the sealing resin and each functional component are polished, and then the back surface opposite to the mounting surface of the substrate is polished. .

  In another aspect of the package component manufacturing method according to the present invention, when the sealing resin and each functional component are polished, the back surface of the substrate is polished as a reference surface, and the back surface of the substrate is polished. At this time, the polishing is performed using the already polished surface opposite to the back surface of the substrate as a reference surface.

  In another aspect of the package component manufacturing method according to the present invention, after the back surface of the substrate is polished, a through electrode is formed on the substrate from the back surface side of the substrate, and the polished back surface of the substrate is formed. A rewiring layer is formed to form an assembly including a plurality of mounting structures, and the assembly is cut to generate a plurality of individual mounting structures.

  In another aspect of the method for manufacturing a package component according to the present invention, after the separated mounting structure is generated, the separated mounting structure is connected to another substrate. And

  In another aspect of the method for manufacturing a package component according to the present invention, the substrate is made of silicon, a compound semiconductor such as GaAs or GaN, a ceramic, or a resin.

  In another aspect of the method of manufacturing a package component according to the present invention, the functional component is a silicon semiconductor device, a compound semiconductor device such as silicon carbide, GaAs, or GaN, or an active component such as a resistor or a capacitor. It is characterized by being.

  The package component according to the present invention includes a substrate, a functional component mounted on the mounting surface of the substrate, and a sealing resin for sealing the functional component on the mounting surface of the substrate, The sealing resin is made of a plurality of types of insulating materials having different resin properties.

  According to the preferred embodiment of the present invention, since the polishing process is performed after securing the thickness and strength by the sealing resin, the processing strain (variation in residual stress) generated by the polishing process is held by the rigidity of the sealing resin. And substrate warpage can be prevented. Further, when a functional component such as a semiconductor chip is mounted on a substrate, it is not necessary to handle a fragile substrate that is thin and singulated. In addition, since the mounting structure whose thickness and strength are secured by the sealing resin is handled, it is possible to avoid the influence of surface contamination and scratches due to the handling. In addition, since the resin sealing is performed in the initial process, it is possible to ensure the protection of the joint portion that joins the substrate and the functional component such as the semiconductor chip in the initial process, and to prevent deterioration in quality in the subsequent process. Therefore, it is possible to prevent poor connection between the substrate and a functional component such as a semiconductor chip and improve the package quality.

The figure which shows the process flow of the semiconductor package in embodiment of this invention The figure which shows the semiconductor package in embodiment of this invention The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. The figure for demonstrating the process of the manufacturing method of the semiconductor package in embodiment of this invention. Sectional view of a conventional semiconductor package

  Hereinafter, a package component manufacturing method and a package component mounting form according to the present invention will be described with reference to the drawings, taking a semiconductor package manufacturing method and a semiconductor package as examples. In this embodiment, a semiconductor package having a structure in which two semiconductor chips are mounted on a substrate will be described. Of course, the number of semiconductor chips is not limited to two.

  FIG. 1 shows a process flow of a semiconductor package in an embodiment of the present invention. Specifically, FIG. 1A to FIG. 1E respectively show an outline of part of the process of the semiconductor package in the embodiment of the present invention.

  First, as shown in FIG. 1A, a plurality of semiconductor chips 2 are aligned and mounted on a mounting surface of a substrate 1a in a wafer state. Next, as shown in FIG. 1B, each semiconductor chip 2 on the mounting surface of the substrate 1 a is sealed with a sealing resin 3. For the sealing resin 3, for example, an insulating material such as epoxy, acrylic, phenol, or silicon can be used.

  Next, with the back surface opposite to the mounting surface of the substrate 1a as a reference surface, polishing is performed from the surface opposite to the surface facing the mounting surface of the substrate 1a of the sealing resin 3, and the sealing resin 3 and the semiconductor After the chip 2 is polished, the back surface of the substrate 1a is polished using the already polished surface opposite to the back surface of the substrate 1a as a reference surface. In this way, the substrate 1a is thinned in the wafer state, and the semiconductor chip 2 mounted on the substrate 1a in the wafer state is thinned.

  Thereafter, a through electrode is formed on the substrate 1a from the back surface side of the substrate 1a, a rewiring layer is formed on the polished back surface of the substrate 1a, and a protruding electrode is provided on the rewiring layer. Then, as shown in FIG. 1C, the assembly is cut by a dicing blade 4, for example, to generate a plurality of separated mounting structures. The protruding electrode on the rewiring layer may be formed on the rewiring layer of each mounting structure after cutting the assembly.

  Next, as shown in FIG. 1D, the separated mounting structure is bonded to another substrate 5. Note that the protruding electrode that connects the mounting structure and the other substrate 5 may be formed on the other substrate 5 instead of on the rewiring layer. Thereafter, the gap between the mounting structure and the other substrate 5 is sealed with resin to obtain a semiconductor package as shown in FIG. In FIG. 1 (d), reference numeral 1b indicates a substrate that is separated.

  According to the manufacturing method as described above, since the polishing process is performed after securing the thickness and strength with the sealing resin, the processing strain (variation in residual stress) generated by the polishing process is held by the rigidity of the sealing resin. And substrate warpage can be prevented. Further, since the semiconductor chip is mounted on the substrate in the wafer state, when mounting the semiconductor chip, it is not necessary to handle a thin and fragile fragile substrate. In addition, since the mounting structure whose thickness and strength are secured by the sealing resin is handled, it is possible to avoid the influence of surface contamination and scratches due to the handling. In addition, since the resin sealing is performed in the initial process, it is possible to ensure the protection of the joint portion between the electrode of the substrate and the electrode of the semiconductor chip in the initial process, and it is possible to prevent quality degradation in the subsequent process. Therefore, from these, it is possible to prevent poor connection between the electrode of the substrate and the electrode of the semiconductor chip and improve the package quality.

  Hereinafter, the semiconductor package and the manufacturing method thereof in this embodiment will be described in detail. 2A and 2B are diagrams showing a semiconductor package according to the embodiment of the present invention. Specifically, FIG. 2A is a plan view of the semiconductor package according to the embodiment of the present invention, and FIG. It is sectional drawing of the semiconductor package in embodiment.

  As shown in FIG. 2, this semiconductor package includes a silicon substrate (hereinafter referred to as a silicon substrate) 11a having wirings 12 formed on the mounting surface, and 2 mounted on the mounting surface of the silicon substrate 11a. A first sealing resin 15 for sealing the semiconductor chips 13, 14, the gaps between the semiconductor chips 13, 14 and the mounting surface of the silicon substrate 11 a and the periphery of the semiconductor chips 13, 14, Second sealing resin 16 that seals one sealing resin 15, through electrode 17 that penetrates silicon substrate 11a, and first protrusion that electrically connects semiconductor chips 13 and 14 and silicon substrate 11a A mounting structure including an electrode 18 and a second protruding electrode 19 provided on the back surface opposite to the mounting surface of the silicon substrate 11a is provided. The mounting structure is a resin substrate (hereinafter referred to as a resin substrate). Called. It is bonded to 20.

  The resin substrate 20 has an electrode 21 on the surface facing the silicon substrate 11a, and the electrode 21 and the second protruding electrode 19 provided on the back surface of the silicon substrate 11a are electrically connected. Further, the gap between the silicon substrate 11 a and the resin substrate 20 and the periphery of the silicon substrate 11 a are sealed with the third sealing resin 22. Further, a third protruding electrode 23 is provided on the surface of the resin substrate 20 opposite to the surface facing the silicon substrate 11a.

  As shown in FIG. 2, the surface of each semiconductor chip 13, 14 opposite to the surface facing the silicon substrate 11a is exposed. Further, the wiring 12 formed on the mounting surface of the silicon substrate 11 a is connected to the first protruding electrode 18. Although not shown, a rewiring layer is formed on the back surface of the silicon substrate 11a, and the second protruding electrode 19 is connected to the rewiring layer.

  Next, a method for manufacturing the semiconductor package having the above-described configuration will be described with reference to FIGS. 3 to 11 are diagrams for explaining a method of manufacturing a semiconductor package according to the embodiment of the present invention. Specifically, FIGS. 3A to 11A illustrate the method according to the embodiment of the present invention. FIGS. 3B to 11B are plan views for explaining a part of the manufacturing process of the semiconductor package, and FIG. 3B to FIG. 11B are process cross sections for explaining a part of the manufacturing process of the semiconductor package in the embodiment of the present invention. FIG. 3 to 10, reference numeral 11b indicates a silicon substrate in a wafer state (hereinafter referred to as a silicon wafer). 3 to 10 show a part of a silicon wafer, specifically, a part constituting one mounting structure. Here, in order to simplify the description, a case where one mounting structure is generated using a silicon wafer will be described.

  First, as shown in FIG. 3, the first semiconductor chip 13 is mounted on the silicon wafer 11b. Specifically, first, a silicon wafer 11b having wiring 12 formed on the surface layer on the mounting surface side is prepared. For example, Au or Cu can be used as the material of the wiring 12. Next, a first protruding electrode 18 for bonding is formed on the electrode 24 provided on the wiring 12. The height of the first protruding electrode 18 is set to about 5 to 30 μm. For example, Au or solder can be used as the material of the first protruding electrode 18. After forming the first protruding electrode 18, the mounting position of the mounting surface of the silicon wafer 11b and the wiring surface of the first semiconductor chip 13 are aligned, and conditions such as heat and load are appropriately set, and then the silicon wafer The first semiconductor chip 13 is mounted on 11b. Thereby, the silicon wafer 11 b and the first semiconductor chip 13 are electrically connected via the first protruding electrode 18. Note that the first protruding electrode for bonding may be formed on the wiring surface of the semiconductor chip 13.

  Next, as shown in FIG. 4, the second semiconductor chip 14 is mounted on the silicon wafer 11b. Since this step is the same as the step of mounting the first semiconductor chip 13 described above, detailed description thereof is omitted.

  Next, as shown in FIG. 5, a gap of about 5 to 20 μm existing between the semiconductor chips 13 and 14 and the silicon wafer 11b and the periphery of the semiconductor chips 13 and 14 (from the mounting surface of the silicon wafer 11b). A region extending over the side surfaces of the semiconductor chips 13 and 14 is sealed with a first sealing resin 15. Accordingly, the upper portions of the semiconductor chips 13 and 14 are exposed from the first sealing resin 15. For the first sealing resin 15, for example, an insulating material such as epoxy, acrylic, phenol, or silicon can be used. The first sealing resin 15 is cured by heating at 150 ° C. for about 1 hour, for example.

  Next, as shown in FIG. 6, the portions of the semiconductor chips 13 and 14 exposed from the first sealing resin 15 and the first sealing resin 15 are sealed with the second sealing resin 16. As the first sealing resin 15, for example, an insulating material such as epoxy, acrylic, phenol, or silicon can be used for the second sealing resin 16. The second sealing resin 16 is cured by heating at 150 ° C. for about 1 hour, for example.

  Next, as shown in FIG. 7, the back surface opposite to the mounting surface of the silicon wafer 11b is used as a reference surface, and the second sealing resin 16 is opposite to the surface facing the mounting surface of the silicon wafer 11b. Polishing is performed from the surface, the second sealing resin 16 and each of the semiconductor chips 13 and 14 are polished, and the side opposite to the surface (wiring surface) facing the mounting surface of the silicon wafer 11b of each semiconductor chip 13 and 14 Expose the surface of The polishing may be performed until the first sealing resin 15 is exposed. In this polishing treatment, the polished surface is made parallel to the reference surface and flattened to such an extent that the surface roughness Ra is 1 μm or less. In this polishing process, the thickness of each semiconductor chip 13 and 14 is set to 50 μm or less.

  Next, as shown in FIG. 8, the back surface of the silicon wafer 11b is polished using the already polished surface opposite to the back surface of the silicon wafer 11b as a reference surface. In this polishing treatment, the polished surface is made parallel to the reference surface and flattened to such an extent that the surface roughness Ra is 1 μm or less. In this polishing process, the thickness of the silicon wafer 11b is set to 50 μm or less.

  Next, as shown in FIG. 9, a through electrode 17 serving as a conduction path that penetrates the silicon wafer 11b is formed from the back side of the silicon wafer 11b by using processes such as photolithography, dry etching, CVD, sputtering, and plating. .

  Next, a rewiring layer is formed on the polished back surface of the silicon wafer 11b using a process such as sputtering, photolithography, plating, etching, and the second protruding electrode is formed on the rewiring layer in a later step. After the solder resist is formed except for the place to be provided, as shown in FIG. 10, a second protruding electrode 19 is provided on the rewiring layer to generate a mounting structure. For example, Ti, Cu, Au, or the like can be used as the wiring material of the rewiring layer. For example, Au, Cu, solder, or the like can be used as the material of the second protruding electrode 19.

  Next, after cutting out the mounting structure by a dicing method or the like, the second projecting electrode 19 of the separated mounting structure is aligned with the electrode 21 on the resin substrate 20 which is another substrate, After appropriately setting conditions such as heat and load, the mounting structure is mounted on the resin substrate 20 as shown in FIG. Note that the second protruding electrode 19 may be formed after the mounting structure is cut out, or may be formed on the resin substrate 20 instead of on the mounting structure. The third protruding electrode 23 may be provided after the mounting structure is mounted on the resin substrate 20 or may be provided before the mounting structure is mounted on the resin substrate 20.

  Next, the gap between the silicon substrate 11a and the resin substrate 20 and the periphery of the silicon substrate 11a are sealed with the third sealing resin 22 to obtain the semiconductor package shown in FIG. For the third sealing resin 22, for example, an insulating material such as epoxy, acrylic, phenol, or silicon can be used. The third sealing resin 22 is cured by heating at 150 ° C. for about 1 hour, for example. The third protruding electrode 23 may be provided after resin sealing with the third sealing resin 22.

  As described above, by using the two types of sealing resins 15 and 16 as the sealing resin for sealing the mounting surface of the silicon wafer 11b, the first sealing resin 15 and the second sealing resin 16 are used. By devising the physical properties of the resin such as the Young's modulus and thermal expansion coefficient, it is possible to suppress the occurrence of substrate warpage due to the release of residual stress by the thermal process.

  For example, when the mounting surface of the silicon substrate 11a warps in a convex shape, the Young's modulus of the first sealing resin 15 is higher than the Young's modulus of the second sealing resin 16 that covers the first sealing resin 15. Then, the thermal expansion coefficient of the first sealing resin 15 is brought close to the thermal expansion coefficient of silicon, and the thermal expansion coefficient of the second sealing resin is made larger than the thermal expansion coefficient of silicon. Thereby, the stress which warps the mounting surface of the silicon substrate 11a to a concave shape is generated, and the warpage of the entire package is alleviated.

  Conversely, when the mounting surface of the silicon substrate 11a warps in a concave shape, the Young's modulus of the first sealing resin 15 is made lower than the Young's modulus of the second sealing resin 16, and the first sealing resin 15 And the thermal expansion coefficient of the second sealing resin 16 are both brought close to the thermal expansion coefficient of silicon. As a result, a stress that warps the mounting surface of the silicon substrate 11a to a convex shape is generated, and the warpage of the entire package is alleviated.

  In the third sealing resin, the Young's modulus and thermal expansion coefficient of the silicon substrate 11a and the resin substrate 20 are reduced so that the stress generated in the protruding electrode part joining the silicon substrate 11a and the resin substrate 20 is reduced. A resin having an intermediate physical property value is used.

  As described above, by selecting the physical property values of the first sealing resin 15 and the second sealing resin, it is possible to control the shape change due to the process temperature during processing and assembly and to prevent the warpage of the package. . In this embodiment, the case where two types of sealing resins having different resin properties are used has been described. However, three or more types of sealing resins having different resin properties may be used.

  According to the embodiment described above, the finished surface roughness and polishing scratches generated when polishing a silicon wafer, and variations in the thickness of the silicon wafer, etc., cause the pressure of the silicon substrate generated by the processing pressure and heat. Warpage can be suppressed.

  Further, even if the thicknesses of the two semiconductor chips mounted on the substrate are different from each other, the thicknesses of the two semiconductor chips are made uniform by simultaneously polishing the surface of each semiconductor chip after mounting each semiconductor chip on the substrate. be able to. Therefore, since the surfaces of the two semiconductor chips appear as the same height on the same surface of the semiconductor package, the heat dissipation of each of the two semiconductor chips becomes the same, and the warpage of the semiconductor package is prevented. Can do.

  In this embodiment, a silicon substrate has been described as an example. However, the substrate material is not limited to silicon, a compound semiconductor substrate such as GaAs or GaN, a ceramic substrate, or a resin substrate. A substrate or the like may be used.

  The material of the semiconductor chip mounted on the substrate is not particularly limited, and for example, silicon or a compound semiconductor such as silicon carbide, GaAs, or GaN can be used.

  In this embodiment, the semiconductor package has been described as an example. However, the present invention can also be applied to a package component having a structure in which a functional component other than a semiconductor chip is mounted on a substrate. The substrate is not limited to a substrate in a wafer state, and may be an aggregate substrate in which a plurality of substrates are connected and assembled. As the functional component, for example, an active component such as a resistor or a capacitor can be used.

  The method for manufacturing a package component and the package component according to the present invention can improve the package quality, and are useful for a package component having a structure in which a functional component is mounted on a substrate, such as a semiconductor package.

DESCRIPTION OF SYMBOLS 1a Wafer substrate 1b Divided substrate 2 Semiconductor chip 3 Sealing resin 4 Dicing blade 5 Other substrate 11a Divided silicon substrate 11b Silicon wafer 12 Wiring 13 First semiconductor chip 14 Second semiconductor Chip 15 First sealing resin 16 Second sealing resin 17 Through electrode 18 First protruding electrode 19 Second protruding electrode 20 Resin substrate 21 Electrode 22 Third sealing resin 23 Third protruding electrode 24 Electrode DESCRIPTION OF SYMBOLS 101 Substrate 102 Semiconductor chip 103 Through electrode 104 Redistribution layer 105 First protruding electrode 106 Second protruding electrode

Claims (9)

Mount multiple functional components on the mounting surface of the board,
Sealing each functional component on the mounting surface of the substrate with a sealing resin,
A method for manufacturing a package component, comprising polishing the sealing resin from a surface opposite to a surface facing the mounting surface of the substrate, and polishing the sealing resin and the functional components.   The sealing resin is composed of a first sealing resin and a second sealing resin, and when sealing with the sealing resin, a gap between each functional component and the mounting surface of the substrate, and After the periphery of each functional component is sealed with the first sealing resin, the portion of each functional component exposed from the first sealing resin and the first sealing resin are the second sealing resin. The package part manufacturing method according to claim 1, wherein sealing is performed with a sealing resin.   3. The method of manufacturing a package component according to claim 1, wherein after the sealing resin and each functional component are polished, the back surface opposite to the mounting surface of the substrate is polished.   When polishing the sealing resin and each functional component, the back surface of the substrate is polished as a reference surface, and when the back surface of the substrate is polished, the already polished surface opposite to the back surface of the substrate is 4. The method of manufacturing a package component according to claim 3, wherein polishing is performed as a reference surface.   After the back surface of the substrate is polished, a through electrode is formed on the substrate from the back surface side of the substrate, a rewiring layer is formed on the polished back surface of the substrate, and an assembly composed of a plurality of mounting structures The package part manufacturing method according to claim 4, wherein the assembly is cut to generate a plurality of singulated mounting structures.   6. The method of manufacturing a package component according to claim 5, wherein after the individual mounting structure is generated, the individual mounting structure is connected to another substrate.   7. The method of manufacturing a package component according to claim 1, wherein the substrate is made of silicon, a compound semiconductor such as GaAs or GaN, a ceramic, or a resin.   8. The functional component according to claim 1, wherein the functional component is a silicon semiconductor device, a compound semiconductor device such as silicon carbide, GaAs, or GaN, or an active component such as a resistor or a capacitor. Manufacturing method of package parts. A substrate,
Functional components mounted on the mounting surface of the substrate;
Sealing resin for sealing the functional component on the mounting surface of the substrate,
The package component, wherein the sealing resin is made of a plurality of types of insulating materials having different resin properties.

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