WO2015060106A1 - Semiconductor package manufacturing method - Google Patents

Semiconductor package manufacturing method Download PDF

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Publication number
WO2015060106A1
WO2015060106A1 PCT/JP2014/076575 JP2014076575W WO2015060106A1 WO 2015060106 A1 WO2015060106 A1 WO 2015060106A1 JP 2014076575 W JP2014076575 W JP 2014076575W WO 2015060106 A1 WO2015060106 A1 WO 2015060106A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
resin sheet
semiconductor wafer
sealing
sealing resin
Prior art date
Application number
PCT/JP2014/076575
Other languages
French (fr)
Japanese (ja)
Inventor
浩介 盛田
石坂　剛
豊田　英志
豪士 志賀
智絵 飯野
Original Assignee
日東電工株式会社
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Filing date
Publication date
Application filed by 日東電工株式会社 filed Critical 日東電工株式会社
Publication of WO2015060106A1 publication Critical patent/WO2015060106A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to a method for manufacturing a semiconductor package.
  • a semiconductor package is manufactured by sealing an electronic component fixed to a semiconductor wafer with a sealing resin, and dicing the sealed product into a package for each electronic component as necessary. Is adopted.
  • a technique for reducing the thickness by grinding a sealing resin or a semiconductor wafer after resin sealing has been proposed (for example, Patent Documents 1 and 2). Thinning by grinding is also important in the manufacturing process of thin semiconductor packages such as flip chip BGA (Ball Grid Array), flip chip SiP (System in Package), fan-in type wafer level package, and fan out type wafer level package. Become an element.
  • An object of the present invention is to provide a semiconductor package manufacturing method capable of forming a target circuit element on a ground surface of a semiconductor wafer with high yield after grinding of a sealing body using a sealing resin sheet.
  • the present invention provides a preparation step of preparing a semiconductor wafer having one or more semiconductor chips mounted on the first main surface, A sealing step of sealing the semiconductor chip by laminating a sealing resin sheet on the first main surface of the semiconductor wafer so as to embed the semiconductor chip; and a first step opposite to the first main surface of the semiconductor wafer. 2 including a back grinding process to grind the main surface,
  • the difference between the thickness of the thickest thickest part and the thinnest thinnest part of the laminate of the sealing resin sheet and the ground semiconductor wafer is 20 ⁇ m or less.
  • the cause of the trouble in forming the circuit element is the state of the second main surface forming the circuit element of the semiconductor wafer after grinding, particularly the bulge of the surface.
  • a bulge is considered to occur during grinding of the semiconductor wafer. That is, the grinding of the second main surface of the semiconductor wafer is performed by fixing the sealing body to a fixing means such as a back surface grinding tape with the sealing resin sheet side as a fixed surface. At this time, a region where the semiconductor chip is interposed and a region where the semiconductor chip is not interposed are mixed between the second main surface of the semiconductor wafer and the fixing means.
  • the hardness of the sealing resin sheet and the hardness of the semiconductor chip are different from each other. It will not be uniformly loaded. Since the hardness of the semiconductor chip is generally higher than the hardness of the encapsulated resin sheet after curing, the repulsion from the encapsulated resin sheet in the region where the semiconductor chip intervenes between the semiconductor wafer and the fixing means.
  • the semiconductor wafer is deeply (thinly) easily ground due to the increased force, and conversely, the sealing resin in the region where the semiconductor chip is not interposed between the semiconductor wafer and the fixing means (the region where only the sealing resin sheet is interposed)
  • the repulsive force from the sheet is weakened, and the semiconductor wafer becomes shallower (thicker) and more easily ground.
  • the ground surface of the semiconductor wafer rises due to the thickness variation in the semiconductor wafer after grinding.
  • laminated body the difference between the thickness of the thickest thickest part and the thickness of the thinnest thinnest part of the laminated body (hereinafter also simply referred to as “laminated body”) of the encapsulating resin sheet and the ground semiconductor wafer.
  • thickness difference is 20 ⁇ m or less, it is possible to suppress the occurrence of swell of the ground surface of the semiconductor wafer and ensure sufficient flatness. Circuit elements can be formed efficiently. If the thickness difference exceeds 20 ⁇ m, there may be a problem in forming the circuit element described above.
  • the sealing step is preferably performed by flat plate pressing or compression molding on the sealing resin sheet. Thereby, the surface of the sealing resin sheet of a laminated body can be smoothed, and the bulge of the grinding surface of a semiconductor wafer can be measured and controlled accurately.
  • the thickest portion of the laminate is also referred to as a region where the semiconductor wafer and the semiconductor chip do not overlap when the semiconductor wafer is seen through in plan view (hereinafter also referred to as “resin sheet region”.
  • the region where the semiconductor wafer and the semiconductor chip overlap when viewed through is also referred to as a “chip overlapping region”).
  • the region where the semiconductor chip is not interposed between the semiconductor wafer and the fixing means that is, the resin sheet region
  • the semiconductor wafer is thicker and easier to grind.
  • circuit elements can be formed on the ground surface of the semiconductor wafer with a high yield.
  • the Shore D hardness at 25 ° C. of the encapsulating resin sheet after being subjected to thermosetting treatment at 150 ° C. for 1 hour is preferably 60 or more.
  • the storage elastic modulus in 25 degreeC of the said sealing resin sheet after performing a thermosetting process at 150 degreeC for 1 hour is 3 GPa or more.
  • a rewiring forming step for forming a rewiring on the ground second main surface of the semiconductor chip may be further included.
  • a dicing step of dicing the semiconductor wafer together with the sealing resin sheet in units of a target semiconductor chip may be further included after the rewiring formation step.
  • the present invention includes a semiconductor package obtained by the method for manufacturing the semiconductor package.
  • FIGS. 1A to 1G are cross-sectional views schematically showing one process of a method for manufacturing a semiconductor package according to an embodiment of the present invention.
  • a semiconductor chip is manufactured by sealing a semiconductor chip mounted on a semiconductor wafer with a sealing resin sheet.
  • the semiconductor package manufacturing method according to the present embodiment is suitable for a chip-on-wafer (COW) process.
  • COW chip-on-wafer
  • Chip mounting wafer preparation process In the chip mounting wafer preparation step, a semiconductor wafer 12A in which a plurality of semiconductor chips 13 are flip-chip connected to the first main surface is prepared (see FIG. 1A).
  • the semiconductor chip 13 can be formed by dicing a semiconductor wafer on which a predetermined circuit is formed by a known method.
  • a known device such as a flip chip bonder can be used for mounting the semiconductor chip 13 on the semiconductor wafer 12A.
  • flip chip connection is employed in which the active surface A1 on which the protruding electrode 13a of the semiconductor chip 13 is formed faces the semiconductor wafer 12A.
  • the semiconductor chip 13 and the semiconductor wafer 12A are electrically connected to each other through bump electrode electrodes 13a formed on the semiconductor chip 13 and through electrodes 12a provided on the semiconductor wafer 12A.
  • a TSV (Through Silicon Via) type electrode can be preferably used as the through-electrode 12a.
  • an underfill material 14 is filled between the semiconductor chip 13 and the semiconductor wafer 12A in order to reduce the difference in thermal expansion coefficient between the semiconductor chip 13 and the semiconductor wafer 12A, in particular, to prevent the occurrence of cracks or the like at the connection site.
  • a known material may be used as the underfill material 14.
  • the underfill material 14 may be arranged by injecting the liquid underfill material 14 between the semiconductor chips 13 after the semiconductor chip 13 is mounted on the semiconductor wafer 12A.
  • the semiconductor chip with the sheet-like underfill material 14 may be disposed. 13 or the semiconductor wafer 12A may be prepared, and the semiconductor chip 13 and the semiconductor wafer 12A may be connected to each other.
  • the sealing resin sheet 11 is laminated on the semiconductor wafer 12A so as to embed the semiconductor chip 13, and the semiconductor chip 13 is resin-sealed with the sealing resin sheet (see FIG. 1B).
  • the sealing resin sheet 11 functions as a sealing resin for protecting the semiconductor chip 13 and its accompanying elements from the external environment.
  • the method for laminating the sealing resin sheet 11 is not particularly limited, and a melt-kneaded product of the resin composition for forming the sealing resin sheet is extruded, and the extruded product is placed on the semiconductor wafer 12A and pressed.
  • the coating film is dried. Examples include a method of forming the sealing resin sheet 11 and transferring the sealing resin sheet 11 onto the semiconductor wafer 12A.
  • the sealing resin sheet 11 by adopting the sealing resin sheet 11, the semiconductor chip 13 can be embedded simply by sticking the semiconductor chip 13 on the semiconductor wafer 12 ⁇ / b> A, thereby improving the production efficiency of the semiconductor package. Can do.
  • the sealing resin sheet 11 can be laminated on the semiconductor wafer 12A by a known method such as compression using a flat plate press, a laminator, or a mold. It is preferable to perform a sealing process by the flat plate press with respect to the sealing resin sheet 11, or compression molding. Thereby, the surface of the sealing resin sheet 11 of the laminate 16B (see FIG. 1D) of the sealing resin sheet 11 and the ground semiconductor wafer 12B can be smoothed, and the rising of the ground surface of the semiconductor wafer 12B can be accurately performed.
  • a hot press using a flat plate press is preferable.
  • the temperature is, for example, 40 to 120 ° C., preferably 50 to 100 ° C.
  • the pressure is, for example, 50 to 2500 kPa, preferably 100 to 2000 kPa
  • the time is, for example, 0 3 to 10 minutes, preferably 0.5 to 5 minutes.
  • it is preferable to press under reduced pressure conditions for example, 10 to 2000 Pa).
  • the temperature is, for example, 40 to 200 ° C., preferably 60 to 160 ° C.
  • the pressure is, for example, 100 to 6000 kPa, preferably 500 to 5000 kPa
  • the time is, for example, 0.5 to 20 minutes, preferably 1 to 15 minutes.
  • the sealing resin sheet is thermally cured to form the sealing body 15 in which the semiconductor chip 13 is embedded in the sealing resin sheet 11 (see FIG. 1B).
  • the conditions for the thermosetting treatment of the sealing resin sheet are preferably 100 to 200 ° C., more preferably 120 to 180 ° C. as the heating temperature, and preferably 10 to 180 minutes, more preferably 30 to 120 minutes as the heating time. You may pressurize as needed. In the pressurization, preferably 0.1 MPa to 10 MPa, more preferably 0.5 MPa to 5 MPa can be employed. Thereby, since this sealing body formation process is included in a sealing process, a sealing process is completed here.
  • a grinding process may be performed in which the sealing resin sheet 11 of the sealing body 15 is ground so that the surface opposite to the active surface A of the semiconductor chip 13 is exposed to form a grinding body 16A (FIG. 1C).
  • the semiconductor chip 13 may be ground together with the sealing resin sheet 11 as shown in FIG. 1C, or only the sealing resin sheet 11 may be ground. Grinding may be performed using a known grinding apparatus.
  • a procedure for forming the grinding body 16A by grinding the surface of the sealing body while feeding the sealing body 15 while rotating a grinding tool such as a diamond tool can be suitably employed. This step can be omitted depending on the specifications of the target semiconductor package.
  • the back surface grinding step In the back surface grinding step, the surface opposite to the grinding surface G1 of the grinding body 16A (that is, the back surface B1) is ground (see FIG. 1D). Thereby, the exposed 2nd main surface (surface on the opposite side to the surface which laminated
  • Laminated body 16B of encapsulating resin sheet 11 and ground semiconductor wafer 12B (Note that when encapsulating resin sheet 11 is ground and semiconductor chip 13 is exposed as shown in FIG.
  • the difference between the thickness T max of the thickest thickest part of the semiconductor chip 13 and the thickness T min of the thinnest thinnest part is 20 ⁇ m or less, preferably 10 ⁇ m or less, and more preferably 5 ⁇ m or less.
  • the lower limit of the thickness difference is preferably 0 ⁇ m, but may be 1 ⁇ m or more as long as it does not affect circuit element formation.
  • the bulge occurs only in the resin sheet region corresponding to the space between the leftmost semiconductor chip and the central semiconductor chip among the illustrated semiconductor chips. Instead of the region or together with the resin sheet region, the resin sheet region corresponding to another semiconductor chip may be raised. When a plurality of swells occur on the ground surface of the semiconductor wafer, the thickness difference is obtained with reference to a portion where the thickness of the stacked body 16B is maximum.
  • a rewiring forming step of forming the rewiring 19 on the surface B1 on the active surface A1 side of the semiconductor chip 13 of the stacked body 16B (see FIG. 1E).
  • a rewiring 39 connected to the through electrode 12a of the semiconductor wafer 12B is formed on the stacked body 16B.
  • a metal seed layer is formed on the exposed semiconductor wafer 12B using a known method such as a vacuum film forming method, and the rewiring is performed by a known method such as a semi-additive method.
  • the wiring 19 can be formed.
  • an insulating layer such as polyimide or PBO may be formed on the rewiring 19 and the stacked body 16B.
  • bumping processing for forming bumps 17 on the formed rewiring 19 may be performed (see FIG. 1D).
  • the bumping process can be performed by a known method such as a solder ball or solder plating.
  • the material of the bump is not particularly limited.
  • tin-lead metal material tin-silver metal material, tin-silver-copper metal material, tin-zinc metal material, tin-zinc-bismuth metal material, etc.
  • Solders alloys
  • gold-based metal materials copper-based metal materials, and the like.
  • Chip back surface protection process When a surface opposite to the active surface A1 of the semiconductor chip 13 is exposed by performing a grinding process, the ground surface of the grinding body 16A is formed to protect the exposed surface 13S of the semiconductor chip 13 after the bumps 17 are formed. G1 (see FIG. 1C) may be resin-sealed again.
  • the sealing method is not particularly limited, and a known liquid or film-like sealing resin may be applied or bonded to the grinding surface G1, dried, and cured. When the grinding process is performed, this process may be performed at any stage after the grinding process and before the dicing process.
  • the grinding body 16C may be diced through bump formation including elements such as the sealing resin sheet 11, the semiconductor wafer 12B, and the semiconductor chip 13 (see FIG. 1G).
  • the semiconductor package 18 can be obtained in the target semiconductor chip 13 unit.
  • dicing is performed corresponding to one semiconductor chip, but dicing may be performed with two or more semiconductor chips as a unit. Dicing is usually performed after the grinding body 16C is fixed by a conventionally known dicing sheet.
  • the alignment of the cut portion may be performed by image recognition using direct illumination or indirect illumination.
  • a cutting method called full cut that cuts up to a dicing sheet can be adopted. It does not specifically limit as a dicing apparatus used at this process, A conventionally well-known thing can be used.
  • the expanding device when expanding a grinding body following a dicing process, this expansion can be performed using a conventionally well-known expanding apparatus.
  • the expanding device includes a donut-shaped outer ring that can push down the dicing sheet through the dicing ring, and an inner ring that has a smaller diameter than the outer ring and supports the dicing sheet.
  • a substrate mounting step of mounting the semiconductor package 18 obtained above on a separate substrate can be performed.
  • a known device such as a flip chip bonder or a die bonder can be used.
  • FIG. 2 is a cross-sectional view schematically showing a sealing resin sheet according to an embodiment of the present invention.
  • the sealing resin sheet 11 is typically provided in a state of being laminated on a support 11a such as a polyethylene terephthalate (PET) film. Note that a release treatment may be applied to the support 11a in order to easily peel off the sealing resin sheet 11.
  • PET polyethylene terephthalate
  • the Shore D hardness at 25 ° C. of the encapsulating resin sheet 11 after performing the thermosetting treatment at 150 ° C. for 1 hour is preferably 60 or more, and more preferably 70 or more.
  • the upper limit of the Shore D hardness is preferably 92 or less.
  • the storage elastic modulus in 25 degreeC of the sealing resin sheet 11 after performing a thermosetting process at 150 degreeC for 1 hour is 3 GPa or more, and it is more preferable that it is 10 GPa or more.
  • the upper limit of the storage elastic modulus is preferably 30 GPa or less.
  • the Shore D hardness and storage elastic modulus of the encapsulating resin sheet 11 after the thermosetting treatment By setting the Shore D hardness and storage elastic modulus of the encapsulating resin sheet 11 after the thermosetting treatment to the above ranges, the difference between the hardness of the semiconductor chip in the chip overlap region and the hardness of the encapsulating resin sheet in the resin sheet region is reduced. Thus, the thickness difference can be reduced.
  • the resin composition for forming the sealing resin sheet is not particularly limited as long as it has the above-described characteristics and can be used for resin sealing of electronic components such as semiconductor chips.
  • An epoxy resin composition containing an A component to an E component is preferable.
  • the C component may or may not be added as necessary.
  • the epoxy resin (component A) is not particularly limited.
  • Various epoxy resins such as an epoxy resin, a phenol novolac type epoxy resin, and a phenoxy resin can be used. These epoxy resins may be used alone or in combination of two or more.
  • a modified bisphenol A type epoxy resin having a flexible skeleton such as an acetal group or a polyoxyalkylene group is preferable, and a modified bisphenol A type epoxy resin having an acetal group is in a liquid state and is easy to handle. Therefore, it can be particularly preferably used.
  • the content of the epoxy resin (component A) is preferably set in the range of 1 to 10% by weight with respect to the entire epoxy resin composition.
  • the phenol resin (component B) is not particularly limited as long as it causes a curing reaction with the epoxy resin (component A).
  • a phenol novolak resin, a phenol aralkyl resin, a biphenyl aralkyl resin, a dicyclopentadiene type phenol resin, a cresol novolak resin, a resole resin, or the like is used. These phenolic resins may be used alone or in combination of two or more.
  • phenol resin those having a hydroxyl equivalent weight of 70 to 250 and a softening point of 50 to 110 ° C. are preferably used from the viewpoint of reactivity with the epoxy resin (component A), and above all, from the viewpoint of high curing reactivity.
  • a phenol novolac resin can be preferably used. From the viewpoint of reliability, low hygroscopic materials such as phenol aralkyl resins and biphenyl aralkyl resins can also be suitably used.
  • the blending ratio of the epoxy resin (component A) and the phenol resin (component B) is a hydroxyl group in the phenol resin (component B) with respect to 1 equivalent of the epoxy group in the epoxy resin (component A). It is preferable to blend so that the total amount becomes 0.7 to 1.5 equivalents, more preferably 0.9 to 1.2 equivalents.
  • the total content of the epoxy resin and the phenol resin in the sealing resin sheet 11 is preferably 2.5% by weight or more, and more preferably 3.0% by weight or more. Adhesive force with respect to the semiconductor chip 13, the semiconductor wafer 12A, etc. is obtained favorably as it is 2.5 wt% or more.
  • the total content of the epoxy resin and the phenol resin in the sealing resin sheet 11 is preferably 20% by weight or less, and more preferably 10% by weight or less. Hygroscopicity can be reduced as it is 20 weight% or less.
  • the elastomer (component C) used together with the epoxy resin (component A) and the phenol resin (component B) provides the epoxy resin composition with the flexibility necessary for sealing electronic components with a sealing resin sheet.
  • the structure is not particularly limited as long as such an effect is exhibited.
  • various acrylic copolymers such as polyacrylates, styrene acrylate copolymers, butadiene rubber, styrene-butadiene rubber (SBR), ethylene-vinyl acetate copolymer (EVA), isoprene rubber, acrylonitrile rubber, etc. Polymers can be used.
  • the heat resistance and strength of the resulting sealing resin sheet can be improved. It is preferable to use an acrylic copolymer. These may be used alone or in combination of two or more.
  • the acrylic copolymer can be synthesized, for example, by radical polymerization of an acrylic monomer mixture having a predetermined mixing ratio by a conventional method.
  • a method for radical polymerization a solution polymerization method in which an organic solvent is used as a solvent or a suspension polymerization method in which polymerization is performed while dispersing raw material monomers in water are used.
  • polymerization initiator used in this case examples include 2,2′-azobisisobutyronitrile, 2,2′-azobis- (2,4-dimethylvaleronitrile), and 2,2′-azobis-4- Methoxy-2,4-dimethylvaleronitrile, other azo or diazo polymerization initiators, peroxide polymerization initiators such as benzoyl peroxide and methyl ethyl ketone peroxide are used.
  • a dispersing agent such as polyacrylamide or polyvinyl alcohol.
  • the content of the elastomer (component C) is 15 to 30% by weight of the entire epoxy resin composition.
  • the content of the elastomer (component C) is less than 15% by weight, it becomes difficult to obtain the flexibility and flexibility of the sealing resin sheet 11, and it is also difficult to perform resin sealing while suppressing warping of the sealing resin sheet. It becomes.
  • the content exceeds 30% by weight, the melt viscosity of the sealing resin sheet 11 is increased, the embedding property of the semiconductor chip 13 is lowered, and the strength and heat resistance of the cured body of the sealing resin sheet 11 are reduced. There is a tendency to decrease.
  • the weight ratio of the elastomer (component C) to the epoxy resin (component A) is preferably set in the range of 3 to 4.7.
  • weight ratio is less than 3, it is difficult to control the fluidity of the sealing resin sheet 11, and when it exceeds 4.7, the adhesion of the sealing resin sheet 11 to the semiconductor chip 13 tends to be inferior. Because it is.
  • the inorganic filler (component D) is not particularly limited, and various conventionally known fillers can be used.
  • silica powder is used in that the internal stress is reduced by reducing the coefficient of thermal expansion of the cured product of the epoxy resin composition, and as a result, warpage of the sealing resin sheet 11 after sealing of the electronic component can be suppressed.
  • a fused silica powder among the silica powders examples include spherical fused silica powder and crushed fused silica powder. From the viewpoint of fluidity, it is particularly preferable to use a spherical fused silica powder. Among them, those having an average particle diameter in the range of 0.1 to 30 ⁇ m are preferably used, and those in the range of 1 to 20 ⁇ m are more preferable.
  • the average particle diameter can be derived by using a sample arbitrarily extracted from the population and measuring it using a laser diffraction / scattering particle size distribution measuring apparatus.
  • the content of the inorganic filler (component D) is preferably 70 to 95% by weight of the entire epoxy resin composition, more preferably 75 to 92% by weight, and still more preferably 80 to 90% by weight.
  • the content of the inorganic filler (component D) is less than 50% by weight, the linear expansion coefficient of the cured product of the epoxy resin composition increases, and thus the warpage of the sealing resin sheet 11 tends to increase.
  • liquidity of the sealing resin sheet 11 will worsen when the said content exceeds 90 weight%, the tendency for adhesiveness with a semiconductor chip to fall is seen.
  • the curing accelerator (component E) is not particularly limited as long as it allows curing of the epoxy resin and the phenol resin, but from the viewpoint of curability and storage stability, triphenylphosphine or tetraphenylphosphonium tetraphenyl. Organic phosphorus compounds such as borates and imidazole compounds are preferably used. These curing accelerators may be used alone or in combination with other curing accelerators.
  • the content of the curing accelerator (component E) is preferably 0.1 to 5 parts by weight with respect to a total of 100 parts by weight of the epoxy resin (component A) and the phenol resin (component B).
  • a flame retardant component may be added to the epoxy resin composition.
  • various metal hydroxides such as aluminum hydroxide, magnesium hydroxide, iron hydroxide, calcium hydroxide, tin hydroxide, and complex metal hydroxide can be used.
  • the average particle diameter of the metal hydroxide is preferably 1 to 10 ⁇ m, more preferably 2 to 5 ⁇ m, from the viewpoint of ensuring appropriate fluidity when the epoxy resin composition is heated. It is.
  • the average particle size of the metal hydroxide is less than 1 ⁇ m, it becomes difficult to uniformly disperse in the epoxy resin composition, and the fluidity during heating of the epoxy resin composition tends to be insufficient.
  • the surface area per addition amount of a metal hydroxide (E component) will become small when an average particle diameter exceeds 10 micrometers, the tendency for a flame-retardant effect to fall is seen.
  • a phosphazene compound can be used in addition to the above metal hydroxide.
  • phosphazene compounds for example, SPR-100, SA-100, SP-100 (above, Otsuka Chemical Co., Ltd.), FP-100, FP-110 (above, Fushimi Pharmaceutical Co., Ltd.) and the like are commercially available. is there.
  • the phosphazene compound represented by the formula (1) or the formula (2) is preferable from the viewpoint of exhibiting a flame retardant effect even in a small amount, and the content of phosphorus element contained in these phosphanzene compounds is 12% by weight or more. Is preferred.
  • n is an integer of 3 to 25
  • R 1 and R 2 are the same or different and are selected from the group consisting of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group.
  • a monovalent organic group having (In the formula (2), n and m are each independently an integer of 3 to 25.
  • R 3 and R 5 are the same or different and are composed of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group.
  • R 4 is a divalent organic group having a functional group selected from the group consisting of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group. .
  • n is an integer of 3 to 25
  • R 6 and R 7 are the same or different and are hydrogen, a hydroxyl group, an alkyl group, an alkoxy group, or a glycidyl group.
  • the cyclic phosphazene oligomer represented by the above formula (3) is commercially available, for example, FP-100, FP-110 (above, Fushimi Pharmaceutical Co., Ltd.) and the like.
  • the content of the phosphazene compound includes the epoxy resin (component A), phenol resin (component B), elastomer (component D), curing accelerator (component E) and phosphazene compound (other components) contained in the epoxy resin composition. It is preferably 10 to 30% by weight of the total organic component containing. That is, when the content of the phosphazene compound is less than 10% by weight of the total organic component, the flame retardancy of the sealing resin sheet 11 is reduced and the unevenness followability to an adherend (semiconductor wafer on which a semiconductor chip is mounted) or the like. Tends to decrease, and voids tend to occur. When the content exceeds 30% by weight of the whole organic component, tackiness is likely to occur on the surface of the sealing resin sheet 11, and the workability tends to be lowered, such as difficulty in alignment with the adherend.
  • the sealing resin sheet 11 having excellent flame retardancy while ensuring the flexibility necessary for sealing the sheet.
  • sufficient flame retardancy when only the metal hydroxide is used and sufficient flexibility can be obtained when only the phosphazene compound is used.
  • organic flame retardants are used from the viewpoint of the deformability of the sealing resin sheet at the time of molding the resin seal, the conformity to the unevenness of the adherend, and the adhesion to the semiconductor chip or the semiconductor wafer.
  • phosphazene flame retardants are preferably used.
  • the epoxy resin composition can be appropriately mixed with other additives such as pigments including carbon black as necessary.
  • an epoxy resin composition is prepared by mixing the above-described components.
  • the mixing method is not particularly limited as long as each component is uniformly dispersed and mixed.
  • a varnish in which each component is dissolved or dispersed in an organic solvent or the like is applied to form a sheet.
  • a kneaded material may be prepared by directly kneading each compounding component with a kneader or the like, and the kneaded material thus obtained may be extruded to form a sheet.
  • the above components A to E and other additives as necessary are mixed as appropriate according to a conventional method, and uniformly dissolved or dispersed in an organic solvent to prepare a varnish.
  • the sealing resin sheet 11 can be obtained by applying the varnish on a support such as polyester and drying it. If necessary, a release sheet such as a polyester film may be bonded to protect the surface of the sealing resin sheet. The release sheet peels at the time of sealing.
  • the organic solvent is not particularly limited, and various conventionally known organic solvents such as methyl ethyl ketone, acetone, cyclohexanone, dioxane, diethyl ketone, toluene, and ethyl acetate can be used. These may be used alone or in combination of two or more. Usually, it is preferable to use an organic solvent so that the solid content concentration of the varnish is in the range of 30 to 60% by weight.
  • the thickness of the sheet after drying the organic solvent is not particularly limited, but is usually preferably set to 5 to 100 ⁇ m, more preferably 20 to 70 ⁇ m, from the viewpoint of thickness uniformity and the amount of residual solvent. is there.
  • the above components A to E and, if necessary, each component of other additives are mixed using a known method such as a mixer, and then kneaded to prepare a kneaded product.
  • the method of melt kneading is not particularly limited, and examples thereof include a method of melt kneading with a known kneader such as a mixing roll, a pressure kneader, or an extruder.
  • the kneading conditions are not particularly limited as long as the temperature is equal to or higher than the softening point of each component described above.
  • thermosetting property of the epoxy resin it is preferably 40 to 140 ° C., more preferably The temperature is 60 to 120 ° C., and the time is, for example, 1 to 30 minutes, preferably 5 to 15 minutes. Thereby, a kneaded material can be prepared.
  • the sealing resin sheet 11 can be obtained by molding the obtained kneaded material by extrusion molding. Specifically, the encapsulating resin sheet 11 can be formed by extrusion molding without cooling the kneaded product after melt-kneading while maintaining a high temperature state.
  • Such an extrusion method is not particularly limited, and examples thereof include a T-die extrusion method, a roll rolling method, a roll kneading method, a co-extrusion method, and a calendar molding method.
  • the extrusion temperature is not particularly limited as long as it is equal to or higher than the softening point of each component described above. However, considering the thermosetting property and moldability of the epoxy resin, for example, 40 to 150 ° C., preferably 50 to 140 ° C. Preferably, it is 70 to 120 ° C.
  • the sealing resin sheet 11 can be formed.
  • the encapsulating resin sheet obtained in this way may be used by being laminated so as to have a desired thickness if necessary. That is, the sealing resin sheet may be used in a single layer structure, or may be used as a laminate formed by laminating two or more multilayer structures.
  • Example 1 (Preparation of sealing resin sheet) The following components were blended with a mixer, melt kneaded at 120 ° C. for 2 minutes with a twin-screw kneader, and then extruded from a T-die to prepare a sealing resin sheet A having a thickness of 500 ⁇ m.
  • Epoxy resin Bisphenol F type epoxy resin (manufactured by Nippon Steel Chemical Co., Ltd., YSLV-80XY (epochine equivalent 200 g / eq. Softening point 80 ° C.)) 286 parts
  • Phenol resin phenol resin having biphenylaralkyl skeleton (Maywa Kasei Co., Ltd.) Manufactured by MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.)
  • Curing accelerator imidazole catalyst as a curing catalyst (manufactured by Shikoku Chemicals Co., Ltd., 2PHZ-PW) 6 parts
  • Inorganic Filler Spherical fused silica powder (manufactured by Denki Kagaku Kogyo Co., Ltd., FB-9454, average particle size 20 ⁇ m) 3695 parts
  • Silane coupling agent Epoxy group-containing silane coupling agent
  • Example 2 Preparation of sealing resin sheet
  • the following components were blended with a mixer, melt-kneaded at 120 ° C. for 2 minutes with a twin-screw kneader, and then extruded from a T die to prepare a sealing resin sheet B having a thickness of 500 ⁇ m.
  • Epoxy resin Bisphenol F type epoxy resin (manufactured by Nippon Steel Chemical Co., Ltd., YSLV-80XY (epochine equivalent 200 g / eq. Softening point 80 ° C.)) 169 parts
  • Phenol resin phenol resin having biphenylaralkyl skeleton (Maywa Kasei Co., Ltd.) Manufactured by MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.) 179 parts
  • Curing accelerator imidazole catalyst as a curing catalyst (manufactured by Shikoku Kasei Co., Ltd., 2PHZ-PW) 6 parts
  • Elastomer Styrene-isobutylene-styrene triblock copolymer (manufactured by Kaneka Corp., SIBSTAR 072T) 152 parts
  • Inorganic filler spherical fused silica
  • the storage elastic modulus was measured using a solid viscoelasticity measuring apparatus (manufactured by Rheometric Scientific: model: RSA-III). Specifically, each sealing resin sheet is heated and cured at 150 ° C. for 1 hour, and a measurement sample is obtained from the cured product with a sample size of 400 mm long ⁇ 2 mm wide ⁇ 80 ⁇ m thick, and then the measurement sample.
  • a film tension measuring jig was set in a film tension measuring jig, and the storage elastic modulus and loss elastic modulus in the temperature range of ⁇ 50 to 300 ° C. were measured under the conditions of a frequency of 1 Hz and a heating rate of 10 ° C./min. It was obtained by reading the storage modulus (E ′).
  • a chip mounting interposer was prepared in which a semiconductor chip having the following specifications was flip-chip mounted on a silicon interposer, and the space between the chip and the interposer was sealed with a bisphenol A type epoxy thermosetting underfill material.
  • Each of the sealing resin sheets A to C was pasted on the obtained chip mounting interposer by a vacuum flat plate press under the following heating and pressing conditions.
  • the sealing resin sheet was thermally cured in a hot air dryer at 150 ° C. for 1 hour to obtain a sealing body.
  • the thickness of the semiconductor chip is obtained by grinding using a cutting device (manufactured by DISCO Corporation, surface planar “DFS8910”) under the conditions of a peripheral speed of the grinding tool of 1000 m / min, a feed pitch of 100 ⁇ m, and a cutting depth of 10 ⁇ m.
  • the exposed surface of the silicon interposer of the obtained grinding body (the surface opposite to the surface on which the sealing resin sheet was bonded) was removed with a grinding device (“DGP8761” manufactured by DISCO) and the thickness of the silicon interposer was 100 ⁇ m. It grinded until it became, and the laminated body was formed.
  • DISCO grinding device
  • polyamic acid obtained by reacting 3,4 ', 3,4'-biphenyltetracarboxylic dianhydride, 4,4'-diaminodiphenyl ether, paraphenylenediamine
  • polyimide layer having a thickness of 10 ⁇ m.
  • An opening was formed by laser processing at a position corresponding to the through-silicon via to expose the via.
  • a gold film and a nickel film were sequentially formed on the surface of the polyimide layer including the opening by plating.
  • sputtering is performed in the order of chromium and copper to form a seed film (chrome layer thickness 20 nm, copper layer thickness 100 nm), and a rewiring layer having a predetermined wiring pattern is formed by electrolytic copper plating.
  • a semiconductor package was produced.
  • the thickness difference of the laminate of the sealing resin sheet and the silicon interposer is 20 ⁇ m or less, so rewiring as a circuit surface element of the semiconductor package
  • the semiconductor package of Comparative Example 1 has a thickness difference exceeding 20 ⁇ m, resulting in poor rewiring formability.
  • Example 3 In the sealing process of manufacturing a semiconductor package using the sealing resin sheet A of Example 1, instead of the vacuum flat plate press, a compression molding apparatus WCM-300 (manufactured by Apic Yamada) was placed on the obtained chip mounting interposer. Measurement and rewiring of the difference between the thickness of the thickest part and the thickness of the thinnest part in the same manner as in Example 1 except that the sealing resin sheet A was pasted under the following molding conditions. The formability of was evaluated. The results are shown in Table 2.

Abstract

Provided is a semiconductor package manufacturing method whereby a circuit element to be formed can be formed, at an excellent yield, on a polished surface of a semiconductor wafer after polishing a sealed body having a sealing resin sheet used therein. This semiconductor package manufacturing method includes: a preparation step, wherein a semiconductor wafer having one or a plurality of semiconductor chips mounted on a first main surface is prepared; a sealing step, wherein the semiconductor chips are sealed by laminating a sealing resin sheet on the first main surface of the semiconductor wafer such that the semiconductor chips are embedded; and a rear surface polishing step, wherein a second main surface of the semiconductor wafer is polished, said second main surface being on the reverse side of the first main surface. In a laminated body of the sealing resin sheet and the polished semiconductor wafer, a difference between the thickness of a thickest part and that of a thinnest part is equal to or less than 20 μm.

Description

半導体パッケージの製造方法Manufacturing method of semiconductor package
　本発明は、半導体パッケージの製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor package.
　近年、電子機器の小型化、軽量化、高機能化の要求が高まっており、それに応じて電子機器を構成するパッケージについても小型化、薄型化、高密度実装が求められている。 In recent years, there has been an increasing demand for downsizing, weight reduction, and high functionality of electronic devices, and accordingly, packages that make up electronic devices are also required to be downsized, thinned, and mounted with high density.
　半導体パッケージの作製には、代表的に、半導体ウェハに固定された電子部品を封止樹脂にて封止し、必要に応じて封止物を電子部品単位のパッケージとなるようにダイシングするという手順が採用されている。このような過程の中で、上記要求に応えるべく、樹脂封止後に封止樹脂や半導体ウェハを研削して薄型化を図る技術が提案されている（例えば、特許文献１、２）。フリップチップＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）、フリップチップＳｉＰ（Ｓｙｓｔｅｍ　ｉｎ　Ｐａｃｋａｇｅ）、ファンイン型ウェハレベルパッケージ、ファンアウト型ウェハレベルパッケージ等の薄型半導体パッケージの製造工程においては、こうした研削による薄型化も重要な要素となる。 Typically, a semiconductor package is manufactured by sealing an electronic component fixed to a semiconductor wafer with a sealing resin, and dicing the sealed product into a package for each electronic component as necessary. Is adopted. In such a process, in order to meet the above-described requirements, a technique for reducing the thickness by grinding a sealing resin or a semiconductor wafer after resin sealing has been proposed (for example, Patent Documents 1 and 2). Thinning by grinding is also important in the manufacturing process of thin semiconductor packages such as flip chip BGA (Ball Grid Array), flip chip SiP (System in Package), fan-in type wafer level package, and fan out type wafer level package. Become an element.
特開２００９－１１０９９５号公報JP 2009-110995 A 国際公開第２０１２／０５３４６３号International Publication No. 2012/053463
　しかしながら、封止後の半導体ウェハの研削後、研削面に対して再配線やバンプ等の回路要素を形成するプロセスを施そうとしても、所望の再配線やバンプを形成することができなかったり、再配線形成後に再配線の剥離が生じたりするという不具合が生じる場合があることが判明した。これらの不具合は、上記特許文献１の技術では認識されておらず、その解決が望まれている。 However, after grinding the sealed semiconductor wafer, even if an attempt is made to form a circuit element such as rewiring or bump on the ground surface, the desired rewiring or bump cannot be formed, It has been found that there may be a problem that the rewiring is peeled off after the rewiring is formed. These inconveniences are not recognized by the technique of the above-mentioned patent document 1, and the solution is desired.
　本発明の目的は、封止樹脂シートを用いた封止体の研削後に半導体ウェハの研削面に目的とする回路要素を歩留まり良く形成可能な半導体パッケージの製造方法を提供することにある。 An object of the present invention is to provide a semiconductor package manufacturing method capable of forming a target circuit element on a ground surface of a semiconductor wafer with high yield after grinding of a sealing body using a sealing resin sheet.
　本発明者らは、半導体ウェハの研削面の平坦性が回路要素形成に影響を及ぼすとの考えに基づき、鋭意検討した結果、以下の構成により上記課題を解決できることを見出し、本発明を完成させた。 As a result of intensive studies based on the idea that the flatness of the ground surface of a semiconductor wafer affects the formation of circuit elements, the present inventors have found that the above problem can be solved by the following configuration, and completed the present invention. It was.
　すなわち、本発明は、第１主面に一又は複数の半導体チップが搭載された半導体ウェハを準備する準備工程、
　前記半導体チップを埋め込むように前記半導体ウェハの第１主面に封止樹脂シートを積層して前記半導体チップを封止する封止工程、及び
　前記半導体ウェハの第１主面とは反対側の第２主面を研削する裏面研削工程を含み、
　前記封止樹脂シートと前記研削された半導体ウェハとの積層体の最も厚い最厚部の厚さと最も薄い最薄部の厚さとの差が２０μｍ以下である半導体パッケージの製造方法である。 That is, the present invention provides a preparation step of preparing a semiconductor wafer having one or more semiconductor chips mounted on the first main surface,
A sealing step of sealing the semiconductor chip by laminating a sealing resin sheet on the first main surface of the semiconductor wafer so as to embed the semiconductor chip; and a first step opposite to the first main surface of the semiconductor wafer. 2 including a back grinding process to grind the main surface,
In this method, the difference between the thickness of the thickest thickest part and the thinnest thinnest part of the laminate of the sealing resin sheet and the ground semiconductor wafer is 20 μm or less.
　本発明者らは、回路要素の形成の際に不具合が生じる原因が、研削後の半導体ウェハの回路要素を形成する第２主面の状態、特に表面の盛り上がりにあることを突き止めた。このような盛り上がりは、半導体ウェハの研削時に生じると考えられる。すなわち、半導体ウェハの第２主面の研削は、封止樹脂シート側を固定面として封止体を裏面研削テープ等の固定手段に固定して行われる。このとき、半導体ウェハの第２主面と固定手段との間には、半導体チップが介在する領域と半導体チップが介在しない領域が混在している。これらを固定面側として半導体ウェハを研削すると、封止樹脂シートの硬度と半導体チップの硬度とは互いに異なることから、両者の硬度差に起因して研削加工の際の圧力が半導体ウェハに対して一様に負荷されなくなる。一般的に半導体チップの硬度は硬化後の封止樹脂シートの硬度より高いことから、半導体ウェハと固定手段との間に半導体チップが介在する領域では半導体チップが介在する分封止樹脂シートからの反発力が強くなって半導体ウェハはより深く（薄く）研削されやすくなり、反対に半導体ウェハと固定手段との間に半導体チップが介在しない領域（封止樹脂シートのみが介在する領域）では封止樹脂シートからの反発力が弱くなって半導体ウェハはより浅く（厚く）研削されやすくなる。このように研削後の半導体ウェハにおける厚さのバラツキに起因して半導体ウェハの研削面における盛り上がりが生じると推測される。当該製造方法では、封止樹脂シートと研削された半導体ウェハとの積層体（以下、単に「積層体」ともいう。）の最も厚い最厚部の厚さと最も薄い最薄部の厚さとの差（以下、単に「厚さ差」ともいう。）を２０μｍ以下としているので、半導体ウェハの研削面の盛り上がりの発生を抑制して十分な平坦性を確保することができ、その結果、目的とする回路要素を効率良く形成することができる。上記厚さ差が２０μｍを超えると、上述の回路要素形成の際の不具合が生じる場合がある。 The inventors of the present invention have found out that the cause of the trouble in forming the circuit element is the state of the second main surface forming the circuit element of the semiconductor wafer after grinding, particularly the bulge of the surface. Such a bulge is considered to occur during grinding of the semiconductor wafer. That is, the grinding of the second main surface of the semiconductor wafer is performed by fixing the sealing body to a fixing means such as a back surface grinding tape with the sealing resin sheet side as a fixed surface. At this time, a region where the semiconductor chip is interposed and a region where the semiconductor chip is not interposed are mixed between the second main surface of the semiconductor wafer and the fixing means. When the semiconductor wafer is ground using these as the fixed surface side, the hardness of the sealing resin sheet and the hardness of the semiconductor chip are different from each other. It will not be uniformly loaded. Since the hardness of the semiconductor chip is generally higher than the hardness of the encapsulated resin sheet after curing, the repulsion from the encapsulated resin sheet in the region where the semiconductor chip intervenes between the semiconductor wafer and the fixing means. The semiconductor wafer is deeply (thinly) easily ground due to the increased force, and conversely, the sealing resin in the region where the semiconductor chip is not interposed between the semiconductor wafer and the fixing means (the region where only the sealing resin sheet is interposed) The repulsive force from the sheet is weakened, and the semiconductor wafer becomes shallower (thicker) and more easily ground. Thus, it is presumed that the ground surface of the semiconductor wafer rises due to the thickness variation in the semiconductor wafer after grinding. In this manufacturing method, the difference between the thickness of the thickest thickest part and the thickness of the thinnest thinnest part of the laminated body (hereinafter also simply referred to as “laminated body”) of the encapsulating resin sheet and the ground semiconductor wafer. (Hereinafter, also simply referred to as “thickness difference”) is 20 μm or less, it is possible to suppress the occurrence of swell of the ground surface of the semiconductor wafer and ensure sufficient flatness. Circuit elements can be formed efficiently. If the thickness difference exceeds 20 μm, there may be a problem in forming the circuit element described above.
　前記封止工程は、前記封止樹脂シートに対する平板プレス又は圧縮成形により行うことが好ましい。これにより積層体の封止樹脂シートの表面を平滑化することができ、半導体ウェハの研削面の盛り上がりを精度良く測定しかつ制御することができる。 The sealing step is preferably performed by flat plate pressing or compression molding on the sealing resin sheet. Thereby, the surface of the sealing resin sheet of a laminated body can be smoothed, and the bulge of the grinding surface of a semiconductor wafer can be measured and controlled accurately.
　前記積層体の最厚部は、前記半導体ウェハを平面視で透視した際に該半導体ウェハと前記半導体チップとが重複しない領域（以下、「樹脂シート領域」ともいう。また、半導体ウェハを平面視で透視した際に半導体ウェハと半導体チップとが重複する領域を「チップ重複領域」ともいう。）に位置していてもよい。上述のように、半導体ウェハと固定手段との間に半導体チップが介在しない領域（すなわち、樹脂シート領域）は比較的浅く研削されやすい。言い換えると、樹脂シート領域では、半導体ウェハはより厚く研削やすいことになる。当該製造方法では積層体の厚さ差を抑制しているので、半導体ウェハの研削面への回路要素形成を歩留まり良く行うことができる。 The thickest portion of the laminate is also referred to as a region where the semiconductor wafer and the semiconductor chip do not overlap when the semiconductor wafer is seen through in plan view (hereinafter also referred to as “resin sheet region”. The region where the semiconductor wafer and the semiconductor chip overlap when viewed through is also referred to as a “chip overlapping region”). As described above, the region where the semiconductor chip is not interposed between the semiconductor wafer and the fixing means (that is, the resin sheet region) is relatively shallow and easily ground. In other words, in the resin sheet region, the semiconductor wafer is thicker and easier to grind. In the manufacturing method, since the thickness difference of the stacked body is suppressed, circuit elements can be formed on the ground surface of the semiconductor wafer with a high yield.
　１５０℃で１時間熱硬化処理を施した後の前記封止樹脂シートの２５℃におけるショアＤ硬度が６０以上であることが好ましい。また、１５０℃で１時間熱硬化処理を施した後の前記封止樹脂シートの２５℃における貯蔵弾性率が３ＧＰａ以上であることが好ましい。当該製造方法において、上記ショアＤ硬度及び／又は上記貯蔵弾性率を上記範囲とすることにより、チップ重複領域と樹脂シート領域との硬度差を小さくして半導体ウェハの研削面における上記盛り上がりを抑制することができ、その結果、該研削面での回路要素の形成効率を向上させることができる。 The Shore D hardness at 25 ° C. of the encapsulating resin sheet after being subjected to thermosetting treatment at 150 ° C. for 1 hour is preferably 60 or more. Moreover, it is preferable that the storage elastic modulus in 25 degreeC of the said sealing resin sheet after performing a thermosetting process at 150 degreeC for 1 hour is 3 GPa or more. In the manufacturing method, by setting the Shore D hardness and / or the storage elastic modulus within the above range, the hardness difference between the chip overlap region and the resin sheet region is reduced to suppress the above-described swell on the ground surface of the semiconductor wafer. As a result, the formation efficiency of the circuit elements on the ground surface can be improved.
　前記研削工程後、前記半導体チップの研削された第２主面に再配線を形成する再配線形成工程をさらに含んでいてもよい。 After the grinding step, a rewiring forming step for forming a rewiring on the ground second main surface of the semiconductor chip may be further included.
　当該製造方法では、前記半導体チップが複数用いられており、
　前記再配線形成工程後に、前記半導体ウェハを前記封止樹脂シートとともに目的の半導体チップ単位でダイシングするダイシング工程をさらに含んでいてもよい。 In the manufacturing method, a plurality of the semiconductor chips are used,
A dicing step of dicing the semiconductor wafer together with the sealing resin sheet in units of a target semiconductor chip may be further included after the rewiring formation step.
　本発明には、当該半導体パッケージの製造方法により得られる半導体パッケージも含まれる。 The present invention includes a semiconductor package obtained by the method for manufacturing the semiconductor package.
本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。It is sectional drawing which shows typically 1 process of the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る封止樹脂シートを模式的に示す断面図である。It is sectional drawing which shows typically the sealing resin sheet which concerns on one Embodiment of this invention.
　本発明の半導体パッケージの製造方法の実施形態について、図面を参照しながら以下に説明する。ただし、図の一部又は全部において、説明に不要な部分は省略し、また説明を容易にするために拡大または縮小等して図示した部分がある。 Embodiments of a method for manufacturing a semiconductor package of the present invention will be described below with reference to the drawings. However, in some or all of the drawings, parts unnecessary for the description are omitted, and there are parts shown enlarged or reduced for easy explanation.
　［半導体パッケージの製造方法］
　封止樹脂シートを用いる本実施形態に係る半導体パッケージの製造方法について図１Ａ～図１Ｇを参照しつつ説明する。図１Ａ～図１Ｇはそれぞれ、本発明の一実施形態に係る半導体パッケージの製造方法の一工程を模式的に示す断面図である。本実施形態では、半導体ウェハ上に搭載された半導体チップを封止樹脂シートにより樹脂封止して半導体パッケージを作製する。本実施形態に係る半導体パッケージの製造方法は、チップ・オン・ウェハ（ＣＯＷ）プロセスに好適である。 [Semiconductor package manufacturing method]
A method of manufacturing a semiconductor package according to this embodiment using a sealing resin sheet will be described with reference to FIGS. 1A to 1G. 1A to 1G are cross-sectional views schematically showing one process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. In this embodiment, a semiconductor chip is manufactured by sealing a semiconductor chip mounted on a semiconductor wafer with a sealing resin sheet. The semiconductor package manufacturing method according to the present embodiment is suitable for a chip-on-wafer (COW) process.
　（チップ搭載ウェハ準備工程）
　チップ搭載ウェハ準備工程では、複数の半導体チップ１３が第１主面にフリップチップ接続された半導体ウェハ１２Ａを準備する（図１Ａ参照）。半導体チップ１３は、所定の回路が形成された半導体ウェハを公知の方法でダイシングして個片化することにより形成することができる。半導体チップ１３の半導体ウェハ１２Ａへの搭載には、フリップチップボンダーなどの公知の装置を用いることができる。本実施形態では、半導体チップ１３の突起電極１３ａが形成された活性面Ａ１が半導体ウェハ１２Ａと対向するフリップチップ接続を採用している。半導体チップ１３に形成されたバンプ等の突起電極１３ａと、半導体ウェハ１２Ａに設けられた貫通電極１２ａとを介して、半導体チップ１３と半導体ウェハ１２Ａとが電気的に接続されている。貫通電極１２ａは、ＴＳＶ（Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）形式の電極を好適に用いることができる。 (Chip mounting wafer preparation process)
In the chip mounting wafer preparation step, a semiconductor wafer 12A in which a plurality of semiconductor chips 13 are flip-chip connected to the first main surface is prepared (see FIG. 1A). The semiconductor chip 13 can be formed by dicing a semiconductor wafer on which a predetermined circuit is formed by a known method. For mounting the semiconductor chip 13 on the semiconductor wafer 12A, a known device such as a flip chip bonder can be used. In the present embodiment, flip chip connection is employed in which the active surface A1 on which the protruding electrode 13a of the semiconductor chip 13 is formed faces the semiconductor wafer 12A. The semiconductor chip 13 and the semiconductor wafer 12A are electrically connected to each other through bump electrode electrodes 13a formed on the semiconductor chip 13 and through electrodes 12a provided on the semiconductor wafer 12A. As the through-electrode 12a, a TSV (Through Silicon Via) type electrode can be preferably used.
　また、半導体チップ１３と半導体ウェハ１２Ａとの間には両者の熱膨張率の差を緩和して特に接続部位におけるクラック等の発生を防止するためのアンダーフィル材１４が充填されている。アンダーフィル材１４としては公知のものを用いればよい。アンダーフィル材１４の配置は、半導体チップ１３の半導体ウェハ１２Ａへの搭載後、両者間に液状のアンダーフィル材１４を注入させることにより行ってもよく、シート状のアンダーフィル材１４付きの半導体チップ１３又は半導体ウェハ１２Ａを用意した上で、半導体チップ１３と半導体ウェハ１２Ａとを接続することにより行ってもよい。 In addition, an underfill material 14 is filled between the semiconductor chip 13 and the semiconductor wafer 12A in order to reduce the difference in thermal expansion coefficient between the semiconductor chip 13 and the semiconductor wafer 12A, in particular, to prevent the occurrence of cracks or the like at the connection site. A known material may be used as the underfill material 14. The underfill material 14 may be arranged by injecting the liquid underfill material 14 between the semiconductor chips 13 after the semiconductor chip 13 is mounted on the semiconductor wafer 12A. The semiconductor chip with the sheet-like underfill material 14 may be disposed. 13 or the semiconductor wafer 12A may be prepared, and the semiconductor chip 13 and the semiconductor wafer 12A may be connected to each other.
　（封止工程）
　封止工程では、半導体チップ１３を埋め込むように半導体ウェハ１２Ａへ封止樹脂シート１１を積層し、半導体チップ１３を上記封止樹脂シートで樹脂封止する（図１Ｂ参照）。この封止樹脂シート１１は、半導体チップ１３及びそれに付随する要素を外部環境から保護するための封止樹脂として機能する。 (Sealing process)
In the sealing step, the sealing resin sheet 11 is laminated on the semiconductor wafer 12A so as to embed the semiconductor chip 13, and the semiconductor chip 13 is resin-sealed with the sealing resin sheet (see FIG. 1B). The sealing resin sheet 11 functions as a sealing resin for protecting the semiconductor chip 13 and its accompanying elements from the external environment.
　封止樹脂シート１１の積層方法としては特に限定されず、封止樹脂シートを形成するための樹脂組成物の溶融混練物を押出成形し、押出成形物を半導体ウェハ１２Ａ上に載置してプレスすることにより封止樹脂シート１１の形成と積層とを一括にて行う方法や、封止樹脂シート１１を形成するための樹脂組成物を離型処理シート上に塗布し、塗布膜を乾燥させて封止樹脂シート１１を形成した上で、この封止樹脂シート１１を半導体ウェハ１２Ａ上に転写する方法などが挙げられる。 The method for laminating the sealing resin sheet 11 is not particularly limited, and a melt-kneaded product of the resin composition for forming the sealing resin sheet is extruded, and the extruded product is placed on the semiconductor wafer 12A and pressed. By applying the resin composition for forming the encapsulating resin sheet 11 and laminating at once or the resin composition for forming the encapsulating resin sheet 11 on the release treatment sheet, the coating film is dried. Examples include a method of forming the sealing resin sheet 11 and transferring the sealing resin sheet 11 onto the semiconductor wafer 12A.
　本実施形態では、上記封止樹脂シート１１を採用することにより、半導体チップ１３の被覆に半導体ウェハ１２Ａ上に貼り付けるだけで半導体チップ１３を埋め込むことができ、半導体パッケージの生産効率を向上させることができる。この場合、平板プレスやラミネータ、金型を用いる圧縮成形など公知の方法により封止樹脂シート１１を半導体ウェハ１２Ａ上に積層することができる。封止工程は、封止樹脂シート１１に対する平板プレス又は圧縮成形により行うことが好ましい。これにより封止樹脂シート１１と研削した半導体ウェハ１２Ｂとの積層体１６Ｂ（図１Ｄ参照）の封止樹脂シート１１の表面を平滑化することができ、半導体ウェハ１２Ｂの研削面の盛り上がりを精度良く測定しかつ制御することができる。中でも、平板プレスによる熱プレスが好ましい。熱プレス条件としては、温度が、例えば、４０～１２０℃、好ましくは、５０～１００℃であり、圧力が、例えば、５０～２５００ｋＰａ、好ましくは、１００～２０００ｋＰａであり、時間が、例えば、０．３～１０分間、好ましくは、０．５～５分間である。また、封止樹脂シート１１の半導体チップ１３及び半導体ウェハ１２Ａへの密着性および追従性の向上を考慮すると、好ましくは、減圧条件下（例えば１０～２０００Ｐａ）において、プレスすることが好ましい。なお、圧縮成形条件としては、温度が、例えば、４０～２００℃、好ましくは、６０～１６０℃であり、圧力が、例えば、１００～６０００ｋＰａ、好ましくは、５００～５０００ｋＰａであり、時間が、例えば、０．５～２０分間、好ましくは、１～１５分間である。 In the present embodiment, by adopting the sealing resin sheet 11, the semiconductor chip 13 can be embedded simply by sticking the semiconductor chip 13 on the semiconductor wafer 12 </ b> A, thereby improving the production efficiency of the semiconductor package. Can do. In this case, the sealing resin sheet 11 can be laminated on the semiconductor wafer 12A by a known method such as compression using a flat plate press, a laminator, or a mold. It is preferable to perform a sealing process by the flat plate press with respect to the sealing resin sheet 11, or compression molding. Thereby, the surface of the sealing resin sheet 11 of the laminate 16B (see FIG. 1D) of the sealing resin sheet 11 and the ground semiconductor wafer 12B can be smoothed, and the rising of the ground surface of the semiconductor wafer 12B can be accurately performed. Can be measured and controlled. Among these, a hot press using a flat plate press is preferable. As hot press conditions, the temperature is, for example, 40 to 120 ° C., preferably 50 to 100 ° C., the pressure is, for example, 50 to 2500 kPa, preferably 100 to 2000 kPa, and the time is, for example, 0 3 to 10 minutes, preferably 0.5 to 5 minutes. Further, in consideration of improvement in the adhesion and followability of the sealing resin sheet 11 to the semiconductor chip 13 and the semiconductor wafer 12A, it is preferable to press under reduced pressure conditions (for example, 10 to 2000 Pa). As compression molding conditions, the temperature is, for example, 40 to 200 ° C., preferably 60 to 160 ° C., the pressure is, for example, 100 to 6000 kPa, preferably 500 to 5000 kPa, and the time is, for example, 0.5 to 20 minutes, preferably 1 to 15 minutes.
　（封止体形成工程）
　封止体形成工程では、上記封止樹脂シートを熱硬化処理して半導体チップ１３が封止樹脂シート１１に埋め込まれた封止体１５を形成する（図１Ｂ参照）。封止樹脂シートの熱硬化処理の条件は、加熱温度として好ましくは１００℃から２００℃、より好ましくは１２０℃から１８０℃、加熱時間として好ましくは１０分から１８０分、より好ましくは３０分から１２０分の間、必要に応じて加圧しても良い。加圧の際は、好ましくは０．１ＭＰａから１０ＭＰａ、より好ましくは０．５ＭＰａから５ＭＰａを採用することができる。これにより、この封止体形成工程は封止工程に含まれるので、封止工程はここで完了する。 (Sealing body forming process)
In the sealing body forming step, the sealing resin sheet is thermally cured to form the sealing body 15 in which the semiconductor chip 13 is embedded in the sealing resin sheet 11 (see FIG. 1B). The conditions for the thermosetting treatment of the sealing resin sheet are preferably 100 to 200 ° C., more preferably 120 to 180 ° C. as the heating temperature, and preferably 10 to 180 minutes, more preferably 30 to 120 minutes as the heating time. You may pressurize as needed. In the pressurization, preferably 0.1 MPa to 10 MPa, more preferably 0.5 MPa to 5 MPa can be employed. Thereby, since this sealing body formation process is included in a sealing process, a sealing process is completed here.
　（研削工程）
　次に、封止体１５の封止樹脂シート１１を半導体チップ１３の活性面Ａとは反対側の表面が露出するように研削して研削体１６Ａを形成する研削工程を行ってもよい（図１Ｃ参照）。研削の際、図１Ｃに示すように封止樹脂シート１１とともに半導体チップ１３も研削してもよく、封止樹脂シート１１のみを研削してもよい。研削は公知の研削装置を用いて行えばよい。ダイアモンドバイト等の研削バイトを回転させながら、そこに封止体１５を送りつつ封止体表面を研削して研削体１６Ａを形成する手順を好適に採用することができる。本工程は、目的とする半導体パッケージの仕様に応じて省略することができる。 (Grinding process)
Next, a grinding process may be performed in which the sealing resin sheet 11 of the sealing body 15 is ground so that the surface opposite to the active surface A of the semiconductor chip 13 is exposed to form a grinding body 16A (FIG. 1C). During grinding, the semiconductor chip 13 may be ground together with the sealing resin sheet 11 as shown in FIG. 1C, or only the sealing resin sheet 11 may be ground. Grinding may be performed using a known grinding apparatus. A procedure for forming the grinding body 16A by grinding the surface of the sealing body while feeding the sealing body 15 while rotating a grinding tool such as a diamond tool can be suitably employed. This step can be omitted depending on the specifications of the target semiconductor package.
　（裏面研削工程）
　裏面研削工程では、研削体１６Ａの研削面Ｇ１とは反対側の面（すなわち、裏面Ｂ１）を研削する（図１Ｄ参照）。これにより、半導体ウェハ１２Ａの露出した第２主面（封止樹脂シート１１を積層した面とは反対側の面）を研削することになり、薄型化した半導体ウェハ１２Ｂを得ることができる。研削後の半導体ウェハ１２Ｂの厚さは目的とするパッケージの仕様により変更すればよく、例えば２５～２００μｍが好ましく、５０～１００μｍがより好ましい。研削は公知の研削装置を用いて行えばよい。研削体１６Ａは裏面研削用テープを用いて固定してもよく、この場合は裏面研削の際の研削面Ｇ１の汚染を防止することができる。裏面研削用テープは公知のものを用いることができる。 (Back grinding process)
In the back surface grinding step, the surface opposite to the grinding surface G1 of the grinding body 16A (that is, the back surface B1) is ground (see FIG. 1D). Thereby, the exposed 2nd main surface (surface on the opposite side to the surface which laminated | stacked the sealing resin sheet 11) of the semiconductor wafer 12A will be ground, and the semiconductor wafer 12B reduced in thickness can be obtained. What is necessary is just to change the thickness of the semiconductor wafer 12B after grinding according to the specification of the target package, for example, 25-200 μm is preferable, and 50-100 μm is more preferable. Grinding may be performed using a known grinding apparatus. The grinding body 16A may be fixed using a back surface grinding tape. In this case, contamination of the grinding surface G1 during back surface grinding can be prevented. A well-known thing can be used for the tape for back surface grinding.
　封止樹脂シート１１と研削された半導体ウェハ１２Ｂとの積層体１６Ｂ（なお、図１Ｄのように、封止樹脂シート１１を研削して半導体チップ１３が露出している場合、積層体１６Ｂには半導体チップ１３も含める。）の最も厚い最厚部の厚さＴｍａｘと最も薄い最薄部の厚さＴｍｉｎとの差は２０μｍ以下であり、１０μｍ以下が好ましく、５μｍ以下がより好ましい。厚さ差を上記範囲とすることにより、半導体ウェハ１２Ｂの研削面の盛り上がりの発生を抑制して十分な平坦性を確保することができ、その結果、目的とする回路要素を効率良く形成することができる。上記厚さ差の下限は０μｍが好ましいものの、回路要素形成に影響を及ぼさない限り１μｍ以上であってもよい。なお、本実施形態では、図示された半導体チップのうち最も左に位置する半導体チップと中央に位置する半導体チップとの間に対応する樹脂シート領域にのみ上記盛り上がりが生じているものの、この樹脂シート領域に代えて、又はこの樹脂シート領域とともに、他の半導体チップ間に対応する樹脂シート領域にも盛り上がりが生じることがある。半導体ウェハの研削面における盛り上がりが複数生じた場合には、この中でも積層体１６Ｂの厚さが最大となる部分を基準にして上記厚さ差を求める。 Laminated body 16B of encapsulating resin sheet 11 and ground semiconductor wafer 12B (Note that when encapsulating resin sheet 11 is ground and semiconductor chip 13 is exposed as shown in FIG. The difference between the thickness T max of the thickest thickest part of the semiconductor chip 13 and the thickness T min of the thinnest thinnest part is 20 μm or less, preferably 10 μm or less, and more preferably 5 μm or less. By setting the thickness difference within the above range, it is possible to suppress the occurrence of swell of the ground surface of the semiconductor wafer 12B and ensure sufficient flatness, and as a result, to efficiently form the target circuit element. Can do. The lower limit of the thickness difference is preferably 0 μm, but may be 1 μm or more as long as it does not affect circuit element formation. In the present embodiment, the bulge occurs only in the resin sheet region corresponding to the space between the leftmost semiconductor chip and the central semiconductor chip among the illustrated semiconductor chips. Instead of the region or together with the resin sheet region, the resin sheet region corresponding to another semiconductor chip may be raised. When a plurality of swells occur on the ground surface of the semiconductor wafer, the thickness difference is obtained with reference to a portion where the thickness of the stacked body 16B is maximum.
　（再配線形成工程）
　本実施形態ではさらに、積層体１６Ｂの半導体チップ１３の活性面Ａ１側の面Ｂ１に再配線１９を形成する再配線形成工程を含むことが好ましい（図１Ｅ参照）。再配線形成工程では、裏面研削による薄型化した半導体ウェハ１２Ｂの形成後、半導体ウェハ１２Ｂの貫通電極１２ａと接続する再配線３９を積層体１６Ｂ上に形成する。 (Rewiring process)
In the present embodiment, it is preferable to further include a rewiring forming step of forming the rewiring 19 on the surface B1 on the active surface A1 side of the semiconductor chip 13 of the stacked body 16B (see FIG. 1E). In the rewiring forming step, after the thinned semiconductor wafer 12B is formed by back grinding, a rewiring 39 connected to the through electrode 12a of the semiconductor wafer 12B is formed on the stacked body 16B.
　再配線の形成方法としては、例えば、露出している半導体ウェハ１２Ｂ上へ真空成膜法などの公知の方法を利用して金属シード層を形成し、セミアディティブ法などの公知の方法により、再配線１９を形成することができる。 As a method for forming the rewiring, for example, a metal seed layer is formed on the exposed semiconductor wafer 12B using a known method such as a vacuum film forming method, and the rewiring is performed by a known method such as a semi-additive method. The wiring 19 can be formed.
　かかる後に、再配線１９及び積層体１６Ｂ上へポリイミドやＰＢＯなどの絶縁層を形成してもよい。 Thereafter, an insulating layer such as polyimide or PBO may be formed on the rewiring 19 and the stacked body 16B.
　（バンプ形成工程）
　次いで、形成した再配線１９上にバンプ１７を形成するバンピング加工を行ってもよい（図１Ｄ参照）。バンピング加工は、半田ボールや半田メッキなど公知の方法で行うことができる。バンプの材質は特に限定されず、例えば、錫－鉛系金属材、錫－銀系金属材、錫－銀－銅系金属材、錫－亜鉛系金属材、錫－亜鉛－ビスマス系金属材等の半田類（合金）や、金系金属材、銅系金属材などが挙げられる。 (Bump formation process)
Next, bumping processing for forming bumps 17 on the formed rewiring 19 may be performed (see FIG. 1D). The bumping process can be performed by a known method such as a solder ball or solder plating. The material of the bump is not particularly limited. For example, tin-lead metal material, tin-silver metal material, tin-silver-copper metal material, tin-zinc metal material, tin-zinc-bismuth metal material, etc. Solders (alloys), gold-based metal materials, copper-based metal materials, and the like.
　（チップ裏面保護工程）
　研削工程を行って半導体チップ１３の活性面Ａ１とは反対側の表面を露出させた場合、バンプ１７を形成した後、半導体チップ１３の露出面１３Ｓを保護するために、研削体１６Ａの研削面Ｇ１（図１Ｃ参照）を再度樹脂封止してもよい。封止方法としては特に限定されず、公知の液状やフィルム状の封止樹脂を研削面Ｇ１に塗布ないし貼り合わせ、乾燥、硬化させればよい。なお研削工程を行った場合、本工程は、研削工程後であってダイシング工程前であればいずれの段階で行ってもよい。 (Chip back surface protection process)
When a surface opposite to the active surface A1 of the semiconductor chip 13 is exposed by performing a grinding process, the ground surface of the grinding body 16A is formed to protect the exposed surface 13S of the semiconductor chip 13 after the bumps 17 are formed. G1 (see FIG. 1C) may be resin-sealed again. The sealing method is not particularly limited, and a known liquid or film-like sealing resin may be applied or bonded to the grinding surface G1, dried, and cured. When the grinding process is performed, this process may be performed at any stage after the grinding process and before the dicing process.
　（ダイシング工程）
　続いて、封止樹脂シート１１、半導体ウェハ１２Ｂ、及び半導体チップ１３などの要素からなるバンプ形成を経た研削体１６Ｃのダイシングを行ってもよい（図１Ｇ参照）。これにより、目的とする半導体チップ１３単位での半導体パッケージ１８を得ることができる。図１Ｇでは、１つの半導体チップに対応させてダイシングしているが、２つ以上の半導体チップを一単位としてダイシングを行ってもよい。ダイシングは、通常、従来公知のダイシングシートにより上記研削体１６Ｃを固定した上で行う。切断箇所の位置合わせは直接照明又は間接照明を用いた画像認識により行ってもよい。 (Dicing process)
Subsequently, the grinding body 16C may be diced through bump formation including elements such as the sealing resin sheet 11, the semiconductor wafer 12B, and the semiconductor chip 13 (see FIG. 1G). As a result, the semiconductor package 18 can be obtained in the target semiconductor chip 13 unit. In FIG. 1G, dicing is performed corresponding to one semiconductor chip, but dicing may be performed with two or more semiconductor chips as a unit. Dicing is usually performed after the grinding body 16C is fixed by a conventionally known dicing sheet. The alignment of the cut portion may be performed by image recognition using direct illumination or indirect illumination.
　本工程では、例えば、ダイシングシートまで切込みを行うフルカットと呼ばれる切断方式等を採用できる。本工程で用いるダイシング装置としては特に限定されず、従来公知のものを用いることができる。 In this step, for example, a cutting method called full cut that cuts up to a dicing sheet can be adopted. It does not specifically limit as a dicing apparatus used at this process, A conventionally well-known thing can be used.
　なお、ダイシング工程に続いて研削体のエキスパンドを行う場合、該エキスパンドは従来公知のエキスパンド装置を用いて行うことができる。エキスパンド装置は、ダイシングリングを介してダイシングシートを下方へ押し下げることが可能なドーナッツ状の外リングと、外リングよりも径が小さくダイシングシートを支持する内リングとを有している。このエキスパンド工程により、隣り合う半導体パッケージ１８同士が接触して破損するのを防ぐことができる。 In addition, when expanding a grinding body following a dicing process, this expansion can be performed using a conventionally well-known expanding apparatus. The expanding device includes a donut-shaped outer ring that can push down the dicing sheet through the dicing ring, and an inner ring that has a smaller diameter than the outer ring and supports the dicing sheet. By this expanding process, it is possible to prevent the adjacent semiconductor packages 18 from coming into contact with each other and being damaged.
　（基板実装工程）
　必要に応じて、上記で得られた半導体パッケージ１８を別途の基板（図示せず）に実装する基板実装工程を行うことができる。半導体パッケージ１８の基板への実装には、フリップチップボンダーやダイボンダーなどの公知の装置を用いることができる。 (Board mounting process)
If necessary, a substrate mounting step of mounting the semiconductor package 18 obtained above on a separate substrate (not shown) can be performed. For mounting the semiconductor package 18 on the substrate, a known device such as a flip chip bonder or a die bonder can be used.
　［封止樹脂シート］
　本実施形態に係る封止樹脂シートについて図２を参照しつつ説明する。図２は、本発明の一実施形態に係る封止樹脂シートを模式的に示す断面図である。封止樹脂シート１１は、代表的に、ポリエチレンテレフタレート（ＰＥＴ）フィルム等の支持体１１ａ上に積層された状態で提供される。なお、支持体１１ａには封止樹脂シート１１の剥離を容易に行うために離型処理が施されていてもよい。 [Sealing resin sheet]
The sealing resin sheet according to the present embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view schematically showing a sealing resin sheet according to an embodiment of the present invention. The sealing resin sheet 11 is typically provided in a state of being laminated on a support 11a such as a polyethylene terephthalate (PET) film. Note that a release treatment may be applied to the support 11a in order to easily peel off the sealing resin sheet 11.
　また、１５０℃で１時間熱硬化処理を施した後の封止樹脂シート１１の２５℃におけるショアＤ硬度が６０以上であることが好ましく、７０以上であることがより好ましい。上記ショアＤ硬度の上限は９２以下であることが好ましい。さらに、１５０℃で１時間熱硬化処理を施した後の封止樹脂シート１１の２５℃における貯蔵弾性率が３ＧＰａ以上であることが好ましく、１０ＧＰａ以上であることがより好ましい。上記貯蔵弾性率の上限は３０ＧＰａ以下であることが好ましい。熱硬化処理後の封止樹脂シート１１のショアＤ硬度や貯蔵弾性率を上記範囲とすることにより、チップ重複領域における半導体チップの硬度と樹脂シート領域における封止樹脂シートの硬度との差を小さくすることができ、これにより上記厚さ差を小さくすることができる。 Further, the Shore D hardness at 25 ° C. of the encapsulating resin sheet 11 after performing the thermosetting treatment at 150 ° C. for 1 hour is preferably 60 or more, and more preferably 70 or more. The upper limit of the Shore D hardness is preferably 92 or less. Furthermore, it is preferable that the storage elastic modulus in 25 degreeC of the sealing resin sheet 11 after performing a thermosetting process at 150 degreeC for 1 hour is 3 GPa or more, and it is more preferable that it is 10 GPa or more. The upper limit of the storage elastic modulus is preferably 30 GPa or less. By setting the Shore D hardness and storage elastic modulus of the encapsulating resin sheet 11 after the thermosetting treatment to the above ranges, the difference between the hardness of the semiconductor chip in the chip overlap region and the hardness of the encapsulating resin sheet in the resin sheet region is reduced. Thus, the thickness difference can be reduced.
　（封止樹脂シートを形成する樹脂組成物）
　封止樹脂シートを形成する樹脂組成物は、上述のような特性を好適に有し、半導体チップ等の電子部品の樹脂封止に利用可能なものであれば、特に限定されないが、例えば以下のＡ成分からＥ成分を含有するエポキシ樹脂組成物が好ましいものとして挙げられる。なお、Ｃ成分は必要に応じて添加しても添加しなくてもよい。
　　Ａ成分：エポキシ樹脂
　　Ｂ成分：フェノール樹脂
　　Ｃ成分：エラストマー
　　Ｄ成分：無機充填剤
　　Ｅ成分：硬化促進剤 (Resin composition forming a sealing resin sheet)
The resin composition for forming the sealing resin sheet is not particularly limited as long as it has the above-described characteristics and can be used for resin sealing of electronic components such as semiconductor chips. An epoxy resin composition containing an A component to an E component is preferable. The C component may or may not be added as necessary.
A component: Epoxy resin B component: Phenol resin C component: Elastomer D component: Inorganic filler E component: Curing accelerator
　（Ａ成分）
　エポキシ樹脂（Ａ成分）としては、特に限定されるものではない。例えば、トリフェニルメタン型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、変性ビスフェノールＡ型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、変性ビスフェノールＦ型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、フェノキシ樹脂等の各種のエポキシ樹脂を用いることができる。これらエポキシ樹脂は単独で用いてもよいし２種以上併用してもよい。 (A component)
The epoxy resin (component A) is not particularly limited. For example, triphenylmethane type epoxy resin, cresol novolac type epoxy resin, biphenyl type epoxy resin, modified bisphenol A type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, modified bisphenol F type epoxy resin, dicyclopentadiene type Various epoxy resins such as an epoxy resin, a phenol novolac type epoxy resin, and a phenoxy resin can be used. These epoxy resins may be used alone or in combination of two or more.
　エポキシ樹脂の硬化後の靭性及びエポキシ樹脂の反応性を確保する観点からは、エポキシ当量１５０～２５０、軟化点もしくは融点が５０～１３０℃の常温で固形のものが好ましく、中でも、信頼性の観点から、トリフェニルメタン型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂が好ましい。 From the viewpoint of ensuring the toughness of the epoxy resin after curing and the reactivity of the epoxy resin, those having a solid at normal temperature having an epoxy equivalent of 150 to 250 and a softening point or melting point of 50 to 130 ° C. are preferable. Therefore, triphenylmethane type epoxy resin, cresol novolac type epoxy resin, and biphenyl type epoxy resin are preferable.
　また、低応力性の観点から、アセタール基やポリオキシアルキレン基等の柔軟性骨格を有する変性ビスフェノールＡ型エポキシ樹脂が好ましく、アセタール基を有する変性ビスフェノールＡ型エポキシ樹脂は、液体状で取り扱いが良好であることから、特に好適に用いることができる。 Also, from the viewpoint of low stress, a modified bisphenol A type epoxy resin having a flexible skeleton such as an acetal group or a polyoxyalkylene group is preferable, and a modified bisphenol A type epoxy resin having an acetal group is in a liquid state and is easy to handle. Therefore, it can be particularly preferably used.
　エポキシ樹脂（Ａ成分）の含有量は、エポキシ樹脂組成物全体に対して１～１０重量％の範囲に設定することが好ましい。 The content of the epoxy resin (component A) is preferably set in the range of 1 to 10% by weight with respect to the entire epoxy resin composition.
　（Ｂ成分）
　フェノール樹脂（Ｂ成分）は、エポキシ樹脂（Ａ成分）との間で硬化反応を生起するものであれば特に限定されるものではない。例えば、フェノールノボラック樹脂、フェノールアラルキル樹脂、ビフェニルアラルキル樹脂、ジシクロペンタジエン型フェノール樹脂、クレゾールノボラック樹脂、レゾール樹脂、等が用いられる。これらフェノール樹脂は単独で用いてもよいし、２種以上併用してもよい。 (B component)
The phenol resin (component B) is not particularly limited as long as it causes a curing reaction with the epoxy resin (component A). For example, a phenol novolak resin, a phenol aralkyl resin, a biphenyl aralkyl resin, a dicyclopentadiene type phenol resin, a cresol novolak resin, a resole resin, or the like is used. These phenolic resins may be used alone or in combination of two or more.
　フェノール樹脂としては、エポキシ樹脂（Ａ成分）との反応性の観点から、水酸基当量が７０～２５０、軟化点が５０～１１０℃のものを用いることが好ましく、中でも硬化反応性が高いという観点から、フェノールノボラック樹脂を好適に用いることができる。また、信頼性の観点から、フェノールアラルキル樹脂やビフェニルアラルキル樹脂のような低吸湿性のものも好適に用いることができる。 As the phenol resin, those having a hydroxyl equivalent weight of 70 to 250 and a softening point of 50 to 110 ° C. are preferably used from the viewpoint of reactivity with the epoxy resin (component A), and above all, from the viewpoint of high curing reactivity. A phenol novolac resin can be preferably used. From the viewpoint of reliability, low hygroscopic materials such as phenol aralkyl resins and biphenyl aralkyl resins can also be suitably used.
　エポキシ樹脂（Ａ成分）とフェノール樹脂（Ｂ成分）の配合割合は、硬化反応性という観点から、エポキシ樹脂（Ａ成分）中のエポキシ基１当量に対して、フェノール樹脂（Ｂ成分）中の水酸基の合計が０．７～１．５当量となるように配合することが好ましく、より好ましくは０．９～１．２当量である。 From the viewpoint of curing reactivity, the blending ratio of the epoxy resin (component A) and the phenol resin (component B) is a hydroxyl group in the phenol resin (component B) with respect to 1 equivalent of the epoxy group in the epoxy resin (component A). It is preferable to blend so that the total amount becomes 0.7 to 1.5 equivalents, more preferably 0.9 to 1.2 equivalents.
　封止樹脂シート１１中のエポキシ樹脂及びフェノール樹脂の合計含有量は、２．５重量％以上が好ましく、３．０重量％以上がより好ましい。２．５重量％以上であると、半導体チップ１３、半導体ウェハ１２Ａなどに対する接着力が良好に得られる。封止樹脂シート１１中のエポキシ樹脂及びフェノール樹脂の合計含有量は、２０重量％以下が好ましく、１０重量％以下がより好ましい。２０重量％以下であると、吸湿性を低減できる。 The total content of the epoxy resin and the phenol resin in the sealing resin sheet 11 is preferably 2.5% by weight or more, and more preferably 3.0% by weight or more. Adhesive force with respect to the semiconductor chip 13, the semiconductor wafer 12A, etc. is obtained favorably as it is 2.5 wt% or more. The total content of the epoxy resin and the phenol resin in the sealing resin sheet 11 is preferably 20% by weight or less, and more preferably 10% by weight or less. Hygroscopicity can be reduced as it is 20 weight% or less.
　（Ｃ成分）
　エポキシ樹脂（Ａ成分）及びフェノール樹脂（Ｂ成分）とともに用いられるエラストマー（Ｃ成分）は、封止樹脂シートによる電子部品の封止に必要な可撓性をエポキシ樹脂組成物に付与するものであり、このような作用を奏するものであれば特にその構造を限定するものではない。例えば、ポリアクリル酸エステル等の各種アクリル系共重合体、スチレンアクリレート系共重合体、ブタジエンゴム、スチレン－ブタジエンゴム（ＳＢＲ）、エチレン－酢酸ビニルコポリマー（ＥＶＡ）、イソプレンゴム、アクリロニトリルゴム等のゴム質重合体を用いることができる。中でも、エポキシ樹脂（Ａ成分）へ分散させやすく、またエポキシ樹脂（Ａ成分）との反応性も高いために、得られる封止樹脂シートの耐熱性や強度を向上させることができるという観点から、アクリル系共重合体を用いることが好ましい。これらは単独で用いてもよいし、２種以上併せて用いてもよい。 (C component)
The elastomer (component C) used together with the epoxy resin (component A) and the phenol resin (component B) provides the epoxy resin composition with the flexibility necessary for sealing electronic components with a sealing resin sheet. The structure is not particularly limited as long as such an effect is exhibited. For example, various acrylic copolymers such as polyacrylates, styrene acrylate copolymers, butadiene rubber, styrene-butadiene rubber (SBR), ethylene-vinyl acetate copolymer (EVA), isoprene rubber, acrylonitrile rubber, etc. Polymers can be used. Among them, from the viewpoint that it is easy to disperse in the epoxy resin (component A), and because the reactivity with the epoxy resin (component A) is high, the heat resistance and strength of the resulting sealing resin sheet can be improved. It is preferable to use an acrylic copolymer. These may be used alone or in combination of two or more.
　なお、アクリル系共重合体は、例えば、所定の混合比にしたアクリルモノマー混合物を、定法によってラジカル重合することにより合成することができる。ラジカル重合の方法としては、有機溶剤を溶媒に行う溶液重合法や、水中に原料モノマーを分散させながら重合を行う懸濁重合法が用いられる。その際に用いる重合開始剤としては、例えば、２，２’－アゾビスイソブチロニトリル、２，２’－アゾビス－（２，４－ジメチルバレロニトリル）、２，２’－アゾビス－４－メトキシ－２，４－ジメチルバレロニトリル、その他のアゾ系又はジアゾ系重合開始剤、ベンゾイルパーオキサイド及びメチルエチルケトンパーオキサイド等の過酸化物系重合開始剤等が用いられる。なお、懸濁重合の場合は、例えばポリアクリルアミド、ポリビニルアルコールのような分散剤を加えることが望ましい。 The acrylic copolymer can be synthesized, for example, by radical polymerization of an acrylic monomer mixture having a predetermined mixing ratio by a conventional method. As a method for radical polymerization, a solution polymerization method in which an organic solvent is used as a solvent or a suspension polymerization method in which polymerization is performed while dispersing raw material monomers in water are used. Examples of the polymerization initiator used in this case include 2,2′-azobisisobutyronitrile, 2,2′-azobis- (2,4-dimethylvaleronitrile), and 2,2′-azobis-4- Methoxy-2,4-dimethylvaleronitrile, other azo or diazo polymerization initiators, peroxide polymerization initiators such as benzoyl peroxide and methyl ethyl ketone peroxide are used. In the case of suspension polymerization, it is desirable to add a dispersing agent such as polyacrylamide or polyvinyl alcohol.
　エラストマー（Ｃ成分）の含有量は、エポキシ樹脂組成物全体の１５～３０重量％である。エラストマー（Ｃ成分）の含有量が１５重量％未満では、封止樹脂シート１１の柔軟性及び可撓性を得るのが困難となり、さらには封止樹脂シートの反りを抑えた樹脂封止も困難となる。逆に上記含有量が３０重量％を超えると、封止樹脂シート１１の溶融粘度が高くなって半導体チップ１３の埋まり込み性が低下するとともに、封止樹脂シート１１の硬化体の強度及び耐熱性が低下する傾向がみられる。 The content of the elastomer (component C) is 15 to 30% by weight of the entire epoxy resin composition. When the content of the elastomer (component C) is less than 15% by weight, it becomes difficult to obtain the flexibility and flexibility of the sealing resin sheet 11, and it is also difficult to perform resin sealing while suppressing warping of the sealing resin sheet. It becomes. On the other hand, when the content exceeds 30% by weight, the melt viscosity of the sealing resin sheet 11 is increased, the embedding property of the semiconductor chip 13 is lowered, and the strength and heat resistance of the cured body of the sealing resin sheet 11 are reduced. There is a tendency to decrease.
　また、エラストマー（Ｃ成分）のエポキシ樹脂（Ａ成分）に対する重量比率（Ｃ成分の重量／Ａ成分の重量）は、３～４．７の範囲に設定することが好ましい。上記重量比率が３未満の場合は、封止樹脂シート１１の流動性をコントロールすることが困難となり、４．７を超えると封止樹脂シート１１の半導体チップ１３への接着性が劣る傾向がみられるためである。 Also, the weight ratio of the elastomer (component C) to the epoxy resin (component A) (weight of component C / weight of component A) is preferably set in the range of 3 to 4.7. When the weight ratio is less than 3, it is difficult to control the fluidity of the sealing resin sheet 11, and when it exceeds 4.7, the adhesion of the sealing resin sheet 11 to the semiconductor chip 13 tends to be inferior. Because it is.
　（Ｄ成分）
　無機質充填剤（Ｄ成分）は、特に限定されるものではなく、従来公知の各種充填剤を用いることができ、例えば、石英ガラス、タルク、シリカ（溶融シリカや結晶性シリカ等）、アルミナ、窒化アルミニウム、窒化珪素、窒化ホウ素の粉末が挙げられる。これらは単独で用いてもよいし、２種以上併用してもよい。 (D component)
The inorganic filler (component D) is not particularly limited, and various conventionally known fillers can be used. For example, quartz glass, talc, silica (fused silica, crystalline silica, etc.), alumina, nitriding Examples thereof include aluminum, silicon nitride, and boron nitride powders. These may be used alone or in combination of two or more.
　中でも、エポキシ樹脂組成物の硬化体の熱線膨張係数が低減することにより内部応力を低減し、その結果、電子部品の封止後の封止樹脂シート１１の反りを抑制できるという点から、シリカ粉末を用いることが好ましく、シリカ粉末の中でも溶融シリカ粉末を用いることがより好ましい。溶融シリカ粉末としては、球状溶融シリカ粉末、破砕溶融シリカ粉末が挙げられるが、流動性という観点から、球状溶融シリカ粉末を用いることが特に好ましい。中でも、平均粒径が０．１～３０μｍの範囲のものを用いることが好ましく、１～２０μｍの範囲のものを用いることがより好ましい。 Among these, silica powder is used in that the internal stress is reduced by reducing the coefficient of thermal expansion of the cured product of the epoxy resin composition, and as a result, warpage of the sealing resin sheet 11 after sealing of the electronic component can be suppressed. It is preferable to use a fused silica powder among the silica powders. Examples of the fused silica powder include spherical fused silica powder and crushed fused silica powder. From the viewpoint of fluidity, it is particularly preferable to use a spherical fused silica powder. Among them, those having an average particle diameter in the range of 0.1 to 30 μm are preferably used, and those in the range of 1 to 20 μm are more preferable.
　なお、平均粒径は、母集団から任意に抽出される試料を用い、レーザー回折散乱式粒度分布測定装置を用いて測定することにより導き出すことができる。 The average particle diameter can be derived by using a sample arbitrarily extracted from the population and measuring it using a laser diffraction / scattering particle size distribution measuring apparatus.
　無機質充填剤（Ｄ成分）の含有量は、好ましくはエポキシ樹脂組成物全体の７０～９５重量％であり、より好ましくは７５～９２重量％であり、さらに好ましくは８０～９０重量％である。無機質充填剤（Ｄ成分）の含有量が５０重量％未満では、エポキシ樹脂組成物の硬化体の線膨張係数が大きくなるために、封止樹脂シート１１の反りが大きくなる傾向がみられる。一方、上記含有量が９０重量％を超えると、封止樹脂シート１１の柔軟性や流動性が悪くなるために、半導体チップとの接着性が低下する傾向がみられる。 The content of the inorganic filler (component D) is preferably 70 to 95% by weight of the entire epoxy resin composition, more preferably 75 to 92% by weight, and still more preferably 80 to 90% by weight. When the content of the inorganic filler (component D) is less than 50% by weight, the linear expansion coefficient of the cured product of the epoxy resin composition increases, and thus the warpage of the sealing resin sheet 11 tends to increase. On the other hand, since the softness | flexibility and fluidity | liquidity of the sealing resin sheet 11 will worsen when the said content exceeds 90 weight%, the tendency for adhesiveness with a semiconductor chip to fall is seen.
　（Ｅ成分）
　硬化促進剤（Ｅ成分）は、エポキシ樹脂とフェノール樹脂の硬化を進行させるものであれば特に限定されるものではないが、硬化性と保存性の観点から、トリフェニルホスフィンやテトラフェニルホスホニウムテトラフェニルボレート等の有機リン系化合物や、イミダゾール系化合物が好適に用いられる。これら硬化促進剤は、単独で用いても良いし、他の硬化促進剤と併用しても構わない。 (E component)
The curing accelerator (component E) is not particularly limited as long as it allows curing of the epoxy resin and the phenol resin, but from the viewpoint of curability and storage stability, triphenylphosphine or tetraphenylphosphonium tetraphenyl. Organic phosphorus compounds such as borates and imidazole compounds are preferably used. These curing accelerators may be used alone or in combination with other curing accelerators.
　硬化促進剤（Ｅ成分）の含有量は、エポキシ樹脂（Ａ成分）及びフェノール樹脂（Ｂ成分）の合計１００重量部に対して０．１～５重量部であることが好ましい。 The content of the curing accelerator (component E) is preferably 0.1 to 5 parts by weight with respect to a total of 100 parts by weight of the epoxy resin (component A) and the phenol resin (component B).
　（その他の成分）
　また、エポキシ樹脂組成物には、Ａ成分からＥ成分に加えて、難燃剤成分を加えてもよい。難燃剤組成分としては、例えば水酸化アルミニウム、水酸化マグネシウム、水酸化鉄、水酸化カルシウム、水酸化スズ、複合化金属水酸化物等の各種金属水酸化物を用いることができる。 (Other ingredients)
In addition to the A component to the E component, a flame retardant component may be added to the epoxy resin composition. As the flame retardant composition, various metal hydroxides such as aluminum hydroxide, magnesium hydroxide, iron hydroxide, calcium hydroxide, tin hydroxide, and complex metal hydroxide can be used.
　金属水酸化物の平均粒径としては、エポキシ樹脂組成物を加熱した際に適当な流動性を確保するという観点から、平均粒径が１～１０μｍであることが好ましく、さらに好ましくは２～５μｍである。金属水酸化物の平均粒径が１μｍ未満では、エポキシ樹脂組成物中に均一に分散させることが困難となるとともに、エポキシ樹脂組成物の加熱時における流動性が十分に得られない傾向がある。また、平均粒径が１０μｍを超えると、金属水酸化物（Ｅ成分）の添加量あたりの表面積が小さくなるため、難燃効果が低下する傾向がみられる。 The average particle diameter of the metal hydroxide is preferably 1 to 10 μm, more preferably 2 to 5 μm, from the viewpoint of ensuring appropriate fluidity when the epoxy resin composition is heated. It is. When the average particle size of the metal hydroxide is less than 1 μm, it becomes difficult to uniformly disperse in the epoxy resin composition, and the fluidity during heating of the epoxy resin composition tends to be insufficient. Moreover, since the surface area per addition amount of a metal hydroxide (E component) will become small when an average particle diameter exceeds 10 micrometers, the tendency for a flame-retardant effect to fall is seen.
　また、難燃剤成分としては上記金属水酸化物のほか、ホスファゼン化合物を用いることができる。ホスファゼン化合物としては、例えばＳＰＲ－１００、ＳＡ－１００、ＳＰ－１００（以上、大塚化学株式会社）、ＦＰ－１００、ＦＰ－１１０（以上、株式会社伏見製薬所）等が市販品として入手可能である。 Further, as the flame retardant component, a phosphazene compound can be used in addition to the above metal hydroxide. As phosphazene compounds, for example, SPR-100, SA-100, SP-100 (above, Otsuka Chemical Co., Ltd.), FP-100, FP-110 (above, Fushimi Pharmaceutical Co., Ltd.) and the like are commercially available. is there.
　少量でも難燃効果を発揮するという観点から、式（１）又は式（２）で表されるホスファゼン化合物が好ましく、これらホスファンゼン化合物に含まれるリン元素の含有率は、１２重量％以上であることが好ましい。
Figure JPOXMLDOC01-appb-C000001
（式（１）中、ｎは３～２５の整数であり、Ｒ１及びＲ２は同一又は異なって、アルコキシ基、フェノキシ基、アミノ基、水酸基及びアリル基からなる群より選択される官能基を有する１価の有機基である。）
Figure JPOXMLDOC01-appb-C000002
（式（２）中、ｎ及びｍは、それぞれ独立して３～２５の整数である。Ｒ３及びＲ５は同一又は異なって、アルコキシ基、フェノキシ基、アミノ基、水酸基及びアリル基からなる群より選択される官能基を有する１価の有機基である。Ｒ４は、アルコキシ基、フェノキシ基、アミノ基、水酸基及びアリル基からなる群より選択される官能基を有する２価の有機基である。） The phosphazene compound represented by the formula (1) or the formula (2) is preferable from the viewpoint of exhibiting a flame retardant effect even in a small amount, and the content of phosphorus element contained in these phosphanzene compounds is 12% by weight or more. Is preferred.
Figure JPOXMLDOC01-appb-C000001
(In the formula (1), n is an integer of 3 to 25, and R 1 and R 2 are the same or different and are selected from the group consisting of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group. A monovalent organic group having
Figure JPOXMLDOC01-appb-C000002
(In the formula (2), n and m are each independently an integer of 3 to 25. R 3 and R 5 are the same or different and are composed of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group. R 4 is a divalent organic group having a functional group selected from the group consisting of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group. .)
　また、安定性及びボイドの生成抑制という観点から、式（３）で表される環状ホスファゼンオリゴマーを用いることが好ましい。
Figure JPOXMLDOC01-appb-C000003
（式（３）中、ｎは３～２５の整数であり、Ｒ６及びＲ７は同一又は異なって、水素、水酸基、アルキル基、アルコキシ基又はグリシジル基である。） Moreover, it is preferable to use the cyclic phosphazene oligomer represented by Formula (3) from a viewpoint of stability and suppression of void formation.
Figure JPOXMLDOC01-appb-C000003
(In the formula (3), n is an integer of 3 to 25, and R 6 and R 7 are the same or different and are hydrogen, a hydroxyl group, an alkyl group, an alkoxy group, or a glycidyl group.)
　上記式（３）で表される環状ホスファゼンオリゴマーは、例えばＦＰ－１００、ＦＰ－１１０（以上、株式会社伏見製薬所）等が市販品として入手可能である。 The cyclic phosphazene oligomer represented by the above formula (3) is commercially available, for example, FP-100, FP-110 (above, Fushimi Pharmaceutical Co., Ltd.) and the like.
　ホスファゼン化合物の含有量は、エポキシ樹脂組成物中に含まれるエポキシ樹脂（Ａ成分）、フェノール樹脂（Ｂ成分）、エラストマー（Ｄ成分）、硬化促進剤（Ｅ成分）及びホスファゼン化合物（その他の成分）を含む有機成分全体の１０～３０重量％であることが好ましい。すなわち、ホスファゼン化合物の含有量が、有機成分全体の１０重量％未満では、封止樹脂シート１１の難燃性が低下するとともに、被着体（半導体チップを搭載した半導体ウェハ）等に対する凹凸追従性が低下し、ボイドが発生する傾向がみられる。上記含有量が有機成分全体の３０重量％を超えると、封止樹脂シート１１の表面にタックが生じやすくなり、被着体に対する位置合わせをしにくくなる等作業性が低下する傾向がみられる。 The content of the phosphazene compound includes the epoxy resin (component A), phenol resin (component B), elastomer (component D), curing accelerator (component E) and phosphazene compound (other components) contained in the epoxy resin composition. It is preferably 10 to 30% by weight of the total organic component containing. That is, when the content of the phosphazene compound is less than 10% by weight of the total organic component, the flame retardancy of the sealing resin sheet 11 is reduced and the unevenness followability to an adherend (semiconductor wafer on which a semiconductor chip is mounted) or the like. Tends to decrease, and voids tend to occur. When the content exceeds 30% by weight of the whole organic component, tackiness is likely to occur on the surface of the sealing resin sheet 11, and the workability tends to be lowered, such as difficulty in alignment with the adherend.
　また、上記金属水酸化物及びホスファゼン化合物を併用し、シート封止に必要な可撓性を確保しつつ、難燃性に優れた封止樹脂シート１１を得ることもできる。両者を併用することにより、金属水酸化物のみを用いた場合の十分な難燃性と、ホスファゼン化合物のみを用いた場合は、十分な可撓性を得ることができる。 Also, by using the metal hydroxide and the phosphazene compound together, it is possible to obtain the sealing resin sheet 11 having excellent flame retardancy while ensuring the flexibility necessary for sealing the sheet. By using both in combination, sufficient flame retardancy when only the metal hydroxide is used and sufficient flexibility can be obtained when only the phosphazene compound is used.
　上記難燃剤のうち、樹脂封止の成型時における封止樹脂シートの変形性、被着体の凹凸への追従性、半導体チップや半導体ウェハへの密着性の点から有機系難燃剤を用いるのが望ましく、特にホスファゼン系難燃剤が好適に用いられる。 Among the above flame retardants, organic flame retardants are used from the viewpoint of the deformability of the sealing resin sheet at the time of molding the resin seal, the conformity to the unevenness of the adherend, and the adhesion to the semiconductor chip or the semiconductor wafer. In particular, phosphazene flame retardants are preferably used.
　なお、エポキシ樹脂組成物は、上記の各成分以外に必要に応じて、カーボンブラックをはじめとする顔料等、他の添加剤を適宜配合することができる。 In addition to the above components, the epoxy resin composition can be appropriately mixed with other additives such as pigments including carbon black as necessary.
　（封止樹脂シートの作製方法）
　封止樹脂シートの作製方法を以下に説明する。まず、上述の各成分を混合することによりエポキシ樹脂組成物を調製する。混合方法は、各成分が均一に分散混合される方法であれば特に限定するものではない。その後、例えば、各成分を有機溶剤等に溶解又は分散したワニスを塗工してシート状に形成する。あるいは、各配合成分を直接ニーダー等で混練することにより混練物を調製し、このようにして得られた混練物を押し出してシート状に形成してもよい。 (Method for producing sealing resin sheet)
A method for producing the sealing resin sheet will be described below. First, an epoxy resin composition is prepared by mixing the above-described components. The mixing method is not particularly limited as long as each component is uniformly dispersed and mixed. Thereafter, for example, a varnish in which each component is dissolved or dispersed in an organic solvent or the like is applied to form a sheet. Alternatively, a kneaded material may be prepared by directly kneading each compounding component with a kneader or the like, and the kneaded material thus obtained may be extruded to form a sheet.
　ワニスを用いる具体的な作製手順としては、上記Ａ～Ｅ成分及び必要に応じて他の添加剤を常法に準じて適宜混合し、有機溶剤に均一に溶解あるいは分散させ、ワニスを調製する。ついで、上記ワニスをポリエステル等の支持体上に塗布し乾燥させることにより封止樹脂シート１１を得ることができる。そして必要により、封止樹脂シートの表面を保護するためにポリエステルフィルム等の剥離シートを貼り合わせてもよい。剥離シートは封止時に剥離する。 As a specific production procedure using a varnish, the above components A to E and other additives as necessary are mixed as appropriate according to a conventional method, and uniformly dissolved or dispersed in an organic solvent to prepare a varnish. Subsequently, the sealing resin sheet 11 can be obtained by applying the varnish on a support such as polyester and drying it. If necessary, a release sheet such as a polyester film may be bonded to protect the surface of the sealing resin sheet. The release sheet peels at the time of sealing.
　上記有機溶剤としては、特に限定されるものではなく従来公知の各種有機溶剤、例えばメチルエチルケトン、アセトン、シクロヘキサノン、ジオキサン、ジエチルケトン、トルエン、酢酸エチル等を用いることができる。これらは単独で用いてもよいし、２種以上併せて用いてもよい。また通常、ワニスの固形分濃度が３０～６０重量％の範囲となるように有機溶剤を用いることが好ましい。 The organic solvent is not particularly limited, and various conventionally known organic solvents such as methyl ethyl ketone, acetone, cyclohexanone, dioxane, diethyl ketone, toluene, and ethyl acetate can be used. These may be used alone or in combination of two or more. Usually, it is preferable to use an organic solvent so that the solid content concentration of the varnish is in the range of 30 to 60% by weight.
　有機溶剤乾燥後のシートの厚みは、特に制限されるものではないが、厚みの均一性と残存溶剤量の観点から、通常、５～１００μｍに設定することが好ましく、より好ましくは２０～７０μｍである。 The thickness of the sheet after drying the organic solvent is not particularly limited, but is usually preferably set to 5 to 100 μm, more preferably 20 to 70 μm, from the viewpoint of thickness uniformity and the amount of residual solvent. is there.
　一方、混練を用いる場合には、上記Ａ～Ｅ成分及び必要に応じて他の添加剤の各成分をミキサーなど公知の方法を用いて混合し、その後、溶融混練することにより混練物を調製する。溶融混練する方法としては、特に限定されないが、例えば、ミキシングロール、加圧式ニーダー、押出機などの公知の混練機により、溶融混練する方法などが挙げられる。混練条件としては、温度が、上記した各成分の軟化点以上であれば特に制限されず、例えば３０～１５０℃、エポキン樹脂の熱硬化性を考慮すると、好ましくは４０～１４０℃、さらに好ましくは６０～１２０℃であり、時間が、例えば１～３０分間、好ましくは５～１５分間である。これによって、混練物を調製することができる。 On the other hand, when kneading is used, the above components A to E and, if necessary, each component of other additives are mixed using a known method such as a mixer, and then kneaded to prepare a kneaded product. . The method of melt kneading is not particularly limited, and examples thereof include a method of melt kneading with a known kneader such as a mixing roll, a pressure kneader, or an extruder. The kneading conditions are not particularly limited as long as the temperature is equal to or higher than the softening point of each component described above. For example, considering the thermosetting property of the epoxy resin, it is preferably 40 to 140 ° C., more preferably The temperature is 60 to 120 ° C., and the time is, for example, 1 to 30 minutes, preferably 5 to 15 minutes. Thereby, a kneaded material can be prepared.
　得られる混練物を押出成形により成形することにより、封止樹脂シート１１を得ることができる。具体的には、溶融混練後の混練物を冷却することなく高温状態のままで、押出成形することで、封止樹脂シート１１を形成することができる。このような押出方法としては、特に制限されず、Ｔダイ押出法、ロール圧延法、ロール混練法、共押出法、カレンダー成形法などが挙げられる。押出温度としては、上記した各成分の軟化点以上であれば、特に制限されないが、エポキシ樹脂の熱硬化性および成形性を考慮すると、例えば４０～１５０℃、好ましくは、５０～１４０℃、さらに好ましくは７０～１２０℃である。以上により、封止樹脂シート１１を形成することができる。 The sealing resin sheet 11 can be obtained by molding the obtained kneaded material by extrusion molding. Specifically, the encapsulating resin sheet 11 can be formed by extrusion molding without cooling the kneaded product after melt-kneading while maintaining a high temperature state. Such an extrusion method is not particularly limited, and examples thereof include a T-die extrusion method, a roll rolling method, a roll kneading method, a co-extrusion method, and a calendar molding method. The extrusion temperature is not particularly limited as long as it is equal to or higher than the softening point of each component described above. However, considering the thermosetting property and moldability of the epoxy resin, for example, 40 to 150 ° C., preferably 50 to 140 ° C. Preferably, it is 70 to 120 ° C. As described above, the sealing resin sheet 11 can be formed.
　このようにして得られた封止樹脂シートは、必要により所望の厚みとなるように積層して使用してもよい。すなわち、封止樹脂シートは、単層構造にて使用してもよいし、２層以上の多層構造に積層してなる積層体として使用してもよい。 The encapsulating resin sheet obtained in this way may be used by being laminated so as to have a desired thickness if necessary. That is, the sealing resin sheet may be used in a single layer structure, or may be used as a laminate formed by laminating two or more multilayer structures.
　以下に、この発明の好適な実施例を例示的に詳しく説明する。ただし、この実施例に記載されている材料や配合量等は、特に限定的な記載がない限りは、この発明の範囲をそれらのみに限定する趣旨のものではない。また、部とあるのは、重量部を意味する。 Hereinafter, preferred embodiments of the present invention will be described in detail by way of example. However, the materials, blending amounts, and the like described in this example are not intended to limit the scope of the present invention only to those unless otherwise specified. The term “parts” means parts by weight.
［実施例１］
　（封止樹脂シートの作製）
　以下の成分をミキサーにてブレンドし、２軸混練機により１２０℃で２分間溶融混練し、続いてＴダイから押出しすることにより、厚さ５００μｍの封止樹脂シートＡを作製した。 [Example 1]
(Preparation of sealing resin sheet)
The following components were blended with a mixer, melt kneaded at 120 ° C. for 2 minutes with a twin-screw kneader, and then extruded from a T-die to prepare a sealing resin sheet A having a thickness of 500 μm.
　エポキシ樹脂：ビスフェノールＦ型エポキシ樹脂（新日鐵化学（株）製、ＹＳＬＶ－８０ＸＹ（エポキン当量２００ｇ／ｅｑ．軟化点８０℃））　　　　　　　　２８６部
　フェノール樹脂：ビフェニルアラルキル骨格を有するフェノール樹脂（明和化成社製、ＭＥＨ－７８５１－ＳＳ（水酸基当量２０３ｇ／ｅｑ．、軟化点６７℃））  ３０３部
　硬化促進剤：硬化触媒としてのイミダゾール系触媒（四国化成工業（株）製、２ＰＨＺ－ＰＷ）　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　６部
　無機充填剤：球状溶融シリカ粉末（電気化学工業社製、ＦＢ－９４５４、平均粒子径２０μｍ）　　　　　　　　　　　　　　　　　　　　　　　　　　　　　３６９５部
　シランカップリング剤：エポキシ基含有シランカップリング剤（信越化学工業（株）製、ＫＢＭ－４０３）　　　　　　　　　　　　　　　　　　　　　　　　　　　５部
　カーボンブラック（三菱化学（株）製、＃２０）　　　　　　　　　　　　　   　　　　５部 Epoxy resin: Bisphenol F type epoxy resin (manufactured by Nippon Steel Chemical Co., Ltd., YSLV-80XY (epochine equivalent 200 g / eq. Softening point 80 ° C.)) 286 parts Phenol resin: phenol resin having biphenylaralkyl skeleton (Maywa Kasei Co., Ltd.) Manufactured by MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.) 303 parts Curing accelerator: imidazole catalyst as a curing catalyst (manufactured by Shikoku Chemicals Co., Ltd., 2PHZ-PW) 6 parts Inorganic Filler: Spherical fused silica powder (manufactured by Denki Kagaku Kogyo Co., Ltd., FB-9454, average particle size 20 μm) 3695 parts Silane coupling agent: Epoxy group-containing silane coupling agent (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-403) 5 parts carbon black (three Chemical Co., Ltd., # 20), 5 parts
［実施例２］
　（封止樹脂シートの作製）
　以下の成分をミキサーにてブレンドし、２軸混練機により１２０℃で２分間溶融混練し、続いてＴダイから押出しすることにより、厚さ５００μｍの封止樹脂シートＢを作製した。 [Example 2]
(Preparation of sealing resin sheet)
The following components were blended with a mixer, melt-kneaded at 120 ° C. for 2 minutes with a twin-screw kneader, and then extruded from a T die to prepare a sealing resin sheet B having a thickness of 500 μm.
　エポキシ樹脂：ビスフェノールＦ型エポキシ樹脂（新日鐵化学（株）製、ＹＳＬＶ－８０ＸＹ（エポキン当量２００ｇ／ｅｑ．軟化点８０℃））　　　　　　　　１６９部
　フェノール樹脂：ビフェニルアラルキル骨格を有するフェノール樹脂（明和化成社製、ＭＥＨ－７８５１－ＳＳ（水酸基当量２０３ｇ／ｅｑ．、軟化点６７℃））  １７９部
　硬化促進剤：硬化触媒としてのイミダゾール系触媒（四国化成工業（株）製、２ＰＨＺ－ＰＷ）　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　６部
　エラストマー：スチレン-イソブチレン-スチレントリブロック共重合体（（株）カネカ製、ＳＩＢＳＴＡＲ　０７２Ｔ）　　　　　　　　　　　　　　　　　　　 １５２部
　無機充填剤：球状溶融シリカ粉末（電気化学工業社製、ＦＢ－９４５４、平均粒子径２０μｍ）　　　　　　　　　　　　　　　　　　　　　　　　　　　　 　１７００部
　シランカップリング剤：エポキシ基含有シランカップリング剤（信越化学工業（株）製、ＫＢＭ－４０３）　　　　　　　　　　　　　　　　　　　　　　　　　　　５部
　カーボンブラック（三菱化学（株）製、＃２０）　　　　　　　　　　　　　　　　　　　５部
　難燃剤：ホスファゼン化合物（（株）伏見製薬所製、ＦＰ－１００）　　　　　　　　　８９部 Epoxy resin: Bisphenol F type epoxy resin (manufactured by Nippon Steel Chemical Co., Ltd., YSLV-80XY (epochine equivalent 200 g / eq. Softening point 80 ° C.)) 169 parts Phenol resin: phenol resin having biphenylaralkyl skeleton (Maywa Kasei Co., Ltd.) Manufactured by MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.) 179 parts Curing accelerator: imidazole catalyst as a curing catalyst (manufactured by Shikoku Kasei Co., Ltd., 2PHZ-PW) 6 parts Elastomer : Styrene-isobutylene-styrene triblock copolymer (manufactured by Kaneka Corp., SIBSTAR 072T) 152 parts Inorganic filler: spherical fused silica powder (manufactured by Denki Kagaku Kogyo, FB-9454, average particle size 20 μm) 1700 parts Ring agent: Epoxy group-containing silane coupling agent (manufactured by Shin-Etsu Chemical Co., Ltd., KBM-403) 5 parts Carbon black (Mitsubishi Chemical Corporation, # 20) 5 parts Flame retardant: Phosphazene compound (Fushimi Co., Ltd.) 89 parts by FP-100
［比較例１］
　（封止樹脂シートの作製）
　以下の成分をメチルエチルケトンに溶解ないし分散し、固形分４０重量％のワニスを作製した。 [Comparative Example 1]
(Preparation of sealing resin sheet)
The following components were dissolved or dispersed in methyl ethyl ketone to prepare a varnish having a solid content of 40% by weight.
　液状エポキシ樹脂（大日本インキ化学工業（株）製、ＥＸＡ－４８５０－１５０）　　　８０部
　固形エポキシ樹脂（日本化薬（株）製、ＥＰＰＮ－５０１－ＨＹ）　　　　　　　　　　２０部
　フェノール樹脂：ビフェニルアラルキル骨格を有するフェノール樹脂（明和化成社製、ＭＥＨ－７８５１－ＳＳ（水酸基当量２０３ｇ／ｅｑ．、軟化点６７℃））　６０部
　硬化促進剤：硬化触媒としてのイミダゾール系触媒（四国化成工業（株）製、２ＰＨＺ－ＰＷ）　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　３部
　アクリル共重合体（ＢＡ（ブチルアクリレート）：ＡＮ（アクリロニトリル）：ＧＭＡ（グリシジルメタクリレート）＝８５：８：７重量％からなる重量平均分子量が８００，０００の共重合体）　　　　　　　　　　　　　　　　　　　　３３０部
　無機充填剤：球状溶融シリカ粉末（電気化学工業社製、ＦＢ－９４５４、平均粒子径２０μｍ）　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　４００部
　カーボンブラック（三菱化学（株）製、＃２０）　　　　　　　　　　　　　　　　　　７部 Liquid epoxy resin (Dainippon Ink Chemical Co., Ltd., EXA-4850-150) 80 parts Solid epoxy resin (Nippon Kayaku Co., Ltd., EPPN-501-HY) 20 parts Phenol resin: biphenylaralkyl skeleton Phenol resin (Maywa Kasei Co., Ltd., MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.)) 60 parts Curing accelerator: imidazole catalyst as curing catalyst (manufactured by Shikoku Chemicals Co., Ltd., 2PHZ -PW) 3 parts Acrylic copolymer (BA (butyl acrylate): AN (acrylonitrile): GMA (glycidyl methacrylate) = 85: 8: 7% by weight copolymer having a weight average molecular weight of 800,000) 330 parts Inorganic filler: Spherical fused silica powder (Electrochemical Industry Co., Ltd.) , FB-9454, average particle size 20 [mu] m) 400 parts Carbon black (Mitsubishi Chemical Co., Ltd., # 20) 7 parts
　（封止樹脂シートの貯蔵弾性率の測定）
　貯蔵弾性率の測定は、固体粘弾性測定装置（レオメトリックサイエンティック社製：形式：ＲＳＡ－ＩＩＩ）を用いて行った。具体的には、各封止樹脂シートを１５０℃で１時間加熱して熱硬化させ、この硬化物からサンプルサイズを長さ４００ｍｍ×幅２ｍｍ×厚さ８０μｍとして測定試料を得た後、測定試料をフィルム引っ張り測定用治具にセットし－５０～３００℃の温度域での貯蔵弾性率及び損失弾性率を、周波数１Ｈｚ、昇温速度１０℃／ｍｉｎの条件下で測定し、２５℃での貯蔵弾性率（Ｅ’）を読み取ることにより得た。 (Measurement of storage elastic modulus of sealing resin sheet)
The storage elastic modulus was measured using a solid viscoelasticity measuring apparatus (manufactured by Rheometric Scientific: model: RSA-III). Specifically, each sealing resin sheet is heated and cured at 150 ° C. for 1 hour, and a measurement sample is obtained from the cured product with a sample size of 400 mm long × 2 mm wide × 80 μm thick, and then the measurement sample. Was set in a film tension measuring jig, and the storage elastic modulus and loss elastic modulus in the temperature range of −50 to 300 ° C. were measured under the conditions of a frequency of 1 Hz and a heating rate of 10 ° C./min. It was obtained by reading the storage modulus (E ′).
　（封止樹脂シートのショアＤ硬度の測定）
　各封止樹脂シートを２ｍｍ厚となるようにラミネータを用いて積層し、この積層体を１５０℃で１時間加熱して熱硬化させた後、ＪＩＳ　Ｋ　７２１５に準拠し、硬度計（（株）ミツトヨ製、プラスチック用硬度計）を用いて、２５℃での測定値を読み取ることで得た。 (Measurement of Shore D hardness of encapsulating resin sheet)
Each sealing resin sheet was laminated using a laminator so as to have a thickness of 2 mm, and this laminate was heated at 150 ° C. for 1 hour to be thermally cured, and in accordance with JIS K 7215, a hardness meter (Corporation) It was obtained by reading the measured value at 25 ° C. using a Mitutoyo plastic hardness tester.
　（半導体パッケージの作製）
　以下の仕様の半導体チップがシリコンインターポーザーにフリップチップ実装され、チップ－インターポーザー間がビスフェノールＡ型エポキシ系熱硬化性アンダーフィル材で封止されたチップ実装インターポーザーを準備した。 (Production of semiconductor package)
A chip mounting interposer was prepared in which a semiconductor chip having the following specifications was flip-chip mounted on a silicon interposer, and the space between the chip and the interposer was sealed with a bisphenol A type epoxy thermosetting underfill material.
　＜半導体チップ＞
　半導体チップサイズ：７．３ｍｍ□（厚さ４００μｍ）
　バンプ材質：Ｃｕ　３０μｍ、Ｓｎ－Ａｇ　１５μｍ厚み
　バンプ数：５４４バンプ
　バンプピッチ：５０μｍ
　チップ数：１６個（４個×４個） <Semiconductor chip>
Semiconductor chip size: 7.3 mm □ (thickness 400 μm)
Bump material: Cu 30μm, Sn-Ag 15μm thickness Number of bumps: 544 bumps Bump pitch: 50μm
Number of chips: 16 (4 x 4)
　＜シリコンインターポーザー＞
　直径：８インチ
　厚さ：７３０μｍ
　電極：スルーシリコンビア（径：３０μｍ） <Silicon interposer>
Diameter: 8 inches Thickness: 730 μm
Electrode: Through silicon via (diameter: 30 μm)
　得られたチップ実装インターポーザー上に、以下に示す加熱加圧条件下、封止樹脂シートＡ～Ｃのそれぞれを真空平板プレスにより貼付けた。 Each of the sealing resin sheets A to C was pasted on the obtained chip mounting interposer by a vacuum flat plate press under the following heating and pressing conditions.
　＜貼り付け条件＞
　温度：９０℃
　加圧力：０．５ＭＰａ
　真空度：２０００Ｐａ
　プレス時間：３分 <Paste conditions>
Temperature: 90 ° C
Applied pressure: 0.5 MPa
Degree of vacuum: 2000Pa
Press time: 3 minutes
　大気圧に開放した後、熱風乾燥機中、１５０℃、１時間の条件で封止樹脂シートを熱硬化させ、封止体を得た。次に、切削装置（（株）ＤＩＳＣＯ製、サーフェスプレーナー「ＤＦＳ８９１０」）を用いた研削により、研削バイトの周速度１０００ｍ／ｍｉｎ、送りピッチ１００μｍ、切り込み深さ１０μｍの条件で、半導体チップの厚さが１００μｍとなるまで封止体を半導体チップ共々薄化することで、研削体を作製した。 After releasing to atmospheric pressure, the sealing resin sheet was thermally cured in a hot air dryer at 150 ° C. for 1 hour to obtain a sealing body. Next, the thickness of the semiconductor chip is obtained by grinding using a cutting device (manufactured by DISCO Corporation, surface planar “DFS8910”) under the conditions of a peripheral speed of the grinding tool of 1000 m / min, a feed pitch of 100 μm, and a cutting depth of 10 μm. By grinding the sealing body together with the semiconductor chip until the thickness becomes 100 μm, a ground body was produced.
　得られた研削体のシリコンインターポーザーの露出面（封止樹脂シートを貼り合わせた面とは反対側の面）を研削装置（ＤＩＳＣＯ製、「ＤＧＰ８７６１」）によりシリコンインターポーザーの厚さが１００μｍとなるまで研削し、積層体を形成した。 The exposed surface of the silicon interposer of the obtained grinding body (the surface opposite to the surface on which the sealing resin sheet was bonded) was removed with a grinding device (“DGP8761” manufactured by DISCO) and the thickness of the silicon interposer was 100 μm. It grinded until it became, and the laminated body was formed.
　（封止樹脂シートとシリコンインターポーザーとの積層体の最厚部の厚さと最薄部の厚さの差の測定）
　積層体（露出した半導体チップを含む。）の最厚部の厚さと最薄部の厚さの差を、ウェハ厚み計測装置（浜松ホトニクス社製、「Ｃ８８７０－０２」）を用いて測定ピッチ２ｍｍで測定した。 (Measurement of the difference between the thickness of the thickest part and the thinnest part of the laminate of the sealing resin sheet and the silicon interposer)
The difference between the thickness of the thickest part and the thickness of the thinnest part of the laminated body (including the exposed semiconductor chip) is measured using a wafer thickness measuring device (“C8880-02” manufactured by Hamamatsu Photonics) with a measurement pitch of 2 mm. Measured with
　続いて、シリコンインターポーザーの研削面にポリアミック酸（３，４’，３，４’－ビフェニルテトラカルボン酸二無水物と４，４’－ジアミノジフェニルエーテル、パラフェニレンジアミンを反応して得たもの）を塗布し、熱硬化させて、厚さ１０μｍのポリイミド層を形成した。スルーシリコンビアに対応する位置に、レーザー加工によって開口を形成し、該ビアを露出させた。開口を含むポリイミド層表面に、めっきによって金膜、ニッケル膜を順次形成した。さらに、クロム、銅の順にスパッタリングを施して、種膜（クロム層の厚さ２０ｎｍ、銅層の厚さ１００ｎｍ）を形成し、電解銅めっきにより所定の配線パターンを有する再配線層を形成することにより半導体パッケージを作製した。 Subsequently, polyamic acid (obtained by reacting 3,4 ', 3,4'-biphenyltetracarboxylic dianhydride, 4,4'-diaminodiphenyl ether, paraphenylenediamine) on the ground surface of the silicon interposer Was applied and thermally cured to form a polyimide layer having a thickness of 10 μm. An opening was formed by laser processing at a position corresponding to the through-silicon via to expose the via. A gold film and a nickel film were sequentially formed on the surface of the polyimide layer including the opening by plating. Further, sputtering is performed in the order of chromium and copper to form a seed film (chrome layer thickness 20 nm, copper layer thickness 100 nm), and a rewiring layer having a predetermined wiring pattern is formed by electrolytic copper plating. Thus, a semiconductor package was produced.
　（再配線の形成性）
　再配線形成面にて、配線の破断があるかどうかを顕微鏡（倍率：５００倍）にて確認し、破断のない場合を「○」、破断のある場合を「×」として評価した。結果を表１に示す。 (Formability of rewiring)
On the rewiring formation surface, whether or not there was a break in the wiring was confirmed with a microscope (magnification: 500 times), and the case where there was no break was evaluated as “◯”, and the case where there was a break was evaluated as “x”. The results are shown in Table 1.
Figure JPOXMLDOC01-appb-T000004
  
Figure JPOXMLDOC01-appb-T000004
  
　表１からも明らかなように、実施例１及び２では、封止樹脂シートとシリコンインターポーザーとの積層体の厚さ差が２０μｍ以下であることから、半導体パッケージの回路面要素としての再配線の形成を歩留りよく行うことができるのに対し、比較例１の半導体パッケージでは、厚さ差が２０μｍを超えていることから、再配線の形成性に劣る結果となった。 As is clear from Table 1, in Examples 1 and 2, the thickness difference of the laminate of the sealing resin sheet and the silicon interposer is 20 μm or less, so rewiring as a circuit surface element of the semiconductor package In contrast, the semiconductor package of Comparative Example 1 has a thickness difference exceeding 20 μm, resulting in poor rewiring formability.
［実施例３］
　実施例１の封止樹脂シートＡを用いる半導体パッケージの作製の封止工程において、真空平板プレスに代えて、得られたチップ実装インターポーザー上に、圧縮成形装置ＷＣＭ－３００（アピックヤマダ社製）を用いて封止樹脂シートＡを下記成形条件にて貼付けたこと以外は、実施例１の場合と同様に、積層体の最厚部の厚さと最薄部の厚さの差の測定及び再配線の形成性の評価を行った。結果を表２に示す。 [Example 3]
In the sealing process of manufacturing a semiconductor package using the sealing resin sheet A of Example 1, instead of the vacuum flat plate press, a compression molding apparatus WCM-300 (manufactured by Apic Yamada) was placed on the obtained chip mounting interposer. Measurement and rewiring of the difference between the thickness of the thickest part and the thickness of the thinnest part in the same manner as in Example 1 except that the sealing resin sheet A was pasted under the following molding conditions. The formability of was evaluated. The results are shown in Table 2.
　＜成形条件＞
　温度：１５０℃
　加圧力：４．５ＭＰａ
　真空度：２０００Ｐａ
　加圧時間：１０分 <Molding conditions>
Temperature: 150 ° C
Applied pressure: 4.5 MPa
Degree of vacuum: 2000Pa
Pressurization time: 10 minutes
Figure JPOXMLDOC01-appb-T000005
  
Figure JPOXMLDOC01-appb-T000005
  
　表２の結果より、封止樹脂シートによる封止工程として、平板プレス及び圧縮成形のいずれも好適に利用可能であることが分かる。 From the results of Table 2, it can be seen that both flat plate press and compression molding can be suitably used as the sealing step with the sealing resin sheet.
　　　　１１、２１　　封止樹脂シート
　　　　１１Ｓ、２１Ｓ　　（研削後の）封止樹脂シートの表面
　　　　１２Ａ　　（研削前の）半導体ウェハ
　　　　１２Ｂ　　（研削後の）半導体ウェハ
　　　　１３、２３　　半導体チップ
　　　　１３Ｓ、２３Ｓ　　（研削後の）半導体チップの露出面
　　　　１５、２５　　封止体
　　　　１６Ａ、１６Ｃ　　研削体
　　　　１６Ｂ　　積層体
　　　　１８、２８　　半導体パッケージ
　　　　１９、２９　　再配線
　　　　Ｔｍａｘ　　積層体の最厚部の厚さ
　　　　Ｔｍｉｎ　　積層体の最薄部の厚さ 
  11, 21 Encapsulating resin sheet 11S, 21S Surface of encapsulating resin sheet (after grinding) 12A (Before grinding) Semiconductor wafer 12B (After grinding) Semiconductor wafer 13, 23 Semiconductor chip 13S, 23S (After grinding) Semiconductor chip exposed surface 15, 25 Sealed body 16A, 16C Grinded body 16B Laminated body 18, 28 Semiconductor package 19, 29 Rewiring T max Thickness of the thickest part of the laminated body T min Thickness of the thinnest part of the laminated body The

Claims (8)

  1. 　第１主面に一又は複数の半導体チップが搭載された半導体ウェハを準備する準備工程、
    　前記半導体チップを埋め込むように前記半導体ウェハの第１主面に封止樹脂シートを積層して前記半導体チップを封止する封止工程、及び
    　前記半導体ウェハの第１主面とは反対側の第２主面を研削する裏面研削工程を含み、
    　前記封止樹脂シートと前記研削された半導体ウェハとの積層体の最も厚い最厚部の厚さと最も薄い最薄部の厚さとの差が２０μｍ以下である半導体パッケージの製造方法。     A preparation step of preparing a semiconductor wafer having one or more semiconductor chips mounted on the first main surface;
    A sealing step of sealing the semiconductor chip by laminating a sealing resin sheet on the first main surface of the semiconductor wafer so as to embed the semiconductor chip; and a first step opposite to the first main surface of the semiconductor wafer. 2 including a back grinding process to grind the main surface,
    A manufacturing method of a semiconductor package, wherein a difference between a thickness of a thickest thickest part and a thickness of a thinnest thinnest part of a laminate of the sealing resin sheet and the ground semiconductor wafer is 20 μm or less.
  2. 　前記封止工程は、前記封止樹脂シートに対する平板プレス又は圧縮成形により行う請求項１に記載の半導体パッケージの製造方法。 The method for manufacturing a semiconductor package according to claim 1, wherein the sealing step is performed by flat plate pressing or compression molding on the sealing resin sheet.
  3. 　前記積層体の最厚部は、前記半導体ウェハを平面視で透視した際に、該半導体ウェハと前記半導体チップとが重複しない領域に位置する請求項１又は２に記載の半導体パッケージの製造方法。 3. The method of manufacturing a semiconductor package according to claim 1, wherein the thickest part of the stacked body is located in a region where the semiconductor wafer and the semiconductor chip do not overlap when the semiconductor wafer is seen through in plan view.
  4. 　１５０℃で１時間熱硬化処理を施した後の前記封止樹脂シートの２５℃におけるショアＤ硬度が６０以上である請求項１～３のいずれか１項に記載の半導体パッケージの製造方法。 The method of manufacturing a semiconductor package according to any one of claims 1 to 3, wherein a Shore D hardness at 25 ° C of the encapsulating resin sheet after performing a thermosetting treatment at 150 ° C for 1 hour is 60 or more.
  5. 　１５０℃で１時間熱硬化処理を施した後の前記封止樹脂シートの２５℃における貯蔵弾性率が３ＧＰａ以上である請求項１～４のいずれか１項に記載の半導体パッケージの製造方法。 The method for producing a semiconductor package according to any one of claims 1 to 4, wherein a storage elastic modulus at 25 ° C of the encapsulating resin sheet after performing a thermosetting treatment at 150 ° C for 1 hour is 3 GPa or more.
  6. 　前記裏面研削工程後、前記半導体チップの研削された第２主面に再配線を形成する再配線形成工程をさらに含む請求項１～５のいずれか１項に記載の半導体パッケージの製造方法。 6. The method for manufacturing a semiconductor package according to claim 1, further comprising a rewiring forming step of forming a rewiring on the ground second main surface of the semiconductor chip after the back surface grinding step.
  7. 　前記半導体チップが複数用いられており、
    　前記再配線形成工程後に、前記半導体ウェハを前記封止樹脂シートとともに目的の半導体チップ単位でダイシングするダイシング工程をさらに含む請求項６に記載の半導体パッケージの製造方法。     A plurality of the semiconductor chips are used,
    The manufacturing method of the semiconductor package of Claim 6 which further includes the dicing process of dicing the said semiconductor wafer with the said sealing resin sheet per target semiconductor chip after the said rewiring formation process.
  8. 　請求項１～７のいずれか１項に記載の半導体パッケージの製造方法により得られる半導体パッケージ。
     
     
          A semiconductor package obtained by the method for manufacturing a semiconductor package according to any one of claims 1 to 7.


PCT/JP2014/076575 2013-10-23 2014-10-03 Semiconductor package manufacturing method WO2015060106A1 (en)

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CN110246809A (en) * 2018-03-08 2019-09-17 日东电工株式会社 Sheet for sealing

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JP6741063B2 (en) * 2016-03-25 2020-08-19 日立化成株式会社 Organic interposer and method for manufacturing organic interposer
KR102140259B1 (en) 2018-01-11 2020-07-31 주식회사 엘지화학 Epoxy resin composition for molding semiconductor, molding film and semiconductor package using the same
JP7217865B2 (en) * 2018-02-22 2023-02-06 味の素株式会社 Wafer level package encapsulation resin composition

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JP2003268203A (en) * 2002-03-18 2003-09-25 Shin Etsu Chem Co Ltd Liquid epoxy resin composition for wafer mold and semiconductor apparatus using the same
JP2005060584A (en) * 2003-08-18 2005-03-10 Hitachi Chem Co Ltd Film for sealing
JP2011243596A (en) * 2010-05-14 2011-12-01 Panasonic Corp Manufacturing method of package component and package component
JP2012227441A (en) * 2011-04-21 2012-11-15 Sumitomo Bakelite Co Ltd Semiconductor device manufacturing method and semiconductor device
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JP2001332654A (en) * 2000-03-17 2001-11-30 Matsushita Electric Ind Co Ltd Module provided with built-in electric element and manufacturing method thereof
JP2003268203A (en) * 2002-03-18 2003-09-25 Shin Etsu Chem Co Ltd Liquid epoxy resin composition for wafer mold and semiconductor apparatus using the same
JP2005060584A (en) * 2003-08-18 2005-03-10 Hitachi Chem Co Ltd Film for sealing
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JP2012227441A (en) * 2011-04-21 2012-11-15 Sumitomo Bakelite Co Ltd Semiconductor device manufacturing method and semiconductor device
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CN110183818A (en) * 2018-02-22 2019-08-30 味之素株式会社 Wafer-class encapsulation resin composition for encapsulating
CN110246809A (en) * 2018-03-08 2019-09-17 日东电工株式会社 Sheet for sealing

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JP2015082606A (en) 2015-04-27

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