JP2017130521A - Semiconductor package substrate with stiffener, semiconductor package, and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method capable of reducing warpage of a semiconductor package substrate, and further capable of suppressing and preventing chipping and cracking in an outer edge part of the semiconductor package substrate and on a side surface thereof even under a high and low temperature environment, a semiconductor package substrate, and a semiconductor package.SOLUTION: A semiconductor package substrate with a stiffener includes: a core base material; insulating resins of two or more layers laminated on the core base material; a wiring pattern formed between the insulating resins, on a surface of the insulating resin, or on a surface of the core base material; an electrode pad connected to at least a part of the wiring pattern; a solder resist laminated in the insulating resin separated farthest from the core base material among the insulating resins and including an opening through which at least the electrode pad is exposed; a semiconductor package substrate including the core base material and a stress relaxation layer formed on a side surface of the insulating resin; and a stiffener stuck via an adhesive layer laminated on the stress relaxation layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor package substrate with a stiffener, and a semiconductor package.

  A semiconductor package substrate is used for electrical connection between a semiconductor chip and a motherboard. The semiconductor package substrate also serves to bridge the difference in thermal expansion coefficient between the semiconductor chip and the printed wiring board on which the semiconductor package is mounted, thereby increasing the bonding reliability of the system mounting. Because of this role, the semiconductor package substrate is called an interposer substrate.

  In addition, the semiconductor package substrate is converted into a line width and pitch between the semiconductor chip and the mother board by changing the wiring width and pitch in the substrate in each layer to obtain electrical connection.

  On the other hand, there are various methods for connecting / mounting the semiconductor package substrate and the semiconductor chip depending on the situation of use, but flip-chip connection / mounting is often used in which the semiconductor chip and the semiconductor package substrate are connected by metal bonding such as solder or gold. Flip chip connection is often used in high performance semiconductor packages because many terminals can be connected to the semiconductor package substrate by arranging the terminal surface of the semiconductor chip on the terminal surface on the substrate side.

  However, when a semiconductor chip is flip-chip mounted on a semiconductor package substrate having a thin substrate thickness and a so-called coreless substrate having no core base material, heating is performed in a high-temperature furnace for solder bonding. At this time, warpage occurs in the semiconductor package substrate, the adjacent solders between the semiconductor chip and the semiconductor package substrate are separated, and an open connection failure occurs. Or, conversely, when the solder is integrated, there is a problem that the connection is short-circuited and the like, and there is a problem that the soldering cannot be performed properly. Further, during cooling after solder bonding, the semiconductor package warps due to the difference in coefficient of linear expansion (CTE) between the semiconductor chip and the semiconductor package substrate, stress is generated in the solder bumps, and cracks are generated in the solder. Due to these effects, there is a problem that the manufacturing yield and the reliability of the solder joint cannot be sufficiently secured.

  Therefore, conventionally, a frame-shaped reinforcing material made of a metal and a resin material having high rigidity called a stiffener has been formed on the surface of the semiconductor package substrate on which the semiconductor chip is mounted and on the surface opposite to the mounting surface. If it does so, the curvature of the board | substrate at the time of the heating and cooling of a solder joint will be suppressed, the stress which arises in the curvature after mounting and a solder bump will be reduced, and connection reliability is ensured.

  In recent years, not only the conventional SoC (System on a Chip) but also SiP (System in Package) for building a large-scale system on one package is used to develop a high-performance system in a short period of time. ing. For example, there are cases where a plurality of semiconductor chips such as a CPU / GPU and a large-capacity memory are arranged next to each other on a single package substrate, or chips are stacked and arranged three-dimensionally.

  Further, in a form in which a plurality of semiconductor chips are arranged two or three-dimensionally, it is required to form fine wiring with a width of several μm and micro bumps with a pitch of several tens of μm on the semiconductor package substrate. In order to realize mounting with such a narrow bump pitch, an interposer using a material having high dimensional stability for the core portion has been proposed. For example, a silicon interposer in which the core part of the substrate is made of the same material as that of the semiconductor chip and a glass interposer having a high insulating property and a linear expansion coefficient close to that of the semiconductor chip have been proposed.

  FIG. 5 is a cross-sectional view showing a configuration of a conventional semiconductor package. It is an example of the structure which has arrange | positioned the semiconductor chip on the semiconductor package board | substrate using the flip chip mounting system. The semiconductor chip 1 and the semiconductor package substrate 2 are joined via solder bumps 3. Further, a stiffener 4 is disposed on the outer edge portion of the semiconductor chip mounting surface.

  FIG. 6 is a diagram showing the structure of the semiconductor package substrate. A core base 6 using glass epoxy resin, glass, or silicon plate is formed at the center of the semiconductor package substrate. Further, the wiring pattern 7 and the insulating resin 8 are laminated in this order on the top and bottom of the core substrate. Further, through-hole electrodes 9 or vias 10 are provided in the core layer and the buildup layer for conduction of each wiring pattern layer. Further, a solder resist 11 is formed on the uppermost or lowermost insulating resin layer, and an electrode pad 12 is formed in a portion without the solder resist.

  Here, silicon interposers, glass interposers, etc. have a higher modulus of elasticity in the core than conventional glass epoxy materials, so jigs and substrates such as contact between the substrate and the case during substrate transportation and jig mounting during the mounting process Due to the contact, chipping and cracking are easily generated on the outer edge and side surfaces of the core. In addition, since a plurality of layers of insulating resin, wiring patterns, and the like are laminated on the core base material, stress is applied to the interface between the core base material and the buildup layer during the lamination. If minute defects are generated on the outer edge and side surfaces of the core base material during dicing or the like, stress acts and cracks may be generated starting from the stress.

  FIG. 7 is a view showing the structure of the end portion of the semiconductor package substrate as an example of chipping or cracking of the core portion. FIG. 7A shows a crack at the center of the core, FIG. 7B shows a chip at the core corner, and FIG. 7C shows a chip at the core center.

  Further, when the direction and magnitude of the stress at the interface between the core base material and the buildup layer change under a high and low temperature environment, chipping and cracking of these core portions may progress and newly occur. In addition, the semiconductor package may warp when the semiconductor package is mounted on a printed wiring board such as a mother board, stress may be generated in the core base material, and chipping or cracking may develop. When the chipping or cracking reaches the through hole or the wiring layer on the base material, it leads to the disconnection of the wiring. For this reason, chipping or cracking of the core portion of the semiconductor package greatly affects the connection reliability of the semiconductor package. Therefore, it is necessary to suppress and prevent the chipping and cracking of the core portion.

  As a solution to these problems, the outer dimension of the stiffener is made larger than the outer dimension of the semiconductor package substrate, and the outer edge and the side surface of the semiconductor package substrate (coreless substrate) are covered by providing a cover portion bent in the thickness direction of the substrate. A structure has been proposed (Patent Document 1). In this method, it is possible to maintain the rigidity of the substrate by the stiffener and to prevent the outer edge portion and the side surface of the substrate from being damaged. However, in this method, since the side surface of the semiconductor package substrate and the stiffener are bonded using an adhesive or the like, the stiffener, the adhesive, and the semiconductor package substrate are used in a high and low temperature environment due to the difference in the coefficient of linear expansion between the stiffener and the semiconductor package substrate. Stress is generated at each of the interfaces, and the tensile stress may cause the core side surface to peel off together with the adhesive, or the compressive stress may cause cracking.

  In addition, chippings and cracks on the side of the semiconductor package substrate that occurred before sticking the stiffener remain even after the stiffener is bonded, so even after the stiffener is formed, it develops due to large impacts and changes in the direction and amount of stress due to high and low temperature environments. There is a possibility that it may lead to disconnection of the wiring.

JP 2010-238828 A

  The present invention has been made under the above circumstances, and in a semiconductor package, the warpage of the semiconductor package substrate is reduced, and further, the chipping and cracking of the outer edge and side surfaces of the semiconductor package substrate are suppressed and prevented even in a high and low temperature environment. It is an object to provide a method, a semiconductor package substrate, and a semiconductor package.

One embodiment of the present invention is a method for manufacturing a semiconductor package, characterized in that in a semiconductor package substrate in which pattern wiring and insulating resin are laminated, a stress relaxation layer is provided on an outer edge portion and a side surface of the semiconductor package substrate.
A stress relaxation layer forming step of forming a stress relaxation layer on at least a part of the outermost surface of the semiconductor package substrate on which the wiring pattern and the insulating resin are laminated or a side surface of the semiconductor package substrate, and a stress relaxation layer after the stress relaxation layer formation step And a stiffener attaching step of attaching a stiffener to the semiconductor package substrate.

  Another embodiment of the present invention is formed between the core base material, at least two or more layers of the insulating resin laminated on the core base material, the insulating resin, the surface of the insulating resin, or the surface of the core base material. A wiring pattern, an electrode pad connected to at least a part of the wiring pattern, and a solder resist having an opening that is laminated on the insulating resin farthest from the core base material, and at least exposes the electrode pad A semiconductor package substrate including a core base material and a stress relaxation layer formed on a side surface of the insulating resin, and a stiffener pasted through an adhesive layer laminated on the stress relaxation layer It is.

  Another aspect of the present invention is a semiconductor package including the semiconductor package substrate with a stiffener and a semiconductor chip connected to an electrode pad through an underfill.

  Another embodiment of the present invention includes a core base material, at least two or more layers of insulating resin laminated on the core base material, a wiring pattern formed between the insulating resins or on the surface of the insulating resin, and wiring An electrode pad connected to at least a part of the pattern, a solder resist laminated on an insulating resin farthest from the core substrate among the insulating resins, and having an opening through which at least the electrode pad is exposed; a core substrate; The semiconductor package substrate includes a stress relaxation layer on a side surface of the insulating resin, a semiconductor chip mounting surface of the semiconductor package substrate, and a stiffener on the opposite surface.

  According to the present invention, it is possible to provide a semiconductor package substrate, a semiconductor package, and a manufacturing method thereof in which warpage is reduced and chipping and cracking of the outer edge and side surfaces of the semiconductor package substrate are suppressed even in a high and low temperature environment.

It is sectional drawing which shows the structure of the semiconductor package in the Example of this invention. It is a top view of the semiconductor package in the Example of this invention. It is sectional drawing which shows the structure of the semiconductor package in the modification of this invention. It is a top view of the semiconductor package in the Example of this invention. It is a figure which shows the structure of the conventional semiconductor package. It is sectional drawing which shows the structure of the conventional semiconductor package board | substrate. It is sectional drawing which shows the chip | tip and the crack of the core part of the conventional semiconductor package board | substrate.

  Hereinafter, a semiconductor package manufacturing method according to the present invention will be described based on an embodiment thereof, but the present invention is not limited thereto.

FIG. 2 is a top view of the semiconductor package in the embodiment of the present invention. In the present invention, the outer dimension of the stiffener 4 is larger than the outer dimension of the semiconductor package substrate 2. The protruding amount of the stiffener is preferably 0.1 mm to 5 mm. Further, the stiffener outer edge portion has a bent portion bent in the substrate thickness direction so as to cover the side surface of the core base material 6 of the semiconductor package substrate. The dimension of the bent portion in the thickness direction of the substrate is equal to or greater than the thickness of the semiconductor package substrate. By doing so, the side surface of the semiconductor package substrate can be reliably covered. Further, the formation surface of the stiffener is not defined, and it is formed on the semiconductor chip 1 mounting surface and the opposite surface according to the hump of the semiconductor package substrate and the design of the wiring pattern 7.
In the present invention, an integrated semiconductor package substrate and stiffener is called a semiconductor package substrate with a stiffener. A semiconductor package in which a semiconductor chip is further bonded to a semiconductor package substrate with a stiffener is called a semiconductor package.

  FIG. 1 is a cross-sectional view showing the structure of a semiconductor package according to the present invention. The semiconductor package substrate 2 has a core base 6, vias 10 formed on both sides of the core base, lands, and wiring patterns 7 on both sides thereof. The core substrate has through-hole electrodes 9 in the thickness direction for connecting each wiring pattern. The via is used to connect the wiring patterns as necessary. The land is appropriately used for connecting the through-hole electrode and the via or the wiring pattern. For example, glass epoxy resin, silicon, or glass can be used as the material of the core base material. Further, one layer or laminated insulating resin 8 is formed on the wiring pattern, and a buildup layer is formed on the core base material.

  The buildup layer is formed by a buildup method and has an insulating resin and a wiring pattern. For example, an epoxy resin or a polyimide resin is used as the insulating resin, and a material obtained by adding a filler to the resin can also be used. Further, for example, copper is used for the wiring pattern. Note that the wiring patterns of each layer are electrically connected to each other by vias.

  Further, electrode pads 12 are formed on the uppermost and lowermost wiring patterns to connect electrical signals to the outside. A solder resist 11 is formed on the outermost surface so as to open on the electrode pad. In addition, the material which added the filler to the photosensitive epoxy resin and resin can also be used for the material of a soldering resist, for example.

  Thereafter, solder bumps 3 are formed on the electrode pads by using a printing method or a solder ball transfer method.

[Stress relaxation layer forming process]
Next, the stress relaxation layer 14 is formed on at least the side surface of the semiconductor package substrate. If necessary, it is also formed on at least a part of the outer edge of the semiconductor package substrate. The outer edge portion is the outermost surface of the semiconductor package substrate and the vicinity of the side surface. Since the stiffener is affixed, the width of the outer edge is required to some extent, and may be several tens of μm or more, for example 100 μm.
A stress relaxation layer is formed on the entire side surface of the semiconductor package substrate including the core part buildup layer. The thickness of the stress relaxation layer is set to a thickness that can relieve the stress generated in a high and low temperature environment. The thickness is preferably 10 μm to 1 mm, although depending on the stress relaxation layer, stiffener, adhesive, and the elastic modulus and linear expansion coefficient of the semiconductor package substrate.

  In addition, if the core substrate is chipped or cracked 13 during the formation of the stress relaxation layer, the thickness of the stress relaxation layer is adjusted as appropriate so that the core substrate chip or crack 13 is completely filled with the stress relaxation layer. To. By carrying out like this, the stress concerning a chip and a crack part can be controlled.

  The elastic modulus of the stress relaxation layer is preferably smaller than the elastic modulus of the core part or the stiffener. By doing so, the stress between the core portion and the stiffener is relaxed by the deformation of the stress relaxation layer. For example, an epoxy resin, a polyimide resin, a phenol resin, a silicone resin or the like is preferable as the material. However, if the elastic modulus has heat resistance up to a temperature that is in close contact with the substrate side surface and is heated when mounted, the physical property value of the above material is sufficient. good.

  The method for forming the stress relaxation layer is not particularly limited, and for example, the stress relaxation layer is formed on the side surface of the semiconductor package substrate using various coating methods. The stress relaxation layer forming step is not limited to after the semiconductor package substrate is manufactured, and may be formed after the solder resist is formed at the time of manufacturing the semiconductor package substrate, or may be formed after the stiffener is attached to the semiconductor package substrate.

[Stiffener pasting process]
Next, a semiconductor package substrate and a stiffener are attached. The stiffener is preferably more rigid than the semiconductor package substrate. By doing so, high rigidity can also be added to the semiconductor package substrate. The thickness of the stiffener is not particularly limited, and may be a thickness that can ensure high rigidity. Stiffener materials include iron, copper, copper alloy, and stainless steel as metal materials, and epoxy resin and polyimide resin as resin materials.

  In order to bring the stiffener and the semiconductor package substrate into close contact with each other, for example, the adhesive layer 15 is applied to the stiffener and is brought into close contact with the semiconductor package substrate and bonded thereto. Examples of the material for the adhesive layer include an epoxy adhesive and an acrylic adhesive.

  Next, after flux is applied onto the semiconductor package substrate, the semiconductor chip is flip-chip mounted, and the semiconductor chip and the semiconductor package substrate are electrically connected. Thereafter, the underfill 5 is inserted between the semiconductor chip and the semiconductor package substrate and heated to cure the underfill.

  Here, under high and low temperature environments, stress is generated at the interface due to the difference in coefficient of linear expansion between the stiffener and the semiconductor package substrate, and the tensile stress causes the side surface of the core to peel off together with the adhesive, and the compressive stress causes cracking. May occur.

  In the method of manufacturing a semiconductor package according to the present invention, the stress buffer layer is configured to form a stress relaxation layer between the side surface of the semiconductor package substrate and the adhesive layer, so that the stress buffer layer can reduce the stress applied to the adhesive layer and the side surface of the substrate even in a high and low temperature environment. By reducing it, it is possible to suppress the peeling, chipping and cracking of the side surface of the core.

  In addition, chippings and cracks on the side of the semiconductor package substrate that occurred before sticking the stiffener remain even after the stiffener is bonded, so even after the stiffener is formed, it develops due to large impacts and changes in the direction and amount of stress due to high and low temperature environments. There is a possibility that it may lead to disconnection of the wiring.

  In the manufacturing method of the semiconductor package of the present invention, by forming the stress relaxation layer, it is possible to suppress the stress applied to the chipping and cracking by filling the chipping and cracking already generated on the side surface of the core portion with the stress relaxation layer, New chipping and cracking can be prevented. Further, by forming stiffeners on the semiconductor chip mounting surface and the opposite surface of the semiconductor package substrate, the rigidity of the substrate can be maintained. Furthermore, by forming the covering portion bent in the thickness direction of the substrate, chipping and cracking of the outer edge portion and side surface of the semiconductor package substrate can be suppressed and prevented.

  FIG. 4 is a top view of a semiconductor package according to a modification of the present invention, and FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor package according to a modification of the present invention. The stiffener 4 is processed so that voids are formed at the four corners of the semiconductor chip mounting surface of the semiconductor package substrate and bonded to the semiconductor package substrate. By doing so, even if an alignment mark or the like is formed at the corner of the semiconductor package substrate, it can be recognized after the stiffener is attached. Further, the gap may be on either the semiconductor chip mounting surface or the opposite surface of the semiconductor package substrate, and its shape and dimensions are not specified. As another effect, an electronic component such as a capacitor can be mounted on the semiconductor package substrate immediately below the gap of the stiffener, and the semiconductor chip placement surface and the opposite surface can be effectively utilized.

  An embodiment of the present invention will be described below, but the present invention is not limited to this.

[Example 1]
As a semiconductor package substrate, a multilayer build-up printed wiring board using an epoxy resin in which a filler is added to an insulating layer on a base material using glass as a core material, copper as a wiring layer, and three wiring layers formed Was used. Also, solder bumps with a pitch of 0.150 mm are formed on the semiconductor element joints by a solder ball mounting method. The size of the semiconductor package substrate is 50 mm square and the thickness is 0.35 mm. A 20 mm square semiconductor chip having solder bumps with a thickness of 0.725 mm and a pitch of 0.150 mm was prepared.

  Next, an epoxy resin as a stress relaxation layer was formed on the side surface of the semiconductor package substrate to a thickness of about 200 μm using a dispenser. Thereafter, the resin was cured by heating at 190 ° C. for 1 hour. Moreover, although the crack of the glass of the core portion was generated on the side surface, it was confirmed with a metal microscope that it was filled with the resin after the stress relaxation layer was formed.

  Next, a stiffener having a rectangular frame shape made of stainless steel, having dimensions of 52.5 mm in length, 52.5 mm in width, and 1.0 mm in thickness is bonded. Note that a coating portion bent 350 μm in the substrate direction is formed on the outer edge of the stiffener to cover the side surface of the semiconductor package substrate. It is applied to the stiffener using an adhesive dispenser and arranged so as to be in contact with the semiconductor chip mounting surface and the stress relaxation layer side surface of the semiconductor package substrate. Thereafter, the adhesive was cured by heating at 120 ° C. for 1 hour.

  Next, the flux was spray-applied to the semiconductor chip connection range using a dispenser on the semiconductor package substrate to which the stiffener was attached. Thereafter, the terminal surface of the semiconductor chip was placed in the mounting region of the semiconductor package substrate using a mounter.

  Thereafter, the semiconductor package substrate and the semiconductor chip were joined using a reflow furnace in which the maximum temperature was 260 ° C.

  Thereafter, the flux was cleaned using a flux cleaner. The flux cleaning liquid used was an alkaline solvent.

  After pre-baking, the surface of the solder joint was modified using a plasma generator. Thereafter, an underfill obtained by adding a filler to an epoxy resin was inserted between the semiconductor chip and the semiconductor package substrate joined by using a dispenser, and was cured by heating. In addition, the insertion method was inserted several times into the underfill arrangement position at regular time intervals, and the heat curing conditions were 165 ° C. and 2 hours.

  Thereafter, the temperature is alternately changed in the range of −55 to 125 ° C. using a thermal cold shock tester for the semiconductor package, and after 1000 cycles, the side surface of the semiconductor package is polished to remove the stiffener layer and the stress relaxation layer. And the presence or absence of the crack of the glass of a core part and the progress of a crack were observed. As a result of observation, the core portion where no crack was seen before sticking the stiffener was not seen after the test, and no crack progress was seen in the portion where the crack was buried with the stress relaxation layer.

[Comparative example]
A semiconductor package was manufactured using a semiconductor package substrate in which no stress relaxation layer was formed on the semiconductor package substrate.

  Then, the temperature of the manufactured semiconductor package was alternately changed in the range of −55 to 125 ° C. using a thermal cold impact tester, and after 1000 cycles, the side surface of the semiconductor chip was polished, and a stiffener layer and a stress relaxation layer And the presence or absence of cracks in the core portion and the progress of cracks were observed. As a result of observation, it was observed that the core portion where no crack was observed before sticking the stiffener partly peeled off at the interface between the adhesive and the glass of the core portion, and the glass was scraped. In addition, in some places where cracks were seen before the stiffeners were attached, some cracks were confirmed.

In comparison with the comparative example, it was confirmed that in the example, the use of the structure of the present invention can suppress and prevent chipping and cracking of the outer edge portion and the side surface of the semiconductor package substrate even under a high and low temperature environment.
According to the present embodiment, by forming a stress relaxation layer between the side surface of the semiconductor package substrate and the adhesive layer, it is possible to reduce the stress applied to the adhesive layer and the side surface of the semiconductor package substrate even in a high and low temperature environment. Occurrence of peeling, chipping and cracking of the part and side can be suppressed. In addition, by forming the stress relaxation layer, the cracks and cracks that have already occurred on the side surfaces of the core are filled with the stress relaxation layer, so that the stress applied to the chips and cracks can be suppressed, and new cracks and cracks can be developed. Can be prevented. Further, by forming stiffeners on the semiconductor chip mounting surface and the opposite surface of the semiconductor package substrate, the rigidity of the substrate can be maintained. Furthermore, by forming the covering portion bent in the thickness direction of the substrate, chipping and cracking of the outer edge portion and side surface of the semiconductor package substrate can be suppressed and prevented.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Semiconductor package board | substrate 3 ... Solder bump 4 ... Stiffener 5 ... Underfill 6 ... Core base material 7 ... Wiring pattern 8 ... Insulating resin 9 ... Through-hole electrode 10 ... Via 11 ... Solder resist 12 ... Electrode pad 13 ... Core substrate chipping / cracking 14 ... Stress relief layer 15 ... Adhesive layer

Claims (8)

A stress relaxation layer forming step of forming a stress relaxation layer on at least a part of the outermost surface of the semiconductor package substrate on which the wiring pattern and the insulating resin are laminated or on a side surface of the semiconductor package substrate;
A method for manufacturing a semiconductor package substrate with a stiffener, comprising: a stiffener pasting step for pasting a stiffener to the semiconductor package substrate through the stress relaxation layer after the stress relaxation layer forming step.   The method of manufacturing a semiconductor package substrate with a stiffener according to claim 1, wherein the thickness of the stress relaxation layer is in a range of 10 μm to 1 mm.   The method of manufacturing a semiconductor package substrate with a stiffener according to claim 1, wherein a material of the stress relaxation layer is a resin.   4. The method for manufacturing a semiconductor package substrate with a stiffener according to claim 1, wherein an outer dimension of the stiffener is larger than an outer dimension of the semiconductor package substrate in a range of 0.1 mm to 5 mm. 5.   5. The method of manufacturing a semiconductor package substrate with a stiffener according to claim 1, wherein an outer edge portion of the stiffener has a bent portion bent in a substrate thickness direction so as to cover a side surface of the semiconductor package substrate.   6. The method of manufacturing a semiconductor package substrate with a stiffener according to claim 5, wherein a dimension of the bent portion is equal to or greater than a thickness of the semiconductor package substrate. A core substrate;
At least two layers of insulating resin laminated on the core substrate;
A wiring pattern formed between the insulating resins, or on the surface of the insulating resin, or on the surface of the core substrate;
An electrode pad connected to at least a part of the wiring pattern;
Among the insulating resins, a solder resist that is laminated on the insulating resin farthest from the core substrate and has an opening that exposes at least the electrode pads;
A semiconductor package substrate including a stress relaxation layer formed on a side surface of the core base material and the insulating resin;
A semiconductor package substrate with a stiffener, comprising a stiffener attached via an adhesive layer laminated on the stress relaxation layer.   A semiconductor package comprising the stiffener-equipped semiconductor package substrate according to claim 8 and a semiconductor chip connected to the electrode pad through an underfill.