JP2009026860A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2009026860A
JP2009026860A JP2007186895A JP2007186895A JP2009026860A JP 2009026860 A JP2009026860 A JP 2009026860A JP 2007186895 A JP2007186895 A JP 2007186895A JP 2007186895 A JP2007186895 A JP 2007186895A JP 2009026860 A JP2009026860 A JP 2009026860A
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Japan
Prior art keywords
semiconductor chip
wiring board
semiconductor
semiconductor device
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007186895A
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Japanese (ja)
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JP5372346B2 (en
Inventor
Mitsuhisa Watabe
光久 渡部
Ichiro Anjo
一郎 安生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
Elpida Memory Inc
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Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Priority to JP2007186895A priority Critical patent/JP5372346B2/en
Priority to TW097123667A priority patent/TWI433282B/en
Priority to DE102008031511A priority patent/DE102008031511A1/en
Priority to US12/173,245 priority patent/US7964962B2/en
Priority to KR1020080070279A priority patent/KR101014577B1/en
Publication of JP2009026860A publication Critical patent/JP2009026860A/en
Priority to US13/106,333 priority patent/US8441126B2/en
Application granted granted Critical
Publication of JP5372346B2 publication Critical patent/JP5372346B2/en
Expired - Fee Related legal-status Critical Current
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has excellent electric characteristics while suppressing a decrease in the number of products per shot, and is improved in reliability by reducing stress applied to a semiconductor chip. <P>SOLUTION: The semiconductor device 1 has a semiconductor chip 2 provided with a plurality of electrode pads 3 on a principal surface 2a and a plurality of bump electrodes 5 provided on the electrode pads 3 of the semiconductor chip 2. Further, the semiconductor device 1 has a wiring board 6 positioned in a center region of the principal surface 2a of the semiconductor chip 2 to be disposed on the side of the principal surface 2a of the semiconductor chip 2 and at least 50 μm apart from ends 2b and 2c of the semiconductor chip 2. Furthermore, the semiconductor device 1 has a plurality of external terminals 14 which are provided on the wiring board 6 and electrically connected to the plurality of bump electrodes 5 through wirings of the wiring board 6, and a sealing portion which is provided between the semiconductor chip 2 and wiring board 6 and formed of an underfilling material 15 covering connection portions between the bump electrodes 5 and wirings. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体チップに配線基板が実装されてなる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device in which a wiring substrate is mounted on a semiconductor chip and a method for manufacturing the same.

従来の半導体装置は、例えば特許文献１に開示されているように、半導体チップの主面上にエラストマを介してフレキシブル配線基板を配置している。そして、半導体チップの電極パッドと配線基板の開口部に配置された配線のリード部は電気的に接続され、配線基板の他面には外部端子を有し、配線基板の開口部内に配置された半導体チップの電極パッドとリード部は絶縁性樹脂からなる封止体で覆われる構成となっている。   In a conventional semiconductor device, for example, as disclosed in Patent Document 1, a flexible wiring substrate is disposed on the main surface of a semiconductor chip via an elastomer. The electrode pad of the semiconductor chip and the lead portion of the wiring arranged in the opening of the wiring board are electrically connected, and the other surface of the wiring board has an external terminal and is arranged in the opening of the wiring board. The electrode pads and lead portions of the semiconductor chip are configured to be covered with a sealing body made of an insulating resin.

このような従来の半導体装置においては、半導体チップの電極パッドと配線基板のリード部とを、配線基板に設けられた開口部にて接続するように構成されているため、半導体チップの電極パッドの直下近傍には、外部端子を配置できない構造となっている。
特開平９−２６０５３６号公報 In such a conventional semiconductor device, the electrode pad of the semiconductor chip and the lead portion of the wiring board are connected to each other through the opening provided in the wiring board. It has a structure in which no external terminal can be placed in the immediate vicinity.
JP-A-9-260536

年々、半導体装置の動作速度は高速化されており、半導体チップの電極パッドからの距離、例えば配線の引き回し距離が長くなると、動作速度の遅延を生じる恐れがある。そのため、良好な電気特性を得るために、半導体装置の配線引き回し距離の大幅な短縮が求められている。   The operation speed of semiconductor devices has been increased year by year, and if the distance from the electrode pad of the semiconductor chip, for example, the wiring routing distance becomes longer, there is a possibility that the operation speed may be delayed. Therefore, in order to obtain good electrical characteristics, there has been a demand for a significant reduction in the wiring routing distance of the semiconductor device.

また半導体チップの電極パッドの直下近傍に外部端子を配置できないため、配線基板の半導体チップの搭載されるエリア内に配置される外部端子が少なくなる恐れもあった。半導体装置の外部端子数は増えてきており、配線基板の半導体チップの搭載されるエリア外に外部端子を配置する必要が生じてしまい、配線基板の面積が大きくなる恐れがある。この配線基板の面積が大きくなることによっては、半導体装置のパッケージサイズの大型化につながってしまう。さらに、配線基板の面積が大きくなることによって、配線基板の製造における１ショットあたりの取り数が減少し、配線基板のコストアップにつながってしまう。   Further, since the external terminals cannot be arranged in the vicinity immediately below the electrode pads of the semiconductor chip, there is a possibility that the number of external terminals arranged in the area of the wiring board where the semiconductor chip is mounted may be reduced. The number of external terminals of the semiconductor device is increasing, and it becomes necessary to dispose the external terminals outside the area of the wiring board where the semiconductor chip is mounted, which may increase the area of the wiring board. An increase in the area of the wiring board leads to an increase in the package size of the semiconductor device. Furthermore, when the area of the wiring board is increased, the number of shots taken per shot in manufacturing the wiring board is reduced, leading to an increase in the cost of the wiring board.

また従来の半導体装置においては、半導体装置の２次実装の信頼性を向上するため、半導体チップをエラストマ（弾性部材）を介して配線基板に搭載するように構成されている。しかしながら、エラストマを介して半導体チップを配線基板に搭載することにより、熱膨張係数の差による応力を緩和し、２次実装の信頼性を向上できるが、エラストマは高価な材料であるため、半導体装置の製造コストが高くなってしまう。   Further, in the conventional semiconductor device, in order to improve the reliability of the secondary mounting of the semiconductor device, the semiconductor chip is mounted on the wiring board via an elastomer (elastic member). However, by mounting the semiconductor chip on the wiring board via the elastomer, stress due to the difference in thermal expansion coefficient can be relieved and the reliability of the secondary mounting can be improved. However, since the elastomer is an expensive material, the semiconductor device The manufacturing cost will be high.

さらに従来の半導体装置においては、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）方式により、フレキシブルな配線基板に半導体チップを搭載するため、シート寸法公差やうねりの影響により、必要な搭載精度が得られない、もしくは高価な搭載設備が必要となる恐れがあった。また半導体装置の電極パッドや配線等は狭ピッチ化してきており、搭載精度を向上させる必要性も高くなっている。   Furthermore, in a conventional semiconductor device, a semiconductor chip is mounted on a flexible wiring board by a TAB (Tape Automated Bonding) method, so that required mounting accuracy cannot be obtained due to the influence of sheet size tolerance and waviness, or is expensive. There was a risk that on-board equipment would be required. In addition, electrode pads, wirings, and the like of semiconductor devices have been narrowed, and the need to improve mounting accuracy has increased.

そこで、本発明は、１ショットあたりの取り数の減少を抑制するとともに、良好な電気特性を得、かつ半導体チップに作用する応力を緩和して信頼性の向上した半導体装置を提供することを目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device with improved reliability by suppressing a decrease in the number of shots per shot, obtaining good electrical characteristics, and reducing stress acting on a semiconductor chip. And

上記目的を達成するため本発明の半導体装置は、主面に複数の電極パッドが設けられた半導体チップと、半導体チップの電極パッド上に設けられた複数のバンプ電極と、半導体チップの主面側に配置され、半導体チップの端部から少なくとも５０μｍ以上離間するように半導体チップの主面の領域内に位置された配線基板と、配線基板上に設けられ、複数のバンプ電極に配線基板の配線を介して電気的に接続された複数の外部端子と、半導体チップと配線基板との間に設けられ、バンプ電極と配線との接続部を覆う絶縁性の封止部と、を備える。   In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor chip provided with a plurality of electrode pads on the main surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, and a main surface side of the semiconductor chip. Disposed on the main surface of the semiconductor chip so as to be at least 50 μm apart from the end of the semiconductor chip, and provided on the wiring board, and wiring of the wiring board is connected to the plurality of bump electrodes. And a plurality of external terminals electrically connected to each other, and an insulating sealing portion that is provided between the semiconductor chip and the wiring board and covers the connection portion between the bump electrode and the wiring.

本発明によれば、１ショットあたりの取り数の減少を抑制することができ、良好な電気特性を得ることができ、さらには半導体チップに作用する応力を緩和して信頼性を向上させることができる。   According to the present invention, it is possible to suppress a reduction in the number of shots per shot, to obtain good electrical characteristics, and to further improve the reliability by relaxing the stress acting on the semiconductor chip. it can.

次に、本発明の実施形態について図面を参照して詳細に説明する。
［第１の実施形態］
図１及び図２は、本実施形態におけるＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体装置１のパッケージ構造を示す図である。図１は側断面図であり、図２は平面図である。また、図３は、本発明の実施形態１である半導体装置のマザーボードへの実装形態を示す図である。 Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
1 and 2 are views showing a package structure of a BGA (Ball Grid Array) type semiconductor device 1 in the present embodiment. 1 is a side sectional view, and FIG. 2 is a plan view. FIG. 3 is a diagram showing a mounting form of the semiconductor device according to the first embodiment of the present invention on a motherboard.

本発明の一実施形態である半導体装置１は、図１及び図２に示すように、略四角形の板状で、主面２ａに所定の回路が形成された半導体チップ２を有している。半導体チップ２の主面２ａ側の中心線２ｄ上に一列で配置された複数の電極パッド３を有している。また電極パッド３を除く、半導体チップ２の主面２ａ上には絶縁性のパッシベーション膜４が形成され、半導体チップの回路形成面を保護している。半導体チップ２は例えばマイクロプロセッサ等のような論理回路またはＳＲＡＭ（Ｓｔａｔｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）やＤＲＡＭ（Ｄｙｎａｍｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）等のような記憶回路等の回路が形成されている。   As shown in FIGS. 1 and 2, a semiconductor device 1 according to an embodiment of the present invention includes a semiconductor chip 2 having a substantially rectangular plate shape and having a predetermined circuit formed on a main surface 2a. The semiconductor chip 2 has a plurality of electrode pads 3 arranged in a line on the center line 2d on the main surface 2a side. Further, an insulating passivation film 4 is formed on the main surface 2a of the semiconductor chip 2 except for the electrode pads 3 to protect the circuit formation surface of the semiconductor chip. The semiconductor chip 2 is formed with a logic circuit such as a microprocessor or a memory circuit such as an SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

また半導体チップ２上に形成された複数の電極パッド３上には、後述する配線基板に接続するためのバンプ電極５がそれぞれ形成されている。バンプ電極５は、例えば電極パッド３上に、溶融され先端にボールが形成されたワイヤを超音波熱圧着し、該ワイヤを引きちぎることにより形成される。   On the plurality of electrode pads 3 formed on the semiconductor chip 2, bump electrodes 5 for connection to a wiring board to be described later are formed. For example, the bump electrode 5 is formed on the electrode pad 3 by ultrasonically thermocompression-bonding a wire that is melted and formed with a ball at the tip and tearing the wire.

半導体チップ２の主面２ａ側には、半導体チップ２の面積より小さい面積で構成された配線基板６が配置されている。配線基板６は、例えばテープ状の配線基板であり、ポリイミド樹脂等からなるテープ基材７に、後述する外部端子を接続するための複数のランド８と、該ランド８と半導体チップ２の電極パッド３上に形成されたバンプ電極５とを接続するための配線９が形成されている。ランド８等の接続部位を除く、テープ基材７の表面上には、絶縁性の保護膜であるソルダーレジスト１０が設けられている。   On the main surface 2a side of the semiconductor chip 2, a wiring substrate 6 having an area smaller than the area of the semiconductor chip 2 is disposed. The wiring board 6 is, for example, a tape-shaped wiring board, and a plurality of lands 8 for connecting external terminals to be described later to a tape base material 7 made of polyimide resin or the like, and the lands 8 and electrode pads of the semiconductor chip 2. A wiring 9 for connecting the bump electrode 5 formed on the wiring 3 is formed. On the surface of the tape base material 7 excluding the connection site such as the land 8, a solder resist 10 that is an insulating protective film is provided.

配線基板６は、バンプ電極５と、導電性材料１１、例えば半田等を介して配線に電気的に接続されることで、半導体チップ２の略中央領域に搭載されている。本実施形態では、バンプ電極５が中心線２ｄ上に一列に設けられているため、半導体チップ２の長手方向に沿って長方形に形成されている。そして配線基板６の端部６ｂ、６ｃと半導体チップ２の端部２ｂ、２ｃとの間には離間領域２ｂ1、２ｃ1が形成されている。離間領域２ｂ1、２ｃ1は少なくとも５０μｍ以上の幅を有する。図２に示す例では配線基板６の端部６ｂから半導体チップ２の端部２ｂの間の離間領域２ｂ1は５０μｍである。なお、中央領域とは、半導体チップ２の主面２ａ上における離間領域２ｂ1、２ｃ1に囲まれた領域を指す。 The wiring substrate 6 is mounted in a substantially central region of the semiconductor chip 2 by being electrically connected to the wiring via the bump electrode 5 and the conductive material 11 such as solder. In the present embodiment, since the bump electrodes 5 are provided in a row on the center line 2 d, the bump electrodes 5 are formed in a rectangular shape along the longitudinal direction of the semiconductor chip 2. Separation regions 2 b 1 and 2 c 1 are formed between the end portions 6 b and 6 c of the wiring substrate 6 and the end portions 2 b and 2 c of the semiconductor chip 2. The separation regions 2b 1 and 2c 1 have a width of at least 50 μm. In the example shown in FIG. 2, the separation region 2 b 1 between the end 6 b of the wiring substrate 6 and the end 2 b of the semiconductor chip 2 is 50 μm. The central region refers to a region surrounded by the separation regions 2b 1 and 2c 1 on the main surface 2a of the semiconductor chip 2.

このように半導体チップ２の端部２ｂ、２ｃより５０μｍ以上離間するように配線基板６を搭載することで、半導体ウエハのダイシング時に回転研削するダイシングブレードが配線基板６に接触しないようにすることができ、配線基板６の剥がれ等を防止できる。また配線基板６の四隅は、面取り部１２が形成されており、配線基板６が剥がれ難くなるように構成されている。なお、面取り部１２は図に示すようなＲ面取りの他、どのような切り欠き形状としてもよく、Ｃ面取りとしてもよい。   In this way, by mounting the wiring board 6 so as to be separated from the end portions 2b and 2c of the semiconductor chip 2 by 50 μm or more, the dicing blade to be rotationally ground at the time of dicing the semiconductor wafer is prevented from coming into contact with the wiring board 6. It is possible to prevent the wiring substrate 6 from peeling off. In addition, chamfered portions 12 are formed at the four corners of the wiring board 6 so that the wiring board 6 is difficult to peel off. The chamfered portion 12 may have any cutout shape other than the R chamfer as shown in the figure, and may be a C chamfer.

なお、半導体チップ２の配線基板６を搭載する部位は、中央領域以外でも良い。しかしながら、熱応力等により半導体チップ２にソリが生じた場合等でも、中央領域はソリの影響を受け難く、信頼性を高めることができるため、配線基板６は半導体チップ２の中央領域に搭載するのが好ましい。   In addition, the site | part which mounts the wiring board 6 of the semiconductor chip 2 may be other than a center area | region. However, even when the semiconductor chip 2 is warped due to thermal stress or the like, the central region is hardly affected by the warp, and the reliability can be improved. Therefore, the wiring board 6 is mounted on the central region of the semiconductor chip 2. Is preferred.

また、配線基板６は４辺とも半導体チップ２の領域内に配置され、半導体チップ２の面積より小さく形成しているため、１ショットあたりの配線基板６の取り数を増やすことができ、半導体装置１の２次実装時の応力も緩和できる。   Further, since all the four sides of the wiring board 6 are arranged in the region of the semiconductor chip 2 and are formed smaller than the area of the semiconductor chip 2, the number of wiring boards 6 taken per shot can be increased. The stress at the time of secondary mounting 1 can be relaxed.

配線基板６に設けられたランド８上には、マザーボード１３等へ実装するための複数の外部端子１４が格子状に配置されている。外部端子１４は、例えば半田等からなるボールをランド８上にフラックスを介して搭載し、リフローすることで形成される。外部端子１４は、例えば０．３５ｍｍ径の大きさで、０．５ｍｍピッチで配置されることで、配線基板上に効率よく配置できる。また、外部端子１４を小さい面積の配線基板６に集約して配置することで、配線基板６上の配線も短くすることもでき、半導体装置の電気特性も向上できる。   On the lands 8 provided on the wiring board 6, a plurality of external terminals 14 for mounting on the mother board 13 and the like are arranged in a grid pattern. The external terminal 14 is formed, for example, by mounting a ball made of solder or the like on the land 8 via a flux and performing reflow. The external terminals 14 have a diameter of, for example, 0.35 mm and can be efficiently arranged on the wiring board by being arranged at a pitch of 0.5 mm. Further, by arranging the external terminals 14 on the wiring board 6 having a small area, the wiring on the wiring board 6 can be shortened, and the electrical characteristics of the semiconductor device can be improved.

また半導体チップ２と配線基板６との間には、絶縁性の封止材としてアンダーフィル材１５が設けられている。アンダーフィル材１５は、少なくともバンプ電極と配線との接続部（接続パッド）１６を覆うように構成されていれば良いが、本実施形態では、半導体チップにテープ状の配線基板が撓むことなく搭載するために、半導体チップと配線基板との間を覆うように設けられている。   An underfill material 15 is provided between the semiconductor chip 2 and the wiring substrate 6 as an insulating sealing material. The underfill material 15 only needs to be configured to cover at least the connection portion (connection pad) 16 between the bump electrode and the wiring, but in this embodiment, the tape-shaped wiring substrate is not bent on the semiconductor chip. In order to mount, it is provided so as to cover between the semiconductor chip and the wiring board.

このように、主面２ａに複数の電極パッド３が設けられた半導体チップ２と、半導体チップ２の電極パッド３上に設けられた複数のバンプ電極５と、半導体チップ２の主面２ａ側に配置され、半導体チップ２の端部２ｂ、２ｃから少なくとも５０μｍ以上離間するように半導体チップ２の主面２ａの中央領域内に位置された配線基板６と、配線基板６上に設けられ、複数のバンプ電極５に配線基板６の配線を介して電気的に接続された複数の外部端子１４と、半導体チップ２と配線基板６との間に設けられ、少なくともバンプ電極５と配線との接続部を覆うアンダーフィル材１５による封止部とからなる半導体装置を構成することにより、リアルチップサイズの半導体装置を実現できる。   Thus, the semiconductor chip 2 provided with the plurality of electrode pads 3 on the main surface 2a, the plurality of bump electrodes 5 provided on the electrode pads 3 of the semiconductor chip 2, and the main surface 2a side of the semiconductor chip 2 A wiring substrate 6 disposed in the central region of the main surface 2a of the semiconductor chip 2 so as to be separated from the ends 2b, 2c of the semiconductor chip 2 by at least 50 μm or more; Provided between the plurality of external terminals 14 electrically connected to the bump electrode 5 via the wiring of the wiring substrate 6 and between the semiconductor chip 2 and the wiring substrate 6, at least a connection portion between the bump electrode 5 and the wiring is provided. By configuring a semiconductor device including a sealing portion formed by the underfill material 15 to be covered, a real chip size semiconductor device can be realized.

また配線基板６の面積が半導体チップ２より小さいため、１ショット当たりの配線基板の取り数を多くでき、半導体装置のコストを低減できる。さらに配線基板６を半導体チップ２より小さい面積とすることで、半導体装置１の２次実装時に応力がかかる半導体チップ２の端部２ｂ、２ｃ近傍を避けて配線基板６を搭載することができるため、半導体装置１にかかる応力を緩和することができる。さらに配線基板６が半導体チップ２よりも小さいため、半導体チップ２と配線基板６との間へのアンダーフィル材１５の注入も容易になる。また配線基板６を半導体チップ２より小さく構成したことにより、マザーボード１３への実装部の面積も小さくできる。さらに配線基板６上の配線を短く構成できるため、半導体装置１の電気特性も向上できる。   Further, since the area of the wiring board 6 is smaller than the semiconductor chip 2, the number of wiring boards per shot can be increased, and the cost of the semiconductor device can be reduced. Furthermore, since the wiring board 6 has a smaller area than the semiconductor chip 2, the wiring board 6 can be mounted avoiding the vicinity of the ends 2 b and 2 c of the semiconductor chip 2 that is stressed during the secondary mounting of the semiconductor device 1. The stress applied to the semiconductor device 1 can be relaxed. Furthermore, since the wiring board 6 is smaller than the semiconductor chip 2, the underfill material 15 can be easily injected between the semiconductor chip 2 and the wiring board 6. Further, since the wiring board 6 is configured to be smaller than the semiconductor chip 2, the area of the mounting portion on the mother board 13 can be reduced. Furthermore, since the wiring on the wiring board 6 can be made short, the electrical characteristics of the semiconductor device 1 can also be improved.

また半導体チップ２の切断領域にレジン等を設けない構造としているため、ダイシング時の切断性能を向上し、かつレジン等に含まれるフィラーに起因するダイシングブレードの磨耗を防止でき、ダイシングブレードの消費を抑制できる。   In addition, since the resin or the like is not provided in the cutting region of the semiconductor chip 2, the cutting performance during dicing can be improved, and wear of the dicing blade due to the filler contained in the resin can be prevented. Can be suppressed.

また上述したように配線基板６を半導体チップ２の面積より小さく構成することにより、図３に示すようにマザーボード１３への実装面積を低減することができる。これによりマザーボード１３の空き領域に、チップコンデンサ等の小型の受動部品１７を搭載でき、マザーボードの小型化にも寄与できる。   Further, by configuring the wiring board 6 to be smaller than the area of the semiconductor chip 2 as described above, the mounting area on the mother board 13 can be reduced as shown in FIG. As a result, a small passive component 17 such as a chip capacitor can be mounted in an empty area of the mother board 13, which can contribute to miniaturization of the mother board.

図４は、半導体チップ２のバンプ電極５と配線基板６との接続構造の変形例を示す図であり、配線基板６のバンプ電極５に対応した位置にそれぞれ凹部１８が設けられている。凹部１８はバンプ電極５が配置される程度の大きさであれば良い。凹部１８には、配線基板６の外部端子側の表層配線が露出するように構成されており、バンプ電極５は導電性材料１１を介して、配線基板６の外部端子側の表層配線に接続される。これにより半導体装置１をさらに薄型化することができる。   FIG. 4 is a view showing a modified example of the connection structure between the bump electrode 5 of the semiconductor chip 2 and the wiring board 6, and the recesses 18 are provided at positions corresponding to the bump electrodes 5 of the wiring board 6. The recess 18 may have a size that allows the bump electrode 5 to be disposed. The surface layer wiring on the external terminal side of the wiring substrate 6 is exposed in the recess 18, and the bump electrode 5 is connected to the surface wiring on the external terminal side of the wiring substrate 6 through the conductive material 11. The Thereby, the semiconductor device 1 can be further reduced in thickness.

また凹部１８内の表層配線には、Ｃｕ／Ｎｉ／Ａｕのメッキ１９が設けられており、半導体チップ２と配線基板６との電気的接続を良好にできる。また電気的接続部に凹部１８を設けたことにより半導体チップと配線基板との接着面積を大きくできる。   In addition, Cu / Ni / Au plating 19 is provided on the surface wiring in the recess 18, so that the electrical connection between the semiconductor chip 2 and the wiring substrate 6 can be improved. Further, by providing the recess 18 in the electrical connection portion, the bonding area between the semiconductor chip and the wiring board can be increased.

図５は、多層配線基板を用いた場合の接続構造の変形例である。図４と同様に配線基板のバンプ電極に対応した部位に凹部１８を設け、凹部１８内に配線が露出するように構成するように、多層配線基板を用いることで、さらに半導体装置の高さを抑えて、高密度な配線が可能となる。   FIG. 5 shows a modification of the connection structure when a multilayer wiring board is used. Similar to FIG. 4, a recess 18 is provided in a portion corresponding to the bump electrode of the wiring board, and the wiring is exposed in the recess 18, so that the height of the semiconductor device is further increased by using the multilayer wiring board. Suppressing and high density wiring becomes possible.

次に、本実施形態の半導体装置の製造方法に関して説明する。   Next, a method for manufacturing the semiconductor device of this embodiment will be described.

図６〜図８は本実施形態の半導体装置の製造フローを示す図である。図６〜図８を参照して、本発明の一実施形態である半導体装置の製造方法について説明する。   6 to 8 are views showing a manufacturing flow of the semiconductor device of this embodiment. With reference to FIGS. 6-8, the manufacturing method of the semiconductor device which is one Embodiment of this invention is demonstrated.

まず半導体装置１の製造に用いられる半導体ウエハ２０は、例えば単結晶引き上げ法等により形成されたシリコンのインゴットをスライスして得られる円盤状の基板の主面に拡散等の工程を通じて、所望の回路及び電極パッドを形成したものが準備される。   First, a semiconductor wafer 20 used for manufacturing the semiconductor device 1 is obtained by performing a process such as diffusion on a main surface of a disk-shaped substrate obtained by slicing a silicon ingot formed by, for example, a single crystal pulling method. And what formed the electrode pad is prepared.

半導体ウエハ２０は、図６に示すように、枠状の治具２１に粘着性を有する耐熱テープ２２を貼り渡し、該耐熱テープ２２に裏面を貼着固定される。半導体ウエハ２０に設けられた半導体チップ２には、それぞれ複数の電極パッド３が形成されており、図７（ａ）に示すように、電極パッド３上にバンプ電極５が形成される。バンプ電極５は、例えば電極パッド３上に、溶融され先端にボールが形成されたワイヤを超音波熱圧着し、該ワイヤを引きちぎることで形成される。尚、バンプ電極は、メッキ等で形成してもよい。   As shown in FIG. 6, the semiconductor wafer 20 is bonded with a heat-resistant tape 22 having adhesiveness to a frame-shaped jig 21, and the back surface is bonded and fixed to the heat-resistant tape 22. A plurality of electrode pads 3 are respectively formed on the semiconductor chip 2 provided on the semiconductor wafer 20, and bump electrodes 5 are formed on the electrode pads 3 as shown in FIG. The bump electrode 5 is formed by, for example, ultrasonically thermocompression-bonding a wire that is melted and formed with a ball at the tip on the electrode pad 3 and tearing the wire. Note that the bump electrode may be formed by plating or the like.

バンプ形成後、半導体ウエハ２０は図７（ｂ）に示すように、それぞれの半導体チップ２のバンプ電極５を覆うように封止材、例えばアンダーフィル材１５が選択的に塗布される。アンダーフィル材１５は、例えば半導体ウエハ２０のバンプ形成領域に開口を有するマスク２３を搭載し、アンダーフィル材１５をスキージ２４で開口部に流し込むことで、選択的に形成できる。尚、アンダーフィル材１５は、半導体ウエハ２０へのスピンナー塗布により全面に形成するように構成しても良い。スピンナー塗布の場合は、より効率的にアンダーフィル材１５を半導体ウエハ上に均一な厚さで形成できる。   After the bump formation, as shown in FIG. 7B, the semiconductor wafer 20 is selectively coated with a sealing material, for example, an underfill material 15 so as to cover the bump electrodes 5 of the respective semiconductor chips 2. The underfill material 15 can be selectively formed, for example, by mounting a mask 23 having an opening in a bump formation region of the semiconductor wafer 20 and pouring the underfill material 15 into the opening with a squeegee 24. The underfill material 15 may be formed on the entire surface by spinner application to the semiconductor wafer 20. In the case of spinner coating, the underfill material 15 can be more efficiently formed on the semiconductor wafer with a uniform thickness.

また前述したように半導体チップ２の面積より小さい面積で構成され、複数のランド８と、該ランド８と半導体チップ２の電極パッド３上に形成されたバンプ電極５と接続するための所望の配線が形成された配線基板６が予め準備されている。配線基板６のバンプ電極５との接続部には、予め導電性材料１１、例えば半田等が設けられている。   Further, as described above, the wiring is configured with an area smaller than the area of the semiconductor chip 2, and a desired wiring for connecting the plurality of lands 8 and the bump electrodes 5 formed on the lands 8 and the electrode pads 3 of the semiconductor chip 2. A wiring board 6 on which is formed is prepared in advance. A conductive material 11, for example, solder or the like is provided in advance at a connection portion of the wiring board 6 with the bump electrode 5.

配線基板６は、図７（ｃ）に示すように、吸着コレット２５等に吸着された状態で、半導体チップ２の電極パッド３と配線基板の接続部（接続パッド）１６を位置合せし、配線基板の接続部（接続パッド）１６とバンプ電極５とを、導電性材料１１を介して電気的に接続することで、半導体チップ２上に搭載される。配線基板６の搭載は、図８に示すように、予めウエハバーンイン等の検査結果等に基づき、半導体ウエハ２０上の良品と判定された半導体チップ２のみに配線基板６が搭載される。このように不良判定された半導体チップ２に配線基板６を搭載しないことにより、配線基板６を搭載する工程の処理効率を向上できる。また配線基板６を効率良く利用できることでコスト低減にもつながる。   As shown in FIG. 7C, the wiring substrate 6 is in a state of being adsorbed by the adsorption collet 25 and the like, aligning the electrode pad 3 of the semiconductor chip 2 and the connection portion (connection pad) 16 of the wiring substrate, The board connection portion (connection pad) 16 and the bump electrode 5 are electrically connected via the conductive material 11 to be mounted on the semiconductor chip 2. As shown in FIG. 8, the wiring substrate 6 is mounted only on the semiconductor chip 2 that has been determined to be a non-defective product on the semiconductor wafer 20 based on the result of inspection such as wafer burn-in. By not mounting the wiring board 6 on the semiconductor chip 2 determined to be defective in this way, the processing efficiency of the process of mounting the wiring board 6 can be improved. Further, the wiring board 6 can be efficiently used, which leads to cost reduction.

また配線基板６を搭載するための吸着コレット２５に加熱機構を設け、配線基板６を搬送すると共に配線基板６を加熱することで、効率的に配線基板６を搭載するように構成しても良い。   Moreover, a heating mechanism may be provided in the suction collet 25 for mounting the wiring board 6 so that the wiring board 6 is transported and heated to heat the wiring board 6 so that the wiring board 6 can be mounted efficiently. .

配線基板６を半導体チップ２上に搭載することで、電極パッド３を覆うように選択的に塗布された封止材であるアンダーフィル材１５が広がり、半導体チップ２と配線基板６との隙間を覆う。このように、バンプ電極５と配線基板６との接合部、及び半導体チップ２と配線基板６の隙間をアンダーフィル材１５で覆うことで、接合部の保護し、配線基板を撓むことなく接着固定することができる。尚、アンダーフィル材１５は、配線基板６を半導体チップ２に搭載した後、配線基板６と半導体チップ２の隙間から、絶縁性のアンダーフィル材を注入することで形成しても良い。   By mounting the wiring substrate 6 on the semiconductor chip 2, the underfill material 15, which is a sealing material selectively applied so as to cover the electrode pads 3, spreads, and a gap between the semiconductor chip 2 and the wiring substrate 6 is formed. cover. In this way, the joint between the bump electrode 5 and the wiring board 6 and the gap between the semiconductor chip 2 and the wiring board 6 are covered with the underfill material 15 to protect the joint and adhere without bending the wiring board. Can be fixed. The underfill material 15 may be formed by injecting an insulating underfill material from the gap between the wiring substrate 6 and the semiconductor chip 2 after mounting the wiring substrate 6 on the semiconductor chip 2.

配線基板６の搭載された半導体チップ２は、ボールマウント工程に移行され、図７（ｄ）に示すように配線基板６上のランド８に導電性のボールが搭載され、複数の外部端子１４が形成される。ボールマウント工程では、配線基板６上のランド８の配置に合わせて複数の吸着孔が形成されたマウントツール２６を用いて、例えば半田等からなるボール２７を吸着孔に保持し、保持されたボール２７にフラックスを転写形成し、配線基板６上のランド８に一括搭載することで形成される。ボール搭載後、リフローすることで固定され、ランド上に外部端子が形成される。   The semiconductor chip 2 on which the wiring board 6 is mounted is transferred to a ball mounting process, and conductive balls are mounted on the lands 8 on the wiring board 6 as shown in FIG. It is formed. In the ball mounting process, a ball 27 made of, for example, solder is held in the suction hole by using the mounting tool 26 in which a plurality of suction holes are formed in accordance with the arrangement of the lands 8 on the wiring board 6. The flux is transferred and formed on 27 and mounted on the lands 8 on the wiring substrate 6 at once. After mounting the ball, it is fixed by reflow, and an external terminal is formed on the land.

その後、半導体ウエハ２０はダイシング工程に移行され、図７（ｅ）に示すように個々の半導体チップ２毎に切断分離される。ダイシング工程では、例えばダイシングテーブル上に載置され、高速回転のダイシングブレード２８により半導体チップ間のダイシングライン２９を回転研削し切断する。   Thereafter, the semiconductor wafer 20 is transferred to a dicing process, and is cut and separated for each individual semiconductor chip 2 as shown in FIG. In the dicing process, for example, the substrate is placed on a dicing table, and a dicing line 29 between semiconductor chips is rotationally ground and cut by a high-speed rotating dicing blade 28.

例えば、配線基板６は、その端部６ｂ、６ｃが、半導体チップ２の端部２ｂ、２ｃから５０μｍ以上離間するように搭載されている。このように半導体チップ２の端部から５０μｍ以上離して配線基板６を搭載することにより、ダイシング時に配線基板６の端部の剥がれを低減することができる。   For example, the wiring board 6 is mounted such that its end portions 6 b and 6 c are separated from the end portions 2 b and 2 c of the semiconductor chip 2 by 50 μm or more. By mounting the wiring board 6 at a distance of 50 μm or more from the end of the semiconductor chip 2 in this way, peeling of the end of the wiring board 6 can be reduced during dicing.

そして図７（ｆ）に示すように、耐熱テープ２２の下方から、ピックアップ装置の突き上げ手段３０により、半導体チップ２を突き上げて耐熱テープ２２から剥離させ、配線基板６の搭載された半導体チップ２をピックアップする。これにより、図１に示すようなリアルチップサイズの半導体装置１が得られる。   Then, as shown in FIG. 7F, the semiconductor chip 2 is pushed up and peeled off from the heat-resistant tape 22 by the push-up means 30 of the pickup device from below the heat-resistant tape 22, and the semiconductor chip 2 on which the wiring board 6 is mounted is removed. Pick up. Thus, a real chip size semiconductor device 1 as shown in FIG. 1 is obtained.

このように半導体チップ２の面積より小さい面積の配線基板を用いて、ウエハ状態で製造することで効率よく、半導体装置１を製造できる。また、半導体チップ２の面積より小さい面積の配線基板６を用いているため、１ショット当たりの取り数を多くできることとなり、半導体装置１のコスト低減が可能となる。また半導体ウエハの良品チップにのみ配線基板６を搭載することで、効率的に配線基板６を搭載することができる。   Thus, the semiconductor device 1 can be efficiently manufactured by manufacturing in a wafer state using the wiring substrate having an area smaller than the area of the semiconductor chip 2. Further, since the wiring substrate 6 having an area smaller than the area of the semiconductor chip 2 is used, the number of shots per shot can be increased, and the cost of the semiconductor device 1 can be reduced. Also, by mounting the wiring board 6 only on non-defective chips of the semiconductor wafer, the wiring board 6 can be mounted efficiently.

また半導体チップ２の端部２ｂ、２ｃから５０μｍ以上離間して配線基板６を搭載するため、ダイシング時にダイシングブレードに接触することなく良好に切断できる。また本実施形態の半導体装置１においては、半導体チップ２の切断領域にレジン等を設けない構造としているため、ダイシング時の切断性能を向上し、かつレジン等に含まれるフィラーに起因するダイシングブレードの磨耗を防止でき、ダイシングブレードの消費を抑制できる。
［第２の実施形態］
図９は、本実施形態の半導体装置１のパッケージ構造を示す側断面図である。図１０は、本実施形態の半導体装置１を裏面側から見た斜視図である。 Further, since the wiring substrate 6 is mounted at a distance of 50 μm or more from the end portions 2b and 2c of the semiconductor chip 2, it can be satisfactorily cut without contacting the dicing blade during dicing. Further, in the semiconductor device 1 of the present embodiment, since the resin or the like is not provided in the cutting region of the semiconductor chip 2, the cutting performance during dicing is improved and the dicing blade caused by the filler contained in the resin or the like is used. Abrasion can be prevented and consumption of the dicing blade can be suppressed.
[Second Embodiment]
FIG. 9 is a side sectional view showing the package structure of the semiconductor device 1 of this embodiment. FIG. 10 is a perspective view of the semiconductor device 1 of this embodiment as viewed from the back side.

本実施形態の半導体装置１は、第１の実施形態と同様に、略四角形の板状で、主面２ａに所定の回路が形成された半導体チップ２を有している。半導体チップ２の主面２ａ側の略中央領域に、例えば中央領域に一列で配置された複数の電極パッド３を有している。また電極パッドを除く、半導体チップ２の主面２ａ上には絶縁性のパッシベーション膜４が形成され、半導体チップ２の回路形成面を保護している。   Similar to the first embodiment, the semiconductor device 1 of the present embodiment has a semiconductor chip 2 that is a substantially rectangular plate shape and has a predetermined circuit formed on the main surface 2a. In a substantially central region on the main surface 2a side of the semiconductor chip 2, for example, a plurality of electrode pads 3 are arranged in a row in the central region. Further, an insulating passivation film 4 is formed on the main surface 2a of the semiconductor chip 2 excluding the electrode pads, and the circuit forming surface of the semiconductor chip 2 is protected.

また半導体チップ２上に形成された複数の電極パッド３上には、第１の実施形態と同様に、配線基板６に接続するためのバンプ電極５がそれぞれ形成されている。半導体チップ２の主面２ａの上方には、半導体チップ２の面積より小さい面積で構成された配線基板６が配置されている。配線基板６は、例えばテープ状の配線基板であり、ポリイミド樹脂等からなるテープ基材７に、後述する外部端子を接続するための複数のランド８と、該ランド８と半導体チップ２の電極パッド上に形成されたバンプ電極５とを接続するための配線９が形成されている。ランド８等の接続部位を除く、テープ基材７の表面上には、絶縁性の保護膜、例えばソルダーレジスト１０が設けられている。   On the plurality of electrode pads 3 formed on the semiconductor chip 2, bump electrodes 5 for connection to the wiring substrate 6 are respectively formed as in the first embodiment. Above the main surface 2 a of the semiconductor chip 2, a wiring substrate 6 having an area smaller than the area of the semiconductor chip 2 is disposed. The wiring board 6 is, for example, a tape-shaped wiring board, and a plurality of lands 8 for connecting external terminals to be described later to a tape base material 7 made of polyimide resin or the like, and the lands 8 and electrode pads of the semiconductor chip 2. A wiring 9 for connecting the bump electrode 5 formed thereon is formed. An insulating protective film, for example, a solder resist 10 is provided on the surface of the tape base material 7 excluding the connection sites such as the lands 8.

そして配線基板６は、バンプ電極５と、導電性材料１１を介して配線に電気的に接続されることで、半導体チップ２の略中央領域に搭載されている。本実施形態では、バンプ電極５が中央領域に一列に設けられているため、半導体チップ２の長手方向に沿って長方形に形成されている。また配線基板６の四隅は、面取り部１２が形成されており、配線基板６が剥がれ難くなるように構成されている。   The wiring substrate 6 is mounted in a substantially central region of the semiconductor chip 2 by being electrically connected to the wiring via the bump electrode 5 and the conductive material 11. In the present embodiment, since the bump electrodes 5 are provided in a row in the central region, the bump electrodes 5 are formed in a rectangular shape along the longitudinal direction of the semiconductor chip 2. In addition, chamfered portions 12 are formed at the four corners of the wiring board 6 so that the wiring board 6 is difficult to peel off.

本実施形態の特徴としては、第１の実施形態の構成の他に、半導体チップ２の主面２ａとは反対側の面（他面）に絶縁性の保護部材（第１の保護部材）３１を全面に設けた構成である。保護部材３１は、例えばエポキシ樹脂等が用いられる。保護部材３１は、例えば半導体ウエハの裏面研磨（バックグラインド）工程後、スピンナー塗布により液状樹脂を塗布することで、半導体ウエハの裏面全面に均一な厚さで形成される。   As a feature of the present embodiment, in addition to the configuration of the first embodiment, an insulating protective member (first protective member) 31 is provided on the surface (other surface) opposite to the main surface 2a of the semiconductor chip 2. Is provided on the entire surface. For example, an epoxy resin or the like is used for the protection member 31. The protective member 31 is formed with a uniform thickness over the entire back surface of the semiconductor wafer, for example, by applying a liquid resin by spinner coating after a back surface polishing (back grinding) process of the semiconductor wafer.

図９に示すように、半導体チップ２の他面側に絶縁性の樹脂からなる第１の保護部材３１を設けたことにより、半導体チップ２の割れ、欠けを低減できる。さらに第１の保護部材３１を有色材料で構成することで、図１０に示すように半導体チップの他面側に形成されるマークを鮮明に表示できるようになる。   As shown in FIG. 9, by providing the first protective member 31 made of an insulating resin on the other surface side of the semiconductor chip 2, it is possible to reduce cracks and chips of the semiconductor chip 2. Furthermore, the first protective member 31 is made of a colored material, so that marks formed on the other surface side of the semiconductor chip can be clearly displayed as shown in FIG.

このように、主面２ａに複数の電極パッド３が設けられた半導体チップ２と、半導体チップ２の電極パッド３上に設けられた複数のバンプ電極５と、半導体チップ２の主面２ａ側に配置され、かつ半導体チップ２の面積より小さい面積の配線基板６と、配線基板６上に設けられ、複数のバンプ電極５に、配線基板６の配線を介して電気的に接続された複数の外部端子１４と、半導体チップ２と配線基板６との間に設けられ、少なくともバンプ電極５と配線との接続部を覆うアンダーフィル材１５からなる封止部材と、半導体チップ２の主面２ａと対向する面側に、半導体チップ２の裏面を覆うように設けた第１の保護部材とから半導体装置１を構成することにより、リアルチップサイズの半導体装置１を実現でき、かつチップ裏面を保護することができる。また半導体チップ２の裏面、全面に有色の保護部材を形成したことで、半導体チップ２の裏面に形成されるマークを鮮明に表示することができる。   Thus, the semiconductor chip 2 provided with the plurality of electrode pads 3 on the main surface 2a, the plurality of bump electrodes 5 provided on the electrode pads 3 of the semiconductor chip 2, and the main surface 2a side of the semiconductor chip 2 A plurality of external wiring boards disposed on the wiring board 6 and having an area smaller than the area of the semiconductor chip 2 and electrically connected to the plurality of bump electrodes 5 via the wiring of the wiring board 6 A terminal 14, a sealing member provided between the semiconductor chip 2 and the wiring board 6 and covering at least a connection portion between the bump electrode 5 and the wiring, and a main member 2 a facing the main surface 2 a of the semiconductor chip 2. By configuring the semiconductor device 1 from the first protective member provided so as to cover the back surface of the semiconductor chip 2 on the surface to be processed, a real chip size semiconductor device 1 can be realized and the back surface of the chip is protected. Door can be. In addition, since the colored protective member is formed on the back surface and the entire surface of the semiconductor chip 2, the mark formed on the back surface of the semiconductor chip 2 can be clearly displayed.

また配線基板６が小さくなり、１ショット当たりの取り数を多くできるため、半導体装置１のコスト低減できる。さらに配線基板６をチップより小さい面積とすることで、チップにかかる応力を低減することができる。さらに配線基板６が小さいため、半導体チップ２と配線基板６との間へのアンダーフィル材１５を注入も容易になる。また配線基板６を小さくしたことにより、マザーボード１３への実装部の面積も小さくできる。さらに配線基板６上の配線を短く構成できるため、半導体装置１の電気特性も向上できる。   Moreover, since the wiring board 6 is reduced and the number of shots per shot can be increased, the cost of the semiconductor device 1 can be reduced. Furthermore, the stress applied to a chip | tip can be reduced by making the wiring board 6 into an area smaller than a chip | tip. Furthermore, since the wiring board 6 is small, it is easy to inject the underfill material 15 between the semiconductor chip 2 and the wiring board 6. Further, the area of the mounting portion on the mother board 13 can be reduced by reducing the size of the wiring board 6. Furthermore, since the wiring on the wiring board 6 can be made short, the electrical characteristics of the semiconductor device 1 can also be improved.

また半導体チップ２の切断領域にレジン等を設けない構造としているため、ダイシング時の切断性能を向上し、かつレジン等に含まれるフィラーに起因するダイシングブレードの磨耗を防止でき、ダイシングブレードの消費を抑制できる。   In addition, since the resin or the like is not provided in the cutting region of the semiconductor chip 2, the cutting performance during dicing can be improved, and wear of the dicing blade due to the filler contained in the resin can be prevented. Can be suppressed.

次に図１１を参照して、本実施形態の半導体装置１の製造方法について説明する。   Next, with reference to FIG. 11, the manufacturing method of the semiconductor device 1 of this embodiment is demonstrated.

まず実施形態１と同様に、所望の回路及び電極パッド３が形成された半導体ウエハ２０が準備される。   First, as in the first embodiment, a semiconductor wafer 20 on which desired circuits and electrode pads 3 are formed is prepared.

半導体ウエハ２０は、図１１（ａ）に示すように、主面、つまりは回路形成面をＢＧテープ３２に貼着固定する。その後、バックグラインド工程により半導体ウエハの他面側を研磨し、図１１（ｂ）に示すように、半導体ウエハ２０を７５０μｍ程度の厚さまで薄型化する。   As shown in FIG. 11A, the semiconductor wafer 20 is bonded and fixed to the BG tape 32 at the main surface, that is, the circuit forming surface. Thereafter, the other side of the semiconductor wafer is polished by a back grinding process, and as shown in FIG. 11B, the semiconductor wafer 20 is thinned to a thickness of about 750 μm.

バックグラインド後、半導体ウエハ２０は、図１１（ｃ）に示すように、ＢＧテープ３２に貼着固定された状態で、半導体ウエハ２０の他面、全面に第１の保護部材３１が形成される。第１の保護部材３１は、例えば絶縁性のポッティング用レジンをスピンナー塗布することで全面に形成する。スピンナー塗布により形成することで、保護部材が均一な厚さで形成できる。半導体ウエハの裏面に第１の保護部材を形成したことで、バックグラインド工程で薄型化された半導体ウエハの取扱い性や搬送が容易になる。   After the back grinding, as shown in FIG. 11C, the first protective member 31 is formed on the other surface and the entire surface of the semiconductor wafer 20 in a state where the semiconductor wafer 20 is bonded and fixed to the BG tape 32. . The first protective member 31 is formed on the entire surface by, for example, applying an insulating potting resin by spinner coating. By forming by spinner coating, the protective member can be formed with a uniform thickness. By forming the first protective member on the back surface of the semiconductor wafer, it becomes easy to handle and transport the semiconductor wafer thinned by the back grinding process.

次に裏面に第１の保護部材３１が形成された半導体ウエハ２０は、第１の実施形態と同様に、半導体チップ２の電極パッド３にバンプ電極５が形成され、半導体チップ２のバンプ電極５を覆うように封止材、例えばアンダーフィル材１５が選択的に塗布される。   Next, in the semiconductor wafer 20 having the first protective member 31 formed on the back surface, the bump electrodes 5 are formed on the electrode pads 3 of the semiconductor chip 2 as in the first embodiment, and the bump electrodes 5 of the semiconductor chip 2 are formed. A sealing material, for example, an underfill material 15 is selectively applied so as to cover the surface.

また前述したように半導体チップ２の面積より小さい面積で構成され、複数のランド８と、該ランド８と半導体チップ２の電極パッド３上に形成されたバンプ電極５と接続するための所望の配線が形成された配線基板６が予め準備されている。配線基板６は、第１の実施形態と同様に、半導体チップ２上に搭載される。配線基板６を半導体チップ２上に搭載することで、電極パッド３を覆うように選択的に塗布された封止材が広がり、半導体チップ２と配線基板６との隙間を覆う。配線基板６の搭載された半導体チップ２は、配線基板６上のランド８に導電性のボールが搭載され、複数の外部端子１４が形成される。   Further, as described above, the wiring is configured with an area smaller than the area of the semiconductor chip 2, and a desired wiring for connecting the plurality of lands 8 and the bump electrodes 5 formed on the lands 8 and the electrode pads 3 of the semiconductor chip 2. A wiring board 6 on which is formed is prepared in advance. The wiring board 6 is mounted on the semiconductor chip 2 as in the first embodiment. By mounting the wiring substrate 6 on the semiconductor chip 2, the sealing material selectively applied so as to cover the electrode pads 3 spreads, and covers the gap between the semiconductor chip 2 and the wiring substrate 6. In the semiconductor chip 2 on which the wiring board 6 is mounted, conductive balls are mounted on the lands 8 on the wiring board 6, and a plurality of external terminals 14 are formed.

その後、半導体ウエハはダイシング工程に移行され、個々の半導体チップ毎に切断分離される。ここで、半導体ウエハ２０の切断と共に、半導体ウエハ２０の裏面に形成された第１の保護部材３１も切断分離する。   Thereafter, the semiconductor wafer is transferred to a dicing process, where each semiconductor chip is cut and separated. Here, along with the cutting of the semiconductor wafer 20, the first protective member 31 formed on the back surface of the semiconductor wafer 20 is also cut and separated.

個々のチップ毎に切断分離した後、ＢＧテープ３２にＵＶ照射することで粘着力を低下させる。そして粘着力の低下したＢＧテープ３２の下方から、ピックアップ装置の突き上げ手段により、半導体チップ２の裏面を突き上げＢＧテープ３２から剥離させ、配線基板６の搭載された半導体チップ２をピックアップする。ここで、本実施形態では、半導体チップ２の裏面に第１の保護部材３１を設けている。このため、ピックアップ時に、半導体チップ２の裏面を直接的に突き上げることが無くなるため、半導体チップの割れ、欠けを低減することができる。   After cutting and separating each chip, the adhesive strength is reduced by irradiating the BG tape 32 with UV. The back surface of the semiconductor chip 2 is pushed up from the BG tape 32 by the pushing-up means of the pickup device from the lower side of the BG tape 32 with reduced adhesive strength, and the semiconductor chip 2 on which the wiring board 6 is mounted is picked up. Here, in the present embodiment, the first protective member 31 is provided on the back surface of the semiconductor chip 2. For this reason, since the back surface of the semiconductor chip 2 is not directly pushed up at the time of picking up, it is possible to reduce cracks and chipping of the semiconductor chip.

また半導体チップ２の面積より小さい面積の配線基板６を用いて、ウエハ状態で製造することで効率良く半導体装置１を製造できる。また、半導体チップ２の面積より小さい面積の配線基板６を用いているため、１ショット当たりの取り数を多くでき、半導体装置１のコスト低減が可能となる。   Further, the semiconductor device 1 can be efficiently manufactured by manufacturing in a wafer state using the wiring substrate 6 having an area smaller than the area of the semiconductor chip 2. Further, since the wiring substrate 6 having an area smaller than the area of the semiconductor chip 2 is used, the number of shots per shot can be increased, and the cost of the semiconductor device 1 can be reduced.

また本実施形態の半導体装置１においては、半導体チップの切断領域にレジン等を設けない構造としているため、ダイシング時の切断性能を向上し、かつレジン等に含まれるフィラーに起因するダイシングブレードの磨耗を防止でき、ダイシングブレードの消費を抑制できる。
［第３の実施形態］
図１２は、本実施形態の半導体装置のパッケージ構造を示す断面図である。 Further, in the semiconductor device 1 of this embodiment, since the resin is not provided in the cutting region of the semiconductor chip, the cutting performance during dicing is improved, and the dicing blade is worn due to the filler contained in the resin. Can be prevented and consumption of the dicing blade can be suppressed.
[Third Embodiment]
FIG. 12 is a cross-sectional view showing the package structure of the semiconductor device of this embodiment.

本実施形態の半導体装置１は、第１の実施形態または第２の実施形態の半導体装置の構成の他に、半導体チップ２の主面２ａ側において、配線基板６が搭載された位置を除いた部位に、絶縁性の第２の保護部材３３を設けている。換言すれば、第２の保護部材３３が、配線基板６が搭載された領域を包囲するように形成されていることにより、半導体装置１の回路面を保護することができる。これにより半導体チップ２の割れ、欠け等を防止することができる。   The semiconductor device 1 of this embodiment excludes the position where the wiring substrate 6 is mounted on the main surface 2a side of the semiconductor chip 2 in addition to the configuration of the semiconductor device of the first embodiment or the second embodiment. An insulating second protective member 33 is provided at the site. In other words, the second protective member 33 is formed so as to surround the region where the wiring substrate 6 is mounted, whereby the circuit surface of the semiconductor device 1 can be protected. Thereby, cracking, chipping, and the like of the semiconductor chip 2 can be prevented.

図１３は、本実施形態の半導体装置の変形例を示す断面図である。   FIG. 13 is a cross-sectional view showing a modification of the semiconductor device of this embodiment.

本実施形態では、前述した封止部材と第２の保護部材３３とを同一の材料で、スピンナー塗布により一括形成するように構成される。図１４に示すように、半導体ウエハへのバンプ電極形成後に、スピンナー塗布によりアンダーフィル材１５を半導体ウエハの主面に形成してから配線基板６を搭載するように構成したことにより、封止部の形成と共に第２の保護部材を効率よく形成することができる。   In the present embodiment, the above-described sealing member and the second protective member 33 are configured to be collectively formed of the same material by spinner application. As shown in FIG. 14, after the bump electrode is formed on the semiconductor wafer, the underfill material 15 is formed on the main surface of the semiconductor wafer by spinner coating, and then the wiring substrate 6 is mounted. Thus, the second protective member can be efficiently formed.

以上、本発明者によってなされた発明を実施形態に基づき具体的に説明したが、本発明は上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。例えば、本実施形態では、中央領域に１列の電極パッドが配列された半導体チップに適用した場合について説明したが、図１５に示すような中央領域に２列の電極パッドが配列された半導体チップ、図１６に示すような中央領域に十字状に電極パッドが配列された半導体チップにも適用可能である。   As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. Yes. For example, in the present embodiment, a case where the present invention is applied to a semiconductor chip in which one row of electrode pads is arranged in the central region has been described. However, a semiconductor chip in which two rows of electrode pads are arranged in the central region as shown in FIG. The present invention is also applicable to a semiconductor chip in which electrode pads are arranged in a cross shape in the central region as shown in FIG.

また、本発明は図１７に示すような中央領域のうちの周辺部分に電極パッドが配列された半導体装置にも適用可能である。   The present invention is also applicable to a semiconductor device in which electrode pads are arranged in the peripheral portion of the central region as shown in FIG.

さらに、図１８に示すように、本発明は配線基板６の他にこの配線基板６よりも面積が小さい小配線基板６’を中央領域に搭載した半導体装置にも適用可能である。なお、本発明は、小配線基板６’が複数搭載されているものであっても当然適用可能である。   Furthermore, as shown in FIG. 18, the present invention can be applied to a semiconductor device in which a small wiring substrate 6 ′ having a smaller area than the wiring substrate 6 is mounted in the central region in addition to the wiring substrate 6. The present invention is naturally applicable even if a plurality of small wiring boards 6 'are mounted.

また、図１９に示すように、本発明は、複数の配線基板６を中央領域に搭載した半導体装置にも適用可能である。   Further, as shown in FIG. 19, the present invention is also applicable to a semiconductor device in which a plurality of wiring boards 6 are mounted in the central region.

また本実施形態ではテープ状の配線基板を用いた場合について説明したが、ガラスエポキシ基板等のリジット基板を用いても良い。   Moreover, although the case where the tape-shaped wiring board was used was demonstrated in this embodiment, you may use rigid boards, such as a glass epoxy board | substrate.

さらに、本実施形態では、ＢＧＡタイプの半導体装置に適用した場合について説明したが、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）、ＭＣＰ（Ｍｕｌｔｉ Ｃｈｉｐ Ｐａｃｋａｇｅ）、ＳｉＰ（Ｓｙｓｔｅｍ Ｉｎ Ｐａｃｋａｇｅ）等、配線基板を用いる半導体装置に適用可能である。   Furthermore, in the present embodiment, the case where the present invention is applied to a BGA type semiconductor device has been described. However, the present invention is applied to a semiconductor device using a wiring substrate, such as CSP (Chip Size Package), MCP (Multi Chip Package), SiP (System In Package). Applicable.

本発明の第１の実施形態における半導体装置の側断面図である。1 is a side sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態における半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態における半導体装置のマザーボードへの実装形態を示す図である。It is a figure which shows the mounting form to the motherboard of the semiconductor device in the 1st Embodiment of this invention. 半導体チップのバンプ電極と配線基板との接続構造の変形例を示す図である。It is a figure which shows the modification of the connection structure of the bump electrode of a semiconductor chip, and a wiring board. 多層配線基板を用いた場合の接続構造の変形例を示す図である。It is a figure which shows the modification of the connection structure at the time of using a multilayer wiring board. 治具により保持された状態の半導体ウエハを示す模式図である。It is a schematic diagram which shows the semiconductor wafer of the state hold | maintained with the jig | tool. 本発明の第１の実施形態における半導体装置の製造工程を示す工程図である。It is process drawing which shows the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. 良品と判定された半導体チップのみに配線基板が搭載されている状態を示す模式図である。It is a schematic diagram which shows the state by which the wiring board is mounted only in the semiconductor chip determined to be non-defective. 本発明の第２の実施形態における半導体装置の側断面図である。It is a sectional side view of the semiconductor device in the 2nd Embodiment of this invention. 本発明の第２の実施形態における半導体装置を裏面側からみた斜視図である。It is the perspective view which looked at the semiconductor device in the 2nd Embodiment of this invention from the back surface side. 本発明の第２の実施形態における半導体装置の製造工程を示す工程図である。It is process drawing which shows the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. 本発明の第３の実施形態における半導体装置の側断面図である。It is a sectional side view of the semiconductor device in the 3rd Embodiment of this invention. 本発明の第３の実施形態の半導体装置において、封止部材と第２の保護部材とを同一の材料でスピンナー塗布により一括形成した例を示す側断面図である。In the semiconductor device of the 3rd Embodiment of this invention, it is a sectional side view which shows the example which formed the sealing member and the 2nd protection member collectively with the same material by spinner application | coating. 図１３に示す半導体装置の製造工程を示す工程図である。FIG. 14 is a process diagram showing a manufacturing process of the semiconductor device shown in FIG. 13; 中央領域に２列の電極パッドが配列された半導体チップを搭載した本発明の半導体装置の平面図である。It is a top view of the semiconductor device of this invention carrying the semiconductor chip by which the electrode pad of 2 rows was arranged in the center area | region. 中央領域に十字状に電極パッドが配列された半導体チップを搭載した本発明の半導体装置の平面図である。It is a top view of the semiconductor device of this invention which mounts the semiconductor chip by which the electrode pad was arranged in the cross shape in the center area | region. 中央領域に十字状に電極パッドが配列された半導体チップを搭載した本発明の半導体装置の平面図である。It is a top view of the semiconductor device of this invention which mounts the semiconductor chip by which the electrode pad was arranged in the cross shape in the center area | region. 配線基板及び小配線基板を半導体チップの中央領域に搭載した半導体装置の平面図である。It is a top view of the semiconductor device which mounted the wiring board and the small wiring board in the center area | region of a semiconductor chip. 複数の配線基板を半導体チップの中央領域に搭載した半導体装置の平面図である。It is a top view of the semiconductor device which mounted the some wiring board in the center area | region of the semiconductor chip.

符号の説明Explanation of symbols

１ 半導体装置
２ 半導体チップ
２ａ 主面
３ 電極パッド
２ｂ、２ｃ 端部
５ バンプ電極
６ 配線基板
１４ 外部端子
１５ アンダーフィル材 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 2a Main surface 3 Electrode pad 2b, 2c End part 5 Bump electrode 6 Wiring board 14 External terminal 15 Underfill material

Claims (17)

主面に複数の電極パッドが設けられた半導体チップと、
前記半導体チップの前記電極パッド上に設けられた複数のバンプ電極と、
前記半導体チップの前記主面側に配置され、前記半導体チップの端部から少なくとも５０μｍ以上離間するように前記半導体チップの前記主面の領域内に位置された配線基板と、
前記配線基板上に設けられ、前記複数のバンプ電極に前記配線基板の配線を介して電気的に接続された複数の外部端子と、
前記半導体チップと前記配線基板との間に設けられ、前記バンプ電極と前記配線との接続部を覆う絶縁性の封止部と、を備える半導体装置。 A semiconductor chip provided with a plurality of electrode pads on the main surface;
A plurality of bump electrodes provided on the electrode pads of the semiconductor chip;
A wiring substrate disposed on the main surface side of the semiconductor chip and positioned in the region of the main surface of the semiconductor chip so as to be separated from the end of the semiconductor chip by at least 50 μm;
A plurality of external terminals provided on the wiring board and electrically connected to the plurality of bump electrodes via the wiring of the wiring board;
A semiconductor device comprising: an insulating sealing portion provided between the semiconductor chip and the wiring substrate and covering a connection portion between the bump electrode and the wiring. 前記複数の電極パッドは、前記半導体チップの一辺の中心線に沿って配置されている、請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the plurality of electrode pads are arranged along a center line of one side of the semiconductor chip. 前記配線基板は、四角形に形成され、角部が面取り加工されている、請求項１または２記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring board is formed in a quadrangular shape and a corner portion is chamfered. 前記配線基板が、前記半導体チップ上に複数配置されている、請求項１ないし３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a plurality of the wiring boards are arranged on the semiconductor chip. 5. 前記配線基板は、フレキシブル配線基板である、請求項１ないし４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring board is a flexible wiring board. 前記配線基板は、前記バンプ電極に対応する位置に凹部が設けられ、該凹部が前記外部端子側の表層配線に電気的に接続されている、請求項１ないし５のいずれか１項に記載の半導体装置。   The said wiring board is provided with the recessed part in the position corresponding to the said bump electrode, This recessed part is electrically connected to the surface layer wiring by the side of the said external terminal. Semiconductor device. 前記半導体チップは、前記主面とは反対側の面に第１の保護部材を有する、請求項１ないし６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip has a first protection member on a surface opposite to the main surface. 前記半導体チップは、前記主面側に第２の保護部材を有する、請求項１ないし６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip has a second protective member on the main surface side. 前記第２の保護部材は前記配線基板が設けられた領域を包囲するように形成されている請求項８に記載の半導体装置。   The semiconductor device according to claim 8, wherein the second protection member is formed so as to surround a region where the wiring board is provided. 主面に所定の回路と複数の電極パッドを備えた半導体チップが形成された半導体ウエハを準備する工程と、
前記複数の電極パッドにバンプ電極を形成する工程と、
前記半導体チップの面積より小さい面積であり、かつ前記半導体チップ上に形成された前記複数の電極パッドにそれぞれに対応したランド部と、前記電極パッドと前記ランド部とを電気的に接続するための配線とを有する配線基板を準備する工程と、
前記半導体ウエハ上に形成された前記半導体チップのうち良品と判定された前記半導体チップに、前記半導体チップの前記バンプ電極と、前記ランドと電気的に接続された前記配線とを電気的に接続することで前記配線基板を搭載する工程と、
前記配線基板の搭載された前記半導体ウエハを個々の前記半導体チップ毎に切断して分離し、分離された該半導体チップをピックアップする工程とを有する半導体装置の製造方法。 Preparing a semiconductor wafer in which a semiconductor chip having a predetermined circuit and a plurality of electrode pads is formed on a main surface;
Forming bump electrodes on the plurality of electrode pads;
A land portion having an area smaller than an area of the semiconductor chip and corresponding to each of the plurality of electrode pads formed on the semiconductor chip, and electrically connecting the electrode pad and the land portion Preparing a wiring board having wiring;
The bump electrode of the semiconductor chip and the wiring electrically connected to the land are electrically connected to the semiconductor chip determined to be non-defective among the semiconductor chips formed on the semiconductor wafer. A step of mounting the wiring board,
A method of manufacturing a semiconductor device, comprising: cutting and separating the semiconductor wafer on which the wiring board is mounted for each semiconductor chip, and picking up the separated semiconductor chip. 前記配線基板を搭載する工程より前に、前記半導体ウエハの前記複数の電極パッドに封止材を塗布し、前記配線基板を搭載する工程にて前記半導体チップと前記配線基板との接合部に絶縁性の保護部材を形成する、請求項１０に記載の半導体装置の製造方法。   Prior to the step of mounting the wiring board, a sealing material is applied to the plurality of electrode pads of the semiconductor wafer, and the semiconductor chip and the wiring board are insulated from each other in the step of mounting the wiring board. The method for manufacturing a semiconductor device according to claim 10, wherein a protective member is formed. 前記封止材の塗布工程は、前記半導体ウエハ上にマスクを搭載し、前記電極パッドに選択的に前記保護部材を形成する、請求項１１に記載の半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 11, wherein, in the sealing material application step, a mask is mounted on the semiconductor wafer, and the protective member is selectively formed on the electrode pad. 前記封止材の塗布工程は、前記半導体ウエハに前記保護部材をスピンナー塗布することで形成する、請求項１１または１２に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 11, wherein the applying step of the sealing material is formed by applying the protective member to the semiconductor wafer by a spinner. 前記配線基板の複数の前記ランド部に導電性のボールを搭載することで外部端子を形成する工程を含む、請求項１０ないし１３のいずれか１項に記載の半導体装置の製造方法。   14. The method for manufacturing a semiconductor device according to claim 10, further comprising a step of forming an external terminal by mounting conductive balls on the plurality of land portions of the wiring board. 前記配線基板は、前記半導体チップの端部から少なくとも５０μｍ以上離間するように前記半導体チップの前記主面の領域内に搭載される、請求項１０ないし１４のいずれか１項に記載の半導体装置の製造方法。   15. The semiconductor device according to claim 10, wherein the wiring substrate is mounted in a region of the main surface of the semiconductor chip so as to be at least 50 μm away from an end portion of the semiconductor chip. Production method. 前記半導体チップをピックアップする工程は、前記配線基板が搭載された前記半導体チップのみをピックアップする、請求項１０ないし１５のいずれか１項に記載の半導体装置の製造方法。   16. The method of manufacturing a semiconductor device according to claim 10, wherein the step of picking up the semiconductor chip picks up only the semiconductor chip on which the wiring board is mounted. 前記バンプ電極を形成する工程より前に、前記半導体チップの前記主面と反対側の面に第１の保護部材を形成する工程を含む、請求項１０ないし１６のいずれか１項に記載の半導体装置の製造方法。   17. The semiconductor according to claim 10, further comprising a step of forming a first protection member on a surface opposite to the main surface of the semiconductor chip before the step of forming the bump electrode. Device manufacturing method.
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DE102008031511A1 (en) 2009-04-23
US20120119356A1 (en) 2012-05-17

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