JP2015128120A - Multi-piece wiring board and manufacturing method of the same - Google Patents

Multi-piece wiring board and manufacturing method of the same Download PDF

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JP2015128120A
JP2015128120A JP2013273631A JP2013273631A JP2015128120A JP 2015128120 A JP2015128120 A JP 2015128120A JP 2013273631 A JP2013273631 A JP 2013273631A JP 2013273631 A JP2013273631 A JP 2013273631A JP 2015128120 A JP2015128120 A JP 2015128120A
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wiring board
support substrate
insulating layer
bottom plate
opening
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知治 土田
Tomoharu Tsuchida
知治 土田
一喜 岡
Kazuki Oka
一喜 岡
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Kyocera Circuit Solutions Inc
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Kyocera Circuit Solutions Inc
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Abstract

PROBLEM TO BE SOLVED: To provide a multi-piece wiring board which is unlikely to cause chips and cracks in wiring board at the time of dicing; and provide a multi-piece wiring board which can form a wiring board having another shape other than a rounded rectangle and a rectangle after being divided by dicing.SOLUTION: A wiring board 10 comprises: an etchable support substrate 1 in which a frame part 4 having an opening 4a to partition a tabular bottom plate 3 into a number of product formation regions X arranged in a matrix is installed on the bottom plate 3 in a protruding manner; an insulation layer 5 which is formed on a top face of the support substrate 1 to fill up the opening 4a and has a thickness to thinly cover a top face of the frame part 4; and a wiring conductor 6 which is formed on the insulation layer 5 on the produce formation regions X to form a wiring board 2 together with the insulation layer 5 on the product formation region X.

Description

本発明は、多数の小型の配線基板を縦横の並びに配列形成して成る多数個取り配線基板およびその製造方法に関するものである。   The present invention relates to a multi-piece wiring board formed by arranging a large number of small wiring boards vertically and horizontally and a method for manufacturing the same.

従来、CSP(チップサイズパッケージ)用の多数個取り配線基板として、金属から成る支持基板上に、絶縁層と導体層とを積層して成る多数の小型の配線基板を縦横の並びに一体的に形成して成る多数個取り配線基板が知られている。   Conventionally, as a multi-cavity wiring board for CSP (chip size package), a large number of small wiring boards formed by laminating an insulating layer and a conductor layer are integrally formed vertically and horizontally on a support substrate made of metal. A multi-cavity wiring board is known.

このような多数個取り配線基板では、支持基板上に一体的に形成された各小型の配線基板上に半導体素子を実装するとともに、上面の略全面に半導体素子を覆うように封止樹脂層を形成し、次に支持基板をエッチング除去した後、各小型の配線基板の境界に沿ってダイシングにより切断して分割することにより、配線基板上に実装された半導体素子が封止樹脂により封止された小型の半導体装置が多数個同時集約的に製造される。   In such a multi-cavity wiring board, a semiconductor element is mounted on each small wiring board formed integrally on a support substrate, and a sealing resin layer is provided so as to cover the semiconductor element on substantially the entire upper surface. After forming and then etching away the support substrate, the semiconductor element mounted on the wiring substrate is sealed with a sealing resin by cutting and dividing along the boundary of each small wiring substrate by dicing A large number of small semiconductor devices are manufactured simultaneously.

しかしながら、上述した従来の多数個取り配線基板においては、配線基板を形成する樹脂層が薄く機械的な強度が低いことから、支持基板をエッチング除去した後にダイシングすると、ダイシングの際に加わる応力により配線基板に割れや欠けが発生しやすい。また、多数個取り配線基板およびその上の封止樹脂をダイシングすることにより小型の半導体装置に分割することから、分割された配線基板の形状は角が立った四角形状に限定されてしまう。そのため、配線基板に半導体素子が実装された半導体装置が収容される電子機器の筐体のデザインに応じて角の丸い四角形状や四角形以外の形状を有する配線基板が要求される場合にその要求に応えることが困難である。   However, in the conventional multi-cavity wiring board described above, since the resin layer forming the wiring board is thin and the mechanical strength is low, if the dicing is performed after the support substrate is removed by etching, the wiring is caused by the stress applied during the dicing. The substrate is easily cracked or chipped. In addition, since the multi-piece wiring board and the sealing resin thereon are diced to be divided into small semiconductor devices, the shape of the divided wiring board is limited to a rectangular shape with corners. Therefore, when a wiring board having a square shape with rounded corners or a shape other than a square is required according to the design of the casing of an electronic device in which a semiconductor device having a semiconductor element mounted on the wiring board is accommodated, this requirement is met. It is difficult to respond.

特開2004−111641号公報JP 2004-111641 A

本発明は、ダイシングする際に配線基板に割れや欠けが発生しにくい多数個取り配線基板を提供することを目的とする。さらに本発明は、ダイシングにより分割された後、角の丸い四角形や四角形以外の他の形状を有する配線基板を形成することが可能な多数個取り配線基板を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-piece wiring board that is less likely to be cracked or chipped when dicing. Furthermore, an object of the present invention is to provide a multi-piece wiring board capable of forming a wiring board having a quadrangular shape with rounded corners or a shape other than a quadrangular shape after being divided by dicing.

本発明の多数個取り配線基板は、平板状の底板上に、該底板上を縦横の並びの多数の製品形成領域に仕切る開口部を有する枠部が突設されて成るエッチング可能な支持基板と、該支持基板の上面に形成されており、前記開口部内を充填するとともに前記枠部上面を薄く覆う厚みの絶縁層と、前記製品形成領域上の前記絶縁層上に形成されており、前記製品形成領域上の前記絶縁層とともに配線基板を形成する配線導体と、を具備して成ることを特徴とするものである。   The multi-cavity wiring board according to the present invention includes an etching support substrate formed by projecting a frame portion having openings on a flat bottom plate to divide the bottom plate into a large number of product formation regions arranged vertically and horizontally. An insulating layer formed on an upper surface of the support substrate, filling the opening and covering the upper surface of the frame portion thinly; and an insulating layer on the product forming region; And a wiring conductor that forms a wiring board together with the insulating layer on the formation region.

また、本発明の多数個取り配線基板の製造方法は、平板状の底板上に、該底板上を縦横の並びの多数の製品形成領域に仕切る開口部を有する枠部が突設されて成るエッチング可能な支持基板を準備する第1の工程と、前記支持基板上に、前記開口部内を充填するとともに前記枠部上を薄く覆う厚みの絶縁層を形成する第2の工程と、前記各製品形成領域上の前記絶縁層上に配線導体を形成する第3の工程と、を行うことを特徴とするものである。   The method of manufacturing a multi-cavity wiring board according to the present invention includes an etching process in which a frame portion having openings that divide the bottom plate into a large number of vertical and horizontal product forming regions is provided on a flat bottom plate. A first step of preparing a possible support substrate, a second step of forming an insulating layer having a thickness that fills the opening and thinly covers the frame portion on the support substrate, and each product formation And a third step of forming a wiring conductor on the insulating layer on the region.

本発明の多数個取り配線基板によれば、支持基板の上面に、枠部の開口部内を充填するとともに枠部上面を薄く覆う厚みの絶縁層が形成されており、製品形成領域上の絶縁層上に配線導体が形成されていることから、各配線基板上に半導体素子を実装するとともに上面の略全面に半導体素子を覆う封止樹脂層を形成し、次に支持基板をエッチング除去すると、各配線基板の境界は、枠部が除去された段差により形成され、薄い絶縁層が残る。したがって、各配線基板の境界に沿ってダイシングにより切断して分割する際、封止樹脂層および薄い絶縁層を切断すればよく、それにより配線基板に割れや欠けが発生することを有効に防止することができる。   According to the multi-cavity wiring board of the present invention, the insulating layer having a thickness that fills the inside of the opening of the frame portion and thinly covers the upper surface of the frame portion is formed on the upper surface of the support substrate. Since the wiring conductor is formed on the upper surface, the semiconductor element is mounted on each wiring board and the sealing resin layer covering the semiconductor element is formed on the substantially entire upper surface, and then the supporting substrate is removed by etching. The boundary of the wiring board is formed by a step from which the frame portion is removed, and a thin insulating layer remains. Therefore, when cutting and dividing along the boundary of each wiring substrate by cutting, it is only necessary to cut the sealing resin layer and the thin insulating layer, thereby effectively preventing the wiring substrate from being cracked or chipped. be able to.

さらに、本発明の多数個取り配線基板によれば、枠部の開口部内周の形状を例えば角の丸い四角形状や四角形以外の形状とし、その内側の各製品形成領域内の底板上に枠部内周の形状に対応した外形の配線基板を形成することで、各配線基板上に半導体素子を実装するとともに上面の略全面に半導体素子を覆う封止樹脂層を形成し、次に支持基板をエッチング除去した後、各配線基板の境界に沿ってダイシングにより封止樹脂層および薄い絶縁層を切断することにより、封止樹脂は角の立った四角形状であるものの、配線基板の厚みの大部分は角の丸い四角形状や四角形以外の形状とすることができる。   Furthermore, according to the multi-cavity wiring board of the present invention, the shape of the inner periphery of the opening portion of the frame portion is, for example, a square shape with rounded corners or a shape other than a square shape, By forming a wiring board having an outer shape corresponding to the shape of the circumference, a semiconductor element is mounted on each wiring board, and a sealing resin layer covering the semiconductor element is formed on substantially the entire upper surface, and then the support substrate is etched. After removing, by cutting the sealing resin layer and the thin insulating layer by dicing along the boundary of each wiring board, the sealing resin is a square with a corner, but most of the thickness of the wiring board is The shape may be a quadrangular shape with rounded corners or a shape other than a quadrangular shape.

また、本発明の多数個取り配線基板の製造方法によれば、平板状の底板上を縦横の並びの多数の製品形成領域に仕切る開口部を有する枠部が突設されたエッチング可能な支持基板上に、開口部内を充填するとともに枠部上を薄く覆う厚みの絶縁層を形成し、次に各製品形成領域上の絶縁層上に配線導体を形成することにより、ダイシングする際に配線基板に割れや欠けが発生しにくい多数個取り配線基板を提供することができる。さらに、底板上を製品形成領域に仕切る開口部内周の形状を例えば角の丸い四角形状や四角形以外の形状としておくと、ダイシングにより分割された後、角の丸い四角形や四角形以外の他の形状を有する配線基板を形成することが可能な多数個取り配線基板を提供することができる。   Further, according to the method for manufacturing a multi-cavity wiring board of the present invention, an etchable support substrate having a projecting frame portion having openings for partitioning a flat bottom plate into a large number of product formation regions arranged in rows and columns. An insulating layer having a thickness that fills the inside of the opening and thinly covers the frame portion is formed on the upper portion, and then a wiring conductor is formed on the insulating layer on each product formation region. It is possible to provide a multi-cavity wiring board that is less likely to be cracked or chipped. Furthermore, if the shape of the inner periphery of the opening that divides the bottom plate into product formation areas is set to, for example, a square shape with rounded corners or a shape other than a quadrangle, after being divided by dicing, other shapes other than the square with a rounded corner or the quadrangle are formed. A multi-piece wiring board capable of forming a wiring board having the wiring board can be provided.

図1(a),(b)は、本発明の多数個取り配線基板の実施形態の一例を示す概略断面図および上面側から見た分解斜視図である。1A and 1B are a schematic cross-sectional view showing an example of an embodiment of a multi-cavity wiring board according to the present invention and an exploded perspective view seen from the upper surface side. 図2(a),(b)は、図1(a),(b)に示す多数個取り配線基板に半導体素子を実装した状態を示す概略断面図および上面側から見た斜視図である。2A and 2B are a schematic cross-sectional view showing a state in which a semiconductor element is mounted on the multi-piece wiring board shown in FIGS. 1A and 1B and a perspective view seen from the upper surface side. 図3(a),(b)は、図2(a),(b)に示した半導体素子が実装された多数個取り配線基板上に封止樹脂層を形成した状態を示す概略断面図および上面側から見た斜視図である。3A and 3B are schematic cross-sectional views showing a state in which a sealing resin layer is formed on a multi-piece wiring board on which the semiconductor elements shown in FIGS. 2A and 2B are mounted. It is the perspective view seen from the upper surface side. 図4(a),(b)は、図3(a),(b)に示した封止樹脂層が形成された多数個取り配線基板に半田バンプを形成した状態を示す概略断面図および上面側から見た斜視図である。4A and 4B are a schematic cross-sectional view and a top view showing a state in which solder bumps are formed on the multi-piece wiring board on which the sealing resin layer shown in FIGS. 3A and 3B is formed. It is the perspective view seen from the side. 図5(a),(b)は、図4(a),(b)に示した多数個取り配線基板における支持基板をエッチング除去した状態を示す概略断面図および下面側から見た斜視図である。5A and 5B are a schematic cross-sectional view showing a state where the support substrate in the multi-piece wiring substrate shown in FIGS. 4A and 4B is removed by etching and a perspective view seen from the lower surface side. is there. 図6(a),(b)は、図5(a),(b)に示した支持基板が除去された多数個取り配線基板をダイシングにより分割した状態を示す概略断面図および下面側から見た斜視図である。6 (a) and 6 (b) are schematic cross-sectional views showing a state in which the multi-piece wiring board from which the supporting board shown in FIGS. 5 (a) and 5 (b) has been removed is divided by dicing, and viewed from the lower surface side. FIG. 図7(a),(b)は、図4(a),(b)に示した支持基板付きの多数個取り配線基板を封止樹脂層とともにダイシングにより分割した状態を示す概略断面図および上面側から見た斜視図である。FIGS. 7A and 7B are a schematic cross-sectional view and a top view showing a state in which the multi-piece wiring board with the supporting substrate shown in FIGS. 4A and 4B is divided together with the sealing resin layer by dicing. It is the perspective view seen from the side. 図8(a),(b)は、本発明の多数個取り配線基板の製造方法を説明するための概略断面図および上面側から見た斜視図である。FIGS. 8A and 8B are a schematic cross-sectional view and a perspective view seen from the upper surface side for explaining the method for manufacturing a multi-piece wiring board of the present invention. 図9(a),(b)は、本発明の多数個取り配線基板の製造方法を説明するための概略断面図および上面側から見た斜視図である。9A and 9B are a schematic cross-sectional view and a perspective view seen from the upper surface side for explaining the method for manufacturing a multi-piece wiring board of the present invention. 図10(a),(b)は、本発明の多数個取り配線基板の製造方法を説明するための概略断面図および上面側から見た斜視図である。10A and 10B are a schematic cross-sectional view and a perspective view seen from the upper surface side for explaining the method for manufacturing a multi-piece wiring board according to the present invention. 図11(a),(b)は、本発明の多数個取り配線基板の製造方法を説明するための概略断面図および上面側から見た斜視図である。11A and 11B are a schematic cross-sectional view and a perspective view seen from the upper surface side for explaining the method for manufacturing a multi-piece wiring board of the present invention.

次に、本発明の多数個取り配線基板の実施形態の一例を添付の図面を基に説明する。図1(a),(b)に示すように、本例の多数個取り配線基板10は、支持基板1と、支持基板1の上に形成された配線基板2とを備えている。   Next, an example of an embodiment of the multi-piece wiring board of the present invention will be described with reference to the accompanying drawings. As shown in FIGS. 1A and 1B, the multi-piece wiring substrate 10 of this example includes a support substrate 1 and a wiring substrate 2 formed on the support substrate 1.

支持基板1は、平板状の底板3と、底板3上に突設された枠部4とから成る。底板3は、その上面に複数の製品形成領域Xを有しており、底板3の上面を製品形成領域Xに仕切る開口部4aを有するように枠部4が突設されている。この例では、開口部4aの内周は角の丸い四角形状をしている。支持基板1は、厚みが120〜240μm程度の銅箔の上面にエッチングを施して製品形成領域Xの部分を食刻すことにより枠部4を突設して成り、底板3の厚みが100〜200μm程度、枠部4の厚みが10〜30μm程度となっている。なお、この例では、簡略のため4つの製品形成領域Xを有する場合を示しているが、実際にはもっと多数の製品形成領域Xが配列される。   The support substrate 1 includes a flat bottom plate 3 and a frame portion 4 projecting from the bottom plate 3. The bottom plate 3 has a plurality of product forming regions X on its upper surface, and a frame portion 4 is projected so as to have an opening 4 a that partitions the upper surface of the bottom plate 3 into the product forming regions X. In this example, the inner periphery of the opening 4a has a quadrangular shape with rounded corners. The support substrate 1 is formed by projecting a frame portion 4 by etching the upper surface of a copper foil having a thickness of about 120 to 240 μm and etching the portion of the product formation region X, and the thickness of the bottom plate 3 is 100 to 100 mm. The thickness of the frame portion 4 is about 10 to 30 μm. In this example, the case where four product forming regions X are provided is shown for the sake of brevity, but a larger number of product forming regions X are actually arranged.

配線基板2は、支持基板1の製品形成領域X上に底板3および枠部4の内周面と密着するようにして形成されている。配線基板2は、製品形成領域Xの底板3上に形成された絶縁層5と、その上に形成された配線導体6と、その上に形成されたソルダーレジスト層7とから成る。なお、絶縁層5の一部は枠部4の上面を1〜5μm程度の厚みで薄く覆っている。   The wiring substrate 2 is formed on the product formation region X of the support substrate 1 so as to be in close contact with the bottom plate 3 and the inner peripheral surface of the frame portion 4. The wiring board 2 includes an insulating layer 5 formed on the bottom plate 3 in the product formation region X, a wiring conductor 6 formed thereon, and a solder resist layer 7 formed thereon. A part of the insulating layer 5 covers the upper surface of the frame 4 thinly with a thickness of about 1 to 5 μm.

絶縁層5は、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂にシリカ等の無機絶縁物フィラーを分散させた電気絶縁材料から成る。絶縁層5の厚みは、例えば10〜30μm程度である。配線導体6は、例えば銅めっき層から成る。配線導体6の厚みは例えば5〜15μm程度である。   The insulating layer 5 is made of an electrically insulating material in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as an epoxy resin or a polyimide resin. The thickness of the insulating layer 5 is, for example, about 10 to 30 μm. The wiring conductor 6 is made of, for example, a copper plating layer. The thickness of the wiring conductor 6 is, for example, about 5 to 15 μm.

配線導体6は、その一部に半導体素子接続パッド8と外部接続パッド9とを有している。これらの半導体素子接続パッド8および外部接続パッド9は、ソルダーレジスト層7に設けた開口部から外部に露出している。   The wiring conductor 6 has a semiconductor element connection pad 8 and an external connection pad 9 in a part thereof. These semiconductor element connection pads 8 and external connection pads 9 are exposed to the outside through openings provided in the solder resist layer 7.

ソルダーレジスト層7は、例えばアクリル変性エポキシ樹脂等の感光性の熱硬化性樹脂から成る。ソルダーレジスト層7の厚みは、配線導体6の上で5〜15μm程度である。   The solder resist layer 7 is made of a photosensitive thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 7 is about 5 to 15 μm on the wiring conductor 6.

ここで、本例の多数個取り配線基板10を用いて、各配線基板2上に半導体素子を実装するとともに樹脂封止して成る半導体装置の製造方法を説明する。   Here, a manufacturing method of a semiconductor device in which a semiconductor element is mounted on each wiring board 2 and resin-sealed using the multi-cavity wiring board 10 of this example will be described.

先ず、図2(a),(b)に示すように、多数個取り配線基板10の各配線基板2上に半導体素子Sを実装する。半導体素子Sの実装は、半導体素子Sの電極端子Tを配線基板2の半導体素子接続パッド8に半田を介してフリップチップ接続することにより行われる。   First, as shown in FIGS. 2A and 2B, the semiconductor element S is mounted on each wiring board 2 of the multi-piece wiring board 10. The semiconductor element S is mounted by flip-chip connecting the electrode terminals T of the semiconductor element S to the semiconductor element connection pads 8 of the wiring board 2 via solder.

次に、図3(a),(b)に示すように、半導体素子Sが実装された多数個取り配線基板10の上面に半導体素子Sを覆うとともに外部接続パッド9を露出させる開口部Maを有する封止樹脂層Mをトランスファーモールド法により形成する。   Next, as shown in FIGS. 3A and 3B, an opening Ma that covers the semiconductor element S and exposes the external connection pad 9 on the upper surface of the multi-piece wiring substrate 10 on which the semiconductor element S is mounted is formed. An encapsulating resin layer M is formed by a transfer molding method.

次に、図4(a),(b)に示すように、開口部Ma内に露出する外部接続パッド9に半田バンプBを形成する。半田バンプBは、開口部Ma内にフラックスを塗布した後、その上に半田ボールを載置してリフロー処理することにより形成される。   Next, as shown in FIGS. 4A and 4B, solder bumps B are formed on the external connection pads 9 exposed in the openings Ma. The solder bump B is formed by applying a flux in the opening Ma, and then placing a solder ball thereon to perform a reflow process.

次に、図5(a),(b)に示すように、支持基板1をエッチングにより除去する。支持基板1は、銅から成るので、例えば塩化第二鉄や塩化第二銅等を含有するエッチング液により容易にエッチングすることができる。このとき、各配線基板2の境界は、枠部4が除去された跡の段差により形成される。段差部には、薄い絶縁層5と封止樹脂層Mのみが存在している。   Next, as shown in FIGS. 5A and 5B, the support substrate 1 is removed by etching. Since the support substrate 1 is made of copper, it can be easily etched with an etchant containing, for example, ferric chloride or cupric chloride. At this time, the boundary of each wiring board 2 is formed by a step of the trace from which the frame portion 4 is removed. Only the thin insulating layer 5 and the sealing resin layer M exist in the stepped portion.

次に、図6(a),(b)に示すように、各配線基板2の境界に沿ってダイシングすることにより配線基板2に実装された半導体素子Sが封止樹脂層Mにより樹脂封止された半導体装置が形成される。このとき、配線基板2の境界に位置する薄い絶縁層5および封止樹脂層Mのみを切断すればよいので、配線基板2にダイシングの応力による割れや欠けが発生することはない。   Next, as shown in FIGS. 6A and 6B, the semiconductor element S mounted on the wiring board 2 is resin-sealed by the sealing resin layer M by dicing along the boundary of each wiring board 2. The formed semiconductor device is formed. At this time, since only the thin insulating layer 5 and the sealing resin layer M located at the boundary of the wiring board 2 have to be cut, the wiring board 2 is not cracked or chipped due to dicing stress.

また、本発明の多数個取り配線基板10によれば、支持基板1の開口部4aの内周は角の丸い四角形状をしており、配線基板2は、支持基板1の製品形成領域X上に底板3および開口部4aの内周面と密着するようにして形成されていることから、上述したように、各配線基板2上に半導体素子Sを実装するとともに上面の略全面に半導体素子Sを覆う封止樹脂層Mを形成し、次に支持基板1をエッチング除去した後、各配線基板2の境界に沿ってダイシングにより切断することにより、得られる半導体装置においては、封止樹脂層Mは角の立った四角形状であるものの、配線基板2自体は角の丸い四角形状とすることができる。さらに、枠部4の開口部4aの形状を四角形以外の形状とし、その開口部4a内周面に密着するように配線基板2を形成することにより、四角形以外の形状の配線基板2を得ることができる。   Further, according to the multi-piece wiring board 10 of the present invention, the inner periphery of the opening 4a of the support substrate 1 has a square shape with rounded corners, and the wiring board 2 is located on the product formation region X of the support substrate 1. Are formed so as to be in close contact with the inner surface of the bottom plate 3 and the opening 4a. Therefore, as described above, the semiconductor element S is mounted on each wiring board 2, and the semiconductor element S is formed on substantially the entire upper surface. In the semiconductor device to be obtained, the sealing resin layer M is formed by cutting the support substrate 1 by etching and then cutting the support substrate 1 by dicing along the boundaries of the wiring substrates 2. Is a quadrangular shape with corners, but the wiring board 2 itself can be a quadrangular shape with rounded corners. Furthermore, the shape of the opening 4a of the frame portion 4 is a shape other than a quadrangle, and the wiring substrate 2 is formed so as to be in close contact with the inner peripheral surface of the opening 4a, thereby obtaining the wiring substrate 2 having a shape other than the quadrangle. Can do.

なお、上述の例では、多数個取り配線基板10の支持基板1をエッチング除去後にダイシングしたが、図7(a),(b)に示すように、配線基板10の支持基板1を付けたままでダイシングし、その後、分割された配線基板2から支持基板1をエッチング除去しても良い。   In the above-described example, the support substrate 1 of the multi-piece wiring substrate 10 is diced after being removed by etching. However, as shown in FIGS. 7A and 7B, the support substrate 1 of the wiring substrate 10 is left attached. After dicing, the support substrate 1 may be removed by etching from the divided wiring substrate 2.

次に、上述した多数個取り配線基板10の製造方法について説明する。先ず図8(a),(b)に示すように、支持基板1を準備する。支持基板1は、上述したように、厚みが100〜200μm程度の底板3の上面に、厚みが10〜30μm程度の枠部4を突設して成る。枠部4には、底板3の上面を複数の製品形成領域Xに仕切る開口部4aが形成されている。このような支持基板1は、厚みが120〜240μm程度の銅箔の上面にエッチングを施すことにより形成される。   Next, a method for manufacturing the multi-piece wiring board 10 described above will be described. First, as shown in FIGS. 8A and 8B, a support substrate 1 is prepared. As described above, the support substrate 1 is formed by protruding the frame portion 4 having a thickness of about 10 to 30 μm on the upper surface of the bottom plate 3 having a thickness of about 100 to 200 μm. An opening 4 a that partitions the upper surface of the bottom plate 3 into a plurality of product formation regions X is formed in the frame portion 4. Such a support substrate 1 is formed by etching the upper surface of a copper foil having a thickness of about 120 to 240 μm.

次に、図9に示すように、底板3の上面に開口部4a内を充填するとともに枠部4上を1〜5μm程度の薄い厚みで覆う絶縁層5を形成する。絶縁層5は、上述したように、エポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂にシリカ等の無機絶縁物フィラーを分散させた電気絶縁材料から成り、10〜30μm程度の厚みである。絶縁層5の形成は、例えば未硬化の電気絶縁材料のフィルムを支持基板1の上面に熱プレスにより貼着した後、熱硬化させることにより行われる。   Next, as shown in FIG. 9, the insulating layer 5 is formed so as to fill the inside of the opening 4 a on the upper surface of the bottom plate 3 and cover the frame 4 with a thin thickness of about 1 to 5 μm. As described above, the insulating layer 5 is made of an electrically insulating material in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as an epoxy resin or a polyimide resin, and has a thickness of about 10 to 30 μm. The insulating layer 5 is formed, for example, by sticking an uncured film of an electrically insulating material to the upper surface of the support substrate 1 by hot pressing and then thermosetting.

次に、図10に示すように、各製品形成領域X上の絶縁層5の上面に配線導体6を形成する。配線導体6は、5〜15μm程度の厚みの銅めっき層から成り、周知のセミアディティブ法により形成される。   Next, as shown in FIG. 10, the wiring conductor 6 is formed on the upper surface of the insulating layer 5 on each product formation region X. The wiring conductor 6 is made of a copper plating layer having a thickness of about 5 to 15 μm and is formed by a known semi-additive method.

最後に、図11に示すように、配線導体6が形成された絶縁層5の上面に配線導体6の一部を半導体素子接続パッド8および外部接続パッド9として露出させる開口部を有するソルダーレジスト層7を形成する。ソルダーレジスト層7は、アクリル変性エポキシ樹脂等の感光性の熱硬化性樹脂から成り、配線導体6の上での厚みが5〜15μm程度である。ソルダーレジスト層7の形成は、感光性の熱硬化性樹脂ペーストを配線導体6が形成された絶縁層5の上面に配線導体6を完全に覆うように塗布するとともに乾燥させた後、周知のフォトリソグラフィー技術により半導体素子接続パッド8および外部接続パッド9を露出させる開口部を有するように露光および現像した後、熱硬化させることにより形成される。   Finally, as shown in FIG. 11, a solder resist layer having openings for exposing a part of the wiring conductor 6 as the semiconductor element connection pad 8 and the external connection pad 9 on the upper surface of the insulating layer 5 on which the wiring conductor 6 is formed. 7 is formed. The solder resist layer 7 is made of a photosensitive thermosetting resin such as an acrylic-modified epoxy resin, and the thickness on the wiring conductor 6 is about 5 to 15 μm. The solder resist layer 7 is formed by applying a photosensitive thermosetting resin paste to the upper surface of the insulating layer 5 on which the wiring conductor 6 is formed so as to completely cover the wiring conductor 6 and drying it, and then performing well-known photo processing. The semiconductor device connection pad 8 and the external connection pad 9 are exposed and developed so as to have an opening for exposing the semiconductor element connection pad 8 and the external connection pad 9, and then thermally cured.

かくして、本発明の多数個取り配線基板10の製造方法によれば、平板状の底板3上に、底板3上を縦横の並びの多数の製品形成領域Xに仕切る開口部4aを有する枠部4が突設されて成るエッチング可能な支持基板1を準備し、次に支持基板1上に、開口部4a内を充填するとともに枠部4上を薄く覆う厚みの絶縁層5を形成し、次に各製品形成領域X上の絶縁層5上に配線導体6を形成することにより、ダイシングする際に配線基板2に割れや欠けが発生しにくい多数個取り配線基板10を提供することができる。さらに、底板3上を製品形成領域Xに仕切る開口部4a内周の形状を例えば角の丸い四角形状や四角形以外の形状としておくと、ダイシングにより分割された後、角の丸い四角形や四角形以外の他の形状を有する配線基板2を形成することが可能な多数個取り配線基板10を提供することができる。   Thus, according to the manufacturing method of the multi-cavity wiring board 10 of the present invention, the frame portion 4 having the openings 4a that divide the bottom plate 3 into a large number of product formation regions X arranged vertically and horizontally on the flat bottom plate 3. Is prepared, and an insulating layer 5 is formed on the support substrate 1 so as to fill the opening 4a and cover the frame 4 thinly. By forming the wiring conductor 6 on the insulating layer 5 on each product forming region X, it is possible to provide a multi-piece wiring substrate 10 in which the wiring substrate 2 is not easily cracked or chipped when dicing. Furthermore, if the shape of the inner periphery of the opening 4a that divides the bottom plate 3 into the product formation region X is set to a square shape with a rounded corner or a shape other than a square, for example, after being divided by dicing, A multi-piece wiring board 10 capable of forming wiring boards 2 having other shapes can be provided.

なお、本発明は、上述の実施形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば上述の実施形態例では、配線導体6はセミアディティブ法により形成されたが、周知のサブトラクティブ法により形成されても良い。この場合、配線導体6として銅箔を用いることもできる。また、上述の実施形態例では、配線基板2は絶縁層5および配線導体6がそれぞれ1層ずつで形成されたが、複数の絶縁層5および配線導体6を積層した多層構造により形成されても良い。   Note that the present invention is not limited to the above-described embodiment, and various modifications are possible as long as they do not depart from the gist of the present invention. For example, in the above-described embodiment, the wiring conductor 6 has Although formed by the semi-additive method, it may be formed by a well-known subtractive method. In this case, a copper foil can be used as the wiring conductor 6. In the above-described embodiment, the wiring board 2 is formed with one insulating layer 5 and one wiring conductor 6 each. However, the wiring board 2 may be formed with a multilayer structure in which a plurality of insulating layers 5 and wiring conductors 6 are stacked. good.

1 支持基板
2 配線基板
3 底板
4 枠部
4a 開口部
5 絶縁層
6 配線導体
7 ソルダーレジスト層
X 製品形成領域
DESCRIPTION OF SYMBOLS 1 Support substrate 2 Wiring board 3 Bottom plate 4 Frame part 4a Opening part 5 Insulating layer 6 Wiring conductor 7 Solder resist layer X Product formation area

Claims (4)

平板状の底板上に、該底板上を縦横の並びの多数の製品形成領域に仕切る開口部を有する枠部が突設されて成るエッチング可能な支持基板と、該支持基板の上面に形成されており、前記開口部内を充填するとともに前記枠部上面を薄く覆う厚みの絶縁層と、前記製品形成領域上の前記絶縁層上に形成されており、前記製品形成領域上の前記絶縁層とともに配線基板を形成する配線導体と、を具備して成ることを特徴とする多数個取り配線基板。   An etchable support substrate is formed on a flat bottom plate by projecting a frame portion having openings for partitioning the bottom plate into a large number of product formation regions arranged vertically and horizontally, and formed on the upper surface of the support substrate. And an insulating layer having a thickness that fills the opening and thinly covers the upper surface of the frame portion, and the insulating layer on the product forming region, and together with the insulating layer on the product forming region, a wiring board And a wiring conductor for forming a multi-piece wiring board. 前記開口部の内周が、角の丸い四角形状、または四角形と異なる形状であることを特徴とする請求項1記載の多数個取り配線基板。   2. The multi-cavity wiring board according to claim 1, wherein the inner periphery of the opening has a quadrangular shape with rounded corners or a shape different from the quadrangular shape. 平板状の底板上に、該底板上を縦横の並びの多数の製品形成領域に仕切る開口部を有する枠部が突設されて成るエッチング可能な支持基板を準備する第1の工程と、前記支持基板上に、前記開口部内を充填するとともに前記枠部上を薄く覆う厚みの絶縁層を形成する第2の工程と、前記各製品形成領域上の前記絶縁層上に配線導体を形成する第3の工程と、を行うことを特徴とする多数個取り配線基板の製造方法。   A first step of preparing an etchable support substrate in which a frame having an opening for partitioning a plurality of product forming regions arranged vertically and horizontally on the bottom plate is provided on a flat bottom plate; A second step of forming an insulating layer having a thickness that fills the inside of the opening and covers the frame portion thinly on the substrate; and a third step of forming a wiring conductor on the insulating layer on each product formation region And a process for producing a multi-piece wiring board. 前記開口部の内周が、角の丸い四角形状、または四角形と異なる形状であることを特徴とする請求項3記載の多数個取り配線基板の製造方法。   4. The method for manufacturing a multi-piece wiring board according to claim 3, wherein an inner periphery of the opening is a quadrangular shape with rounded corners or a shape different from the quadrangular shape.
JP2013273631A 2013-12-28 2013-12-28 Multi-piece wiring board and manufacturing method of the same Pending JP2015128120A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113130434A (en) * 2019-12-31 2021-07-16 力成科技股份有限公司 Package structure and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327141A (en) * 1992-05-25 1993-12-10 Murata Mfg Co Ltd Dielectric board and its manufacture
JP2001160659A (en) * 1999-11-30 2001-06-12 Murata Mfg Co Ltd Mounted component having electronic circuit
JP2009016466A (en) * 2007-07-03 2009-01-22 Nec Corp Wiring board complex, and manufacturing method of the wiring board complex, wiring board and semiconductor device
JP2009026860A (en) * 2007-07-18 2009-02-05 Elpida Memory Inc Semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327141A (en) * 1992-05-25 1993-12-10 Murata Mfg Co Ltd Dielectric board and its manufacture
JP2001160659A (en) * 1999-11-30 2001-06-12 Murata Mfg Co Ltd Mounted component having electronic circuit
JP2009016466A (en) * 2007-07-03 2009-01-22 Nec Corp Wiring board complex, and manufacturing method of the wiring board complex, wiring board and semiconductor device
JP2009026860A (en) * 2007-07-18 2009-02-05 Elpida Memory Inc Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113130434A (en) * 2019-12-31 2021-07-16 力成科技股份有限公司 Package structure and method for manufacturing the same
CN113130434B (en) * 2019-12-31 2023-08-01 力成科技股份有限公司 Package structure and method for manufacturing the same

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