JP2017069446A - Printed wiring board and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a thickness of the whole body including an electronic component, of a printed wiring board.SOLUTION: A printed wiring board 1 according to an embodiment comprises: a first circuit board 10 that has an opening 10a at the center part of an insulating layer 11; and a second circuit board 20 that has a third surface 20T and has a mounting area M for an electronic component at the third surface 20T side, and that is laminated on a first surface 10F of the first circuit board 10, and that exposes the mounting area M to the inside of the opening 10a. In addition, a recessed part 11C is formed at a second surface 10S side of the first circuit board 10.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a printed wiring board having a conductor post around an opening, and a method for manufacturing the same.

  Patent Document 1 discloses a package substrate that includes a base substrate on which a semiconductor element is mounted and a cavity substrate having a cavity portion that houses the semiconductor element. Around the cavity portion, a copper post that connects the base substrate and the cavity substrate and connects the package substrate to another package substrate is formed. The base substrate and the cavity substrate are bonded with an adhesive.

Japanese Patent Laying-Open No. 2015-60912

  In the package substrate of Patent Document 1, a cavity portion having a depth corresponding to the thickness of the cavity substrate is formed. When mounting a plurality of electronic components (semiconductor elements, passive components, etc.) having different thicknesses, it is considered preferable that the cavity portion has a depth that can accommodate the thicker electronic component. However, in that case, it is considered that the vertical stroke of the component suction nozzle of the mounter increases when the thinner electronic component is mounted. Installation time will be longer. Further, it is considered that the mounting position accuracy is lowered. However, even if it is a thin electronic component, if it is mounted on the surface of the cavity substrate, the thickness of the entire substrate including the electronic component will increase, and the effect of providing the cavity will be reduced.

  The printed wiring board of the present invention has a first circuit board having an opening at the center of an insulating layer having a first surface and a second surface opposite to the first surface, and is opposite to the third surface and the third surface. The fourth surface has a mounting area for electronic components on the third surface, and is laminated on the first surface of the first circuit board, and the opening is formed in the opening of the first circuit board. And a second circuit board exposing the mounting area. A recess is formed on the second surface of the first circuit board.

  The printed wiring board manufacturing method of the present invention includes an insulating layer having a first surface and a second surface opposite to the first surface on the base plate, and the first surface and the second surface of the insulating layer. Forming a first circuit board having first and second conductor posts penetrating therethrough, forming a frame-like groove from a first surface of the insulating layer opposite to the base plate, and the frame-like shape Providing a release film so as to cover the groove and the insulating layer surrounded by the groove, forming a second circuit board on the first surface of the insulating layer and on the release film, and the base Removing the plate, exposing the frame-like groove on the side of the insulating layer peeled from the base plate, and peeling a portion of the insulating layer surrounded by the groove. The second circuit is formed by forming an opening by removing the peeling film. And includes a be exposed in the opening part of the plate as a mounting area, and a forming a recessed portion by removing a portion of the insulating layer.

  According to the embodiment of the present invention, electronic components having different thicknesses can be mounted in openings or recesses having different depths. Even when electronic components having different heights are arranged, a stroke for arranging the electronic components can be shortened. Each component can be quickly mounted with high accuracy. Along with the reduction in the height of printed wiring boards including electronic components, it is considered that an improvement in component mounting productivity and an improvement in yield are achieved.

Sectional drawing of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the other example of the 2nd surface of the 1st circuit board of the printed wiring board of one Embodiment. The top view of the printed wiring board shown by FIG. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the other example of the printed wiring board of one Embodiment of this invention. The enlarged view which shows the other example of the shape of the inner wall of the recessed part of the printed wiring board of one Embodiment. The figure which shows an example of the manufacturing method of the printed wiring board shown by FIG. Sectional drawing which shows the example of the printed wiring board of other embodiment of this invention.

  Next, a printed wiring board according to an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the printed wiring board 1 according to the embodiment includes a first circuit having an opening 10a at the center of an insulating layer 11 having a first surface 11F and a second surface 11S opposite to the first surface 11F. A substrate 10 and a second circuit substrate 20 having a third surface 20T and a fourth surface 20F opposite to the third surface 20T are provided. The first surface 11F and the second surface 11S of the insulating layer 11 constitute the first surface 10F and the second surface 10S of the first circuit board 10, respectively. The second circuit board 20 is stacked on the first surface 10F of the first circuit board 10. The second circuit board 20 has a mounting area M for electronic components (not shown) on the third surface 20T side. The mounting area M is exposed to the mounting area M in the opening 10 a of the first circuit board 10. A cavity C having the mounting area M as a bottom surface is formed. The cavity C is formed to a depth of, for example, 100 μm or more and 170 μm or less.

  In the embodiment, the first circuit board 10 has a recess 11c on the second surface 11S of the insulating layer 11 in the first circuit board. That is, the depth of the recess 11 c is smaller than the thickness of the insulating layer 11. A recess 11c having a depth smaller than that of the cavity C is formed. The recess 11c is formed to a depth of 30 μm or more and 140 μm or less, for example.

  In the cavity C, electronic components (not shown) are arranged. Examples of the electronic component include a semiconductor element, a passive element, an interposer having a rewiring layer, a semiconductor element having a rewiring layer, and an electronic component such as WLP (Wafer Level Package). An electronic component (not shown) can also be disposed in the recess 11c. The depths of the cavity C and the recess 11c can be determined, for example, according to the thickness of the electronic component disposed inside. For example, a thicker electronic component is mounted in the cavity C, and another electronic component thinner than the electronic component disposed in the cavity C is accommodated in the recess 11c. It is considered that the entire thickness of the electronic component and the printed wiring board 1 in a state where the electronic component is mounted can be reduced. Further, since the thin electronic component can be mounted in the recess 11c shallower than the cavity C, it is considered that the amount of movement of the nozzle of the mounter of the electronic component in the vertical direction is small. It is considered that the mounting position accuracy of electronic parts is high. It is thought that the yield of electronic component mounting will increase. Moreover, it is thought that the mounting time of an electronic component is short. It is thought that the productivity of component mounting is high.

  The first circuit board 10 has first and second conductor posts 12 and 13 penetrating the insulating layer 11 around the opening 10a. An end surface of the first conductor post 12 opposite to the second circuit board 20 is exposed on the bottom surface of the recess 11c to form a first pad 12a. An electronic component may be mounted on the first pad 12a. An end surface of the second conductor post 13 on the second surface 10S side of the first circuit board 10 is exposed to the second surface 10S to form a second pad 13a. In the example shown in FIG. 1, the second pad 13 a is recessed from the second surface 10 </ b> S of the first circuit board 10. When an external wiring board or the like is connected to the second pad 13a using solder or the like, excessive flow of solder can be suppressed. Solder short-circuit between the adjacent second pads 13a can be prevented. However, the second pad 13a and the second surface 10S may be flush with each other. Alternatively, as shown in FIG. 2, an embedded wiring layer 16 embedded in the insulating layer 11 may be formed on the second surface 10S. In the example shown in FIG. 2, the second pad 13 b is formed by the exposed surface of the embedded wiring layer 16. The second pad 13 b has a width larger than the width of the second conductor post 13. The connection area with an external electronic component connected to the second pad 13b is large. Thereby, it is considered that a strong connection can be obtained.

  As shown in FIG. 3, the first circuit board 10 includes an opening 10a, a recess 11c, and a plurality of conductor posts including the first and second conductor posts 12 and 13 disposed so as to surround the opening 10a. Have. A cross-sectional view taken along the line II of FIG. 3 is shown in FIG. In the example of FIG. 3, the opening 10a of the first circuit board 10 is formed in a rectangular planar shape. Therefore, the planar shape of the cavity C can also be a quadrangle. However, the planar shape of the opening 10a and the cavity C is not limited to this, and may be a polygon other than a rectangle, a circle, or the like. Depending on the shape of the electronic component housed in the cavity C, the opening 10a and the cavity C can be formed in an arbitrary planar shape.

  FIG. 3 shows an example in which the planar shape of the recess 11c is also a quadrangle. Depending on the shape of the electronic component housed in the recess 11c, the recess 11c may also be formed in an arbitrary planar shape. FIG. 3 shows an example in which one recess 11 c is formed in the first circuit board 10. However, the recess 11 c can be formed at any desired position in the first circuit board 10. The recess 11 c is preferably formed by removing a part of the first conductor post 12 together with a part of the insulating layer 11. An arbitrary area of the first circuit board 10 can be a formation area of the recess 11c. It is considered that the degree of freedom in designing the printed wiring board is high.

  A plurality of the recesses 11 c may be formed on the first circuit board 10. It is considered that electronic components can be arranged more efficiently. For example, two concave portions 11c can be formed separately in two directions around the cavity C. The depth of each of the plurality of recessed portions 11c may be different. For example, electronic components having different thicknesses may be disposed in the respective recesses 11c. Alternatively, some or all of the electronic components arranged in each recess 11c may be of the same type. When the first circuit board 10 has a plurality of recesses 11c, the shape of each recess 11c is not limited to the example shown in FIG. Each can be determined appropriately according to the size and type.

  As shown in FIG. 3, the first pad 12a is exposed in the recess 11c. An electrode of an electronic component mounted in the recess 11c is connected to the first pad 12a. FIG. 3 shows an example in which four first pads 12a are formed on the bottom surface of the recess 11c. The first pads 12a may be formed with more or less than four according to the number of electrodes of the electronic component to be mounted. A second pad 13a is exposed on the second surface 10S of the first circuit board 10 so as to surround the opening 10a. An external wiring board (not shown) or an electrode of an electronic component can be connected to the second pad 13a.

  In FIG. 3, the plurality of conductor posts forming the first pad 12a or the second pad 13a are formed in three rows around the opening 10a, but the number of conductor posts and the positions where the conductor posts are formed are as follows. It is not limited to the example of FIG. Further, the planar shapes of the conductor posts and the first and second pads 12a and 13a are not limited to a circle as shown in FIG. 3, and may be formed in an arbitrary planar shape such as a polygon. The first and second pads 12a and 13a may be formed in different shapes.

  The first and second conductor posts 12 and 13 are columnar conductors made of a metal such as copper, for example, and the side surfaces are covered with the insulating layer 11. As shown in FIG. 1, the end surfaces of the first circuit board 10 on the first surface 10F side of the first and second conductor posts 12, 13 are exposed from the insulating layer 11 and are substantially flush with the first surface 10F. It is. It is considered that the adhesion between the first circuit board 10 and the second circuit board 20 is good.

  The insulating layer 11 is formed of, for example, an insulating resin material such as epoxy. The insulating layer 11 is preferably formed of a resin material that does not include a reinforcing material such as glass fiber. It is considered that the resin material flows sufficiently when the insulating layer 11 is formed, and the first and second conductor posts are appropriately covered without generating many voids. The insulating layer 11 is preferably formed of a mold resin for molding including an inorganic filler such as silica.

  As shown in FIG. 1, the second circuit board 20 has a first resin insulating layer 21 on the first surface 10 </ b> F side of the first circuit board 10. On the first circuit board 10 side of the first resin insulating layer 21, a recessed portion 21a is formed in a region corresponding to the opening 10a. A cavity C in which an electronic component (not shown) is arranged is formed by the opening 10a and the recessed portion 21a. A mounting area M is exposed on the bottom surface of the cavity C. The depth of the cavity C can be adjusted according to the thickness of the electronic component disposed in the cavity C by selecting the thickness of the insulating layer 11 or the like.

  The first resin insulation layer 21 is formed of a resin material such as epoxy, for example. The resin material may contain an inorganic filler such as silica. The first resin insulation layer 21 is preferably formed of a resin material impregnated in the reinforcing material 21b as shown in FIG. An example of the reinforcing material 21b is glass fiber. The mechanical strength is increased by the reinforcing material 21b. Therefore, even if the printed wiring board 1 is warped or stress is generated around the cavity C, it is considered that cracks are unlikely to occur. However, the first resin insulating layer 21 may be formed of a resin material such as epoxy that does not include a reinforcing material.

  A first via conductor 22 and a second via conductor 23 that pass through the first resin insulation layer 21 are formed in the first resin insulation layer 21. The first via conductor 22 is formed in the mounting area M of the second circuit board 20. The second via conductor 23 is formed in a region other than the mounting area M. The end face of the first via conductor 22 is exposed in the mounting area M. A connection pad with an electronic component (not shown) is formed by a surface exposed to the mounting area M of the first via conductor 22. An electrode of an electronic component arranged in the cavity C or the like can be directly connected to the exposed surface of the first via conductor 22. In the example of FIG. 1, 3 × 3 first via conductors 22 are formed in the mounting area M of the second circuit board 20. However, the number of the first via conductors 22 is not limited to this example, and can be appropriately selected according to the number of electrodes of the electronic component mounted in the cavity C, for example. The end face of the second via conductor 23 on the first circuit board 10 side is directly connected to the end face of the first circuit board 10 on the first face 10F side of the first and second conductor posts 12 and 13 without interposing any inclusions therebetween. It is connected. It is considered that the first circuit board 10 and the second circuit board 20 are bonded more firmly.

  In the printed wiring board 1 of the embodiment, the second circuit board 20 includes the build-up wiring layer 25 including the first resin insulating layer 21. The buildup wiring layer 25 is stacked on the first surface 10F of the first circuit board 10. Conductive layers and resin insulating layers are alternately stacked on the build-up wiring layer 25. In the example of FIG. 1, the build-up wiring layer 25 is formed by alternately laminating each of the conductor layers 26a to 26d and each of the first resin insulating layer 21 and the interlayer resin insulating layers 27a to 27c. Third via conductors 28a-28c penetrating interlayer resin insulation layers 27a-27c are formed in interlayer resin insulation layers 27a-27c, respectively. The number of conductor layers 26a to 26d of the build-up wiring layer 25 is four in the example of FIG. 1, but may include three or less conductor layers or five or more conductor layers. For example, only the first resin insulating layer 21 and the conductor layer 26a on the first resin insulating layer 21 may be formed.

  In the example of FIG. 1, a solder resist layer 29 is formed on the fourth surface 20 </ b> F of the second circuit board 20. The solder resist layer 29 has a plurality of openings 29a that expose a part of the surface of the second circuit board 20 on the fourth surface 20F side of the conductor layer 26d. The exposed surface in the opening 29a of the conductor layer 26d is the third pad 26d1.

  The material of the interlayer resin insulation layers 27a to 27c is not particularly limited, and is formed of, for example, an epoxy resin. Preferably, a resin material that does not include a reinforcing material is used. Conductor layers 26b to 26d having a fine pitch conductor pattern can be easily formed.

  The end surfaces of the first and second via conductors 22 and 23 opposite to the first circuit board 10 side are connected to the conductor layer 26a, and are connected to the third via conductor 28a via the conductor layer 26a. The first via conductor 22, the second via conductor 23, and the third via conductors 28 a to 28 c are all tapered with a diameter decreasing from the fourth surface 20 F side to the third surface 20 T side of the second circuit board 20. It is formed into a shape. The third via conductors 28a to 28c are formed at positions overlapping each other in plan view, and form so-called stacked vias.

  The third pad 26d1 is connected to, for example, an external motherboard. For example, an external electronic component connected to the first and second pads 12a and 13a can be electrically connected to an external motherboard or the like on the third pad 26d1 side through a short path. Connection reliability is considered high.

  The manufacturing method of the printed wiring board of one Embodiment is demonstrated with reference to FIG.

  As shown in FIG. 4A, for example, a base plate 80 and a metal film 81 are prepared. For the base plate 80, for example, a resin insulating plate made of prepreg or the like or a metal plate such as copper is used. The metal film 81 is attached to the carrier copper foil 81b so as to be referred to as a copper foil with a carrier copper foil, for example. The carrier copper foil 81b and the metal film 81 are bonded to each other with an adhesive, for example, in a blank portion near the outer periphery. The carrier copper foil 81b and the metal film 81 may be bonded on the entire surface with a thermoplastic adhesive (not shown). For example, the metal film 81 has a thickness of 3 μm or more and 8 μm or less. The carrier copper foil 81b is attached to the base plate 80 by thermocompression bonding.

  4A to 4L show an example in which the printed wiring board 1 is formed on both sides of the base plate 80. FIG. However, the printed wiring board 1 may be formed only on one surface of the base plate 80. In the following description with reference to FIGS. 4B to 4L, the description of the other surface side of the base plate 80 is omitted. The reference numerals on the other surface side of the base plate 80 in FIGS. 4B to 4L are also appropriately omitted.

  As shown in FIG. 4B, a resist mask 82 for forming the first and second conductor posts 12 and 13 is formed on the metal film 81. The resist mask 82 is provided with an opening 82 a 1 for forming the first conductor post 12 and an opening 82 a 2 for forming the second conductor post 12. The opening 82a1 is provided in the formation region of the recess 11c (see FIG. 1). The resist mask 82 is formed with a thickness of 100 μm or more and 250 μm or less, for example.

  The first conductor post 12 and the second conductor post 13 are formed in the openings 82a1 and 82a2 of the resist mask 82 by copper electroplating using the metal film 81 as a seed layer, respectively. Thereafter, as shown in FIG. 4C, the resist mask 82 is removed. The end surfaces and side surfaces of the first and second conductor posts 12 and 13 may be roughened by soft etching or the like.

  As shown in FIG. 4D, the insulating layer 11 is formed on the metal film 81 so as to cover the first and second conductor posts 12 and 13. For example, the insulating layer 11 is formed by laminating a film-like resin material on the first and second conductor posts 12 and 13 and heating and pressing. For the resin material of the insulating layer 11, for example, an epoxy resin that does not include a reinforcing material such as glass fiber, preferably a resin for molding with good fluidity is used.

  As shown in FIG. 4E, the surface of the insulating layer 11 opposite to the base plate 80 is polished by, for example, buffing. This polishing is performed so that the end faces of the first and second conductor posts 12 and 13 are exposed. Even if the heights of the first and second conductor posts 12 and 13 vary, the end surfaces of the first and second conductor posts 12 and 13 are flattened by this polishing. Further, the first surface 11F of the insulating layer 11 and the end surfaces of the first and second conductor posts 12, 13 are substantially flush. Through the steps up to FIG. 4E, the first circuit board 10 having the insulating layer having the first surface 11F and the second surface 11S opposite to the first surface 11F is formed on the base plate 80. The first circuit board 10 is formed to a thickness of 100 μm or more and 250 μm or less, for example. The first and second conductor posts 12 and 13 have substantially the same length (height from the metal film 81) as the thickness of the first circuit board 10.

  As shown in FIG. 4F, a frame-shaped groove 10c is formed in the insulating layer 11 from the first surface 11F on the side opposite to the base plate 80 side. The frame-shaped groove 10c may not reach the second surface 11S. That is, after removing the metal film 81 from the second surface 10S of the first circuit board 10 shown in FIG. 4M described later, the frame-shaped groove 10c is exposed on the second surface 10S side of the first circuit board 10. It does not have to be. It is only necessary that the portion 11a of the insulating layer 11 surrounded by the frame-shaped groove 10c can be removed from the first circuit board 10 (see FIG. 4N). The groove 10 c is formed so as to surround the formation region 10 b of the opening 10 a of the first circuit board 10. The groove 10c is formed by, for example, laser light irradiation. The groove 10c may be formed by other methods such as drilling.

  As shown in FIG. 4G, a release film 83 is provided so as to cover a portion surrounded by the frame-like groove 10c and the groove 10c of the insulating layer 11. For example, a film-like fixing material 84 is laminated on the insulating layer 11 so as to cover a portion surrounded by the frame-like groove 10 c and the groove 10 c of the insulating layer 11, and the release film 83 is fixed by the fixing material 84. The The peeling film 83 facilitates peeling of a portion surrounded by the groove 10 c of the insulating layer 11. The release film 83, together with the fixing material 84, prevents the resin material of the first resin insulation layer from entering the groove 10c in the formation of the first resin insulation layer described later. In the example shown in FIG. 4G, a release film 83 having the same size as the region in the outer edge 10c1 of the frame-like groove 10c is provided. The release film 83 may be pressed toward the insulating layer 11 so that a part of the fixing material 84 enters the groove 10c. Intrusion of the resin material of the first resin insulating layer 21 (see FIG. 4H) into the groove 10c can be prevented more reliably. Further, the release film 83 can serve as a laser beam stopper used for forming a first via conductor 22 described later. The release film 83 is exemplified by a metal foil, preferably a copper foil.

  The fixing material 84 is made of a material that is separably adhered to the release film 83 and that is also well adhered to the insulating layer 11. As shown in FIG. 4G, a part of the fixing member 84 may enter the groove 10c. It is considered that the resin material of the first resin insulation layer 21 is reliably prevented from entering the groove 10c. An example of the material of the fixing member 84 is polyimide resin. A material used for a release agent or the like, silicone rubber, or the like may be included. The fixing material 84 may be applied using a mask or the like in a paste state.

  Next, the second circuit board 20 (see FIG. 4K) is formed on the first surface 11F of the insulating layer 11 and the release film 83.

  As shown in FIG. 4H, the first resin insulating layer 21 is formed on the first surface 11F of the insulating layer 11 and the release film 83. For example, a prepreg including a reinforcing material 21b such as glass fiber is laminated on the first surface 11F of the insulating layer 11 and the release film 83, and heated and pressurized. As shown in FIG. 4H, the copper foil 26a1 may be laminated on the first resin insulating layer 21. However, the first resin insulating layer 21 may be formed by laminating a film-like epoxy resin that does not include a reinforcing material or the like on the first surface 11F of the insulating layer 11 and the release film 83.

  As shown in FIG. 4I, a conductor layer 26 a is formed in the first resin insulating layer 21 together with the first via conductor 22 and the second via conductor 23. Specifically, for example, through holes 22a and 23a penetrating through the first resin insulating layer 21 by laser light irradiation are formed at the positions where the first and second via conductors 22 and 23 of the first resin insulating layer 21 are formed, respectively. It is formed. The end surfaces of the first and second conductor posts 12 and 13 and the release film 83 are used as laser light stoppers. A metal film (not shown) is formed in the through holes 22a and 23a and on the first resin insulating layer 21 (or on the copper foil 26a1 when the copper foil 26a1 is laminated) by electroless plating or sputtering. The Using this metal film as a seed layer, the conductor layer 26a and the first and second via conductors 22 and 23 are formed by a semi-additive method. The second via conductor 23 is formed on the end surfaces of the first and second conductor posts 12 and 13 exposed in the through hole 23a. The second via conductor 23 is directly connected to the first conductor post 12 or the second conductor post 13 as shown in FIG. 4I. Although not shown, the conductor layer 26a includes a metal film used as a seed layer. The conductor layer 26a may include a copper foil 26a1. The metal film exposed without being contained in the conductor layer 26a and the underlying copper foil 26a1 are removed by etching.

  As shown in FIG. 4J, the interlayer resin insulation layer 27a is formed on the first resin insulation layer 21 and the conductor layer 26a by, for example, laminating a film-like resin material, heating and pressing. Then, a conductor layer 26b is formed on the interlayer resin insulation layer 27a. In addition, a third via conductor 28a that penetrates the interlayer resin insulation layer 27a and connects the conductor layer 26a and the conductor layer 26b is formed. The conductor layer 26b and the third via conductor 28a are formed by the same method as the formation of the conductor layer 26a, the first via conductor 22 and the second via conductor 23 on the first resin insulating layer 21.

  As shown in FIG. 4K, the interlayer resin insulation layer 27b, the conductor layer 26c, the interlayer resin insulation layer 27c, and the conductor layer 26d are formed on the interlayer resin insulation layer 27a and the conductor layer 26b in the same manner as the method shown in FIG. 4J. Are formed in order. Also, third via conductors 28b and 28c penetrating interlayer resin insulation layers 27b and 27c are formed. The interlayer resin insulation layers 27b and 27c are the same as the interlayer resin insulation layer 27a, the conductor layers 26c and 26d are the same as the conductor layer 26b, and the third via conductors 28b and 28c are the same as the third via conductor 28a. Each can be formed in a similar manner. Thereby, the second circuit board 20 is formed on the first surface 10F of the first circuit board 10.

  Interlayer resin insulation layers 27a-27c are each formed to a thickness of, for example, 10 μm or more and 100 μm or less. The materials of the conductor layers 26a to 26d, the first and second via conductors 22 and 23, and the third via conductors 28a to 28c are not particularly limited, but copper is preferably used. The conductor layers 26a to 26d are each formed to a thickness of 10 μm or more and 25 μm or less, for example.

  In the example shown in FIG. 4K, the solder resist layer 29 is formed on the fourth surface 20F of the second circuit board 20. For example, the solder resist layer 29 having the openings 29a is formed by forming a photosensitive epoxy resin layer on the fourth surface 20F, exposure, and development. The photosensitive epoxy resin may contain an inorganic filler.

  As shown in FIG. 4L, the metal film 81 and the base plate 80 are separated. For example, the metal film 81 and the carrier copper foil 81b are separated from each other by cutting off the joint portion of the blank portion where the carrier copper foil 81b and the metal film 81 are joined. When a thermoplastic adhesive is used, the metal film 81 and the carrier copper foil 81b are separated in a heated state. The metal film 81 exposed on the second surface 10S of the first circuit board 10 by the separation from the base plate 80 is removed by etching or the like. By removing the base plate 80 and the metal film 81, the frame-shaped groove 10c is exposed on the second surface 10S side of the first circuit board 10, as shown in FIG. 4M. In FIG. 4M and FIG. 4N, only the lower printed wiring board in FIG. 4L is shown. The end surfaces of the first circuit board 10 on the second surface 10S side of the first and second conductor posts 12, 13 may be recessed from the second surface 10S by overetching when removing the metal film 81. If even a thin film of the metal film 81 remains, the second conductor posts 13 are short-circuited, so it is preferable to perform over-etching.

  A portion 11 a surrounded by the frame-shaped groove 10 c in the insulating layer 11 is peeled off from the peeling film 83 and removed from the first circuit board 10. For example, the portion 11a surrounded by the groove 10c is fixed to a jig or the like by vacuum suction or adhesion. The portion 11a surrounded by the groove 10c is peeled from the peeling film 83 by pulling up the jig and the like. As shown in FIG. 4N, the fixing member 84 is also preferably peeled off from the peeling film 83 and removed together with the removed portion 11a of the insulating layer 11. An opening 10 a is formed in the first circuit board 10. The release film 83 is exposed in the opening 10a.

  As shown in FIG. 4O, the peeling film 83 exposed in the opening 10a is removed by, for example, etching. When the fixing material 84 remains on the peeling film 83, the residual material of the fixing material 84 is preferably removed together with the peeling film 83. By etching, the end surfaces of the first circuit board 10 on the second surface 10S side of the first and second conductor posts 12 and 13 can be recessed from the second surface 10S. A recessed portion 21 a is formed in the first resin insulating layer 21. A cavity C composed of the opening 10a and the recessed portion 21a is formed. At the bottom surface of the cavity C, the end face of the first via conductor 22 is exposed, and a connection pad for an electronic component is formed. A part of the second circuit board 20 is exposed as an electronic component mounting area M in the opening 10a.

  Subsequently, as shown in FIG. 4O, the recess 11 c is formed by removing a part of the insulating layer 11. The printed wiring board 1 of one embodiment shown in FIG. 1 is completed. The removal can be performed by, for example, drilling from the second surface 10S side of the first circuit board 10. The formation of the recess 11c may be performed by sandblasting.

  In the present embodiment, as shown in FIG. 4O, a part of the first conductor post 12 on the second surface 10S side of the first circuit board 10 is removed together with a part of the insulating layer 11 to thereby form the bottom surface of the recess 11c. The end face of the first conductor post 12 is exposed. A first pad 12a is formed by the exposed end surface. An electronic component disposed in the recess 11c can be mounted via the first pad 12a. By adjusting the depth of the insulating layer 11 to be removed and the size of the insulating layer 11 in a plan view, the concave portion 11c having a shape corresponding to the thickness or size of the electronic component disposed in the concave portion 11c can be formed. The recess 11 c is provided in the insulating layer 11. That is, the depth of the recess 11 c is smaller than the thickness of the insulating layer 11. The bottom surface of the recess 11c is formed by the insulating layer 11 and the end surface of the first conductor post 12 exposed in the recess 11c.

  The formation of the recess 11c may be performed before the step of removing the release film 83 by etching. In this case, etching for removing the release film 83 is performed in a state where the first pad 12a is exposed on the bottom surface of the recess 11c. For this reason, the first pad 12a can be recessed from the bottom surface of the recess 11c. An example of this is shown in FIG.

  When the second circuit board 20 having fewer than four conductor layers is formed, the formation of any one or all of the conductor layers 26b to 26d and the interlayer resin insulating layers 27a to 27c is omitted. When the second circuit board 20 having more than four conductor layers is formed, the interlayer resin insulation layer and the conductor layer are formed by the same method as the formation of the interlayer resin insulation layer 27a and the conductor layer 26b according to the number of layers. The formation of is repeated.

  In the example shown in FIG. 2 in which the embedded wiring layer 16 is formed on the second surface 10S of the printed wiring board 1, for example, in the step shown in FIG. 4B, the resist mask 82 for forming the conductor posts 12 and 13 and By using a different resist mask, the buried wiring layer 16 can be formed. That is, a resist mask (not shown) for forming the buried wiring layer 16 is formed on the metal film 81 before the resist mask 82 is formed. An opening for forming the second pad 13b is provided at a position corresponding to the position where the conductor post 13 of the resist mask for forming the buried wiring layer 16 is formed. The opening for forming the second pad 13b is formed larger than the opening 82a2 for forming the conductor post 13. In the opening of the resist mask for forming the buried wiring layer 16, a conductor layer 16a is formed by electrolytic plating of copper using the metal film 81 as a seed layer. A resist mask 82 is formed on the conductor layer 16a so as to have an opening 82a2. The resist mask for forming the buried wiring layer 16 may be removed before the resist mask 82 is formed. Alternatively, the removal of the resist mask for forming the buried wiring layer 16 may be performed simultaneously with the removal of the resist mask 82 (see FIG. 4C). The second conductor post 13 is formed in the opening 82a2 by electrolytic plating of copper using the conductor layer 16a forming the embedded wiring layer 16 as a seed layer.

  After the resist mask 82 is removed, the conductor layer 16a is covered with the insulating layer 11 together with the conductor posts 12 and 13 by the same method as that shown in FIG. 4D. A buried wiring layer 16 is formed. The exposed surface of the embedded wiring layer 16 on the second surface 10S side can be recessed from the second surface 10S by removing the peeling film 83 by etching in the process shown in FIG. An example of this is shown in FIG.

  FIG. 6 shows a modification of the inner wall shape of the cavity C of the printed wiring board 1 according to the embodiment. In FIG. 1, a modified example of the V portion surrounded by the alternate long and short dash line is shown enlarged. A portion of the inner wall of the cavity C in the first resin insulating layer 21 is recessed more than a portion in the first circuit board 10. That is, the recessed portion 21 a of the first resin insulating layer 21 is formed larger than the opening 10 a of the first circuit board 10 in plan view. It is considered that stress that may be generated due to a difference in thermal expansion coefficient between the first circuit board 10 and the second circuit board 20 is dispersed in the corner portions C1 to C3.

  The recess in the portion of the inner wall of the cavity C in the first resin insulating layer 21 can be formed, for example, by using a release film 83a that is larger than the portion surrounded by the frame-shaped groove 10c, as shown in FIG. . FIG. 7 is an enlarged view of the peripheral portion of the release film of the printed wiring board in the process shown in FIG. 4H described above. The release film 83a is provided so as to reach the outside of the left and right grooves of the frame-like groove 10c. The fixing material 84 is also laminated in a range corresponding to the size of the release film 83a. From the state shown in FIG. 7, the portion 11 a surrounded by the groove 10 c of the insulating layer 11, the fixing material 84 and the release film 83 a are removed by the same method as described above. The removed portion of the release film 83a and the fixing material 84 outside the groove 10c can be a recess in the inner wall of the cavity C.

  In the printed wiring board 1 according to the embodiment, the end surface of the first conductor post 12 is exposed on the bottom surface of the recess 11c. However, the bottom surface of the recess 11c may be formed of only the insulating layer 11. That is, as illustrated in FIG. 8, the conductor post that penetrates the insulating layer 11 may not be formed at a position overlapping the concave portion 11 c in plan view. Even in that case, an electronic component may be mounted in the recess 11c. For example, the electronic component can be mounted in the recess 11c with an adhesive or the like so that the electrode portion faces the second surface 10S side of the first circuit board 10. And the electrode part which faces the 2nd surface 10S side, and an external wiring board and an electronic component may be connected.

DESCRIPTION OF SYMBOLS 1 Printed wiring board 10 1st circuit board 10F 1st surface 10S 2nd surface 10a Opening 10c Frame-shaped groove | channel 11 Insulating layer 11F 1st surface 11S 2nd surface 11c Recessed part 12 1st conductor post 12a 1st pad 13 2nd conductor Post 13a Second pad 20 Second circuit board 20T Third surface 20F Fourth surface 21 First resin insulation layer 22 First via conductor 23 Second via conductor 25 Build-up wiring layers 26a to 26d Conductor layer 26d1 Third pad 27a to 27c Interlayer resin insulating layers 28a to 28c Third via conductor 29 Solder resist layer 80 Base plate 81 Metal film 82 Resist mask 83 Release film 84 Fixing material M Mounting area C Cavity

Claims (15)

A first circuit board having an opening in a central portion of an insulating layer having a first surface and a second surface opposite to the first surface;
A third surface and a fourth surface opposite to the third surface, and an electronic component mounting area on the third surface, stacked on the first surface of the first circuit board, A second circuit board exposing the mounting area in the opening of the first circuit board;
A printed wiring board comprising:
A recess is formed in the second surface of the first circuit board. 2. The printed wiring board according to claim 1, wherein a depth of the concave portion from the second surface is smaller than a thickness of the first circuit board. 2. The printed wiring board according to claim 1, wherein the first circuit board further includes a first conductor post penetrating the first circuit board, and the first conductor post is exposed to a bottom surface of the recess. Yes. 4. The printed wiring board according to claim 3, wherein the first circuit board further includes a second conductor post penetrating the first circuit board, and the second conductor post is a second of the first circuit board. It is exposed on the surface side. 5. The printed wiring board according to claim 4, wherein the second circuit board further comprises a first resin insulation layer and a conductor layer on a first surface side of the first circuit board, and an interlayer resin insulation layer and a conductor layer. And a buildup wiring layer comprising a laminated structure. The printed wiring board according to claim 5, wherein the insulating layer constituting the first circuit board is formed of a resin not including a reinforcing material, and the first resin insulating layer is formed of a resin including a reinforcing material. Is formed. 7. The printed wiring board according to claim 6, wherein the interlayer resin insulation layer is formed of a resin that does not include a reinforcing material. 5. The printed wiring board according to claim 4, wherein end surfaces of the first conductor post and the second conductor post on the first surface side are substantially flush with the first surface. The printed wiring board according to claim 5, wherein the second circuit board further includes a first via conductor that penetrates the first resin insulating layer, and the first via conductor is in the mounting area. Is exposed. 10. The printed wiring board according to claim 9, wherein the second circuit board further includes a second via conductor penetrating the first resin insulating layer, and the first conductor post and the second conductor post are the Directly connected to the second via conductor. An insulating layer having a first surface and a second surface opposite to the first surface, and first and second conductor posts penetrating the first surface and the second surface of the insulating layer are provided on the base plate. Forming a first circuit board;
Forming a frame-shaped groove from the first surface opposite to the base plate side of the insulating layer;
Providing a release film so as to cover the frame-shaped groove and the insulating layer surrounded by the groove;
Forming a second circuit board on the first surface of the insulating layer and on the release film;
Removing the base plate;
Exposing the frame-like groove on the surface side of the insulating layer peeled from the base plate;
Forming an opening by peeling a portion of the insulating layer surrounded by the groove;
Removing a part of the second circuit board as a mounting area by removing the release film; and
Forming a recess by removing a portion of the insulating layer;
A method of manufacturing a printed wiring board including: 12. The method of manufacturing a printed wiring board according to claim 11, wherein the first circuit board is formed.
Providing a metal film on the base plate;
Forming the first and second conductor posts on the metal film;
Forming the insulating layer on the metal film so as to cover the first and second conductor posts;
Polishing the surface of the insulating layer to flatten the end faces of the first and second conductor posts;
In addition. 12. The method for manufacturing a printed wiring board according to claim 11, wherein the recess is formed by removing a part of the insulating layer so that the depth is smaller than the thickness of the first circuit board. 13. The method of manufacturing a printed wiring board according to claim 12, wherein the step of forming the recess includes removing the part of the first conductor post together with a part of the insulating layer to form the first on the bottom surface of the recess. It includes exposing the end face of one conductor post. It is a manufacturing method of the printed wiring board of Claim 11, Comprising: The process of forming the said recessed part is performed by drilling.

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